Kioxia Corporation patent applications on March 21st, 2024
Patent Applications by Kioxia Corporation on March 21st, 2024
Kioxia Corporation: 93 patent applications
Kioxia Corporation has applied for patents in the areas of H10B43/27 (30), G11C16/26 (18), H10B43/35 (16), G06F3/06 (15), H10B80/00 (15)
With keywords such as: memory, layer, semiconductor, data, direction, third, device, region, circuit, and voltage in patent application abstracts.
Patent Applications by Kioxia Corporation
20240091681.END MATERIAL RECOVERY APPARATUS_simplified_abstract_(kioxia corporation)
Inventor(s): Takafumi YONEZAWA of Yokohama Kanagawa (JP) for kioxia corporation
IPC Code(s): B01D29/35, B01D29/92, B01D29/94
Abstract: an end material recovery apparatus includes a plurality of cages each in which an upper portion is opened, the plurality of cages each having at least one surface formed of at least one of a mesh-like surface and a porous surface, the plurality of cages being configured to receive a mixed liquid in which an end material is mixed with a liquid from the upper portion, collect at least a part of the end material in the mixed liquid, and discharge the liquid from the at least one surface; a rotation drive mechanism configured to individually rotate the plurality of cages in a direction in which the upper portion faces downward; and a plurality of recovery containers configured to recover the end material dropped by individually rotating the plurality of cages in the direction in which the upper portion faces downward.
Inventor(s): Tsunehiro KITA of Fujisawa Kanagawa (JP) for kioxia corporation, Soichiro IBARAKI of Yokohama Kanagawa (JP) for kioxia corporation
IPC Code(s): G01R1/04, G01R31/28
Abstract: a socket board used for testing a semiconductor device having one or more terminals, by raising a temperature of the semiconductor device to a predetermined temperature, includes a substrate, a socket that is provided on the substrate and capable of holding the semiconductor device, a pin that penetrates a bottom portion of the socket, and has an upper portion that is to come into contact with a terminal of the semiconductor device, and a heat conductive material that is disposed on the bottom portion of the socket to come into contact with the terminals of the semiconductor device held in the socket. the heat conductive material includes a macromolecular gel, and electrically-insulating metal-containing particles added to the macromolecular gel.
Inventor(s): Atsushi YAMAZAKI of Hachioji Tokyo (JP) for kioxia corporation
IPC Code(s): G01R31/317
Abstract: a memory having a first authentication code includes a communication port configured to transmit information including debug data to or receive the information including debug data from the external device; and a debug port controller that is usable for blocking of a communication path connecting to the communication port. the debug port controller is configured to receive an authentication request including a second authentication code from an external device, determine whether the second authentication code matches the first authentication code, and block the communication path if the second authentication code is not determined to match the first authentication code. the communication port may be configured to be disabled until the second authentication code matches the first authentication code.
Inventor(s): Masaki MITSUYASU of Kuwana Mie (JP) for kioxia corporation, Ryo OGAWA of Mie Mie (JP) for kioxia corporation, Anupam MITRA of Yokkaichi Mie (JP) for kioxia corporation
IPC Code(s): G03F1/42, G03F7/00, G03F9/00, H01L21/3213
Abstract: according to one embodiment, a pattern formation method includes holding a substrate on a suction chuck that an outer suction region for an outer edge portion of the substrate and an inner suction region for an inner region of the substrate. a partial shot region at an outer edge of the substrate has a first alignment mark in the inner region and a second alignment mark at the outer edge portion. while a template is being pressed against a resin film in the shot region, position alignment using the second and fourth alignment marks is performed by adjusting a suction force for the outer suction region for changing a warpage amount of the substrate while observing the second and fourth alignment marks through the template.
20240094904.MEMORY SYSTEM AND METHOD_simplified_abstract_(kioxia corporation)
Inventor(s): Yifan TANG of Yokohama (JP) for kioxia corporation
IPC Code(s): G06F3/06
Abstract: according to one embodiment, a memory system comprises a first memory including a nonvolatile memory cell array, a second memory configured to operate at higher speed than the first memory, and a memory controller. the memory controller executes, in response to a write command from a host, data transfer from the host to the second memory, a data-in operation, and a program operation, with respect to first data instructed to be written by the write command. after the data-in operation for the first data is started and before the data-in operation is completed, the memory controller transfers the first data from the second memory to the host in response to a read command to read the first data. after the program operation for the first data is started, the memory controller transfers the first data from the first memory to the host in response to the read command.
20240094913.STORAGE DEVICE AND MEMORY SYSTEM_simplified_abstract_(kioxia corporation)
Inventor(s): Shinichiro TAGAMI of Kawasaki Kanagawa (JP) for kioxia corporation
IPC Code(s): G06F3/06
Abstract: a storage device includes: a non-volatile memory; a parameter storage unit that stores a plurality of parameters for setting different operating conditions in the non-volatile memory; an access pattern analysis unit that analyzes an access pattern indicating a tendency to access the non-volatile memory by a command from a host device; a parameter selection unit that selects an optimal parameter from among the plurality of parameters based on the access pattern analyzed by the access pattern analysis unit; and an access control unit that accesses the non-volatile memory in a state where the optimal parameter is set in the non-volatile memory.
20240094914.MEMORY SYSTEM AND NON-VOLATILE MEMORY_simplified_abstract_(kioxia corporation)
Inventor(s): Keisuke TAKAHASHI of Yokohama Kanagawa (JP) for kioxia corporation
IPC Code(s): G06F3/06, G11C16/04, G11C16/10, G11C16/26
Abstract: a memory system includes a non-volatile memory and a controller. the non-volatile memory includes a memory cell array and a register storing first table data including feature information indicating feature of an address designating a storage area in the memory cell array. the controller can control the non-volatile memory. when receiving address information indicating the address from the controller, the non-volatile memory reads the feature information from the first table data in the register and transmits the feature information to the controller. when receiving the feature information from the non-volatile memory, the controller can execute a response operation in response to a request with respect to the address based on the received feature information.
20240094916.MEMORY SYSTEM_simplified_abstract_(kioxia corporation)
Inventor(s): Takeshi MIURA of Kamakura Kanagawa (JP) for kioxia corporation
IPC Code(s): G06F3/06
Abstract: a memory system includes a nonvolatile memory including first and second planes each including a plurality of memory cells, and a memory controller configured to transmit commands to the first and second planes via a first signal line and receive data from the first and second planes via a second signal line. the memory controller is configured such that, when the first plane is executing a first process, the memory controller suspends transmission of a first command instructing reservation of the first process to the second plane until a first condition is satisfied.
20240094923.MEMORY SYSTEM_simplified_abstract_(kioxia corporation)
Inventor(s): Takashi WAKUTSU of Kamakura Kanagawa (JP) for kioxia corporation, Yasuaki NAKAZATO of Kamakura Kanagawa (JP) for kioxia corporation, Takeshi NAKANO of Kawasaki Kanagawa (JP) for kioxia corporation
IPC Code(s): G06F3/06
Abstract: a controller assigns a first plurality of blocks among a plurality of blocks provided in a non-volatile memory to a first area, assigns a second plurality of blocks to a second area, and assigns a third plurality of blocks to a third area. the controller uses each block assigned to the first area in a first mode, uses each block assigned to the second area in a second mode in which the number of bits of data written in each memory cell is larger than that in the first mode, and uses each block assigned to the third area in the first mode or the second mode. the controller writes data received from a host device to an area that corresponds to a designation from the host device out of the first area and the third area. the controller transcribes valid data written to the first area and the third area to the second area.
20240094924.STORAGE DEVICE_simplified_abstract_(kioxia corporation)
Inventor(s): Hirotomo KOBAYASHI of Yokosuka (JP) for kioxia corporation
IPC Code(s): G06F3/06
Abstract: according to one embodiment, a storage device includes a nonvolatile memory and a controller. the controller manages first user identification information and first authentication information including a hash value calculated from the first user identification information and a first device identification information of a first client device. the controller receives an access request to the nonvolatile memory, user identification information, and authentication information transmitted from an external device, and accepts the access request in a case where the user identification information received matches the first user identification information, and the authentication information received matches the first authentication information.
Inventor(s): Saswati DAS of Milpitas CA (US) for kioxia corporation
IPC Code(s): G06F3/06
Abstract: a method performed by a controller of a solid-state drive (ssd) comprising receiving a command from a host, the command identifying a namespace in a non-volatile semiconductor memory device of the ssd to be formatted, identifying a plurality of regions in the non-volatile semiconductor memory device corresponding to the namespace, unmapping a dummy region in a volatile semiconductor memory device of the ssd using invalid addresses, and copying the invalidated dummy region to each region of the plurality of regions of the namespace.
20240094932.MEMORY SYSTEM_simplified_abstract_(kioxia corporation)
Inventor(s): Tomoyuki KANTANI of Yokohama Kanagawa (JP) for kioxia corporation, Kousuke FUJITA of Yokohama Kanagawa (JP) for kioxia corporation, Iku ENDO of Odawara Kanagawa (JP) for kioxia corporation
IPC Code(s): G06F3/06
Abstract: a memory system includes a memory controller configured to write data in a first mode to a first block of a first area of a non-volatile memory. the first mode is a write mode for writing data with a first number of bits per memory cell. the memory controller is further configured to execute copy processing on the data written in the first mode to the first block, by writing system data written in the first block to a second block of the first area in the first mode and writing user data written in the first block to a third block of a second area of the non-volatile memory in the second mode. the second mode is a write mode for writing data with a second number of bits larger than the first number of bits per memory cell.
20240094940.MEMORY SYSTEM_simplified_abstract_(kioxia corporation)
Inventor(s): Kensaku YAMAGUCHI of Kawasaki Kanagawa (JP) for kioxia corporation, Kiyotaka IWASAKI of Yokohama Kanagawa (JP) for kioxia corporation, Takashi TAKEMOTO of Yokohama Kanagawa (JP) for kioxia corporation, Kohei OIKAWA of Kawasaki Kanagawa (JP) for kioxia corporation
IPC Code(s): G06F3/06
Abstract: a memory system includes a non-volatile memory and a controller. the controller is configured to perform a write operation of a first data cluster and a first partial overwrite operation of the first data cluster with first overwrite data. the write operation includes compressing and then encrypting the first data cluster, and writing the compressed and encrypted first data cluster into a first physical location of the non-volatile memory. the first partial overwrite operation includes encrypting the first overwrite data without performing compression, reading the compressed and encrypted first data cluster from the first physical location of the non-volatile memory, generating a first composite data cluster with the compressed and encrypted first data cluster read from the first physical location and the encrypted first overwrite data that is not compressed, and writing the first composite data cluster into a second physical location of the non-volatile memory.
20240094941.Memory system_simplified_abstract_(kioxia corporation)
Inventor(s): Kensuke YAMAMOTO of Yokohama Kanagawa (JP) for kioxia corporation
IPC Code(s): G06F3/06, G06F13/16, G11C7/10, G11C7/22
Abstract: a semiconductor memory device includes a memory cell storing data; a signal pad inputting write data to the memory cell and from which read data read from the memory cell is output to an external controller; a first control pad receiving a first timing control signal from the external controller; and a second control pad outputting a second timing control signal to the external controller. in a first time period after a data out command is received, dummy data are output from the signal pad while the second timing control signal from the second control pad is toggling in response to toggling of the first timing control signal input to the first control pad. in a second time period after the first time period, read data are output from the signal pad while the second timing control signal is toggling in response to toggling of the first timing control signal.
20240094946.MEMORY SYSTEM_simplified_abstract_(kioxia corporation)
Inventor(s): Toru Katagiri of Sagamihara Kanagawa (JP) for kioxia corporation
IPC Code(s): G06F3/06
Abstract: according to one embodiment, a controller of a memory system receives, from a host, a first read command that specifies a first logical address and a data pointer, the first logical address corresponding to first data stored in the nonvolatile memory, the data pointer indicating a first data buffer of a memory of the host to which the first data is to be transferred. the controller performs read access to the first data buffer of the memory of the host, based on the data pointer specified by the first read command.
20240094947.MEMORY SYSTEM_simplified_abstract_(kioxia corporation)
Inventor(s): Atsuo SHONO of Kamakura (JP) for kioxia corporation, Kiyotaka IWASAKI of Yokohama (JP) for kioxia corporation
IPC Code(s): G06F3/06
Abstract: according to one embodiment, a system includes: a memory, and a controller, wherein the memory includes a first die including first and second planes and a second die including a third plane, and the controller issues a read command to the first and second dies, if a read time for first data in the first plane has ended, a read time for second data in the second plane has ended after the end of the read time for the first data, and a read time for third data in the third plane has ended after the end of the read time for the second data, receives the first data from the first die, receives the third data from the second die after completion of receiving the first data, and receives the second data from the first die after completion of receiving the third data.
20240094955.MEMORY SYSTEM_simplified_abstract_(kioxia corporation)
Inventor(s): Shinichi MATSUKAWA of Shinagawa Tokyo (JP) for kioxia corporation
IPC Code(s): G06F3/06
Abstract: a memory system includes a non-volatile memory and a memory controller. the memory controller is configured to perform write, read, and erase operations in accordance with write commands, read commands, and erase commands, respectively, from a host, and receive, from the host, time information indicating times when the write, read, and erase commands have been transmitted from or issued by the host. the memory controller is further configured to generate, from the received time information, history data including a value representing a busy state of the memory system with respect to each time range in a predetermined time period, and perform a maintenance operation with respect to the non-volatile memory upon time at which a command received from the host has been transmitted from or issued by the host falling in one or more of the time ranges corresponding to values smaller than the other of the time ranges.
20240094957.MEMORY SYSTEM_simplified_abstract_(kioxia corporation)
Inventor(s): Marie TAKADA of Yokohama (JP) for kioxia corporation, Masanobu SHIRAKAWA of Chigasaki (JP) for kioxia corporation, Tsukasa TOKUTOMI of Kamakura (JP) for kioxia corporation
IPC Code(s): G06F3/06, G06F11/10, G11C16/04, G11C16/08, G11C16/10, G11C16/16, G11C16/26, G11C29/52
Abstract: according to one embodiment, a memory system includes a semiconductor memory and a controller. the memory system is capable of executing a first operation and a second operation. in the first operation, the controller issues a first command sequence, the semiconductor memory applies a first voltage to a first word line and applies a second voltage to a second word line to read data from the first memory, and the read data is transmitted to the controller from the semiconductor memory. in the second operation, the controller issues a second command sequence, the semiconductor memory applies a third voltage to the first word line and applies a fourth voltage to the second word line, and data held in the memory cell array is left untransmitted to the controller.
20240094959.SEMICONDUCTOR MEMORY DEVICE_simplified_abstract_(kioxia corporation)
Inventor(s): Akio SUGAHARA of Yokohama (JP) for kioxia corporation, Zhao LU of Ebina (JP) for kioxia corporation, Takehisa KUROSAWA of Yokohama (JP) for kioxia corporation, Yuji NAGAI of Sagamihara (JP) for kioxia corporation
IPC Code(s): G06F3/06, G11C16/04, G11C16/26
Abstract: a semiconductor memory device comprises: a first pad receiving a first signal; a second pad receiving a second signal; a first memory cell array; a first sense amplifier connected to the first memory cell array; a first data register connected to the first sense amplifier and configured to store user data read from the first memory cell array; and a control circuit configured to execute an operation targeting the first memory cell array. the first memory cell array comprises a plurality of first memory strings. the first memory strings each comprise a plurality of first memory cell transistors. in a first mode of this semiconductor memory device, a command set instructing the operation is inputted via the first pad. in a second mode of this semiconductor memory device, the command set is inputted via the second pad.
20240095112.MEMORY SYSTEM AND METHOD_simplified_abstract_(kioxia corporation)
Inventor(s): Marie TAKADA of Yokohama Kanagawa (JP) for kioxia corporation, Masanobu SHIRAKAWA of Chigasaki Kanagawa (JP) for kioxia corporation, Naomi TAKEDA of Yokohama Kanagawa (JP) for kioxia corporation
IPC Code(s): G06F11/07, G06F12/02
Abstract: according to an embodiment, a controller acquires a first temperature detection value and executes an acquisition operation on a first storage area. the controller converts a first voltage value into a second voltage value representing the read voltage in a temperature set value based on the first temperature detection value and records the second voltage value. the acquisition operation is an operation of determining, by using the read voltages, whether memory cells are on or off and acquiring the first voltage value representing the read voltage for suppressing error bits. after that, the controller acquires a second temperature detection value and converts the second voltage value into a third voltage value representing the read voltage in the second temperature detection value. the controller reads data from the memory cells by using, as the read voltage, a voltage indicated by the third voltage value.
Inventor(s): Katsuyuki SHIMADA of Ota Tokyo (JP) for kioxia corporation, Yuki KOMATSU of Yokohama Kanagawa (JP) for kioxia corporation
IPC Code(s): G06F12/02, G06N3/0455, G11C16/04, G11C16/10
Abstract: according to one embodiment, a memory controller includes a compression unit that compresses two or more determination voltage values for threshold voltages of a memory cell to a vector quantity, the memory cell being capable of storing three or more data values. the memory controller further includes a storing unit that stores the vector quantity into a memory region. the memory controller further includes a decompression unit that decompresses the stored vector quantity to provide the determination voltage values.
Inventor(s): Shinichi KANNO of Ota (JP) for kioxia corporation, Aurelien Nam Phong TRAN of Yokohama (JP) for kioxia corporation, Yuki SASAKI of Zhubei City (TW) for kioxia corporation
IPC Code(s): G06F12/02, G06F12/1027
Abstract: according to one embodiment, in response to restoration of power to a memory system, a controller in the memory system notifies a host that the memory system is ready. when an input/output command specifying a logical address belonging to a logical address range is received, the controller selects a block corresponding to the logical address range and rebuilds, based on address translation information and an update log which are stored in the selected block, the latest address translation information corresponding to the logical address range. the controller updates the rebuilt latest address translation information, based on a list of logical addresses corresponding to lost write data, stored in the selected block.
20240095182.MEMORY SYSTEM AND CONTROL METHOD_simplified_abstract_(kioxia corporation)
Inventor(s): Mitsunori TADOKORO of Fujisawa Kanagawa (JP) for kioxia corporation
IPC Code(s): G06F12/1009
Abstract: a controller assigns, for each namespace, one logical area of a logical address space as a first logical area including a last logical address of the namespace and assigns one or more of logical areas as second logical areas. the controller divides a memory region in which an address translation table is stored into buffer regions. for each second logical area, the controller assigns one buffer region for storing map segments corresponding to the second logical area, and manages a first pointer indicating a storage location of the buffer region assigned thereto. the controller also assigns one buffer region for map segments corresponding to the first logical areas of two or more namespaces, and manages second pointers respectively indicating storage locations in the one buffer region, in which the map segments corresponding to the first logical areas of the two or more namespaces are respectively stored.
20240095192.MEMORY SYSTEM, CONTROL DEVICE, AND METHOD_simplified_abstract_(kioxia corporation)
Inventor(s): Goichi OOTOMO of Kawasaki Kanagawa (JP) for kioxia corporation
IPC Code(s): G06F13/16, G06F11/10
Abstract: according to one embodiment, a memory system includes a semiconductor memory device and a control device. the memory system includes a first device and first channels. the first channels are each connected to one or more second devices. the control device is connected to the first device via a second channel. the control device includes first circuits and a second circuit. the first circuits each execute data transfer to the second device as an access destination. the second circuit is provided between the first circuits and the second channel. the second circuit combines data from the first circuits and transfers the combined data to the second channel at a transfer rate higher than that of pre-combining data. the second circuit divides data received via the second channel and distributes pieces of divided data to the first circuits at a transfer rate lower than that of pre-dividing data.
20240095193.MEMORY SYSTEM, METHOD, AND CONTROL CIRCUIT_simplified_abstract_(kioxia corporation)
Inventor(s): Tomoaki SUZUKI of Chigasaki (JP) for kioxia corporation
IPC Code(s): G06F13/16
Abstract: according to one embodiment, a semiconductor memory device includes a first circuit, multiple second circuits, and a first number of first channels connected to the first circuit. one or more second circuits are connected to each first channel. the control circuit is connected to the semiconductor memory device via a second channel. the control circuit generates multiple first access requests each for one of the second circuits. the control circuit determines order of execution of the first access requests to allow concurrent execution of a second number of first access requests designating two or more of the second circuits connected to different first channels. the control circuit executes in parallel the second number of data transfers responsive to the second number of first access requests via the second channel at a transfer rate the second number of times a transfer rate of one of the first number of first channels.
20240095244.METHOD AND INFORMATION PROCESSING DEVICE_simplified_abstract_(kioxia corporation)
Inventor(s): Daisuke MIYASHITA of Kawasaki (JP) for kioxia corporation, Taiga IKEDA of Kawasaki (JP) for kioxia corporation, Jun DEGUCHI of Kawasaki (JP) for kioxia corporation
IPC Code(s): G06F16/2455, G06F16/2453, G06N3/08
Abstract: according to an embodiment, a method includes receiving a query, and selecting one of first objects on the basis of the query and a neural network model. each of the first objects is associated with one or more pieces of first data in a group of first data stored on a first memory. the method further includes calculating a metric of a distance between the query and one or more pieces of second data. the one or more pieces of second data are one or more pieces of first data associated with a second object. the second object is the one of the first objects having been selected. the method further includes identifying third data on the basis of the metric of the distance. the third data is first data closest to the query in the group of the first data.
Inventor(s): Osamu TORII of Minato Tokyo (JP) for kioxia corporation, Shinichiro MANABE of Yokohama Kanagawa (JP) for kioxia corporation
IPC Code(s): G06F17/18
Abstract: an information processing apparatus comprising processing circuitry. the processing circuitry is configured to acquire objective variables and explanatory variables which are regression analysis targets, extract a plurality of first explanatory variables having a high degree of influence on the objective variable from among the explanatory variables by sparse modeling using a first regression equation, and extract a second explanatory variable having a high degree of influence on the plurality of first explanatory variables by sparse modeling using a second regression equation.
Inventor(s): Shinichi Ikeda of Fujisawa Kanagawa (JP) for kioxia corporation, Shinya Kawakami of Yokohama Kanagawa (JP) for kioxia corporation
IPC Code(s): G11C7/10, G06F13/16, H04L25/03
Abstract: according to one embodiment, a semiconductor integrated circuit includes an equalizer circuit and a toggle detection circuit. the equalizer circuit is configured to amplify an input signal that are externally input to output an amplified signal as a first signal. the toggle detection circuit is configured to detect toggling of the first signal and to dynamically switch a gain of the equalizer circuit based on whether or not toggling of the first signal is detected.
20240096385.MEMORY SYSTEM AND CONTROL METHOD_simplified_abstract_(kioxia corporation)
Inventor(s): Mariko MATSUMOTO of Kawasaki Kanagawa (JP) for kioxia corporation
IPC Code(s): G11C7/22, G06F13/42, G11C7/20
Abstract: a memory system includes a memory, a control circuit, and an interface circuit. the interface circuit includes a first terminal capable of receiving a first clock supplied from an outside, and a second terminal capable of receiving a first signal. when in a first state, the control circuit transitions to a second state in response to input of a first signal, and to a third state in response to input of the first clock. when in the second state, the control circuit executes initialization processing of a first mode for an operation based on an internally generated second clock or is in an operable state in the first mode, and ends the operable state in the first mode in response to input of the first clock and transitions to the third state. when in the third state, the control circuit transitions to a fourth state in response to input of the first signal. when in the fourth state, the control circuit executes initialization processing of a second mode for an operation based on the first clock or is in an operable state in the second mode.
Inventor(s): Kunifumi SUZUKI of Yokkaichi Mie (JP) for kioxia corporation, Yuuichi KAMIMUTA of Nagoya Aichi (JP) for kioxia corporation
IPC Code(s): G11C11/22, G11C16/04, H01L21/28, H01L29/51, H01L29/66, H01L29/78, H10B51/10, H10B51/20, H10B51/30
Abstract: a memory cell includes: a core structure extending in a first direction orthogonal to a semiconductor substrate; a semiconductor layer extending in the first direction and in contact with the core structure; an insulating layer extending in the first direction and in contact with the semiconductor layer; a ferroelectric layer extending in the first direction and in contact with the insulating layer; a first electrode extending in a second direction orthogonal to the first direction and in contact with the ferroelectric layer; a second electrode adjacent to the first electrode in the first direction, extending in the second direction, and in contact with the ferroelectric layer; an insulating layer stacked in the first direction and disposed between the first and second electrodes; and an antiferroelectric layer disposed between the first and second electrodes, and in contact with the insulating layer and the ferroelectric layer.
20240096413.SEMICONDUCTOR MEMORY DEVICE_simplified_abstract_(kioxia corporation)
Inventor(s): Natsuki SAKAGUCHI of Chiyoda Tokyo (JP) for kioxia corporation, Takashi MAEDA of Kamakura Kanagawa (JP) for kioxia corporation, Rieko FUNATSUKI of Yokohama Kanagawa (JP) for kioxia corporation, Hidehiro SHIGA of Yokohama Kanagawa (JP) for kioxia corporation
IPC Code(s): G11C16/04, G11C7/06, G11C16/24
Abstract: a control circuit of a semiconductor memory device performs a write operation on a memory cell transistor of the semiconductor memory device by performing a first pulse application operation of lowering a threshold voltage of the memory cell transistor, a precharge operation, and then a second pulse application operation. in the precharge operation, in a state in which first and second select transistors connected to the memory cell transistor are turned on, a bit line connected to the memory cell transistor is charged by applying a ground voltage to a word line connected to a gate of the memory cell transistor and applying a voltage higher than the ground voltage to a source line. in the second pulse application operation, in a state in which the first select transistor is turned on and the second select transistor is turned off, a program voltage is applied to the word line.
20240096416.SEMICONDUCTOR MEMORY DEVICE_simplified_abstract_(kioxia corporation)
Inventor(s): Kohei DATE of Yokkaichi (JP) for kioxia corporation, Keisuke SUDA of Yokkaichi (JP) for kioxia corporation
IPC Code(s): G11C16/04, H01L23/528, H10B41/10, H10B41/27, H10B41/35, H10B43/10, H10B43/27, H10B43/35
Abstract: according to one embodiment, a semiconductor memory device includes: stacked interconnects including a first interconnect layer and a second interconnect layer, the first interconnect layer including a first area and a second area arranged in a first direction, the second interconnect layer being arranged above the first interconnect layer in a second direction intersecting the first direction, the second interconnect layer not including the first area and including the second area; a first memory pillar arranged in the first area and passing through the first interconnect layer in the second direction; and a second memory pillar arranged in the second area and passing through the first interconnect layer and the second interconnect layer in the second direction.
20240096417.SEMICONDUCTOR STORAGE DEVICE_simplified_abstract_(kioxia corporation)
Inventor(s): Hiroshi MAEJIMA of Setagaya Tokyo (JP) for kioxia corporation, Katsuaki ISOBE of Yokohama Kanagawa (JP) for kioxia corporation, Keita KIMURA of Fujisawa Kanagawa (JP) for kioxia corporation
IPC Code(s): G11C16/04, G11C5/06, G11C16/14, G11C16/26
Abstract: in one embodiment, a semiconductor storage device includes a string that has one end electrically connected to a bit line, and another end electrically connected to a source line, and includes a plurality of memory cells. an operation of writing data to each of a plurality of adjacent first memory cells among the plurality of memory cells is sequentially performed in a direction from a first memory cell on a side of the source line to a first memory cell on a side of the bit line. an operation of reading data from each of the plurality of adjacent first memory cells is performed to allow a current to flow through the string in a first direction from the source line to the bit line.
Inventor(s): Satoshi NAGASHIMA of Yokkaichi Mie (JP) for kioxia corporation
IPC Code(s): G11C16/04, H10B41/10, H10B41/27, H10B41/35, H10B43/10, H10B43/27, H10B43/35
Abstract: a semiconductor memory device includes a first stacked body, a second stacked body, an interposed portion, and a columnar body. the interposed portion is disposed between the first stacked body and the second stacked body. the columnar body includes a first columnar portion extending in a first direction inside the first stacked body, a second columnar portion extending in the first direction inside the second stacked body, and a connection portion disposed in the interposed portion and connecting the first columnar portion to the second columnar portion. at least part of the interposed portion has a first layer containing a first insulating material, a second layer disposed between the first layer and the second stacked body in the first direction and containing the first insulating material, and a third layer disposed between the first layer and the second layer in the first direction and containing a first material different from the first insulating material.
20240096419.SEMICONDUCTOR MEMORY DEVICE_simplified_abstract_(kioxia corporation)
Inventor(s): Hiroshi MAEJIMA of Setagaya Tokyo (JP) for kioxia corporation
IPC Code(s): G11C16/04, G11C16/08, G11C16/24, G11C16/26, G11C16/28, G11C16/34
Abstract: a semiconductor memory device includes a memory cell array having memory strings that include memory cells and first and second selection transistors. during a read operation, a controller applies a first voltage higher than ground to a source line, and a second voltage to a first and second selection gate lines that are connected to a selected memory string. the second voltage is also applied to the first selection gate lines connected to non-selected memory strings during a first period of the read operation. a third voltage higher than ground and lower than the second voltage is applied to the first selection gate lines connected to non-selected memory strings during a second period of the read operation subsequent to the first period.
20240096422.STORAGE DEVICE_simplified_abstract_(kioxia corporation)
Inventor(s): Hiroaki KOSAKO of Yokkaichi Mie (JP) for kioxia corporation, Kota NISHIKAWA of Zama Kanagawa (JP) for kioxia corporation, Kenrou KIKUCHI of Fujisawa Kanagawa (JP) for kioxia corporation
IPC Code(s): G11C16/16, G11C16/04, G11C16/34
Abstract: a first select transistor is connected to a first wiring. a first memory cell transistor and a second memory cell transistor are connected in series between the first select transistor and a second select transistor. a first word line is connected to the first memory cell transistor. a second word line is connected to the second memory cell transistor. during a first period in which the first voltage is applied to the first wiring, a second voltage lower than a first voltage is applied in parallel to the first word line and the second word line. during a second period in which a third voltage higher than the first voltage is applied to the first wiring, the second voltage is applied to the first word line, and a fourth voltage higher than the second voltage and lower than the third voltage is applied to the second word line. during a third period in which the third voltage is applied to the first wiring, the fourth voltage is applied to the first word line, and the second voltage is applied to the second word line.
20240096423.MEMORY SYSTEM_simplified_abstract_(kioxia corporation)
Inventor(s): Dongxiao YU of Adachi Tokyo (JP) for kioxia corporation, Masahiro KIYOOKA of Yokohama Kanagawa (JP) for kioxia corporation, Suguru NISHIKAWA of Kita Tokyo (JP) for kioxia corporation, Yoshihisa KOJIMA of Kawasaki Kanagawa (JP) for kioxia corporation
IPC Code(s): G11C16/26, G11C16/08, G11C16/34
Abstract: a memory system includes a semiconductor memory that includes a cell unit having a plurality of memory cells, and a control circuit for controlling the plurality of memory cells, and a memory controller configured to control the semiconductor memory. the control circuit is configured to execute a data read operation on the cell unit by using one or more read voltages, acquire first data by the data read operation, generate second data with a data size smaller than the first data, based on the first data, and transmit the second data to the memory controller. the memory controller is configured to determine, based on the second data, whether or not to rewrite the page data written in the cell unit.
20240096424.MEMORY DEVICE_simplified_abstract_(kioxia corporation)
Inventor(s): Takuya FUTATSUYAMA of Yokohama Kanagawa (JP) for kioxia corporation, Kenichi ABE of Kawasaki Kanagawa (JP) for kioxia corporation
IPC Code(s): G11C16/26, G11C16/04, G11C16/08, G11C16/10, H10B41/27, H10B41/35
Abstract: a memory device includes a semiconductor column extending above a substrate, a first conductive layer on a first side of the semiconductor column, a second conductive layer on a second side of the semiconductor column, opposite to the first conductive layer, a third conductive layer above or below the first conductive layer and on the first side of the semiconductor column, a fourth conductive layer on the second side of the semiconductor column, opposite to the third conductive layer, and a bit line connected to the semiconductor column. during reading in which a positive voltage is applied to the bit line, first, second, third, and fourth voltages applied to the first, second, third, and fourth conductive layers, respectively, wherein the first voltage and the third voltage are higher than each of the second voltage and the fourth voltage, and the third voltage is higher than the first voltage.
20240096426.SEMICONDUCTOR STORAGE DEVICE_simplified_abstract_(kioxia corporation)
Inventor(s): Katsuaki SAKURAI of Yokohama Kanagawa (JP) for kioxia corporation, Tooru TATEGAMI of Kawasaki Kanagawa (JP) for kioxia corporation
IPC Code(s): G11C16/30, G11C16/08
Abstract: a semiconductor storage device includes a first region including a level shifter, a second region including a level shifter, a power input pad, and an internal power generation circuit configured to generate an internal power supply voltage using a first power supply voltage supplied through the power input pad and supply the internal power supply voltage to the first and second regions. the internal power generation circuit separately transmits a first signal to the level shifter of the first region for triggering a start of a first operation of the first region and a second signal to the level shifter of the second region for triggering a start of a second operation of the second region.
20240096429.SEMICONDUCTOR STORAGE DEVICE_simplified_abstract_(kioxia corporation)
Inventor(s): Shingo NAKAZAWA of Kamakura Kanagawa (JP) for kioxia corporation, Yuki INUZUKA of Yokohama Kanagawa (JP) for kioxia corporation
IPC Code(s): G11C16/34, G11C11/56, G11C16/04, G11C16/08, G11C16/26
Abstract: a semiconductor storage device includes a first word line, a second word line, a first select gate line, a second select gate line, a third select gate line, a fourth select gate line, a first memory pillar including a first memory cell connected to the first word line, a first select transistor connected to the first select gate line, a second memory cell connected to the second word line, and a second select transistor connected to the second select gate line, and a logic control circuit configured to perform a read operation to read threshold voltages of the first and second memory cells, respectively. the logic control circuit independently controls the first to fourth select gate lines during the read operation to turn the select transistors electrically connected to memory cells other than the memory cell to be read to off state.
20240096430.SEMICONDUCTOR STORAGE DEVICE_simplified_abstract_(kioxia corporation)
Inventor(s): Hiroki DATE of Chigasaki Kanagawa (JP) for kioxia corporation
IPC Code(s): G11C16/34, G11C16/08, G11C16/26
Abstract: in one embodiment, a semiconductor storage device includes memory cell transistors, and a word line electrically connected to the memory cell transistors. the device further includes a voltage generator configured to generate a first voltage transferred to the word line, the voltage generator including a voltage divider configured to divide the first voltage with first and second resistance elements, the first or second resistance element being a variable resistance element that receives a first digital signal indicating a resistance value and is changeable to the resistance value. the device further includes a control unit configured to output the first digital signal, wherein the control unit outputs the first digital signal such that a theoretical waveform of the first voltage in boosting the first voltage in an erasing verifying operation is different from a theoretical waveform of the first voltage in boosting the first voltage in a reading operation.
20240096515.IMAGING DEVICE AND IMAGE GENERATION METHOD_simplified_abstract_(kioxia corporation)
Inventor(s): Takeshi YAMANE of Tsukuba Ibaraki (JP) for kioxia corporation
IPC Code(s): G21K7/00, G02B21/06, G02B21/26, G02B21/36
Abstract: an imaging device includes an image processor configured to: i) determine that a detection intensity distribution indicating detection intensity with respect to position coordinates of a stage is a convolution of an image intensity distribution on an extension line of a linear pixel and a window function; (ii) calculate an image intensity distribution for each linear pixel by deconvolution from the detection intensity distribution; and (iii) generate an image of the subject by disposing the image intensity distribution calculated in all the linear pixels in an arrangement direction of the linear pixels.
Inventor(s): Toshiyuki SASAKI of Yokkaichi Mie (JP) for kioxia corporation
IPC Code(s): H01J37/32, H01L21/311
Abstract: a plasma processing device includes a chamber, a plurality of direct current power supplies, and a controller. the direct current power supplies are provided in an upper portion and on a side wall of the chamber, wherein the direct current power supplies are configured to operate individually. the controller is configured to control the direct current power supplies such that the direct current power supplies apply respective direct current voltages independent of each other.
Inventor(s): Takeharu MOTOKAWA of Zushi Kanagawa (JP) for kioxia corporation, Noriko SAKURAI of Yokohama Kanagawa (JP) for kioxia corporation, Hideaki SAKURAI of Kawasaki Kanagawa (JP) for kioxia corporation
IPC Code(s): H01J37/32, C01B32/05, G03F1/58, G03F1/80
Abstract: a target processing method includes: importing a target into a processing chamber; forming a film including carbon on the target using at least one of first ion including carbon and a first plasma including carbon; and removing the film by a reaction between a second plasma and the film, wherein the forming of the film and the removing of the film are alternately performed a number of times in the processing chamber without removing the target from the processing chamber.
Inventor(s): Shohei ARAKAWA of Mie Mie (JP) for kioxia corporation, Yuta OSADA of Yokkaichi Mie (JP) for kioxia corporation
IPC Code(s): H01J37/32, H01L21/3213, H01L21/683, H01L21/687
Abstract: a semiconductor manufacturing apparatus includes: a chamber including a top plate; a holder provided in the chamber and configured to place a substrate; a high-frequency power source configured to apply high-frequency power to the holder; a gas supply pipe configured to supply a gas to the chamber; a gas discharge pipe configured to discharge a gas from the chamber; and a plurality of lift pins configured to move the substrate in a direction away from the holder to the top plate, which allows tip ends of the lift pins to move from an upper surface of the holder to a position with a first distance, wherein the first distance is equal to or greater than about 70% of a second distance between the upper surface of the holder and the top plate.
20240096626.METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE_simplified_abstract_(kioxia corporation)
Inventor(s): Toshiyuki SASAKI of Yokkaichi Mie (JP) for kioxia corporation
IPC Code(s): H01L21/033, H01L21/311
Abstract: a method for manufacturing a semiconductor device includes forming, on a to-be-processed film above an underlying film, a mask material containing a first metal and comprising a first mask layer which is provided on the to-be-processed film and whose content of the first metal is lower than a first predetermined percentage, and a second mask layer which is provided on the first mask layer and whose content of the first metal is equal to or higher than the first predetermined percentage. the manufacturing method includes patterning the mask material. the manufacturing method includes processing the to-be-processed film using the mask material as a mask. the processing of the to-be-processed film includes performing a first treatment to process the to-be-processed film at a first temperature in an atmosphere of a first gas. the processing of the to-be-processed film includes performing a second treatment to process the to-be-processed film at a second temperature higher than the first temperature in an atmosphere of a second gas different from the first gas.
Inventor(s): Koki UEHA of Yokkaichi Mie (JP) for kioxia corporation, Katsuyoshi KODERA of Yokohama Kanagawa (JP) for kioxia corporation
IPC Code(s): H01L21/3213, G03F7/00, H01L21/768
Abstract: according to one embodiment, a pattern forming method uses a template having a first region with a first recessed portion and a second region adjacent to the first region. the second region has a second recessed portion therein. the recessed portions satisfy a specific relationship (d>2(h+h)/�), where dis a shortest distance between the first and second recessed portions, his a depth of the first recessed portion, and his a depth of the second recessed portion. the pattern forming method includes placing an imprint material on an object and pressing the template against the material to mold the imprint material. the molded imprint material is then cured, and the template removed.
Inventor(s): Mana TANABE of Setagaya Tokyo (JP) for kioxia corporation, Kaori UMEZAWA of Fujisawa Kanagawa (JP) for kioxia corporation, Kosuke TAKAI of Yokohama Kanagawa (JP) for kioxia corporation
IPC Code(s): H01L21/67, H01L21/687
Abstract: according to an embodiment, a substrate processing method includes forming a liquid film on a substrate including a first region provided with a first film on an outermost surface thereof and a second region provided with a second film on an outermost surface thereof, the first film and the second film being different from each other in material. the method further includes forming a solidified film by solidifying the liquid film. the method further includes causing the solidified film on the first region to melt prior to the solidified film on the second region.
Inventor(s): Fuyuma ITO of Yokkaichi Mie (JP) for kioxia corporation, Jun TAKAGI of Yokkaichi Mie (JP) for kioxia corporation, Ai MORI of Yokkaichi Mie (JP) for kioxia corporation, Yosuke MARUYAMA of Yokkaichi Mie (JP) for kioxia corporation, Yuya AKEBOSHI of Yokkaichi Mie (JP) for kioxia corporation, Takashi WATANABE of Yokkaichi Mie (JP) for kioxia corporation, Hiroyasu IIMORI of Nagoya Aichi (JP) for kioxia corporation
IPC Code(s): H01L21/67, H01L21/311, H01L21/3213
Abstract: a substrate processing apparatus includes: a plurality of roller pairs configured to place a plurality of substrates, respectively, wherein the substrates are arranged side by side in a horizontal direction with a predetermined interval, and rotate the plurality of substrates, respectively, in a circumferential direction; a first, second, and third circulation groove that are disposed along outer peripheral portions of each of the plurality of substrates; a chemical solution supplier configured to supply a chemical solution to the outer peripheral portions of the plurality of substrates through the first circulation groove; a rinse solution supplier configured to supply a rinse solution to the outer peripheral portions of the plurality of substrates through the second circulation groove; and a fluid supplier configured to supply a fluid for drying the rinse solution to the outer peripheral portions of the plurality of substrates through the third circulation groove.
Inventor(s): Fumiki AISO of Nagoya Aichi (JP) for kioxia corporation
IPC Code(s): H01L21/673, C23C16/455, C23C16/458
Abstract: a substrate processing apparatus according to an embodiment includes a boat capable of accommodating a plurality of substrates taken out from a storage container, a reactor capable of housing the boat and processing the plurality of substrates, and first and second arms that transfer the plurality of substrates. the boat accommodates the substrates in a first direction intersecting surfaces of the substrates. the first arm holds both ends of one substrate in a second direction intersecting the first direction, and is capable of transferring the one substrate between the storage container and the second arm. the second arm has a first holder that can support two substrates in a third direction intersecting the first and second directions, and is capable of transferring the two substrates between the first arm and the boat.
Inventor(s): Takuro OKUBO of Yokkaichi Mie (JP) for kioxia corporation, Hidekazu HAYASHI of Yokkaichi Mie (JP) for kioxia corporation
IPC Code(s): H01L21/683, B23K26/073, B23K26/08, B23K26/18, H01L23/00
Abstract: a processing apparatus using laser according to an embodiment includes a stage configured to hold a substrate and rotate, and a laser irradiation apparatus capable of moving in a radial direction of the rotation. the laser irradiation apparatus includes a control unit configured to control an output of an infrared pulsed laser so that l1/l2 satisfies 1.2 or more and 10 or less when a distance between laser spots adjacent to each other in a rotation direction of the stage is l1 and a distance between laser spots adjacent to each other in the radial direction of the rotation is l2.
Inventor(s): Shingo HONDA of Yokkaichi Mie (JP) for kioxia corporation
IPC Code(s): H01L21/768, H01L23/522, H10B69/00
Abstract: a semiconductor device includes a first layer including a first recess portion on an upper surface; and a second recess portion that extends from a bottom surface of the first recess portion in the first layer, and the second recess portion has a tapered shape in which a width in a first direction along a surface direction of the first layer reduces from the bottom surface of the first recess portion in a depth direction of the first layer.
Inventor(s): Kotaro FUJII of Yokkaichi (JP) for kioxia corporation
IPC Code(s): H01L23/528, H01L23/522, H10B41/10, H10B41/27, H10B41/35, H10B43/10, H10B43/27, H10B43/35
Abstract: a semiconductor storage device according to an embodiment includes a first wiring, a second wiring, a first insulating layer, a first insulator, and a conductor. the first insulating layer has a first portion, a second portion, and a third portion. the first portion is stacked on the first wiring. the second portion is stacked on the second wiring. the third portion is on the opposite side of the first wiring and the second wiring with respect to the first portion and the second portion.
20240096821.SEMICONDUCTOR STORAGE DEVICE_simplified_abstract_(kioxia corporation)
Inventor(s): Kenta SASAKI of Mie Mie (JP) for kioxia corporation
IPC Code(s): H01L23/00, H01L23/528, H01L25/065, H10B43/10, H10B43/20, H10B43/35, H10B43/40, H10B80/00
Abstract: according to one embodiment, a semiconductor storage device includes a first chip with a substrate and a second chip. the second chip has a memory cell array with wiring layers spaced apart from each other in a first direction and a memory pillar that penetrates the wiring layers in the first direction. connection pads are in a boundary between the first and second chips. contacts extend in the first direction from the connection pads. an insulator layer surrounds the contacts in a plane parallel to the substrate. a first member is adjacent to the insulator layer in the plane. the insulator layer separates the first member from the first contacts, and the first member has a stress value different from a stress value of the first insulator layer.
Inventor(s): Yuya OMURA of Yokkaichi Mie (JP) for kioxia corporation
IPC Code(s): H01L27/06, H01L29/94
Abstract: according to one embodiment, transistors and a resistance-capacitance element are provided. the transistors each have a gate insulating film with a gate dielectric film and a gate electrode of a metal material. the resistance-capacitance element is provided by stacking a first insulating film, a first conductive layer, a stopper insulating film, a second insulating film, and a second conductive layer on an upper surface of a semiconductor substrate. the second insulating film includes the gate dielectric film like the gate insulating film. the second conductive layer is made of the same metal material as the gate electrode. the first conductive layer is a conductive material having a higher resistance than the second conductive layer.
Inventor(s): Tomoyuki FUNABASAMA of Yokkaichi Mie (JP) for kioxia corporation
IPC Code(s): H01L29/786, H01L29/66, H10B41/35, H10B43/35
Abstract: a semiconductor device is provided with a substrate, a first transistor, and a second transistor. the first transistor has a first diffusion layer region, a second diffusion layer region, a first gate insulating film, a first gate electrode, and a first silicide layer. the first silicide layer is provided on the first diffusion layer region and the second diffusion layer region. the second transistor has a third diffusion layer region, a fourth diffusion layer region, a second gate insulating film, a second gate electrode, and a second silicide layer. the second silicide layer is provided on the third diffusion layer region and the fourth diffusion layer region. a distance between the first silicide layer and the first gate insulating film is larger than a distance between the second silicide layer and the second gate insulating film.
20240097044.SEMICONDUCTOR DEVICE_simplified_abstract_(kioxia corporation)
Inventor(s): Yusuke KASAHARA of Yokkaichi Mie (JP) for kioxia corporation, Kappei IMAMURA of Kuwana Mie (JP) for kioxia corporation, Akifumi GAWASE of Kuwana Mie (JP) for kioxia corporation, Shinji MORI of Nagoya Aichi (JP) for kioxia corporation, Akihiro KAJITA of Yokkaichi Mie (JP) for kioxia corporation
IPC Code(s): H01L29/786, H01L29/417, H10B12/00
Abstract: according to one embodiment, a semiconductor device includes a first conductive layer between first and second insulating layers with an oxide semiconductor column extending in the first direction through these layers. a third insulating layer covers the column. the column has a first semiconductor portion at a first position matching the first insulating layer, a second semiconductor portion at a second position matching second insulating layer, and a third semiconductor portion at a third position matching the first conductive layer. the first semiconductor portion is continuous along a second direction between the third insulating layer, the second semiconductor portion is continuous along the second direction between the third insulating layer, but the third semiconductor portion is not continuous between the third insulating layer.
20240097561.POWER SUPPLY DEVICE AND SEMICONDUCTOR DEVICE_simplified_abstract_(kioxia corporation)
Inventor(s): Takayuki TSUKAMOTO of Yokohama Kanagawa (JP) for kioxia corporation
IPC Code(s): H02M1/36, H02M3/155
Abstract: a power supply device includes a switching circuit and first and second control circuits. the switching circuit is between a regulator circuit and a terminal and is configured to transition between a first state in which a second power supply voltage is supplied to the terminal and a second state in which supply of the second power supply voltage to the terminal is cut off. the first control circuit is configured to output a reset signal that is set to a first voltage or a second voltage. the second control circuit is configured to be driven by the second power supply voltage and to perform control so that the switching circuit transitions to the first or second state when the reset signal is at the first voltage. the switching circuit is configured to switch to the second state when the reset signal is set to the second voltage.
20240097570.MEMORY SYSTEM AND POWER CONTROL CIRCUIT_simplified_abstract_(kioxia corporation)
Inventor(s): Hajime MATSUMOTO of Higashimurayama (JP) for kioxia corporation
IPC Code(s): H02M3/20, G06F13/42, H02M3/157
Abstract: according to one embodiment, a memory system connectable to a host includes a nonvolatile memory, a controller, and a power control circuit. the controller controls the nonvolatile memory. the power control circuit controls power to be supplied to the controller and the nonvolatile memory and includes one or more dc/dc converters. the nonvolatile memory and the controller include one or more circuit blocks. each of the one or more dc/dc converters supplies an internal power supply voltage to one of the one or more circuit blocks. a first dc/dc converter of the one or more dc/dc converters transitions to a forced pulse width modulation mode in response to the memory system that has transitioned from a low power consumption mode to a normal operation mode.
20240097658.SEMICONDUCTOR DEVICE_simplified_abstract_(kioxia corporation)
Inventor(s): Fumiya WATANABE of Ota Tokyo (JP) for kioxia corporation, Toshifumi WATANABE of Yokohama Kanagawa (JP) for kioxia corporation, Kazuhiko SATOU of Yokohama Kanagawa (JP) for kioxia corporation, Shouichi OZAKI of Komae Tokyo (JP) for kioxia corporation, Kenro KUBOTA of Fujisawa Kanagawa (JP) for kioxia corporation, Atsuko SAEKI of Yokohama Kanagawa (JP) for kioxia corporation, Ryota TSUCHIYA of Kamakura Kanagawa (JP) for kioxia corporation, Harumi ABE of Kawasaki Kanagawa (JP) for kioxia corporation
IPC Code(s): H03K3/011, G11C7/10, H03K17/14
Abstract: a semiconductor device includes a first pad, a second pad, a first output driver provided for the first pad and configured to output a first transmission signal to the first pad, a second output driver provided for the second pad and configured to output a second transmission signal to the second pad, a register that stores first and second calibration values, a first reference resistor for the first pad and having a resistance value that is set according to the first calibration value, a second reference resistor for the second pad and having a resistance value that is set according to the second calibration value, a first setting circuit configured to calibrate a resistance value of the first output driver using the first reference resistor, and a second setting circuit configured to calibrate a resistance value of the second output driver using the second reference resistor.
Inventor(s): Kiyohito SATO of Kawasaki Kanagawa (JP) for kioxia corporation
IPC Code(s): H03L7/099
Abstract: in a semiconductor integrated circuit, a first oscillation circuit receives a first clock signal and outputs a second clock signal synchronized with the first clock signal in frequency and phase. a second oscillation circuit receives a control signal and outputs a third clock signal having a frequency corresponding to the received control signal. a detection circuit detects a frequency difference between the second clock signal and the third clock signal. a determination circuit determines whether a frequency locked state is established between the first clock signal and the second clock signal. a control circuit varies the control signal, such that the frequency difference decreases while the frequency locked state has not been established and increases after the frequency locked state is established.
Inventor(s): Huy Cu NGO of Isehara Kanagawa (JP) for kioxia corporation
IPC Code(s): H03M1/46, H03M1/14
Abstract: according to one embodiment, a semiconductor integrated circuit includes: first and second converters respectively configured to determine first and second bit strings based on first and second clock signals; a circuit. the circuit includes: first, second, and third capacitors; first and second switching elements; and first, second, and third buffers. the first buffer includes an output end coupled to the first capacitor, a first end of the each of the first and second switching elements. the second buffer includes an output end coupled to the second capacitor, a second end of the first switching element, and the first converter. the third buffer includes an output end coupled to the third capacitor, a second end of the second switching element, and the second converter. a reference voltage is supplied to an input end of each of the first, second, and third buffers.
20240097950.TRANSMISSION DEVICE AND RECEPTION DEVICE_simplified_abstract_(kioxia corporation)
Inventor(s): Ushio JIMBO of Kamakura Kanagawa (JP) for kioxia corporation, Manabu WATANABE of Kawasaki Kanagawa (JP) for kioxia corporation, Daisuke SONODA of Yokohama Kanagawa (JP) for kioxia corporation
IPC Code(s): H04L25/49, H03M5/14
Abstract: a transmission device includes an encoding circuit and a modulation circuit. the encoding circuit is configured to encode first and second data stream portions of a transmission data stream in accordance with first and second encoding protocols, respectively, convert each m bit of the encoded second data stream portion into a high-resolution value of n bit, and generate a baseband data stream including the encoded first data stream portion and the converted second data stream portion. the modulation circuit is configured to perform a 2-level pulse amplitude modulation with respect to each n bit of the encoded first data stream portion in the baseband data stream and each n bit of the converted second data stream portion in the baseband data stream, to generate a transmission signal. m is an integer equal to or greater than 1 and n is an integer greater than m.
20240098930.SEMICONDUCTOR STORAGE DEVICE_simplified_abstract_(kioxia corporation)
Inventor(s): Keishi SHIMIZU of Yokohama Kanagawa (JP) for kioxia corporation
IPC Code(s): H05K7/20, H01L23/367, H01L25/16, H10B80/00
Abstract: a semiconductor storage device includes a housing, a substrate, a first semiconductor component, a capacitor, and a first regulating plate. the substrate is accommodated in the housing. the first semiconductor component is mounted on the substrate. the capacitor on the substrate, the capacitor includes a portion that overlaps the first semiconductor component from a side opposite to the substrate when viewed in a first direction, which is a thickness direction of the substrate. the first regulating plate guides at least a part of air, which flows inside the housing, toward a gap between the capacitor and the substrate.
Inventor(s): Daisuke WATANABE of Yokkaichi Mie (JP) for kioxia corporation, Akifumi GAWASE of Kuwana Mie (JP) for kioxia corporation, Takeshi IWASAKI of Kuwana Mie (JP) for kioxia corporation, Kazuhiro KATONO of Yokkaichi Mie (JP) for kioxia corporation, Yusuke MUTO of Yokkaichi Mie (JP) for kioxia corporation, Yusuke MIKI of Yokkaichi Mie (JP) for kioxia corporation, Akinori KIMURA of Yokkaichi Mie (JP) for kioxia corporation
IPC Code(s): H10B10/00, H01L29/786
Abstract: a semiconductor device including a first electrode, a second electrode, an oxide semiconductor disposed between the first electrode and the second electrode, and a first oxide layer containing a predetermined element, oxygen, and an additional element and disposed between the first electrode and the oxide semiconductor, wherein the predetermined element is at least one of tantalum, boron, hafnium, silicon, zirconium, or niobium, and the additional element is at least one of phosphorus, sulfur, copper, zinc, gallium, germanium, arsenic, selenium, silver, indium, tin, antimony, tellurium, or bismuth.
Inventor(s): Yasuyuki SONODA of Kumage (JP) for kioxia corporation
IPC Code(s): H10B12/00
Abstract: a semiconductor device includes: a first conductor; a second conductor; an oxide semiconductor layer provided between the first conductor and the second conductor and extending in a first direction; a first wiring extending in a second direction across the first direction and surrounding the oxide semiconductor layer; an insulating film provided between the first wiring and the oxide semiconductor layer; a second wiring provided on the second conductor and extending in a third direction across each of the first direction and the second direction; a first insulating layer provided on a side surface of the second wiring and having a first void; and a second insulating layer provided on the first insulating layer and having a second void.
20240098977.SEMICONDUCTOR DEVICE_simplified_abstract_(kioxia corporation)
Inventor(s): Takashi Inukai of Yokohama Kanagawa (JP) for kioxia corporation, Hiroki Tokuhira of Kawasaki Kanagawa (JP) for kioxia corporation, Tsuneo Inaba of Kamakura Kanagawa (JP) for kioxia corporation
IPC Code(s): H10B12/00
Abstract: according to one embodiment, a semiconductor device includes a first wiring line provided in a first layer and extending in a first direction, a second wiring line provided in a second layer and extending in the first direction, a first semiconductor layer penetrating the first wiring line without penetrating the second wiring line and extending in a second direction, a second semiconductor layer penetrating the second wiring line without penetrating the first wiring line and extending in the second direction, a first insulating layer provided between the first wiring line and the first semiconductor layer, a second insulating layer provided between the second wiring line and the second semiconductor layer.
20240098981.SEMICONDUCTOR DEVICE_simplified_abstract_(kioxia corporation)
Inventor(s): Daichi NISHIKAWA of Mie Mie (JP) for kioxia corporation, Daisuke IKENO of Yokkaichi Mie (JP) for kioxia corporation, Atsuko SAKATA of Yokkaichi Mie (JP) for kioxia corporation
IPC Code(s): H10B12/00, H01L29/786
Abstract: according to one embodiment, a semiconductor device includes a pillar of an oxide semiconductor material and a gate insulating layer that surrounds a side surface of the pillar. the gate insulating layer includes a lower portion, an upper portion, and an intermediate portion. a gate electrode surrounds the intermediate portion of the gate insulating layer. a lower electrode is provided that includes a first oxide conductor portion that is connected to a lower surface of the pillar. an upper electrode is provided connected to an upper surface of the pillar. the gate electrode includes a metal portion containing a metallic element and a first nitrogen-containing portion between the metal portion and the gate insulating layer. the first oxide conductor portion includes a second nitrogen-containing at an interface between the first oxide conductor portion and the gate insulating layer.
20240098983.MEMORY DEVICE_simplified_abstract_(kioxia corporation)
Inventor(s): Takashi Inukai of Yokohama Kanagawa (JP) for kioxia corporation
IPC Code(s): H10B12/00
Abstract: according to one embodiment, a memory device includes word lines, bit lines, transistors, capacitors, and a plate line. the transistors include first transistors and second transistors. the first and second transistors are coupled to first and second word lines, respectively. the first and second transistors are arranged to alternate each other in a first direction. the bit lines include first to fourth bit lines arranged sequentially in the first direction. the first and third bit lines are coupled to the other end of the first and second transistors. the second bit line is coupled to the other end of the first transistors and is not coupled to the other end of the second transistors. the fourth bit line is coupled to the other end of the second transistors and is not coupled to the other end of the first transistors.
20240098995.SEMICONDUCTOR STORAGE DEVICE_simplified_abstract_(kioxia corporation)
Inventor(s): Ryota NIHEI of Yokkaichi Mie (JP) for kioxia corporation, Koji MATSUO of Ama Aichi (JP) for kioxia corporation
IPC Code(s): H10B43/27, H10B43/10, H10B43/35
Abstract: according to one embodiment, a semiconductor storage device has first and second gate electrodes extending in one direction. a first semiconductor layer is between the first gate electrode and the second gate electrode. a second semiconductor layer is also between the first semiconductor layer and the second gate electrode but separated from the first semiconductor layer. a third semiconductor layer is between the first gate electrode and the second gate electrode but is spaced from the first semiconductor layer by a gap. a first charge trapping layer is between the first gate electrode and the first semiconductor layer. a second charge trapping layer is between the second gate electrode and the second semiconductor layer. a third charge trapping layer is between the first gate electrode and the third semiconductor layer.
Inventor(s): Ryosuke UMINO of Kuwana Mie (JP) for kioxia corporation, Daisuke IKENO of Yokkaichi Mie (JP) for kioxia corporation
IPC Code(s): H10B43/27
Abstract: a semiconductor device includes: a stacked film alternately including a plurality of electrode layers and a plurality of first insulating films; a charge storage layer provided on the side surfaces of the electrode layers via a second insulating film; and a semiconductor layer provided on the side surface of the charge storage layer via a third insulating film. at least one electrode layer of the plurality of electrode layers includes a first electrode layer which is an amorphous layer comprising a metal element and silicon.
Inventor(s): Saori MATSUSHITA of Yokkaichi Mie (JP) for kioxia corporation, Tomonari SHIODA of Nagoya Aichi (JP) for kioxia corporation, Takanori YAMANAKA of Yokkaichi Mie (JP) for kioxia corporation, Ryota FUJITSUKA of Yokkaichi Mie (JP) for kioxia corporation
IPC Code(s): H10B43/27
Abstract: a semiconductor memory device includes: a stacked body in which a plurality of conductive layers and a plurality of insulating layers are stacked one by one alternately; and a pillar that extends in the stacked body in a stacking direction of the stacked body and includes a memory cell formed at each of intersections with the plurality of conductive layers, in which the pillar includes a semiconductor layer extending in the stacking direction, a silicon oxynitride layer covering a side wall of the semiconductor layer, a silicon nitride layer covering a side wall of the silicon oxynitride layer, and a silicon oxide layer covering a side wall of the silicon nitride layer, in which the silicon oxynitride layer has a hydrogen concentration of 1�10atm/cc or less in terms of average value.
Inventor(s): Junichi HASHIMOTO of Yokkaichi Mie (JP) for kioxia corporation, Toshiyuki SASAKI of Yokkaichi Mie (JP) for kioxia corporation
IPC Code(s): H10B43/27, H01L23/00, H01L25/00, H01L25/065, H01L25/18, H10B80/00
Abstract: according to one embodiment, a semiconductor memory device includes a lower layer, a stacked body above the lower layer with first conductive layers and first insulating layers alternately stacked. a pillar penetrates through the stacked body to reach the lower layer. at least one first insulating layer other than the lowest among the first insulating layers in a first region of the stacked body is thicker than first insulating layers in a second region above the first region. the pillar has a first bowing shape at the height of the at least one thicker first insulating layer and a second bowing shape at a height in the second region.
Inventor(s): Kotaro NOMURA of Yokkaichi (JP) for kioxia corporation
IPC Code(s): H10B43/27
Abstract: a semiconductor memory device of an embodiment includes a first region having a first stack and a first pillar, and a second region having a second stack and a second pillar. the first stack comprises an alternate stack in a first direction of a plurality of first insulating films containing oxygen and a plurality of first conductive films. the first pillar comprises a semiconductor layer and extends in the first direction within the first stack. the second stack comprises a repeated stack in the first direction of the plurality of first insulating films, a plurality of second insulating films, and a plurality of third insulating films in the order of the first insulating film, the second insulating film, and the third insulating film. the second insulating film contains nitrogen. the third insulating film contains nitrogen and at least one of oxygen and hydrogen. the second pillar comprises a semiconductor layer and extends in the first direction within the second stack. the first region and the second region are adjacent to each other in a second direction intersecting the first direction.
Inventor(s): Tadashi IGUCHI of Yokkaichi Mie (JP) for kioxia corporation
IPC Code(s): H10B43/27
Abstract: according to one embodiment, a semiconductor memory device has a first film and a stacked body on the first film. the stacked body includes insulating films and conductive films stacked in a first direction. a first pillar extends through the stacked body and has a first semiconductor portion and a first insulator portion on an outer peripheral surface. a plurality of second pillars extend in the stacked body and reach the first film. the second pillars each comprise an insulator material and have a bottom surface with a protrusion protruding into the first film. a third pillar extends in the stacked body between adjacent second pillars. the third pillar comprises a conductor material that is electrically connected to one of the conductive films of the stacked body.
20240099002.SEMICONDUCTOR MEMORY DEVICE_simplified_abstract_(kioxia corporation)
Inventor(s): Hiroshi KANNO of Yokkaichi Mie (JP) for kioxia corporation
IPC Code(s): H10B43/27, H10B41/27
Abstract: according to one embodiment, a semiconductor memory device includes a first wiring layer above a first semiconductor layer in a first direction and a second wiring layer above the first semiconductor layer and spaced from the first wiring layer in a second direction. a first memory pillar extends through the first wiring layer. a second memory pillar extends through the second wiring layer. a member is between the first and second wiring layers in the second direction and includes a first conductor contacting the first semiconductor layer, a first insulator between the wiring layers and the first conductor, and a plurality of second insulators arranged along a third direction and between the first conductor and the first semiconductor layer in the first direction.
Inventor(s): Tomoya SANUKI of Yokkaichi (JP) for kioxia corporation
IPC Code(s): H10B43/27, G11C5/06, H01L23/00, H01L25/065
Abstract: in one embodiment, a semiconductor device includes a first substrate including first and second regions on its surface, a first control circuit on the first substrate in the first region, a first memory cell array above the first control circuit in the first region and connected to the first control circuit, and a first pad above the first memory cell array in the first region and connected to the first control circuit. the device further includes a second control circuit on the first substrate in the second region, a second memory cell array above the second control circuit in the second region and connected to the second control circuit, a second pad above the second memory cell array in the second region and connected to the second control circuit, and a connection line above the first and second memory cell arrays and connecting the first and second pads.
20240099009.METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE_simplified_abstract_(kioxia corporation)
Inventor(s): Mariko SUMIYA of Yokkaichi Mie (JP) for kioxia corporation, Ryosuke YAMAMOTO of Nagoya Aichi (JP) for kioxia corporation
IPC Code(s): H10B43/35, H01L21/02, H01L21/20, H10B43/27, H10B43/40
Abstract: a method for manufacturing a semiconductor device includes: forming a release layer including a first polycrystalline semiconductor layer provided on a first substrate, and a second polycrystalline semiconductor layer provided between the first substrate and the first polycrystalline semiconductor layer and having a p-type impurity concentration which is lower than that of the first polycrystalline semiconductor layer, and an n-type impurity concentration which is higher than that of the first polycrystalline semiconductor layer; subjecting the first polycrystalline semiconductor layer to anodic chemical conversion to form a first porous layer; forming a first device layer on the first porous layer; and bonding together the first device layer and a second device layer provided on a second substrate.
20240099010.SEMICONDUCTOR MEMORY DEVICE_simplified_abstract_(kioxia corporation)
Inventor(s): Takamitsu ISHIHARA of Yokohama Kanagawa (JP) for kioxia corporation, Kazuya MATSUZAWA of Kamakura Kanagawa (JP) for kioxia corporation
IPC Code(s): H10B43/35, H10B41/27, H10B41/35, H10B43/27
Abstract: a semiconductor memory device includes a gate electrode and a first and second semiconductor layer surrounding the gate electrode. a first electrode layer surrounds the gate electrode and contacts the first semiconductor layer. a second electrode layer surrounds the gate electrode and contacts the first and second semiconductor layers. the first semiconductor layer is between the first and second electrode layers. a third electrode layer surrounds the gate electrode and contacts the second semiconductor layer. the second semiconductor layer is between the second and third electrode layers. a first charge storage layer is between the gate electrode and the first semiconductor layer. a second charge storage layer is between the gate electrode and the second semiconductor layer.
20240099013.SEMICONDUCTOR MEMORY DEVICE_simplified_abstract_(kioxia corporation)
Inventor(s): Yoshiaki FUKUZUMI of Yokkaichi (JP) for kioxia corporation, Hideaki AOCHI of Yokkaichi (JP) for kioxia corporation, Mie MATSUO of Yokkaichi (JP) for kioxia corporation, Kenichiro YOSHII of Bunkyo (JP) for kioxia corporation, Koichiro SHINDO of Yokohama (JP) for kioxia corporation, Kazushige KAWASAKI of Kawasaki (JP) for kioxia corporation, Tomoya SANUKI of Yokkaichi (JP) for kioxia corporation
IPC Code(s): H10B43/40, H01L21/18, H01L21/768, H01L23/00, H01L25/065, H01L25/18, H10B43/27, H10B43/30, H10B43/50
Abstract: according to one embodiment, the array chip includes a three-dimensionally disposed plurality of memory cells and a memory-side interconnection layer connected to the memory cells. the circuit chip includes a substrate, a control circuit provided on the substrate, and a circuit-side interconnection layer provided on the control circuit and connected to the control circuit. the circuit chip is stuck to the array chip with the circuit-side interconnection layer facing to the memory-side interconnection layer. the bonding metal is provided between the memory-side interconnection layer and the circuit-side interconnection layer. the bonding metal is bonded to the memory-side interconnection layer and the circuit-side interconnection layer.
Inventor(s): Hyung-woo AHN of Seongnam-si (KR) for kioxia corporation, Young Min EEH of Yokohama Kanagawa (JP) for kioxia corporation, Tadaaki OIKAWA of Seoul (KR) for kioxia corporation, Taiga ISODA of Tokyo (JP) for kioxia corporation
IPC Code(s): H10B61/00, H10N50/01, H10N50/10, H10N50/80
Abstract: a magnetoresistance memory device includes a lower electrode, a barrier layer, a variable resistance layer, an upper electrode, and a first layer stack. the lower electrode contains one of amorphous carbon and amorphous carbon nitride. the barrier layer is provided on the lower electrode and contains one of tungsten nitride (wn) and silicon tungsten nitride (wsin). the variable resistance layer is provided on the barrier layer and contains a variable resistance material. the upper electrode is provided on the variable resistance layer and contains one of amorphous carbon and amorphous carbon nitride. the first layer stack is provided on the upper electrode and includes a first ferromagnetic layer, a second ferromagnetic layer, and an insulating layer between the first ferromagnetic layer and the second ferromagnetic layer.
20240099020.MEMORY DEVICE_simplified_abstract_(kioxia corporation)
Inventor(s): Takeshi IWASAKI of Kuwana Mie (JP) for kioxia corporation, Yosuke MATSUSHIMA of Yokkaichi Mie (JP) for kioxia corporation, Katsuyoshi KOMATSU of Yokkaichi Mie (JP) for kioxia corporation
IPC Code(s): H10B61/00
Abstract: according to one embodiment, memory device includes a first, second, and third conductive layers in this order, a resistance change layer between the first and the second conductive layers, and a switching layer between the second and the third conductive layers. the switching layer contains: at least one first substance from a group consisting of oxide of at least one element from a group consisting of cr, la, ce, y, sc, zr, and hf, nitride of the at least one element, and oxynitride of the at least one element; a second substance being at least one metal from a group consisting of te, se, sb, bi, ge, and sn; and at least one third substance from a group consisting of oxide of the second substance, nitride of the second substance, and oxynitride of the second substance.
20240099021.MAGNETIC MEMORY DEVICE_simplified_abstract_(kioxia corporation)
Inventor(s): Naoki AKIYAMA of Seoul (KR) for kioxia corporation, Kenichi YOSHINO of Seongnam-si Gyeonggi-do (KR) for kioxia corporation, Kazuya SAWADA of Seoul (KR) for kioxia corporation, Hyungjun CHO of Seoul (KR) for kioxia corporation, Takuya SHIMANO of Seoul (KR) for kioxia corporation
IPC Code(s): H10B61/00
Abstract: according to one embodiment, a magnetic memory device includes a lower insulating layer, first and second conductive portions provided in the lower insulating layer, first and second memory cells provided on the lower insulating layer and on the respective first and second conductive portions, and each including a magnetoresistance effect element, a switching element and a bottom electrode connected to corresponding one of the first and second conductive portions. as viewed from a third direction, a width of each of the first and second conductive portions is less than a width of a corresponding bottom electrode. the lower insulating layer has a void under a region between the first and second memory cells.
Inventor(s): Kensuke TAKAHASHI of Yokkaichi Mie (JP) for kioxia corporation, Daisaburo TAKASHIMA of Yokohama Kanagawa (JP) for kioxia corporation, Naoki KAI of Kuwana Mie (JP) for kioxia corporation, Yasumi ISHIMOTO of Yokkaichi Mie (JP) for kioxia corporation
IPC Code(s): H10B63/00, H10B63/10
Abstract: according to one embodiment, a cell block includes memory cells and select transistors. the memory cells correspond are connected in parallel between a local source line and a local bit line. the select transistor is connected between the local bit line and a bit line. the memory cell includes a cell transistor and a resistance change element. a gate of the cell transistor is connected to a word line. the resistance change element is connected to the cell transistor in series between the local source line and the local bit line. each cell block is configured as a columnar structure penetrating a plurality of conductive films functioning as word lines. the select transistor and the local bit line are connected at a contact portion formed of a material different from a material of the local bit line.
Inventor(s): Yoshiki NAGASHIMA of Tokyo (JP) for kioxia corporation
IPC Code(s): H10B80/00
Abstract: a semiconductor memory device includes a first memory die, a second memory die disposed above the first memory die via adhesives, a first wiring connected to the first memory die, and configured to apply a power supply voltage to the first memory die, a first switch element connected to the first wiring, a second wiring connected to the second memory die, and configured to apply the power supply voltage to the second memory die, a second switch element connected to the second wiring, and a third wiring configured to electrically connect to the first wiring via the first switch element, and configured to electrically connect to the second wiring via the second switch element. the first switch element and the second switch element are independently controllable.
20240099031.SEMICONDUCTOR MEMORY DEVICE_simplified_abstract_(kioxia corporation)
Inventor(s): Toshifumi HASHIMOTO of Fujisawa (JP) for kioxia corporation
IPC Code(s): H10B80/00, H01L23/00, H01L25/065, H01L25/18, H10B41/10, H10B41/27, H10B41/41, H10B43/10, H10B43/27, H10B43/40
Abstract: a memory plane region includes a first structure and a second structure having conductive layers, and includes a first memory region to a third memory region, a first region between the first memory region and the second memory region, and a second region between the second memory region and the third memory region. the first structure comprises first via contact electrodes in the first region. the second structure comprises second via contact electrodes in the second region. the first via contact electrodes are electrically connected to transistors provided at positions where the first structure and the first region overlap, and where the second structure and the first region overlap. the second via contact electrodes are electrically connected to transistors provided at positions where the first structure and the second region overlap, and where the second structure and the second region overlap.
20240099032.SEMICONDUCTOR STORAGE DEVICE_simplified_abstract_(kioxia corporation)
Inventor(s): Kazuki AKAMINE of Yokkaichi Mie (JP) for kioxia corporation, Shigeki KOBAYASHI of Kuwana Mie (JP) for kioxia corporation
IPC Code(s): H10B80/00, H01L23/00, H01L25/065, H01L25/18
Abstract: a semiconductor storage device includes: a stacked body in which a plurality of electrically conductive layers is stacked with an insulating layer interposed in between; and a circuit section that is provided to overlap with the stacked body in a stack direction. the stacked body includes a memory section in which a plurality of memory cells is disposed and a staircase section in which the plurality of electrically conductive layers has stepped ends. the circuit section includes row decoders that are joined to the plurality of electrically conductive layers. the staircase section includes a first structure in which the row decoders are provided to overlap with each other in the stack direction and a second structure different from the first structure. the second structure has a greater step gap than a step gap of the first structure.
20240099033.SEMICONDUCTOR MEMORY DEVICE_simplified_abstract_(kioxia corporation)
Inventor(s): Toshiaki SATO of Yokohama (JP) for kioxia corporation, Masaki UNNO of Fujisawa (JP) for kioxia corporation
IPC Code(s): H10B80/00, H01L23/00, H01L25/065, H01L25/18
Abstract: a semiconductor memory device includes a plurality of sense amplifier regions, a first wiring layer including a plurality of bit lines electrically connected to a plurality of semiconductor layers, and a second wiring layer including a plurality of first wirings electrically connecting the respective plurality of sense amplifier regions to the plurality of bit lines. the semiconductor substrate includes a first region and a second region arranged in a second direction. the (n1) (n1 is an integer of 2 or more) first wirings arranged in the third direction are disposed at a position where the first region overlaps with the sense amplifier region viewed in the first direction. the (n2) (n2 is an integer of 2 or more different from n1) first wirings arranged in the third direction are disposed at a position where the second region overlaps with the other sense amplifier region viewed in the first direction.
20240099153.STORAGE DEVICE_simplified_abstract_(kioxia corporation)
Inventor(s): Takeshi IWASAKI of Kuwana Mie (JP) for kioxia corporation, Zhu QI of Yokkaichi Mie (JP) for kioxia corporation, Katsuyoshi KOMATSU of Yokkaichi Mie (JP) for kioxia corporation, Jieqiong ZHANG of Chiyoda Tokyo (JP) for kioxia corporation
IPC Code(s): H10N50/10, G11C5/08, H10B61/00, H10N50/85
Abstract: a storage device includes a first conductive layer, a second conductive layer, a third conductive layer, a variable resistance layer disposed between the first conductive layer and the second conductive layer, and a switching layer disposed between the second conductive layer and the third conductive layer. the second conductive layer is disposed between the first conductive layer and the third conductive layer. the switching layer includes a first area, a second area, and a third area disposed between the first area and the second area. the first area includes a first element selected from sn, ga, zn, ta, ti, and in, and o or n. the second area includes a second element selected from sn, ga, zn, ta, ti, and in, and o or n. the third area includes a third element selected from zr, y, ce, hf, al, mg, and nb, o or n, and a metal element selected from te, sb, bi, ti, and zn.
20240099155.MAGNETIC MEMORY_simplified_abstract_(kioxia corporation)
Inventor(s): Masahiro KOIKE of Yokohama Kanagawa (JP) for kioxia corporation, Michael Arnaud QUINSAT of Yokohama Kanagawa (JP) for kioxia corporation, Nobuyuki UMETSU of Kawasaki Kanagawa (JP) for kioxia corporation, Tsutomu NAKANISHI of Yokohama Kanagawa (JP) for kioxia corporation, Agung SETIADI of Kokubunji Tokyo (JP) for kioxia corporation, Megumi YAKABE of Kawasaki Kanagawa (JP) for kioxia corporation, Shigeyuki HIRAYAMA of Tokyo (JP) for kioxia corporation, Masaki KADO of Kamakura Kanagawa (JP) for kioxia corporation, Yasuaki OOTERA of Yokohama Kanagawa (JP) for kioxia corporation, Shiho NAKAMURA of Kawasaki Kanagawa (JP) for kioxia corporation, Susumu HASHIMOTO of Tokyo (JP) for kioxia corporation, Tsuyoshi KONDO of Kawasaki Kanagawa (JP) for kioxia corporation
IPC Code(s): H10N50/80, G11C11/16, H10B61/00, H10N50/10
Abstract: a memory includes: a magnet including a first and second portions adjacent in a first direction. the first portion has a first dimension in a second direction at a first position at which a dimension of the magnet in the second direction is maximum, the second direction perpendicular to the first direction, the second portion has a second dimension in the second direction at a second position at which a dimension of the magnet in the second direction is minimum, the second dimension smaller than the first dimension, the first portion is continuous to the second portion via a third position between the first and second positions, a curve corresponding to an outer of the magnet extends between the first and third positions, and the curve passes through a side closer to the central axis of the magnet than a straight line connecting the first and second positions.
20240099156.MAGNETIC MEMORY DEVICE_simplified_abstract_(kioxia corporation)
Inventor(s): Kazuya SAWADA of Seoul (KR) for kioxia corporation, Toshihiko NAGASE of Seoul (KR) for kioxia corporation, Kenichi YOSHINO of Seongnam-si Gyeonggi-do (KR) for kioxia corporation, Hyungjun CHO of Seoul (KR) for kioxia corporation, Naoki AKIYAMA of Seoul (KR) for kioxia corporation, Takuya SHIMANO of Seoul (KR) for kioxia corporation, Tadaaki OIKAWA of Seoul (KR) for kioxia corporation
IPC Code(s): H10N50/80, H10B61/00, H10N50/01, H10N50/20
Abstract: according to one embodiment, a magnetic memory device includes an electrode, and a magnetoresistance effect element provided on the electrode. the electrode includes a first electrode portion and a second electrode portion provided between the magnetoresistance effect element and the first electrode portion and containing a metal element selected from molybdenum (mo) and ruthenium (ru).
20240099158.MAGNETIC MEMORY DEVICE_simplified_abstract_(kioxia corporation)
Inventor(s): Kenichi YOSHINO of Seongnam-si Gyeonggi-do (KR) for kioxia corporation, Tadaaki OIKAWA of Seoul (KR) for kioxia corporation, Kazuya SAWADA of Seoul (KR) for kioxia corporation, Naoki AKIYAMA of Seoul (KR) for kioxia corporation, Takuya SHIMANO of Seoul (KR) for kioxia corporation, Hyungjun CHO of Seoul (KR) for kioxia corporation
IPC Code(s): H10N50/85, G11C11/16, H10B61/00, H10N50/10
Abstract: according to one embodiment, a magnetic memory device includes a first wiring line extending in a first direction, a second wiring line provided on an upper layer side of the first wiring line and extending in a second direction intersecting the first direction, and a memory cell provided between the first wiring line and the second wiring line and including a magnetoresistance effect element and a switching element which are stacked in a third direction intersecting the first direction and the second direction. the first wiring line includes a first conductive layer and a second conductive layer provided on the first conductive layer and formed of a material containing carbon (c).
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