Kioxia Corporation patent applications on December 26th, 2024
Patent Applications by Kioxia Corporation on December 26th, 2024
Kioxia Corporation: 29 patent applications
Kioxia Corporation has applied for patents in the areas of H10B43/27 (5), G03F7/00 (3), G11C16/04 (3), H01L23/31 (3), H01L25/065 (3) H10B43/27 (2), G03F7/0002 (2), G11C29/38 (1), H10B41/41 (1), H03K21/38 (1)
With keywords such as: memory, layer, substrate, semiconductor, configured, conductive, layers, between, provided, and film in patent application abstracts.
Patent Applications by Kioxia Corporation
Inventor(s): Taiki ITO of Kawasaki (JP) for kioxia corporation
IPC Code(s): G01B15/04, G03F1/86, G03F7/00, G06F30/32, G06T7/00, G06T7/12, G06T7/50
CPC Code(s): G01B15/04
Abstract: a pattern shape measurement method includes generating, based on shape data on a pattern being a measurement target, contour point data including pieces of position information on contour points of the pattern (e.g., mask pattern); selecting sets of pieces of position information on consecutive contour points from the contour point data and generating a plurality of items of extracted point data including the respective sets of pieces of position information on consecutive contour points; calculating, with circuitry, for each of the plurality of items of extracted point data, a determined angle formed between a marker line based on the consecutive contour points and a base line that extends in a prescribed direction in the pattern; determining a scan angle for the charged particles with respect to the pattern based on a frequency of occurrence of the determined angle; and scanning the pattern at the determined scan angle.
Inventor(s): Kosuke TAKAI of Yokohama Kanagawa (JP) for kioxia corporation, Katsuyoshi KODERA of Yokohama Kanagawa (JP) for kioxia corporation
IPC Code(s): G03F1/26, G03F1/48, G03F1/80
CPC Code(s): G03F1/26
Abstract: a photomask blank includes a substrate, a first transmittance adjusting film provided on the substrate, a phase shifter film provided on the first transmittance adjusting film, and a second transmittance adjusting film provided on the phase shifter film. when light having a wavelength transmits through the phase shifter film, a phase of the light transmitted through the phase shifter film and the first transmittance adjusting film is different from a phase of light passed through atmosphere with about 180 degrees, and a phase of the light transmitted through the phase shifter film and the second transmittance adjusting film is different from a phase of the light passed through the atmosphere with about 180 degrees.
Inventor(s): Katsuyoshi KODERA of Yokohama Kanagawa (JP) for kioxia corporation, Yukio OPPATA of Chiba Chiba (JP) for kioxia corporation, Shoji MIMOTOGI of Yokohama Kanagawa (JP) for kioxia corporation
IPC Code(s): G03F1/32, G03F1/36, G03F1/60, G03F1/70
CPC Code(s): G03F1/32
Abstract: a method of manufacturing a photomask comprises forming a mask film on a surface of a substrate, and forming, with the mask film, a first mask pattern in a first region of the substrate and a second mask pattern in a second region of the substrate. a coverage ratio of the first mask pattern is different from a coverage ratio of the second mask pattern. a light transmittance rate of light through the substrate in the first region and the first mask pattern is different from a light transmittance rate of the light through the substrate in the second region and the second mask pattern.
Inventor(s): Shunsuke HONDA of Yokkaichi Mie (JP) for kioxia corporation, Masayuki HATANO of Yokohama Kanagawa (JP) for kioxia corporation
IPC Code(s): G03F7/00
CPC Code(s): G03F7/0002
Abstract: an imprint apparatus: a stage having a face on which an object is placed, the object having a first surface; a dropping device configured to drop a droplet of a photocurable resin in a first direction intersecting with the face; a irradiation device configured to irradiate a first light in a second direction intersecting with the first direction; a holder configured to hold a template having a second surface, the second surface having a pattern; an exposure device configured to irradiate a second light in a third direction intersecting with the face; and a control device configured to drive the dropping device and the irradiation device and control selecting whether to irradiate the first light to the droplet according to a position where the droplet is to be dropped on the first surface.
Inventor(s): Kazuya FUKUHARA of Yokkaichi Mie (JP) for kioxia corporation, Masayuki HATANO of Yokohama Kanagawa (JP) for kioxia corporation, Tetsuro NAKASUGI of Yokohama Kanagawa (JP) for kioxia corporation
IPC Code(s): G03F7/00, G03F7/16, H01L21/027, H01L21/311
CPC Code(s): G03F7/0002
Abstract: an imprint method includes: forming a liquid film of a first photocurable resin to have a substantially flat upper surface on a central region of a substrate; depositing droplets of a second photocurable resin on an outer peripheral region of the substrate; pressing a template against the first photocurable resin and the second photocurable resin; irradiating the first photocurable resin and the second photocurable resin with light to cure the first photocurable resin and the second photocurable resin; and releasing the template from the first photocurable resin and the second photocurable resin to expose a pattern on the substrate, that is formed by the cured first photocurable resin and the cured second photocurable resin.
Inventor(s): Yasufumi KURIHASHI of Yokohama (JP) for kioxia corporation
IPC Code(s): G06F12/02
CPC Code(s): G06F12/0246
Abstract: a memory system includes a nonvolatile memory including memory cells capable of storing user data by a plurality of different storage methods; and a memory controller configured to control the nonvolatile memory. the nonvolatile memory includes a firmware storage area and a user data area, the firmware storage area configured to store firmware and the user data area configured to store user data, and firmware corresponding to each of the storage methods is stored in the firmware storage area. the memory controller uses the firmware corresponding to an externally instructed storage method among the storage methods, thereby controls settings of the nonvolatile memory.
Inventor(s): Atsushi KAWASUMI of Fujisawa Kanagawa (JP) for kioxia corporation
IPC Code(s): G06F17/16
CPC Code(s): G06F17/16
Abstract: an information processing apparatus configured to detect similarity between a first vector having a plurality of elements and a second vector having a plurality of elements based on an inner product value of the first vector and the second vector, the information processing apparatus has a wiring line having a current flowing therethrough, the current being a sum of currents each corresponding to a product of a value obtained by subtracting one of the elements of the first vector from a reference value and a corresponding one of the elements of the second vector, a sense amplifier configured to sense a voltage on the wiring line, and a similarity detection circuit configured to detect the similarity based on an output signal of the sense amplifier.
Inventor(s): Riichi FUKUDA of Yokohama Kanagawa (JP) for kioxia corporation
IPC Code(s): G06F21/31, G06F21/60
CPC Code(s): G06F21/31
Abstract: an information processing system includes a memory system including a memory configured to store data; a host attachable to the memory system; and an authentication server. the host includes a user interface configured to transmit an initialization command to a command generator when an input is received from a user, generate user identification information for identifying the user, and transmit the generated user identification information to a first user authenticator. the command generator can transmit a first command, causing the memory system to start the initialization of the memory when the initialization command is received.
20240427941. MEMORY SYSTEM GENERATING ERASE CERTIFICATE_simplified_abstract_(kioxia corporation)
Inventor(s): Naoki ESAKA of Kawasaki (JP) for kioxia corporation, Yoshiyuki KUDOH of Kawasaki (JP) for kioxia corporation
IPC Code(s): G06F21/64, G06F21/79
CPC Code(s): G06F21/64
Abstract: according to one embodiment, a memory system includes a nonvolatile memory and a controller. the nonvolatile memory includes storage areas each configured to store user data. the controller acquires first information related to the number of program/erase cycles for at least one of the storage areas. in response to acquisition of the first information, the controller executes a data erase operation on each of the storage areas. in response to completion of the data erase operation, the controller acquires second information related to the number of program/erase cycles for the at least one of the storage areas. the controller generates an erase certificate that includes the first information and the second information.
20240428836. MEMORY SYSTEM_simplified_abstract_(kioxia corporation)
Inventor(s): Masahiko NAKAYAMA of Yokohama Kawagawa (JP) for kioxia corporation, Tatsuo SHIOZAWA of Setagaya Tokyo (JP) for kioxia corporation
IPC Code(s): G11C11/16, H10B61/00
CPC Code(s): G11C11/1659
Abstract: according to one embodiment, a memory system includes a memory unit including a memory cell array which includes a plurality of memory cells and which is divided into a plurality of memory cell blocks, and a drive circuit which drives the plurality of memory cells, and a controller which controls the memory unit. each of the plurality of memory cells includes a resistance change memory element and a switching element connected in series to the resistance change memory element, and the controller is configured to control the memory unit in such a manner that the number of times of predetermined access to each of the plurality of memory cell blocks increases or decreases according to a distance from the drive circuit to each of the plurality of memory cell blocks.
20240428837. MEMORY DEVICE_simplified_abstract_(kioxia corporation)
Inventor(s): Kosuke HATSUDA of Bunkyo Tokyo (JP) for kioxia corporation
IPC Code(s): G11C11/16, G11C5/06
CPC Code(s): G11C11/1673
Abstract: a memory device includes a first wiring, a second wiring, a memory cell connected between the first wiring and the second wiring, a first power line, a sense amplifier, a current control circuit provided between the first power line and the sense amplifier and including a control terminal connected to a first node, a capacitance element provided between the first node and the second wiring and including a first terminal electrically connected to the second wiring and a second terminal connected to the first node, a second power line, and a first element having an electrical resistance provided between the first node and the second power line.
20240428843. HOST APPARATUS AND EXTENSION DEVICE_simplified_abstract_(kioxia corporation)
Inventor(s): Akihisa FUJIMOTO of Yamato (JP) for kioxia corporation
IPC Code(s): G11C11/4074, G11C5/14, G11C7/22, G11C11/409, G11C29/02, G11C29/50
CPC Code(s): G11C11/4074
Abstract: according to one embodiment, a first power-supply voltage is applied to i/o cells, an i/o cell connected to a clock terminal is initially set to a threshold of a second voltage signaling, an i/o cell connected to a command terminal and i/o cells connected to data terminals are initially set as an input, and when a clock control unit detects receipt of one clock pulse and a signal voltage control unit detects a host using the second voltage signaling, a signal voltage control unit drives the i/o cell of a first data terminal high level after a second power-supply voltage is applied to i/o cells and the threshold of a second voltage signaling is set to i/o cells of the clock, command and data terminals.
Inventor(s): Akira TAKASHIMA of Fuchu (JP) for kioxia corporation, Tsunehiro INO of Fujisawa (JP) for kioxia corporation
IPC Code(s): G11C16/04, H10B43/27, H10B43/35
CPC Code(s): G11C16/0483
Abstract: a semiconductor memory device of an embodiment includes a stacked body including a first insulating layer, a first conductive layer and a second insulating layer; a semiconductor film extending in a first direction; a tunnel insulating film provided between the stacked body and the semiconductor film, the tunnel insulating film extending in the first direction; a first block insulating film provided between the first conductive layer and the tunnel insulating film; and a first charge storage film containing a metal oxide or a metal oxynitride and including: a first portion provided between the tunnel insulating film and the first block insulating film, a second portion provided between the tunnel insulating film and the first insulating layer, the second portion being connected to the first portion and a third portion provided between the tunnel insulating film and the second insulating layer, the third portion being connected to the first portion.
20240428866. SEMICONDUCTOR MEMORY DEVICE_simplified_abstract_(kioxia corporation)
Inventor(s): Yuki INUZUKA of Yokohama Kanagawa (JP) for kioxia corporation, Akiyuki MURAYAMA of Koto Tokyo (JP) for kioxia corporation
IPC Code(s): G11C16/26, G11C16/04, G11C16/08, G11C16/30, H10B43/10, H10B43/27
CPC Code(s): G11C16/26
Abstract: a semiconductor memory device includes a memory pillar; first and second conductive layers on either side of the memory pillar; third and fourth conductive layers and fifth and sixth conductive layer respectively below and above first and second conductive layers; seventh and eighth conductive layers below third and fourth conductive layers; ninth and tenth conductive layers above fifth and sixth conductive layers; memory cells formed between a respective first through tenth conductive layers and the memory pillar; and a control circuit, which applies a read voltage to the first conductive layer, a negative voltage to second, fourth, and sixth conductive layers, and a read pass voltage to other conductive layers, applies the read pass voltage to first, second, fourth, and sixth conductive layers, applies a ground voltage or lower to a first group of conductive layers, and then a ground voltage to a second group of conductive layers.
20240428868. MEMORY SYSTEM_simplified_abstract_(kioxia corporation)
Inventor(s): Naoto KUMANO of Yokohama Kanagawa (JP) for kioxia corporation, Kenji SAKURADA of Yamato Kanagawa (JP) for kioxia corporation
IPC Code(s): G11C16/34, G11C16/04, G11C16/20
CPC Code(s): G11C16/3404
Abstract: a memory system includes a semiconductor memory including a plurality of first memory cells each configured to store data in a non-volatile manner according to a threshold voltage, and a controller. the controller is configured to perform a first error correction process for the plurality of first memory cells, based on first hard bit data and first soft bit data acquired using a plurality of first soft bit voltages that have been calculated based on a shift voltage, and to correct the shift voltage when a condition based on correction data generated during the first error correction process, is satisfied.
Inventor(s): Hayato KONNO of Yokohama Kanagawa (JP) for kioxia corporation, Makoto MIAKASHI of Yokohama Kanagawa (JP) for kioxia corporation
IPC Code(s): G11C16/34, G11C16/16
CPC Code(s): G11C16/3445
Abstract: a memory includes a plurality of planes, a controller, and a source line. the controller is configured to erase data of each memory cell in an erase target block selected in each of the planes, by executing an erase sequence that repeats a plurality of loops, each of the loops including a set of an erase operation that erases the data of each memory cell in the erase target block and an erase verification operation that checks whether the data is erased. for each erase target block, the controller is configured to detect whether there is a current leak from the source line, determine validity of the erase sequence based on a detection result, and stop execution of the erase sequence for the erase target blocks that are determined not to be valid.
20240428875. CHIP HEAT TREATMENT SYSTEM_simplified_abstract_(kioxia corporation)
Inventor(s): Tomoya SANUKI of Yokkaichi Mie (JP) for kioxia corporation, Hitomi TANAKA of Ota Tokyo (JP) for kioxia corporation, Hajime SANO of Katsushika Tokyo (JP) for kioxia corporation, Tatsuro HITOMI of Yokohama Kanagawa (JP) for kioxia corporation, Yasuhito YOSHIMIZU of Kawasaki Kanagawa (JP) for kioxia corporation, Kazuma HASEGAWA of Kamakura Kanagawa (JP) for kioxia corporation
IPC Code(s): G11C29/38, G06F13/16
CPC Code(s): G11C29/38
Abstract: a system includes a rack, a heat treatment device configured to perform a heat treatment, one or more conveyance devices, and a host. the host is configured to determine a target memory chip to be subjected to the heat treatment by the heat treatment device among memory chips in a plurality of drives mounted on the rack, and disable communication with a target drive on which the target memory chip is mounted. the host is configured to control the conveyance devices to dismount the target drive from the rack, detach a component including the target memory chip from the target drive, convey the detached component to the heat treatment device, reattach the component including the target memory chip that has undergone the heat treatment to a drive, and mount the drive with the component including the target memory chip that has undergone the heat treatment on the rack.
20240429030. PLASMA TREATMENT APPARATUS_simplified_abstract_(kioxia corporation)
Inventor(s): Kazuya EMURA of Yatomi Aichi (JP) for kioxia corporation
IPC Code(s): H01J37/32
CPC Code(s): H01J37/32715
Abstract: a plasma treatment apparatus including a stage, an edge ring, a drive mechanism, and a plasma generation portion is provided. the stage is disposed in a treatment chamber. the stage includes a main surface. a substrate is placed on the main surface. the edge ring is disposed in the treatment chamber. the edge ring surrounds the main surface when viewed from a direction perpendicular to the main surface. the drive mechanism can drive the edge ring in a direction along the main surface. the plasma generation portion can generate plasma in a space adjacent to the main surface in the treatment chamber.
Inventor(s): Ryo ITO of Yokkaichi Mie (JP) for kioxia corporation, Hiroshi FUJITA of Yokohama Kanagawa (JP) for kioxia corporation, Tatsuhiko KOIDE of Kuwana Mie (JP) for kioxia corporation
IPC Code(s): H01L21/67, H01L21/311, H01L21/66
CPC Code(s): H01L21/67253
Abstract: a substrate processing apparatus according to an embodiment includes a processing tank configured to store a chemical and perform processing by immersing a substrate in the chemical, a holder configured to hold the substrate and having a lifting part, a chemical liquid supply device configured to supply the chemical, a light irradiation part configured to irradiate light to the substrate taken out from the processing tank, the substrate being taken out from the processing tank by the lifting part after immersing the substrate in the chemical, a light detection part configured to detect reflected light generated from the light being reflected by the substrate, and a control device configured to control an amount of chemical supplied by the chemical liquid supply device in response to a detection result of the light detection part.
20240429114. SEMICONDUCTOR DEVICE_simplified_abstract_(kioxia corporation)
Inventor(s): Yoshiharu OKADA of Yokkaichi (JP) for kioxia corporation
IPC Code(s): H01L23/31, H01L21/304, H01L25/00, H01L25/065, H01L25/16
CPC Code(s): H01L23/3114
Abstract: a semiconductor device including a first semiconductor chip that has a first surface including a first region and a second region adjacent to the first region; a second semiconductor chip provided on the first region; and resin provided on the second region and adjoining the second semiconductor chip, wherein at least a part of an interface between the first semiconductor chip and the resin has recesses and protrusions.
Inventor(s): Keisuke TOKUBUCHI of Yokkaichi Mie (JP) for kioxia corporation
IPC Code(s): H01L23/31, H01L21/56, H01L21/762, H01L23/00, H01L23/29, H01L23/498, H01L23/528, H01L25/065
CPC Code(s): H01L23/3128
Abstract: a semiconductor device includes: a first substrate; a second substrate provided above the first substrate, the second substrate being smaller in area than the first substrate when the second substrate is viewed from above; a first layer provided between the first substrate and the second substrate and having a first conductive pad; a second layer provided between the first layer and the second substrate and having a second conductive pad bonded to the first conductive pad; and an insulator covering each of at least one side surface of the first substrate and at least one side surface of the second substrate.
20240429158. SEMICONDUCTOR MEMORY DEVICE_simplified_abstract_(kioxia corporation)
Inventor(s): Genki KAWAGUCHI of Yokkaichi (JP) for kioxia corporation
IPC Code(s): H01L23/522, H10B41/27, H10B43/27
CPC Code(s): H01L23/5226
Abstract: according to one embodiment, a semiconductor memory device includes a substrate expanding in a first direction and a second direction, a plurality of conductive layers arranged in a third direction with a distance therebetween, the conductive layers including a first conductive layer, and each including a first portion and a second portion being arranged with the first portion in the second direction and including a terrace portion provided so as not to overlap an upper conductive layer in the third direction, a first insulating portion provided between the first portions and the second portions, and a first insulating layer arranged with the first portion of the first conductive layer in the second direction with the first insulating portion interposed therebetween.
Inventor(s): Jun TANAKA of Kuwana Mie (JP) for kioxia corporation
IPC Code(s): H01L23/00, H01L23/31, H01L23/48, H01L23/498, H01L23/538, H01L25/065, H01L25/10, H10B80/00
CPC Code(s): H01L24/14
Abstract: a semiconductor device includes a substrate, a first semiconductor chip, an adhesive layer, a second semiconductor chip, a first joint, and a second joint. the adhesive layer fixes the substrate to the first semiconductor chip. the second semiconductor chip includes a first region overlapping the first semiconductor chip in a thickness direction of the substrate and a second region excluding the first region. the first joint is disposed between the first semiconductor chip and the first region of the second semiconductor chip and electrically connects the first semiconductor chip to the second semiconductor chip. the second joint is disposed between the substrate and the second region of the second semiconductor chip, is larger than the first joint in volume, and electrically connects the substrate to the second semiconductor chip. a fusion point of the first joint is lower than a fusion point of the second joint.
Inventor(s): Tomoaki YABE of Suginami (JP) for kioxia corporation
IPC Code(s): H01L27/02, G06F30/327, H01L27/118
CPC Code(s): H01L27/0207
Abstract: according to one embodiment, a semiconductor integrated circuit includes a first semiconductor layer stacked as a (2n−1)layer, and a second semiconductor layer stacked as a (2n)layer. the semiconductor integrated circuit further includes: a first standard cell in which a first conductivity type mos as a (4i−1)layer and a second conductivity type mos as a (4i)layer share a gate terminal; a second standard cell in which the first conductivity type mos as a (4i−3)layer and the second conductivity type mos as a (4i−2)layer share a gate terminal; and a third standard cell in which the first conductivity type moss as the (4i−3)layer and as the (4i−1)layer and the second conductivity type moss as the (4i)layer and as the (4i−2)layer shares a gate terminal.
Inventor(s): Takashi Toi of Yokohama Kanagawa (JP) for kioxia corporation
IPC Code(s): H10B41/00
CPC Code(s): H01L28/10
Abstract: according to one embodiment, a semiconductor circuit includes a semiconductor substrate, a first t-coil including a first inductive element and a second inductive element which are coupled in series, and a second t-coil including a third inductive element and a fourth inductive element which are coupled in series. a part of the first t-coil is provided at a first position. a part of the second t-coil is provided at a second position to overlap with the part of the first t-coil in the vertical direction. a first distance from the semiconductor substrate to the first position is different from a second distance from the semiconductor substrate to the second position. the first t-coil is configured to receive a first signal having a first polarity of a differential signal. the second t-coil is configured to receive a second signal having a second polarity different from the first polarity.
20240429921. SEMICONDUCTOR DEVICE AND COUNTING METHOD_simplified_abstract_(kioxia corporation)
Inventor(s): Yasuhiro HIRASHIMA of Kawasaki (JP) for kioxia corporation, Toshiyuki KOUCHI of Kawasaki (JP) for kioxia corporation, Junya MATSUNO of Yokohama (JP) for kioxia corporation, Masato DOME of Kamakura (JP) for kioxia corporation
IPC Code(s): H03K21/38, G06F1/12, H03K21/40
CPC Code(s): H03K21/38
Abstract: a semiconductor device including an oscillator configured to output a first signal, and circuitry configured to count a cycle number of the first signal osc. before the oscillator outputs an n-th (n is an integer equal to or larger than 2) cycle of the first signal, the circuitry changes a count value of the cycle number of the first signal to n.
20240431101. SEMICONDUCTOR DEVICE_simplified_abstract_(kioxia corporation)
Inventor(s): Mitsuhiro NOGUCHI of Yokohama Kanagawa (JP) for kioxia corporation, Masayuki AKOU of Yokohama Kanagawa (JP) for kioxia corporation
IPC Code(s): H10B41/41, G11C16/08, H10B43/40
CPC Code(s): H10B41/41
Abstract: a switch element configured to apply a voltage to and block a voltage from a gate electrode of a memory cell is provided. the e-type transistor includes a gate insulating film with a thickness in a range of 13 nm to 50 nm, a first current terminal, and a second current terminal. the e-type transistor includes a first source diffusion layer and a first drain diffusion layer having a first n-type impurity density and formed in a vicinity of the gate electrode; and a second source diffusion layer and a second drain diffusion layer having a second n-type impurity density higher than the first n-type impurity density. the second current terminal of the e-type transistor is electrically connected to a voltage source configured to provide a voltage equal to or larger than 15 v.
Inventor(s): Junichi KANEYAMA of Yokkaichi Mie (JP) for kioxia corporation, Tatsunori ISOGAI of Yokkaichi Mie (JP) for kioxia corporation
IPC Code(s): H10B43/27, H10B43/10, H10B43/35
CPC Code(s): H10B43/27
Abstract: a semiconductor storage device includes a stacked body in which electrode layers and first insulation layers are alternately stacked in a first direction. a semiconductor layer extends through the stacked body in the first direction. a second insulation layer is provided between the stacked body and the semiconductor layer. a third insulation layer is provided between the stacked body and the second insulation layer. a first thickness of the third insulation layer between the electrode layers and the second insulation layer is thicker than a second thickness of the third insulation layer between the first insulation layers and the second insulation layer. fourth insulation layers are provided between the electrode layers and the third insulation layer. a fifth insulation layer is provided between an electrode layer and the first insulation layers adjacent to the electrode layer and between the electrode layer and one of the fourth insulation layers.
Inventor(s): Koichi YAMAMOTO of Yokkaichi Mie (JP) for kioxia corporation
IPC Code(s): H10B43/27
CPC Code(s): H10B43/27
Abstract: a semiconductor storage device includes a stacked body in which a plurality of conductive layers are stacked one layer apart from each other and which has a staircase portion in which the plurality of conductive layers have been processed into a staircase shape, a first pillar that extends in a stacking direction of the stacked body in a portion of the stacked body different from the staircase portion and forms memory cells at each intersection between the first pillar and at least a part of the plurality of conductive layers, a plurality of second pillars that are arranged with periodicity in the staircase portion and extend in the stacking direction within the stacked body, and a contact having a diameter larger than a distance between the plurality of second pillars, that is disposed in the staircase portion and that is electrically connected to one of the plurality of conductive layers.
Kioxia Corporation patent applications on December 26th, 2024
- Kioxia Corporation
- G01B15/04
- G03F1/86
- G03F7/00
- G06F30/32
- G06T7/00
- G06T7/12
- G06T7/50
- CPC G01B15/04
- Kioxia corporation
- G03F1/26
- G03F1/48
- G03F1/80
- CPC G03F1/26
- G03F1/32
- G03F1/36
- G03F1/60
- G03F1/70
- CPC G03F1/32
- CPC G03F7/0002
- G03F7/16
- H01L21/027
- H01L21/311
- G06F12/02
- CPC G06F12/0246
- G06F17/16
- CPC G06F17/16
- G06F21/31
- G06F21/60
- CPC G06F21/31
- G06F21/64
- G06F21/79
- CPC G06F21/64
- G11C11/16
- H10B61/00
- CPC G11C11/1659
- G11C5/06
- CPC G11C11/1673
- G11C11/4074
- G11C5/14
- G11C7/22
- G11C11/409
- G11C29/02
- G11C29/50
- CPC G11C11/4074
- G11C16/04
- H10B43/27
- H10B43/35
- CPC G11C16/0483
- G11C16/26
- G11C16/08
- G11C16/30
- H10B43/10
- CPC G11C16/26
- G11C16/34
- G11C16/20
- CPC G11C16/3404
- G11C16/16
- CPC G11C16/3445
- G11C29/38
- G06F13/16
- CPC G11C29/38
- H01J37/32
- CPC H01J37/32715
- H01L21/67
- H01L21/66
- CPC H01L21/67253
- H01L23/31
- H01L21/304
- H01L25/00
- H01L25/065
- H01L25/16
- CPC H01L23/3114
- H01L21/56
- H01L21/762
- H01L23/00
- H01L23/29
- H01L23/498
- H01L23/528
- CPC H01L23/3128
- H01L23/522
- H10B41/27
- CPC H01L23/5226
- H01L23/48
- H01L23/538
- H01L25/10
- H10B80/00
- CPC H01L24/14
- H01L27/02
- G06F30/327
- H01L27/118
- CPC H01L27/0207
- H10B41/00
- CPC H01L28/10
- H03K21/38
- G06F1/12
- H03K21/40
- CPC H03K21/38
- H10B41/41
- H10B43/40
- CPC H10B41/41
- CPC H10B43/27
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