KIOXIA CORPORATION patent applications on September 5th, 2024
Patent Applications by KIOXIA CORPORATION on September 5th, 2024
KIOXIA CORPORATION: 15 patent applications
KIOXIA CORPORATION has applied for patents in the areas of H01L23/00 (5), G11C16/04 (4), G06F3/06 (4), H10B80/00 (3), G11C16/26 (3) H10B43/27 (2), G05F3/24 (1), G06F3/0619 (1), G06F3/0647 (1), G06F3/0659 (1)
With keywords such as: layer, memory, substrate, semiconductor, direction, lines, bit, device, forming, and including in patent application abstracts.
Patent Applications by KIOXIA CORPORATION
Inventor(s): Koji OOIWA of Yokohama (JP) for kioxia corporation
IPC Code(s): G05F3/24, G06F13/16, G11C16/04
CPC Code(s): G05F3/24
Abstract: according to one embodiment, a voltage generation circuit includes a voltage dividing circuit, a first current path, a second current path, a first output terminal, a second output terminal, and a switching circuit. the first current path is in parallel with the voltage dividing circuit between a first node connected to a power source line and a second node. the second current path is in parallel with the voltage dividing circuit between a third node and a fourth node. the first output terminal is connected to the second node. the second output terminal is connected to the third node. the switching circuit is configured to switch connection of the first current path and the second current path. the first node, the second node, the third node, and the fourth node are connected in series in the voltage dividing circuit.
Inventor(s): Suguru NISHIKAWA of Tokyo (JP) for kioxia corporation, Takehiko AMAKI of Yokohama (JP) for kioxia corporation, Shunichi IGAHARA of Fujisawa (JP) for kioxia corporation, Toshikatsu HIDA of Kawasaki (JP) for kioxia corporation, Yoshihisa KOJIMA of Kawasaki (JP) for kioxia corporation
IPC Code(s): G06F3/06
CPC Code(s): G06F3/0619
Abstract: according to an embodiment, a memory system includes a nonvolatile memory and a memory controller. the nonvolatile memory includes a first memory cell configured to nonvolatilely store data of a plurality of bits including a first bit and a second bit, and a second memory cell configured to nonvolatilely store data of at least one bit. the memory controller is configured to execute a save operation in accordance with reception of a command from a host, in the save operation, write first bit data to the second memory cell in a case where the first memory cell stores the first bit data as the first bit and does not store data as the second bit, and transmit, to the host, a completion response to the command after the first bit data has been written to the second memory cell.
Inventor(s): Atsushi YAMAZAKI of Hachioji Tokyo (JP) for kioxia corporation, Kentaro UMESAWA of Kawasaki Kanagawa (JP) for kioxia corporation, Naoko YAMADA of Yokohama Kanagawa (JP) for kioxia corporation, Yuta KAGEYAMA of Yokohama Kanagawa (JP) for kioxia corporation
IPC Code(s): G06F3/06, G06F11/26
CPC Code(s): G06F3/0647
Abstract: a memory system comprising a first storage region which stores first firmware corresponding to an external first electronic control apparatus; a second storage region which stores second firmware corresponding to an external gateway and third firmware corresponding to the first electronic control apparatus; and a controller configured to transmit the second firmware and the third firmware to the gateway on the basis of a first command received from the gateway, and transmit the first firmware to the gateway on the basis of a second command received from the gateway.
Inventor(s): Shinichi KANNO of Ota (JP) for kioxia corporation
IPC Code(s): G06F3/06
CPC Code(s): G06F3/0659
Abstract: according to one embodiment, a memory system checks a first total size indicative of a sum of data lengths specified by first write commands stored in a first submission queue of a host corresponding to a first stream. when the first total size is greater than or equal to a minimum write size, the memory system fetches a set of first write commands stored in the first submission queue, transfers first write data associated with the set of first write commands from a memory of the host to the memory system, and writes the first write data into a first write destination block allocated for the first stream.
20240296888. SEMICONDUCTOR STORAGE DEVICE_simplified_abstract_(kioxia corporation)
Inventor(s): Hiroshi MAEJIMA of Setagaya Tokyo (JP) for kioxia corporation
IPC Code(s): G11C16/04, G11C5/06, G11C7/06, G11C16/08, G11C16/26, H01L23/522, H01L23/528, H10B43/10, H10B43/27, H10B43/35, H10B43/40
CPC Code(s): G11C16/0483
Abstract: a semiconductor storage device includes word lines extending in first and second directions, and separated from each other in a third direction, sense amplifier circuits that partially overlap the word lines in the third direction, memory strings intersecting the word lines and extending in the third direction, memory-side bit lines extending in the first direction, separated from each other in the second direction, and including first and second adjacent memory-side bit lines, circuit-side bit lines between the word lines and the sense amplifier circuits and partially overlapping the respective memory-side bit lines in the third direction, and contact plugs extending in the third direction and respectively connecting the memory-side bit lines and the circuit-side bit lines. the contact plugs include first and second contract plugs that are electrically connected to the first and second memory-side bit lines, respectively, and are not aligned along the first or second direction.
20240296893. SEMICONDUCTOR MEMORY DEVICE_simplified_abstract_(kioxia corporation)
Inventor(s): Naoya TOKIWA of Fujisawa Kanagawa (JP) for kioxia corporation
IPC Code(s): G11C16/16, G11C16/04, G11C16/06, G11C16/08, G11C16/10, G11C16/26, G11C16/34
CPC Code(s): G11C16/16
Abstract: a semiconductor memory device includes a memory block, a plurality of bit lines, a plurality of select gate lines, a plurality of word lines, and a controller. the memory block includes a plurality of memory strings, each memory string including a selection transistor and a plurality of memory cells. the plurality of bit lines are arranged in the first direction and connected to the respective memory strings. the plurality of select gate lines are arranged in the second direction and connected to gates of the respective selection transistors of the memory strings. the plurality of word lines are arranged in the third direction and connected to gates of the respective memory cells of the memory strings. the controller is configured to perform an erase operation in a unit of the memory block, and perform a sequence of erase verify operations.
20240296895. SEMICONDUCTOR MEMORY_simplified_abstract_(kioxia corporation)
Inventor(s): Noboru SHIBATA of Kawasaki Kanagawa (JP) for kioxia corporation, Hironori UCHIKAWA of Fujisawa Kanagawa (JP) for kioxia corporation, Taira SHIBUYA of Fujisawa Kanagawa (JP) for kioxia corporation
IPC Code(s): G11C16/26, G06F3/06, G11C16/04, G11C16/08, G11C16/10, G11C16/32, G11C16/34, H10B69/00
CPC Code(s): G11C16/26
Abstract: a semiconductor memory includes a first memory cell configured to be set with a first threshold voltage, the first threshold voltage being one of different threshold voltage levels, a second memory cell configured to be set with a second threshold voltage, the second threshold voltage being one of different threshold voltage levels, a first word line coupled to the first memory cell, a second word line coupled to the second memory cell, and a controller configured to read data of one of different bits based on a combination of the first threshold voltage of the first memory cell and the second threshold voltage of the second memory cell.
20240297045. METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE_simplified_abstract_(kioxia corporation)
Inventor(s): Yoshio MIZUTA of Yokkaichi (JP) for kioxia corporation, Sadatoshi MURAKAMI of Yokkaichi (JP) for kioxia corporation
IPC Code(s): H01L21/268, H01L21/683, H01L21/762, H01L21/78, H01L23/00, H01L25/065, H10B80/00
CPC Code(s): H01L21/268
Abstract: according to one embodiment, there is provided a method of manufacturing a semiconductor device. the method includes preparing a first substrate on which multiple projections distributed in a two-dimensional fashion are formed. the method includes stacking a first film over the multiple projections on the first substrate. the method includes stacking a second film on a second substrate. the method includes bonding a principal surface of the first film which is disposed on an opposite side of the first substrate to a principal surface of the second film which is disposed on an opposite side of the second substrate. the method includes performing irradiation with a laser beam from the first substrate. the method includes peeling the first substrate. a diameter of a spot area formed by the laser beam is larger than an average pitch between the projections arranged on the principal surface of the first substrate.
Inventor(s): Mariko SUMIYA of Yokkaichi Mie (JP) for kioxia corporation, Takuro OKUBO of Yokkaichi Mie (JP) for kioxia corporation
IPC Code(s): H01L21/78, H01L21/02, H01L21/3205, H01L21/321, H01L21/3213, H01L21/683, H01L21/762, H01L23/00, H10B80/00
CPC Code(s): H01L21/7813
Abstract: in one embodiment, a method of manufacturing a semiconductor device includes forming a first insulator or a first conductor layer on a first substrate, forming a porous layer on the first insulator or the first conductor layer, forming a first film including a first device, above the porous layer, and forming a second film including a second device, on a second substrate. the method further includes bonding the first substrate and the second substrate to sandwich the first insulator or the first conductor layer, the porous layer, the first film, and the second film. the method further includes separating the first substrate and the second substrate such that the first insulator or the first conductor layer and a first portion of the porous layer remain above the first substrate, and a second portion of the porous layer remains above the second substrate.
20240297145. METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE_simplified_abstract_(kioxia corporation)
Inventor(s): Miki TOSHIMA of Nagoya (JP) for kioxia corporation, Sadatoshi MURAKAMI of Yokkaichi (JP) for kioxia corporation
IPC Code(s): H01L23/00, H01L21/762
CPC Code(s): H01L24/80
Abstract: a method of manufacturing a semiconductor device according to one embodiment includes: forming, on a first substrate, a first layer having a refractive index lower than a refractive index of the first substrate; forming, on the first layer, a second layer having a refractive index lower than a refractive index of the first layer; forming a first circuit layer on the second layer; bonding the first and second substrate after forming the first circuit layer; irradiating a back surface of the first substrate with a laser beam after bonding the first substrate and the second substrate; and peeling the first substrate so that the first circuit layer remains on a side of the second substrate after irradiating the back surface of the first substrate with the laser beam.
Inventor(s): Shota KONUMA of Yokkaichi Mie (JP) for kioxia corporation, Hiroshi FUJITA of Yokohama Kanagawa (JP) for kioxia corporation, Hisashi KATO of Yokkaichi Mie (JP) for kioxia corporation, Naomi YANAI of Kuwana Mie (JP) for kioxia corporation
IPC Code(s): H01L23/00, H01L21/265, H01L21/324, H10B80/00
CPC Code(s): H01L24/96
Abstract: according to one embodiment, a method for manufacturing a semiconductor device includes forming, on a substrate, an active layer in which a dopant is implanted; forming a porous layer by making the active layer porous by an anodization treatment; forming a device layer including at least a part of a configuration of the semiconductor device above the porous layer; and cleaving the porous layer to remove the substrate.
Inventor(s): Mitsuhiko NODA of Kuwana Mie (JP) for kioxia corporation, Saori KASHIWADA of Yokkaichi Mie (JP) for kioxia corporation
IPC Code(s): H10B43/27, H01L21/683, H01L23/00, H10B41/27, H10B41/35, H10B43/35
CPC Code(s): H10B43/27
Abstract: according to one embodiment, a method of manufacturing a semiconductor device includes: forming a laser peeling film above a first semiconductor substrate; forming, inside the laser peeling film, a thermal diffusion layer including a member has a coefficient of thermal conductivity higher than that of the laser peeling film is distributed in a plane parallel to a front surface of the first semiconductor substrate; forming a circuit layer including a semiconductor circuit above the laser peeling film; bonding the first and a second semiconductor substrates; applying a laser beam to a back surface of the first semiconductor substrate; and peeling the first semiconductor substrate to maintain the circuit layer on a side of the second semiconductor substrate.
Inventor(s): Yosuke MITSUNO of Yokkaichi Mie (JP) for kioxia corporation, Ryouji MASUDA of Yokkaichi Mie (JP) for kioxia corporation, Tatsufumi HAMADA of Nagoya Aichi (JP) for kioxia corporation, Tomohiro KUKI of Yokkaichi Mie (JP) for kioxia corporation, Yusuke MORIKAWA of Yokkaichi Mie (JP) for kioxia corporation
IPC Code(s): H10B43/27
CPC Code(s): H10B43/27
Abstract: a semiconductor memory device has a chip shape. a stacked body is formed by alternately stacking, in a first direction, a plurality of first insulating layers and a plurality of first conductive layers each of which functions as a control gate of a memory cell transistor. a first columnar body extends in the first direction in the stacked body and includes a first semiconductor portion. an insulating film is provided at an end portion of the semiconductor memory device. a second columnar body extends in the first direction in the insulating film and includes a second semiconductor portion that is shorter than the first semiconductor portion in the first direction. an impurity concentration of the second semiconductor portion at a bottom portion of the second columnar body is higher than that of the first semiconductor portion at an intersection portion between the first columnar body and the first conductive layer.
20240298450. MEMORY DEVICE_simplified_abstract_(kioxia corporation)
Inventor(s): Haruka SAKUMA of Yokkaichi Mie (JP) for kioxia corporation, Masumi SAITOH of Yokohama Kanagawa (JP) for kioxia corporation, Kouji MATSUO of Ama Aichi (JP) for kioxia corporation
IPC Code(s): H10B53/20, H01L21/28, H01L23/528, H01L29/51, H10B53/10
CPC Code(s): H10B53/20
Abstract: a memory device includes: a first electrode layer extending in a first direction intersecting a surface of a substrate; a second electrode layer extending in the first direction; a first conductive layer surrounding the first electrode layer and the second electrode layer; a first insulating layer between the first electrode layer and the first conductive layer, surrounding the first electrode layer, and including hafnium oxide and/or zirconium oxide; a second insulating layer between the second electrode layer and the first conductive layer, surrounding the second electrode layer, and including hafnium oxide and/or zirconium oxide; a first gate electrode layer extending in the first direction, a first semiconductor layer surrounding the first gate electrode layer and electrically connected to the first conductive layer; and a first gate insulating layer between the first gate electrode layer and the first semiconductor layer and surrounding the first gate electrode layer.
20240298549. MAGNETIC DEVICE AND MAGNETIC STORAGE DEVICE_simplified_abstract_(kioxia corporation)
Inventor(s): Rina NOMOTO of Bunkyo Tokyo (JP) for kioxia corporation, Hideyuki SUGIYAMA of Kawasaki Kanagawa (JP) for kioxia corporation, Daisuke WATANABE of Yokkaichi Mie (JP) for kioxia corporation, Bao NGUYEN VIET of Yokohama Kanagawa (JP) for kioxia corporation, Youngmin EEH of Kawagoe Saitama (JP) for kioxia corporation, Masaru TOKO of Kodaira Tokyo (JP) for kioxia corporation, Taiga ISODA of Yokohama Kanagawa (JP) for kioxia corporation
IPC Code(s): H10N50/85, H10B61/00, H10N50/20
CPC Code(s): H10N50/85
Abstract: a magnetic device includes a first magnetic layer, a second magnetic layer, and a nonmagnetic layer between the first and second magnetic layers and including: a first layer in contact with the first magnetic layer and including a magnesium oxide, a second layer in contact with the second magnetic layer and including a magnesium oxide, and a third layer between the first and second layers and including a scandium nitride.
KIOXIA CORPORATION patent applications on September 5th, 2024
- KIOXIA CORPORATION
- G05F3/24
- G06F13/16
- G11C16/04
- CPC G05F3/24
- Kioxia corporation
- G06F3/06
- CPC G06F3/0619
- G06F11/26
- CPC G06F3/0647
- CPC G06F3/0659
- G11C5/06
- G11C7/06
- G11C16/08
- G11C16/26
- H01L23/522
- H01L23/528
- H10B43/10
- H10B43/27
- H10B43/35
- H10B43/40
- CPC G11C16/0483
- G11C16/16
- G11C16/06
- G11C16/10
- G11C16/34
- CPC G11C16/16
- G11C16/32
- H10B69/00
- CPC G11C16/26
- H01L21/268
- H01L21/683
- H01L21/762
- H01L21/78
- H01L23/00
- H01L25/065
- H10B80/00
- CPC H01L21/268
- H01L21/02
- H01L21/3205
- H01L21/321
- H01L21/3213
- CPC H01L21/7813
- CPC H01L24/80
- H01L21/265
- H01L21/324
- CPC H01L24/96
- H10B41/27
- H10B41/35
- CPC H10B43/27
- H10B53/20
- H01L21/28
- H01L29/51
- H10B53/10
- CPC H10B53/20
- H10N50/85
- H10B61/00
- H10N50/20
- CPC H10N50/85
