KABUSHIKI KAISHA TOSHIBA patent applications on March 21st, 2024
Patent Applications by KABUSHIKI KAISHA TOSHIBA on March 21st, 2024
KABUSHIKI KAISHA TOSHIBA: 91 patent applications
KABUSHIKI KAISHA TOSHIBA has applied for patents in the areas of H01L29/7813 (11), H01L29/78 (11), C25B9/19 (10), C25B1/04 (8), H01L29/66 (8)
With keywords such as: electrode, semiconductor, region, layer, data, device, between, surface, embodiment, and portion in patent application abstracts.
Patent Applications by KABUSHIKI KAISHA TOSHIBA
20240091736.SEQUESTRATION SYSTEM_simplified_abstract_(kabushiki kaisha toshiba)
Inventor(s): Ryota KITAGAWA of Setagaya Tokyo (JP) for kabushiki kaisha toshiba, Naoya FUJIWARA of Toshima Tokyo (JP) for kabushiki kaisha toshiba, Yusuke KOFUJI of Hiratsuka Kanagawa (JP) for kabushiki kaisha toshiba, Akihiko ONO of Kita Tokyo (JP) for kabushiki kaisha toshiba, Satoshi MIKOSHIBA of Yamato Kanagawa (JP) for kabushiki kaisha toshiba
IPC Code(s): B01J19/24, C25B1/04, C25B1/23, C25B9/19, C25B15/021, C25B15/08
Abstract: a sequestration system includes: an electrolysis part having an electrolysis cell having an anode, a cathode, an anode flow path facing on the anode, and a cathode flow path facing on the cathode; and a reaction part configured to switch a first operation and a second operation, the first operation including producing solid carbon using a catalyst from a first raw material containing a first fluid to be introduced from the cathode flow path, and the second operation including performing a reaction of a second raw material containing a second fluid to be introduced from the anode flow path and solid carbon to be deposited on the catalyst to remove at least a part of the deposited solid carbon from the catalyst.
20240092181.SOLAR CELL SYSTEM AND VEHICLE SYSTEM_simplified_abstract_(kabushiki kaisha toshiba)
Inventor(s): Kenichirou OGAWA of Kawasaki Kanagawa (JP) for kabushiki kaisha toshiba, Tetsu SHIJO of Setagaya Tokyo (JP) for kabushiki kaisha toshiba, Yasuhiro KANEKIYO of Yokohama Kanagawa (JP) for kabushiki kaisha toshiba
IPC Code(s): B60L8/00, B60L53/60
Abstract: according to one embodiment, a solar cell system includes a first solar cell, a first electric circuit and controller. the first solar cell is provided on a hood of a vehicle. the first electric circuit is connected to the first solar cell. the controller is configured to electrically connect the first solar cell with the first electric circuit in a case where a traveling speed of the vehicle is less than a first threshold, and electrically disconnect the first solar cell from the first electric circuit in a case where the traveling speed of the vehicle is equal to or greater than the first threshold.
20240092213.CHARGE/DISCHARGE SYSTEM AND MOVING BODY_simplified_abstract_(kabushiki kaisha toshiba)
Inventor(s): Masaaki ISHIDA of Kawasaki Kanagawa (JP) for kabushiki kaisha toshiba, Tetsu SHIJO of Setagaya Tokyo (JP) for kabushiki kaisha toshiba, Kenichirou OGAWA of Kawasaki Kanagawa (JP) for kabushiki kaisha toshiba
IPC Code(s): B60L53/64, G06Q50/06, H02J7/00
Abstract: according to one embodiment, a charge/discharge system includes a storage battery and a control device. the storage battery is configured to absorb co2 during charging and release co2 during discharging. the control device is configured to control a charge/discharge operation of the storage battery. the control device is configured to calculate a power trading price. the control device is configured to calculate a power trading price. the control device is configured to control the charge/discharge operation of the storage battery to perform charging and discharging when the power trading price during charging is lower than the power trading price during discharging.
Inventor(s): Tatsuro SAITO of Kawasaki (JP) for kabushiki kaisha toshiba
IPC Code(s): C12Q1/00, G01N27/414, G01N33/00
Abstract: according to one embodiment, a sensing device includes a component incorporating unit, enzyme-immobilized tank, an enzyme capture tank, a substrate tank and a sensor.
Inventor(s): Norihiro YOSHINAGA of Yokohama Kanagawa (JP) for kabushiki kaisha toshiba, Yoshitsune SUGANO of Kawasaki Kanagawa (JP) for kabushiki kaisha toshiba, Taishi FUKAZAWA of Chofu Tokyo (JP) for kabushiki kaisha toshiba, Yasuharu HOSONO of Kawasaki Kanagawa (JP) for kabushiki kaisha toshiba
IPC Code(s): C25B11/093, C25B9/19, C25B11/031
Abstract: a laminated catalyst according to an embodiment includes an oxide layer, a first catalyst layer on the oxide layer and a second catalyst layer on the first catalyst layer. the oxide layer is a layer of oxide including one or more non-noble metals as a main component. the first catalyst layer includes an oxide of noble metal including ir and/or ru as a main component. the second catalyst layer includes an oxide of noble metal including ir and/or ru as a main component. the first catalyst layer is denser than the second catalyst layer.
Inventor(s): Norihiro YOSHINAGA of Yokohama Kanagawa (JP) for kabushiki kaisha toshiba, Akihiko ONO of Kita Tokyo (JP) for kabushiki kaisha toshiba, Yoshitsune SUGANO of Kawasaki Kanagawa (JP) for kabushiki kaisha toshiba, Yoshihiko NAKANO of Yokohama Kanagawa (JP) for kabushiki kaisha toshiba, Hiroaki HIRAZAWA of Kawasaki Kanagawa (JP) for kabushiki kaisha toshiba
IPC Code(s): C25B13/02, C25B9/19, C25B11/031, C25B11/056, C25B11/063, C25B11/091
Abstract: a membrane electrode assembly according to an embodiment includes a first electrode, a second electrode, an electrolyte membrane provided between the first electrode and the second electrode and a first seal provided on a peripheral portion of the first electrode, having a first opening, housing the first electrode in the first opening, and being contact with the electrolyte membrane or the first seal and a second seal provided on a peripheral portion of the second electrode, having a second opening, housing the second electrode in the second opening, and being contact with the electrolyte membrane.
20240093393.HYDROGEN SYSTEM OPERATION PLANNING DEVICE_simplified_abstract_(kabushiki kaisha toshiba)
Inventor(s): Junsuke BABA of Fuchu Tokyo (JP) for kabushiki kaisha toshiba, Takashi AKIBA of Kawasaki Kanagawa (JP) for kabushiki kaisha toshiba, Fumiyuki YAMANE of Kawasaki Kanagawa (JP) for kabushiki kaisha toshiba
IPC Code(s): C25B15/02, C25B1/04
Abstract: to accurately prepare an operation plan that achieves efficient operation in a hydrogen system. in a hydrogen system operation planning device of an embodiment, an acquisition unit is configured to acquire performance data regarding performance of a plurality of hydrogen production devices and tentative operation plan data regarding a tentative operation plan tentatively prepared for the operation plan. a prediction unit is configured to acquire performance prediction data by predicting the performance of the plurality of hydrogen production devices during the planning target period based on the performance data and tentative operation plan data acquired by the acquisition unit. a planning unit is configured to acquire the operation plan by correcting the tentative operation plan based on the performance prediction data acquired by the prediction of the prediction unit.
Inventor(s): Yasuhiro KIYOTA of Kawasaki Kanagawa (JP) for kabushiki kaisha toshiba, Akihiko ONO of Kita Tokyo (JP) for kabushiki kaisha toshiba, Satoshi MIKOSHIBA of Yamato Kanagawa (JP) for kabushiki kaisha toshiba, Ryota KITAGAWA of Setagaya Tokyo (JP) for kabushiki kaisha toshiba
IPC Code(s): C25B15/027, C25B1/04, C25B1/23, C25B1/27, C25B9/19, C25B15/08
Abstract: an electrolysis device includes: an electrolysis cell having a cathode flow path, an anode flow path, a cathode, an anode, and a diaphragm; an anode supply flow path; an anode discharge flow path; a cathode supply flow path; a cathode discharge flow path through which a cathode fluid flows; first to third pressure detectors; first and second pressure controllers that control pressures of the cathode and anode flow paths; a first gas/liquid separator that separates a reduction product from the cathode fluid; a gas detector that measures a concentration of the separated reduction product; and an arithmetic device that calculates pressure values of the anode and cathode flow paths based on the measured concentration and pressures, and controls the pressure controllers to adjust the pressures of the anode and cathode flow paths to the calculated pressure values.
Inventor(s): Yuki KUDO of Yokohama Kanagawa (JP) for kabushiki kaisha toshiba, Akihiko ONO of Kita Tokyo (JP) for kabushiki kaisha toshiba, Satoshi MIKOSHIBA of Yamato Kanagawa (JP) for kabushiki kaisha toshiba, Ryota KITAGAWA of Setagaya Tokyo (JP) for kabushiki kaisha toshiba
IPC Code(s): C25B15/027, C25B1/04, C25B1/23, C25B3/26, C25B9/19, C25B9/23, C25B9/65, C25B15/021, C25B15/029
Abstract: an electrolysis device of an embodiment includes: an electrolysis cell including a cathode part in which a reduction electrode is disposed, an anode part in which an oxidation electrode is disposed, and a diaphragm provided between the cathode part and the anode part; a supply power property obtaining unit that obtains a property of power that is to be supplied to the electrolysis cell; an input gas property obtaining unit that obtains a property of a gas that is to be input to the electrolysis cell; an electric property obtaining unit that obtains an electric property of the electrolysis cell; an output gas property obtaining unit that obtains a property of an output gas of the electrolysis cell; a temperature obtaining unit that obtains a temperature of the electrolysis cell; a data storage unit that stores data from the obtaining units; and a data processing unit to which the data is sent from the data storage unit and that processes the data to determine a state of the electrolysis cell.
Inventor(s): Wataru WATANABE of Tokyo (JP) for kabushiki kaisha toshiba, Keisuke KAWAUCHI of Kawasaki Kanagawa (JP) for kabushiki kaisha toshiba, Takayuki ITOH of Kawasaki Kanagawa (JP) for kabushiki kaisha toshiba, Jumpei ANDO of Yokohama Kanagawa (JP) for kabushiki kaisha toshiba, Toshiyuki ONO of Kawasaki Kanagawa (JP) for kabushiki kaisha toshiba
IPC Code(s): G01M99/00
Abstract: according to one embodiment, a manufacturing data analysis device includes processing circuitry. the processing circuitry acquires manufacturing data including a manufacturing condition data group and a quality data group. the processing circuitry calculates one or more degrees of influence exerted by first manufacturing condition data included in the manufacturing condition data group on respective pieces of quality data included in the quality data group by analyzing the manufacturing data. the processing circuitry, in a case where one or more degrees of influence satisfy a determination condition, generates output data related to at least one of the first manufacturing condition data, one or more pieces of quality data on which the first manufacturing condition data has exerted the degrees of influence satisfying the determination condition, or the degrees of influence satisfying the determination condition.
Inventor(s): Wataru WATANABE of Tokyo (JP) for kabushiki kaisha toshiba, Keisuke KAWAUCHI of Kawasaki Kanagawa (JP) for kabushiki kaisha toshiba, Takayuki ITOH of Kawasaki Kanagawa (JP) for kabushiki kaisha toshiba, Jumpei ANDO of Yokohama Kanagawa (JP) for kabushiki kaisha toshiba, Toshiyuki ONO of Kawasaki Kanagawa (JP) for kabushiki kaisha toshiba
IPC Code(s): G01M99/00
Abstract: according to one embodiment, a manufacturing data analysis device includes processing circuitry. the processing circuitry acquires, from manufacturing data related to a plurality of products, first manufacturing data under a first acquisition condition. the first manufacturing data includes manufacturing condition data related to a manufacturing condition for each of the products and quality data related to quality for each of the products. the processing circuitry determines a second acquisition condition different from the first acquisition condition based on the first manufacturing data. the processing circuitry acquires second manufacturing data including the manufacturing condition data and the quality data from the manufacturing data under the second acquisition condition. the processing circuitry calculates an analysis result of a relationship between the manufacturing condition data and the quality data by analyzing the second manufacturing data. the processing circuitry generates output data including the analysis result.
Inventor(s): Hiroshi OHNO of Tokyo (JP) for kabushiki kaisha toshiba, Hiroya KANO of Kawasaki Kanagawa (JP) for kabushiki kaisha toshiba, Hideaki OKANO of Yokohama Kanagawa (JP) for kabushiki kaisha toshiba
IPC Code(s): G01N21/25, G01N21/29
Abstract: according to an embodiment, an optical inspection apparatus includes: an illumination portion, a wavelength selection portion and an imaging portion. the illumination portion irradiates a first object point of a surface of an object with first illumination light, and a second object point of the surface of the object with second illumination light. the imaging portion images light from the first object point through the wavelength selection portion when a normal direction at the first object point and a direction of the first illumination light have an opposing relationship, and images light from the second object point through the wavelength selection portion when a normal direction at the second object point and a direction of the second illumination light have an opposing relationship.
Inventor(s): Hiroshi OHNO of Tokyo (JP) for kabushiki kaisha toshiba, Hiroya KANO of Kawasaki Kanagawa (JP) for kabushiki kaisha toshiba, Hideaki OKANO of Yokohama Kanagawa (JP) for kabushiki kaisha toshiba
IPC Code(s): G01N21/31, G06T5/00, G06T5/10, G06T5/20, G06T7/00
Abstract: according to an embodiment, a non-transitory storage medium stores an optical inspection program. the optical inspection program causes a processor to execute generating a wavelength selection portion-removed image by removing, from a captured image of an object surface imaged through a wavelength selection portion configured to select at least two different wavelength spectra from incident light, an image of the wavelength selection portion included in the captured image.
Inventor(s): Yuki UEDA of Yokohama Kanagawa (JP) for kabushiki kaisha toshiba, Takashi USUI of Saitama Saitama (JP) for kabushiki kaisha toshiba
IPC Code(s): G01N29/07, G01N29/12
Abstract: according to one embodiment, a structure evaluation system of an embodiment includes one or more sensors, a signal processing apparatus, and an evaluator. the plurality of sensors detect elastic waves generated from a structure. the signal processing apparatus calculates information on a frequency distribution by amplitude scale based on the plurality of elastic waves detected by each of the one or more sensors, and transmits the calculated information on the frequency distribution by amplitude scale in a wireless manner. the evaluator evaluates a state of deterioration of the structure based on the information on the frequency distribution by amplitude scale which is transmitted from the signal processing apparatus.
Inventor(s): Takashi USUI of Saitama Saitama (JP) for kabushiki kaisha toshiba, Hidefumi TAKAMINE of Shinagawa Tokyo (JP) for kabushiki kaisha toshiba, Kazuo WATABE of Yokohama Kanagawa (JP) for kabushiki kaisha toshiba, Tetsuya KUGIMIYA of Kawasaki Kanagawa (JP) for kabushiki kaisha toshiba
IPC Code(s): G01N29/14, G01N29/04, G01N29/44
Abstract: according to one embodiment, a structure evaluation system according to an embodiment includes a plurality of sensors, a position locator, a corrector, and an evaluator. the plurality of sensors detect elastic waves generated from a structure. the position locator is configured to locate positions of sources of a plurality of elastic waves detected by the plurality of sensors on the basis of the plurality of elastic waves. the corrector is configured to correct information based on the position location in the position locator using a correction value which is determined according to a temperature of the structure. the evaluator is configured to evaluate a deterioration state of the structure on the basis of the corrected information.
Inventor(s): Keita SASAKI of Yokohama Kanagawa (JP) for kabushiki kaisha toshiba, Mariko SHIMIZU of Setagaya Tokyo (JP) for kabushiki kaisha toshiba, Kazuhiro SUZUKI of Meguro Tokyo (JP) for kabushiki kaisha toshiba
IPC Code(s): G01S7/481, G01S17/08
Abstract: a light detector according to one embodiment, includes a substrate. the substrate includes a first semiconductor layer, an insulating layer, and a second semiconductor layer. the insulating layer is located on the first semiconductor layer. the second semiconductor layer is located on the insulating layer. the second semiconductor layer includes a photoelectric conversion part. the photoelectric conversion part includes a first semiconductor region and a second semiconductor region. the substrate includes a void and a trench. the void is positioned below the photoelectric conversion part and between the first semiconductor layer and the second semiconductor layer. the trench surrounds the photoelectric conversion part. a lower end of the trench is positioned in the second semiconductor layer. the photoelectric conversion part is electrically connected with an upper surface side of the substrate via a portion below the trench.
Inventor(s): Takashi SEKI of Yokohama Kanagawa (JP) for kabushiki kaisha toshiba, Akira MORIYA of Kawasaki Kanagawa (JP) for kabushiki kaisha toshiba, Kazuhiro TSUJIMURA of Kawasaki Kanagawa (JP) for kabushiki kaisha toshiba, Ryota SEKIYA of Kamakura Kanagawa (JP) for kabushiki kaisha toshiba, Hiroki MORI of Kawasaki Kanagawa (JP) for kabushiki kaisha toshiba
IPC Code(s): G01S13/34, G01S7/35
Abstract: according to one embodiment, a radar device comprises a panel including clusters and a controller. the controller is configured to cause a first cluster of the clusters to transmit an electromagnetic wave to a target, cause the first cluster and at least one second cluster adjacent to the first cluster to receive a reflected wave from the target, and cause the first cluster and the at least one second cluster to output a reception signal. at least one cluster other than the first cluster and other than the at least one second cluster does not output the reception signal.
Inventor(s): Hiroki MORI of Kawasaki Kanagawa (JP) for kabushiki kaisha toshiba
IPC Code(s): G01S13/88, G01S13/89, G01V3/12, G01V8/00
Abstract: according to one embodiment, a security inspection system includes a determination device and a control device. the determination device performs first determination regarding whether a target has a predetermined object. the control device controls a passage management device which performs second determination regarding whether the target has been permitted to pass. the control device transmits a second signal to the determination device when receiving a first signal from the passage management device. the first signal indicates a start of the second determination. the determination device starts the first determination when receiving the second signal.
Inventor(s): Shota OCHI of Yokohama Kanagawa (JP) for kabushiki kaisha toshiba, Noritsugu SHIOKAWA of Yokohama Kanagawa (JP) for kabushiki kaisha toshiba, Yoshimasa EGASHIRA of Yokohama Kanagawa (JP) for kabushiki kaisha toshiba, Masakazu WADA of Yokohama Kanagawa (JP) for kabushiki kaisha toshiba, Tetsuya KOBAYASHI of Nerima Tokyo (JP) for kabushiki kaisha toshiba
IPC Code(s): G01W1/10, G01S13/95, G01W1/02, G01W1/14
Abstract: according to one embodiment, an information processing apparatus includes a processing circuitry. the processing circuitry is configured to acquire first and second weather data in a first time zone and ground rainfall amount data, acquire, based on the first and second weather data, first feature values, generate learning data based on the ground rainfall amount data and the first feature values, generate, based on the learning data, a learned model, acquire first and second weather data in a second time zone, acquire, based on the first and second weather data, second feature values, acquire a parameter output from the learned model by inputting the plurality of second feature values, and generate, based on the parameter, composite rainfall amount data.
Inventor(s): Yoshinari HIGASHINO of Chigasaki Kanagawa (JP) for kabushiki kaisha toshiba
IPC Code(s): G05B23/02, G11B20/18
Abstract: according to an embodiment, there is provided a failure diagnosis method. the failure diagnosis method includes installing a disk device in a manufacturing rack. the failure diagnosis method acquiring, by the disk device, data on a state of a predetermined constituent unit in the manufacturing rack with the disk device being installed in the manufacturing rack. the failure diagnosis method includes determining, by the disk device, whether or not the state of the predetermined constituent unit falls within an allowable range by using the data acquired.
20240094755.SIGNAL TRANSMISSION DEVICE_simplified_abstract_(kabushiki kaisha toshiba)
Inventor(s): Tatsuhiro OGAWA of Kawasaki Kanagawa (JP) for kabushiki kaisha toshiba
IPC Code(s): G05F1/607, H03K17/687
Abstract: a transmission buffer of a signal transmission device according to the embodiment includes: a differential circuit portion that is connected between the first potential and the second potential; a variable current source portion that supplies current to the differential circuit portion; a switch port that switches between a conductive state and a disconnected state between the first transmission terminal and the fixed potential and between the second transmission terminal and the fixed potential; and a controller that controls the current supplied by the variable current source portion to the differential circuit portion, and that controls the operation of the switch portion.
Inventor(s): Hiroaki KOMAKI of Tachikawa (JP) for kabushiki kaisha toshiba
IPC Code(s): G06F3/01, A61B5/398, H04N13/344
Abstract: according to one embodiment, an eye movement detecting device comprises first, second, third, fourth and fifth electrodes. a line connecting the first and the third electrodes passes through the right eye and a line connecting the second and the fourth electrodes passes through the left eye on at least one of a front view, a plan view or a side view. a distance between the fifth and the first electrodes is equal to a distance between the fifth and the second electrodes. a distance between the fifth and the third electrodes is equal to a distance between the fifth and the fourth electrodes. the detector respectively detects a horizontal movement of the right eye and a horizontal movement of the left eye.
20240094833.TRAJECTORY INPUT SYSTEM_simplified_abstract_(kabushiki kaisha toshiba)
Inventor(s): Junichi TAKEDA of Yokohama Kanagawa (JP) for kabushiki kaisha toshiba, Koji RYUGO of Yokohama Kanagawa (JP) for kabushiki kaisha toshiba
IPC Code(s): G06F3/0354, G06F3/01, G06F3/041
Abstract: a trajectory input system of an embodiment includes a plurality of pen-shaped terminals that respectively store unique id data; and a display configured to receive trajectory data inputted by one of the plurality of pen-shaped terminals that contacts a surface of the display, in which the pen-shaped terminal detects input of the trajectory data to the display while the pen-shaped terminal is in proximity to the surface of the display and is within 10 mm from the surface of the display or while the pen-shaped terminal is in contact with the surface of the display, and transmits the unique id data to the display, and the display manages the trajectory data by linking the unique id to the trajectory data.
Inventor(s): Mikio HASHIMOTO of Bunkyo Tokyo (JP) for kabushiki kaisha toshiba, Atsushi SHIMBO of Bunkyo Tokyo (JP) for kabushiki kaisha toshiba, Jiro AMEMIYA of Machida Tokyo (JP) for kabushiki kaisha toshiba
IPC Code(s): G06F11/10, H04L9/14, H04L9/30
Abstract: according to one embodiment, an information processing apparatus is allowed to access a storage device storing time-series data generated by a first device. the information processing apparatus includes a processor holding a first public key and a first private key. the processor is configured to acquire a program for correcting an error in first data on a first product from a first entity. the processor is configured to correct the correction target first data, using data in a predetermined range of the time-series data. the processor is configured to generate ground data indicating correction grounds for the corrected correction target first data, based on the data in the predetermined range, and add the ground data to the corrected correction target first data.
Inventor(s): Masaru SUZUKI of Ota Tokyo (JP) for kabushiki kaisha toshiba
IPC Code(s): G06F17/11
Abstract: a 0-1 combinatorial-optimization-problem is solved under constraint-conditions expressed using inequality expressions. a solution-finding device includes an updating-unit and an output-unit. for each of plural elements associated with first- and second-variables, the updating-unit sequentially updates, for each unit-time between initial-timing and end-timing, the first-variable and the second-variable alternatively. the output-unit outputs the solution of the 0-1 combinatorial-optimization-problem based on the first-variable of each of the plural elements at the end-timing. during the updating operation for each unit-time, for each of one or more constraint-conditions, when the inequality expression in which the first-variable corresponding to each of the plural discrete variables is substituted is unsatisfied; the updating-unit subtracts, from the second-variable of each of the plural elements, a correction value corresponding to the component of the element corresponding to the distance from the boundary of the inequality expression to positions identified by the plural elements.
Inventor(s): Tatsuya UEHARA of Kawasaki Kanagawa (JP) for kabushiki kaisha toshiba, Jun KANAI of Inagi Tokyo (JP) for kabushiki kaisha toshiba, Ryuiti KOIKE of Kawasaki Kanagawa (JP) for kabushiki kaisha toshiba
IPC Code(s): G06F21/57, G06F21/54
Abstract: an information processing apparatus according to one embodiment, includes: a vulnerability database storing vulnerability information including a vulnerability identifier for uniquely specifying vulnerability, a software identifier for uniquely specifying software including the vulnerability, and vulnerability description indicating content of the vulnerability; a matching processor to specify, in the vulnerability database, vulnerability information matching a software identifier of a target software provided in target equipment; a causal component specifier to specify, from the vulnerability description in the vulnerability information specified by the matching processor, a causal component that is a cause of the vulnerability; a type determiner to determine a type of the causal component from a name of the specified causal component; and an output processor to determine, based on the software identifier of the target software and the type of the causal component, an investigation procedure concerning vulnerability of the target software and output information indicating the investigation procedure.
Inventor(s): Kentaro TAKAGI of Yokohama Kanagawa (JP) for kabushiki kaisha toshiba, Toshiyuki Oshima of Tokyo (JP) for kabushiki kaisha toshiba
IPC Code(s): G06N3/08, G06N3/045
Abstract: a representation learning apparatus executing: calculating a latent vector sx in a latent space of the target data x using a first model parameter, calculate a non-interest latent vector zx in a latent space of an non-interest feature included in the target data x and a non-interest latent vector zb in the latent space of a non-interest data using a second model parameter, calculate a similarity s obtained by correcting a similarity between the latent vector sx and its representative value s′x by a similarity between the latent vector zx and its representative value z′x, and a similarity s between the latent vector zb and its representative value z′b, and update the first and/or the second model parameter based on the loss function including the similarity s and s
Inventor(s): Yasutaka NISHIDA of Tama Tokyo (JP) for kabushiki kaisha toshiba, Fumihiko AIGA of Kawasaki Kanagawa (JP) for kabushiki kaisha toshiba
IPC Code(s): G06N10/60, G06N10/40
Abstract: quantum circuit includes 1st block and 2nd block. 1st block includes gate operation layer and measurement layer. gate operation layer includes encoding gate parameterized with encoding parameter including encoded input information for constructing 1st hf state, and transformation gate parameterized with learning parameter for transforming 1st hf state into 1st quantum state. measurement layer outputs measurement value of 1st quantum state. 2nd block includes gate operation layer. gate operation layer includes 2nd encoding gate parameterized with encoding parameter including encoded measurement value for constructing 2nd hf state, and transformation gate parameterized with learning parameter for transforming 2nd hf state into 2nd quantum state.
Inventor(s): Hiroshi ISOKAWA of Yokohama Kanagawa (JP) for kabushiki kaisha toshiba, Takuya MATSUMOTO of Kawasaki Kanagawa (JP) for kabushiki kaisha toshiba
IPC Code(s): G11B5/012
Abstract: according to one embodiment, a magnetic disk device includes magnetic disks, a plurality of magnetic heads, and a control unit. a plurality of magnetic heads each includes a heat-assist unit which applies a preheating current of such magnitude that data already written to the magnetic disk is not erased to a near-field optical element for the preheat time. the control unit measures the time elapsing from a start of write to the time when a value of an index indicating the quality of a recording signal of data written by the magnetic head converges to within a first threshold range, and adjusts the preheat time for each of the magnetic heads in such a manner that the measured lapse time becomes less than or equal to a second threshold.
20240096350.MAGNETIC RECORDING/REPRODUCING DEVICE_simplified_abstract_(kabushiki kaisha toshiba)
Inventor(s): Takuya MATSUMOTO of Kawasaki Kanagawa (JP) for kabushiki kaisha toshiba
IPC Code(s): G11B5/09, G11B13/08
Abstract: according to one embodiment, a magnetic recording/reproducing device comprises a magnetic head including an assist element and configured to perform assist recording by applying assist power to the assist element, a rotation driver configured to perform rotation drive of the magnetic recording medium, a rotation number controller, and an assist power controller. the assist recording is performed under a first condition including a first rotation number and a first assist power, or under a second condition including a second rotation number which is different from the first rotation number and a second assist power which is different from the first assist power.
20240096352.MAGNETIC DISK DEVICE AND METHOD_simplified_abstract_(kabushiki kaisha toshiba)
Inventor(s): Tomonari TASHIRO of Yokohama kanagawa (JP) for kabushiki kaisha toshiba
IPC Code(s): G11B5/40
Abstract: according to an embodiment, a magnetic disk device includes a first component and a second component. the first component operates at a voltage of a first value. the second component is connected to the first component by a power line for transmitting power to the first component, and operates at a voltage of a second value. in response to supply of the voltage of the second value, the second component outputs a voltage of a third value smaller than the first value to the power line and measures a fourth value, which is a value of current flowing through the power line. the second component starts output of the voltage of the first value to the power line when the fourth value is smaller than the first threshold, and stops output of the voltage to the power line when the fourth value is larger than the first threshold.
20240096353.DISK DEVICE WITH POSITIONED RAMP_simplified_abstract_(kabushiki kaisha toshiba)
Inventor(s): Hisashi HASEGAWA of Yokohama Kanagawa (JP) for kabushiki kaisha toshiba, Hideki YAMAGUCHI of Sagamihara Kanagawa (JP) for kabushiki kaisha toshiba, Sinji TUKADA of Kawasaki Kanagawa (JP) for kabushiki kaisha toshiba
IPC Code(s): G11B5/48
Abstract: in general, according to one embodiment, a disk device includes a magnetic disk, a magnetic head, a suspension, a ramp, a housing, and a screw. the suspension holds the magnetic head and moves to an unload position. the ramp includes an attachment tab with a through hole. the ramp holds the suspension at the unload position. the housing has a support surface with a screw hole to support the attachment tab. the screw includes a screw head, a screw shaft, and a first contact surface. the screw shaft extends from the screw head in a first direction and is fitted into the screw hole through the through hole. the first contact surface is located on the screw head, tapers in the first direction, and contacts the attachment tab. the screw holds the attachment tab in-between the support surface and the first contact surface.
20240096354.DISK DEVICE_simplified_abstract_(kabushiki kaisha toshiba)
Inventor(s): Yusuke NOJIMA of Yokohama Kanagawa (JP) for kabushiki kaisha toshiba
IPC Code(s): G11B5/48, G11B5/596
Abstract: according to one embodiment, a disk device includes a magnetic head, a piezoelectric element and a flexure. the piezoelectric element includes two electrodes. the flexure includes a first part and a second part that swings. the first part has a first surface to which a first electrode is joined. the second part has a second surface to which the magnetic head is joined. the magnetic head has a third surface facing the first surface and the second surface. the first electrode is spaced apart from a second electrode in a first direction. the first surface and an end of the third surface face each other. the second surface and another end of the third surface face each other. a distance between the first surface and the one end of the third surface is longer than a distance between the second surface and the other end of the third surface.
20240096355.DISK DEVICE_simplified_abstract_(kabushiki kaisha toshiba)
Inventor(s): Naoto AKATSUKA of Yokohama Kanagawa (JP) for kabushiki kaisha toshiba
IPC Code(s): G11B5/48
Abstract: a disk device includes magnetic disks, a magnetic head, a suspension, and a carriage. the suspension includes a flexible substrate on which the magnetic head is mounted. the carriage includes an arm to which the suspension is attached. the arm includes opposing first and second end surfaces, a side surface extending between the first end surface and the second end surface, and a protruding body that protrudes from the side surface and has a first surface parallel to and spaced apart from the first end surface and a second surface parallel to and spaced apart from the second end surface. the flexible substrate includes a strip extending along the side surface. the strip includes a portion positioned between the first end surface and the protruding body in the axial direction and is positioned between the first end surface and the second end surface in the axial direction.
Inventor(s): Tomoyuki TOKIZAKI of Yokohama Kanagawa (JP) for kabushiki kaisha toshiba
IPC Code(s): G11B5/48
Abstract: according to one embodiment, a disk device includes magnetic disks, a first head gimbal assembly, a first damper, and a carriage. the first head gimbal assembly includes a first magnetic head, a first load beam, and a first base plate. the first load beam supports the first magnetic head. the first base plate is connected to the first load beam. the first damper includes a first viscoelastic material, and a first member attached to the first viscoelastic material. the carriage rotates about a rotation axis to move the first magnetic head along a recording surface of a first magnetic disk. the carriage includes an arm, and a first flat surface of the arm. the first flat surface faces the recording surface of the first magnetic disk. the first base plate and the first viscoelastic material are fixed to the first flat surface.
20240096357.MAGNETIC DISK DEVICE_simplified_abstract_(kabushiki kaisha toshiba)
Inventor(s): Shinichi Kobatake of Yokohama Kanagawa (JP) for kabushiki kaisha toshiba, Toru Watanabe of Yokohama Kanagawa (JP) for kabushiki kaisha toshiba, Masami Yamane of Yokohama Kanagawa (JP) for kabushiki kaisha toshiba
IPC Code(s): G11B5/55, G11B5/012, G11B19/28
Abstract: according to one embodiment, a disk device includes a rotatable magnetic disk, an actuator which supports and moves a head, a ramp which holds the head at an unloaded position, a motor which rotates the magnetic disk, and a controller which performs a load operation and a seek operation. when a radial travel speed of the head during the load operation is referred to as vr, a circumferential travel speed of the head is referred to as vt, a radial travel speed of the head during the seek operation is referred to as vrs, and a circumferential travel speed is referred to as vts, the controller controls at least one of the radial travel speed of the head and number of revolutions of the magnetic disk to satisfy a relationship (vr/vt)<(vrs/vts).
20240096358.MAGNETIC DISK DEVICE AND METHOD_simplified_abstract_(kabushiki kaisha toshiba)
Inventor(s): Yusuke TOMODA of Kawasaki Kanagawa (JP) for kabushiki kaisha toshiba
IPC Code(s): G11B5/55
Abstract: according to an embodiment, a magnetic disk device includes a magnetic disk, a magnetic head, and a control circuit. the magnetic disk has a plurality of first storage regions disposed in the radial direction. the recording method is changeable for each of the plurality of first storage regions. the control circuit operates such that, when having received a first command instructing to change the recording method of one first storage region out of a plurality of first storage regions, the control circuit changes the recording method of the one first storage region in accordance with the first command, and moves a magnetic head onto the second storage region before receiving a second command.
20240096359.MAGNETIC DISK DEVICE AND METHOD_simplified_abstract_(kabushiki kaisha toshiba)
Inventor(s): Yu YAMAMOTO of Meguro Tokyo (JP) for kabushiki kaisha toshiba, Takao ABE of Yokohama Kanagawa (JP) for kabushiki kaisha toshiba
IPC Code(s): G11B5/596
Abstract: according to embodiments, a magnetic disk device includes a magnetic disk, a magnetic head, and a controller. in the magnetic disk, a plurality of servo sectors is arranged in a circumferential direction. servo information including a post code indicating a repeatable runout (rro) correction amount is written to each of the plurality of servo sectors. the magnetic head writes and reads data to and from the magnetic disk. in positioning control for the magnetic head, when a read error of a first post code continuously occurs, the controller uses a first rro correction value, which is different from a second rro correction value based on the rro correction value indicated by the first post code. the first post code is a post code of a first servo sector, which is one of the plurality of servo sectors.
Inventor(s): Hiroshi TANI of Kawasaki Kanagawa (JP) for kabushiki kaisha toshiba, Kazuhiko TAKAISHI of Machida Tokyo (JP) for kabushiki kaisha toshiba
IPC Code(s): G11B5/596
Abstract: according to one embodiment, a magnetic disk device writes a plurality of simulated reference patterns to the magnetic disk on write conditions different from each other, detects a write state of each of the simulated reference patterns, selects one of the write conditions according to detection results, and writes a plurality of regular reference patterns which become criteria for predetermined processing to be executed on the magnetic disk to the magnetic disk on the selected write condition.
20240096361.MAGNETIC DISK DEVICE_simplified_abstract_(kabushiki kaisha toshiba)
Inventor(s): Yuugo TANNO of Kawasaki Kanagawa (JP) for kabushiki kaisha toshiba
IPC Code(s): G11B5/60, G11B27/36
Abstract: according to one embodiment, a magnetic disk device includes a magnetic disk, a magnetic head including a write head, a read head, a heater which adjusts a flying height of the read head and a detection portion which detects a flying height of the read head, and a controller which controls a power value supplied to the heater in accordance with the flying height, and, when a read error occurs, detects, with the detection portion, the flying height of the read head in an error occurrence region, determines an assist amount to bring the flying height in the error occurrence region to a pre-set reference flying height, and executes re-try read of the error occurrence region while inputting a power value corresponding to the assist amount to the heater.
20240096362.MAGNETIC DISK DEVICE_simplified_abstract_(kabushiki kaisha toshiba)
Inventor(s): Takao FURUHASHI of Kawasaki Kanagawa (JP) for kabushiki kaisha toshiba
IPC Code(s): G11B5/60, G11B5/54, G11B33/12
Abstract: according to one embodiment, a magnetic disk device includes a magnetic disk, a magnetic head including a write head which writes data to the magnetic disk, a read head which reads data from the magnetic disk, a first heater which adjusts a flying height of the write head, a second heater which adjusts a flying height of the read head and a controller which controls powers supplied to the first heater and the second heat, and controls a power value of the power supplied to the first heater according to a ratio between an electric resistance value of the first heater and an electric resistance value of the second heater.
Inventor(s): Tomoyuki TOKIZAKI of Yokohama Kanagawa (JP) for kabushiki kaisha toshiba
IPC Code(s): G11B25/04, G11B33/14, H05K5/00, H05K5/06
Abstract: a disk drive according to an embodiment includes a housing, a seal, and a piercing member. the housing includes a base having a first space, a first cover with a first hole, attached to the base, and a second cover covering the first cover. the first cover closes the first space. the first cover and the second cover are placed with a second space in-between. the first hole allows communication between the first space and the second space. the seal with a second hole, is attached to the first cover, the second hole allowing communication between the first space or the second space and the first hole. the piercing member includes an attachment part attached to the second cover in the second space, and a needle protruding from the attachment part toward the second hole.
20240096376.DISK DEVICE_simplified_abstract_(kabushiki kaisha toshiba)
Inventor(s): Yutaka HORIGUCHI of Yokohama Kanagawa (JP) for kabushiki kaisha toshiba, Osamu YOSHIDA of Kawasaki Kanagawa (JP) for kabushiki kaisha toshiba
IPC Code(s): G11B27/36, G11B19/20
Abstract: according to one embodiment, there is provided a disk device including a first connector, a second connector and a controller. the first connector is connectable to a host. the first connector includes a first pin that is electrically connectable to a light emitting device in the host. the second connector is connectable to the host. the second connector includes a second pin that is receivable with data from the host. the controller is communicable with predetermined information with the host via the first pin.
20240096377.DISK DEVICE_simplified_abstract_(kabushiki kaisha toshiba)
Inventor(s): Hiroshi Minami of Yokohama Kanagawa (JP) for kabushiki kaisha toshiba, Shigeru Juman of Kawasaki Kanagawa (JP) for kabushiki kaisha toshiba, Kouichi Toukairin of Kawasaki Kanagawa (JP) for kabushiki kaisha toshiba, Yasuhiko Kato of Setagaya Tokyo (JP) for kabushiki kaisha toshiba, Hirofumi Kuribara of Chuo Tokyo (JP) for kabushiki kaisha toshiba, Kenji Mizuochi of Kamakura Kanagawa (JP) for kabushiki kaisha toshiba
IPC Code(s): G11B33/02
Abstract: according to one embodiment, a disk device includes a housing, magnetic disks in the housing, and a printed circuit board attached to an outer surface of a bottom wall of the housing. the housing includes a base including a bottom wall and a side wall, and at least two base-side positioning portions provided on the bottom wall in a region overlapping the side wall. the printed circuit board includes at least two board-side positioning portions each engaged with the base-side positioning portion. one of the base-side positioning portion and the board-side positioning portion includes a pin extending substantially perpendicular to the bottom wall, and another includes a hole into which the pin is fitted.
20240096378.ELECTRONIC DEVICE_simplified_abstract_(kabushiki kaisha toshiba)
Inventor(s): Nobuhiro YAMAMOTO of Yokohama (JP) for kabushiki kaisha toshiba, Masahide TAKAZAWA of Hachioji Tokyo (JP) for kabushiki kaisha toshiba
IPC Code(s): G11B33/12, H05K1/02
Abstract: according to one embodiment, an electronic device includes a wall and a substrate. the substrate is provided with an opening. the substrate includes an organic compound layer, a first surface of the organic compound layer, a second surface of the organic compound layer opposite the first surface, first wiring on the second surface, second wiring on the second surface, a first pad, and a second pad. the first surface is attached to the wall. the first pad is connected to the first wiring. the second pad is connected to the second wiring away from the first pad. the opening penetrates the organic compound layer to open to the first surface and the second surface between the first pad and the second pad.
20240096379.SUSPENSION ASSEMBLY AND DISK DEVICE_simplified_abstract_(kabushiki kaisha toshiba)
Inventor(s): Yasuo SUZUKI of Fujisawa Kanagawa (JP) for kabushiki kaisha toshiba, Takuma KIDO of Mitaka Tokyo (JP) for kabushiki kaisha toshiba
IPC Code(s): G11B33/14, G11B5/48, H10N30/20, H10N30/50, H10N30/87
Abstract: according to one embodiment, a flexure for use in a suspension assembly includes: a supporting plate; a wiring member including a metal plate and a wiring substrate placed on the metal plate and has a tip-side portion placed on the supporting plate, a base end-side portion extending to an outside of the supporting plate, and a first end provided at an extension end of the base end-side portion; and a piezoelectric element mounted on the wiring member. the wiring substrate includes an insulating layer and a conductive layer stacked on the insulating layer, the conductive layer having a plurality of connecting pads including a ground pad to which a ground electrode of the piezoelectric element is connected, a plurality of connecting terminals provided at the first end and including a ground terminal, and a plurality of traces including a ground trace connecting the ground pad and the ground terminal.
20240096380.SEMICONDUCTOR STORAGE DEVICE_simplified_abstract_(kabushiki kaisha toshiba)
Inventor(s): Tsuyoshi MIDORIKAWA of Yokohama Kanagawa (JP) for kabushiki kaisha toshiba
IPC Code(s): G11C7/06, G11C7/10, G11C7/22
Abstract: a semiconductor storage device according to an embodiment comprises: a first memory circuit; a second memory circuit having a storage capacity smaller than that of the first memory circuit; a readout line commonly connected to the first memory circuit and the second memory circuit; a sense amplifier configured to compare a voltage of a first bit signal or a second bit signal with a reference voltage, where the first bit signal being inputted from the first memory circuit through the readout line and the second bit signal being inputted from the second memory circuit through the readout line; and a readout conditioning circuit configured to change at least one of an operation timing of the sense amplifier and the reference voltage corresponding to the first bit signal and the second bit signal.
Inventor(s): Yasutaka NISHIDA of Tama Tokyo (JP) for kabushiki kaisha toshiba, Fumihiko AIGA of Kawasaki Kanagawa (JP) for kabushiki kaisha toshiba
IPC Code(s): G16C10/00, G06N10/20
Abstract: a molecular structure optimization system includes a quantum computer and a classical computer. the quantum computer uses a parameterized quantum circuit to calculate a loss function from a coordinate parameter of a target molecule. the classical computer updates the coordinate parameter and the circuit parameter based on the loss function, and determines optimum values of the circuit parameter and the coordinate parameter. the classical computer updates a provisional value of the circuit parameter while fixing the coordinate parameter and changing the circuit parameter. the classical computer updates a provisional value of the coordinate parameter while fixing the circuit parameter and changing the coordinate parameter.
20240096542.SIGNAL TRANSMISSION DEVICE_simplified_abstract_(kabushiki kaisha toshiba)
Inventor(s): Bowen DANG of Kawasaki Kanagawa (JP) for kabushiki kaisha toshiba, Takeshi MURASAKI of Yokohama Kanagawa (JP) for kabushiki kaisha toshiba, Takaya KITAHARA of Yokohama Kanagawa (JP) for kabushiki kaisha toshiba, Makoto ARAI of Tachikawa Tokyo (JP) for kabushiki kaisha toshiba, Shoji OOTAKA of Yokohama Kanagawa (JP) for kabushiki kaisha toshiba
IPC Code(s): H01F27/28, H05K1/11, H05K1/18
Abstract: a signal transmission device according to the embodiment includes: a first integrated circuit chip provided with a first coil that constitutes the isolation transformer; a printed circuit board provided with a second coil that is magnetically coupled with the first coil to form the insulating transformer; a second integrated circuit chip having a first connection terminal and a second connection terminal provided on the upper surface; a first wire that electrically connects between one end of the second coil and the first connection terminal; and a second wire that electrically connects between the other end of the second coil and the second connection terminal, wherein the second coil is provided only in the wiring layer of the printed circuit board, which has a single wiring layer structure.
Inventor(s): Yuta SUGIMOTO of Kawasaki (JP) for kabushiki kaisha toshiba, Kenta KURODA of Tokyo (JP) for kabushiki kaisha toshiba
IPC Code(s): H01L21/768, H01L23/00, H01L23/48
Abstract: a manufacturing method of a semiconductor apparatus according to an embodiment includes forming an electrode on a first main surface of a semiconductor substrate made from a compound semiconductor; forming, at a location where the electrode is formed, a via hole that penetrates the first main surface and a second main surface of the semiconductor substrate, wherein a ratio of a thickness of the semiconductor substrate to a maximum value of a width of an opening in the second main surface is greater than 1; forming a rear-side electrode on a second main surface of the semiconductor substrate in such a manner that the rear-side electrode is electrically coupled to the electrode in the via hole; forming an insulating layer arranged at least a layer above the opening; and forming a solder layer in a layer above the rear-side electrode and the insulating layer.
20240096762.SEMICONDUCTOR DEVICE_simplified_abstract_(kabushiki kaisha toshiba)
Inventor(s): Kyo Tanabiki of Himeji Hyogo (JP) for kabushiki kaisha toshiba, Yoshihiro Higashikawa of Tokyo (JP) for kabushiki kaisha toshiba, Hajime Takagi of Nonoichi Ishikawa (JP) for kabushiki kaisha toshiba
IPC Code(s): H01L23/495, H01L23/31, H01L23/48
Abstract: a first chip on a first lead frame includes a first source electrode on a surface opposite to the first lead frame. a first source terminal is located in a first direction from the first lead frame. a first gate terminal is located in a second direction from the first source terminal. a first conductor contacts the first source electrode and the first source terminal via conductors. a second chip on a second lead frame includes a second source electrode on a surface opposite to the second lead frame. a second gate terminal is located in a second direction from the first gate terminal. a second source terminal is located in the second direction from the second gate terminal. a second conductor contacts the second source electrode and the second source terminal via conductors.
20240096843.SEMICONDUCTOR DEVICE_simplified_abstract_(kabushiki kaisha toshiba)
Inventor(s): Kyo TANABIKI of Himeji Hyogo (JP) for kabushiki kaisha toshiba
IPC Code(s): H01L23/00
Abstract: according to one embodiment, a semiconductor device includes: a chip; a first electrode provided on the chip; a first connector provided above the first electrode, extending in a first direction, and provided with a joint portion to be joined to the first electrode, on an end portion in the first direction of the first connector; and a joint member for use in joint between the first electrode and the joint portion. the joint portion is provided with a notch portion on at least one end portion in the first direction of an upper surface of the joint portion. the joint member is in contact with the first electrode, a lower surface of the joint portion facing the first electrode, and at least, part of the notch portion.
20240096876.SEMICONDUCTOR DEVICE_simplified_abstract_(kabushiki kaisha toshiba)
Inventor(s): Takahiro NAKAGAWA of Kawasaki Kanagawa (JP) for kabushiki kaisha toshiba, Kazuya NISHIHORI of Tokyo (JP) for kabushiki kaisha toshiba, Yasuhiko KURIYAMA of Yokohama Kanagawa (JP) for kabushiki kaisha toshiba
IPC Code(s): H01L27/06, H01L23/498
Abstract: according to one embodiment, a semiconductor device includes a plurality of transistors. the transistors are coupled through serial coupling. the transistors include a first transistor and a second transistor. the semiconductor device further includes a third transistor and a first diode. the second transistor includes a first sub-transistor and a second sub-transistor that are coupled in parallel with each other. the first transistor, the first sub-transistor, the second sub-transistor, the third transistor, and the first diode are arranged on a substrate, with the third transistor interposed between the first sub-transistor and the second sub-transistor in a first direction.
Inventor(s): Tatsuo SHIMIZU of Shinagawa Tokyo (JP) for kabushiki kaisha toshiba
IPC Code(s): H01L29/06, H01L21/04, H01L29/10, H01L29/16, H01L29/66, H01L29/78
Abstract: a semiconductor device of an embodiment includes a silicon carbide layer including a first face parallel to a first direction, a first trench and a second trench extending in the first direction, a first gate electrode in the first trench, a second gate electrode in the second trench, an n-type first silicon carbide region, a p-type second silicon carbide region between the first silicon carbide region and the first face, an n-type third silicon carbide region between the second silicon carbide region and the first face, a p-type fourth silicon carbide region at a bottom of the first trench, and a fifth silicon carbide region at a bottom of the second trench. a width of the fourth silicon carbide region is less than a width of the first trench, and a length of the fourth silicon carbide region is more than the width of the fourth silicon carbide region.
Inventor(s): Junpei HISADA of Nonoichi Ishikawa (JP) for kabushiki kaisha toshiba, Hiroaki KATOU of Nonoichi Ishikawa (JP) for kabushiki kaisha toshiba
IPC Code(s): H01L29/08, H01L21/265, H01L21/266, H01L29/417, H01L29/66, H01L29/78
Abstract: according to one embodiment, a semiconductor device includes a first electrode, first to fourth semiconductor regions, a gate electrode, and a second electrode. the third semiconductor region is located on a portion of the second semiconductor region. the fourth semiconductor region includes a first portion positioned on the third semiconductor region and a second portion arranged with the first portion in a second direction. a first-conductivity-type impurity concentration of the first portion is less than a first-conductivity-type impurity concentration of the second portion. the gate electrode faces the second semiconductor region via a gate insulating layer in the second direction. the second electrode is located on the second and fourth semiconductor regions. the second electrode contacts the first and second portions. the second electrode includes a connection part that contacts the third semiconductor region and the portion of the second semiconductor region in the second direction.
20240096966.SEMICONDUCTOR DEVICE_simplified_abstract_(kabushiki kaisha toshiba)
Inventor(s): Katsuhisa TANAKA of Himeji Hyogo (JP) for kabushiki kaisha toshiba, Hiroshi KONO of Himeji Hyogo (JP) for kabushiki kaisha toshiba
IPC Code(s): H01L29/16, H01L29/06, H01L29/78
Abstract: a semiconductor device includes a first electrode, a second electrode, a third electrode located between the first electrode and the second electrode, a first semiconductor layer connected to the first electrode, a second semiconductor layer connected to the second electrode, a third semiconductor layer of a second conductivity type, and a fourth semiconductor layer of the second conductivity type. the third electrode includes first and second portions. the first semiconductor layer faces the first portion via an insulating layer. the first and second semiconductor layers are of a first conductivity type and include silicon and carbon. a carrier concentration of the fourth semiconductor layer is greater than a carrier concentration of the third semiconductor layer.
Inventor(s): Tatsuo SHIMIZU of Shinagawa Tokyo (JP) for kabushiki kaisha toshiba
IPC Code(s): H01L29/20, H01L29/66, H01L29/778
Abstract: a semiconductor device of an embodiment includes a first gallium nitride region being an n-type semiconductor, and a second gallium nitride region in contact with the first gallium nitride region, the second gallium nitride region being metal, the second gallium nitride region containing a first element being at least one element selected from a group consisting of be, mg, ca, sr, ba, sc, y, la, ce, pr, nd, pm, sm, eu, gd, tb, dy, ho, er, tm, yb, lu, v, nb, ta, li, na, k, rb, ce, and zn.
Inventor(s): Toshiki HIKOSAKA of Kawasaki (JP) for kabushiki kaisha toshiba, Hajime NAGO of Yokohama (JP) for kabushiki kaisha toshiba, Jumpei TAJIMA of Mitaka (JP) for kabushiki kaisha toshiba, Shinya NUNOUE of Ichikawa (JP) for kabushiki kaisha toshiba
IPC Code(s): H01L29/20, H01L21/02, H01L29/15, H01L29/207, H01L29/36, H01L29/778
Abstract: according to one embodiment, a nitride semiconductor includes a nitride member. the nitride member includes a first nitride region including algan (0<x1≤1), a second nitride region including algan (0<x2<1, x2<x1), and a third nitride region. the second nitride region is between the first nitride region and the third nitride region. the third nitride region includes al, ga, and n. the third nitride region does not include carbon, alternately a third carbon concentration in the third nitride region is lower than a second carbon concentration in the second nitride region.
20240096972.SEMICONDUCTOR DEVICE_simplified_abstract_(kabushiki kaisha toshiba)
Inventor(s): Shuhei TOKUYAMA of Nonoichi Ishikawa (JP) for kabushiki kaisha toshiba, Tsuyoshi KACHI of Kanazawa Ishikawa (JP) for kabushiki kaisha toshiba, Toshifumi NISHIGUCHI of Hakusan Ishikawa (JP) for kabushiki kaisha toshiba, Hiroaki KATOU of Nonoichi Ishikawa (JP) for kabushiki kaisha toshiba
IPC Code(s): H01L29/40, H01L29/78
Abstract: a semiconductor device according to the present embodiment includes: a first electrode; a first semiconductor region of a first conductivity type disposed above the first electrode; a second semiconductor region of a second conductivity type disposed on the first semiconductor region; a third semiconductor region of the first conductivity type disposed on the second semiconductor region; a second electrode disposed in the first semiconductor region; a third electrode facing the second semiconductor region via a second insulating film; a fourth electrode having a portion adjacent to a part of the second semiconductor region and the third semiconductor region in the second direction, the second semiconductor region, and the third semiconductor region; and a fifth electrode disposed in the first insulating film, having a bottom located closer to the first electrode than a bottom of the portion, having a top located on an upper surface of the first insulating film.
20240096973.SEMICONDUCTOR DEVICE_simplified_abstract_(kabushiki kaisha toshiba)
Inventor(s): Keita SAITO of Nonoichi Ishikawa (JP) for kabushiki kaisha toshiba, Kouta TOMITA of Nonoichi Ishikawa (JP) for kabushiki kaisha toshiba, Tatsuya NISHIWAKI of Yokohama Kanagawa (JP) for kabushiki kaisha toshiba, Yasunobu SAITO of Nomi Ishikawa (JP) for kabushiki kaisha toshiba
IPC Code(s): H01L29/40, H01L29/78
Abstract: a semiconductor device includes: a first electrode; a semiconductor part located on the first electrode; a second electrode located in a first region on the semiconductor part; a third electrode located in a second region on the semiconductor part; an insulating member located in the semiconductor part in the first and second regions; a fourth electrode located in the insulating member in the first and second regions; a fifth electrode located in the insulating member between the first electrode and the fourth electrode in the first and second regions; and a conductive member located at least in the second region. the conductive member is connected to the third, fourth, and fifth electrodes.
20240096974.SEMICONDUCTOR DEVICE_simplified_abstract_(kabushiki kaisha toshiba)
Inventor(s): Takuya YASUTAKE of Kanazawa Ishikawa (JP) for kabushiki kaisha toshiba, Hiroaki KATOU of Nonoichi Ishikawa (JP) for kabushiki kaisha toshiba
IPC Code(s): H01L29/40, H01L29/66, H01L29/78
Abstract: a semiconductor device according to the present embodiment includes a drain electrode, a source electrode, a semiconductor region disposed between the drain electrode and the source electrode, a gate electrode disposed in the semiconductor region via a first insulation film, and a second insulation film disposed between the gate electrode and the source electrode and having a specific dielectric constant higher than a specific dielectric constant of the first insulation film.
Inventor(s): Tatsuo SHIMIZU of () for kabushiki kaisha toshiba
IPC Code(s): H01L29/45, H01L21/265, H01L21/285, H01L29/20, H01L29/778
Abstract: a semiconductor device of an embodiment includes a first nitride region being nitride selected from aluminum gallium nitride and aluminum nitride, the first nitride region being an n-type semiconductor, and a second gallium nitride region in contact with the first nitride region, the second gallium nitride region being the nitride, the second gallium nitride region being metal, the second gallium nitride region containing a first element being at least one element selected from a group consisting of be, mg, ca, sr, ba, sc, y, la, ce, pr, nd, pm, sm, eu, gd, tb, dy, ho, er, tm, yb, lu, v, nb, ta, li, na, k, rb, ce, and zn.
20240097012.SEMICONDUCTOR DEVICE_simplified_abstract_(kabushiki kaisha toshiba)
Inventor(s): Hiroko ITOKAZU of Kawasaki Kanagawa (JP) for kabushiki kaisha toshiba, Yoko IWAKAJI of Meguro Tokyo (JP) for kabushiki kaisha toshiba, Keiko KAWAMURA of Yokohama Kanagawa (JP) for kabushiki kaisha toshiba, Tomoko MATSUDAI of Shibuya Tokyo (JP) for kabushiki kaisha toshiba, Kaori FUSE of Yokohama Kanagawa (JP) for kabushiki kaisha toshiba, Takako MOTAI of Yokohama Kanagawa (JP) for kabushiki kaisha toshiba
IPC Code(s): H01L29/739, H01L29/423
Abstract: a semiconductor device includes a semiconductor part, first to fourth electrodes and a control electrode. the first and second electrodes are provided respectively on back and front surfaces of the semiconductor part. the third electrode is provided between the first and second electrodes, and provided in the semiconductor part with a first insulating film interposed. the fourth and control electrodes are provided between the second and third electrodes. the fourth and control electrodes extends into the semiconductor part from the front side and faces the third electrode with a second insulating film interposed. the fourth electrode is positioned between the semiconductor part and the control electrode. the first insulating film extends between the semiconductor part and the control electrode and between the semiconductor part and the fourth electrode. the fourth electrode faces the control electrode with a third insulating film interposed, and is electrically connected to the third electrode.
Inventor(s): Tatsuo SHIMIZU of Tokyo (JP) for kabushiki kaisha toshiba
IPC Code(s): H01L29/78, H01L29/06, H01L29/16
Abstract: a semiconductor device of an embodiment includes a sic layer including a first face parallel to first direction and second direction perpendicular to the first direction, a trench extending in the first direction, a gate electrode, an n-type first sic region, a p-type second sic region between the first sic region and the trench, extending in the second direction, an n-type third sic region extending in the second direction, and alternately and repeatedly provided with the second sic region in the first direction, a p-type fourth sic region between the third sic region and the first face, an n-type fifth sic region between the fourth sic region and the first face. the first face is inclined with respect to a (0001) face by 0.1 to 8 degrees in a <11-20> direction, and the first direction is along the <11-20> direction, and the second direction is along a <1-100> direction.
Inventor(s): Takako MOTAI of Yokohama Kanagawa (JP) for kabushiki kaisha toshiba, Yoko IWAKAJI of Meguro Tokyo (JP) for kabushiki kaisha toshiba, Kaori FUSE of Yokohama Kanagawa (JP) for kabushiki kaisha toshiba, Keiko KAWAMURA of Yokohama Kanagawa (JP) for kabushiki kaisha toshiba, Kentaro ICHINOSEKI of Higashimurayama Tokyo (JP) for kabushiki kaisha toshiba
IPC Code(s): H01L29/78, H01L29/66
Abstract: a semiconductor device includes a semiconductor substrate, a cell region provided, and a termination region. the termination region surrounds the cell region and includes a plurality of first diffusion layers containing a first conductive impurity, a plurality of second diffusion layers each disposed on an outer side of each of the plurality of first diffusion layers and having a concentration of the first conductive impurity lower than that of the first diffusion layers, and a plurality of conductive layers opposing the first diffusion layers and the second diffusion layers on the front face of the semiconductor substrate, the plurality of conductive layers electrically connected to the first diffusion layers, the plurality of conductive layers each having an outer end portion. on a lower side of the outer end portion, any one of the plurality of second diffusion layers is present.
Inventor(s): Kentaro ICHINOSEKI of Higashimurayama Tokyo (JP) for kabushiki kaisha toshiba, Keiko KAWAMURA of Yokohama Kanagawa (JP) for kabushiki kaisha toshiba, Tatsuya NISHIWAKI of Yokohama Kanagawa (JP) for kabushiki kaisha toshiba, Kohei OASA of Setagaya Tokyo (JP) for kabushiki kaisha toshiba
IPC Code(s): H01L29/78, H01L29/40, H01L29/423, H01L29/66
Abstract: a semiconductor device includes a semiconductor part, first to third and control electrodes. the first electrode is provided on a back surface of the semiconductor part; and the second electrode is provided on a front surface thereof. the third electrode is provided between the first and second electrodes. the third electrode extends into the semiconductor part from the front surface side thereof. the third electrode is electrically insulated from the semiconductor part via an insulating space between the semiconductor part and the third electrode. the control electrode includes first and second portions. the first portion is linked to the second portion and extends between the semiconductor part and the third electrode. the second portion is provided between the second electrode and the third electrode. the first portion faces the insulating space via the third electrode; and the second portion extends between the insulating space and the second electrode.
Inventor(s): Yuhki FUJINO of Kanazawa Ishikawa (JP) for kabushiki kaisha toshiba, Tsuyoshi KACHI of Kanazawa Ishikawa (JP) for kabushiki kaisha toshiba, Katsura MIYASHITA of Naka Kanagawa (JP) for kabushiki kaisha toshiba, Shingo SATO of Kanawawa Ishikawa (JP) for kabushiki kaisha toshiba
IPC Code(s): H01L29/78, H01L29/423, H01L29/66
Abstract: a semiconductor device includes: a semiconductor part including a first semiconductor layer and a second semiconductor layer in contact with the first semiconductor layer; a first electrode electrically connected to the first semiconductor layer on a front surface side or a back surface side of the semiconductor part; a second electrode electrically connected to the second semiconductor layer on the front surface side of the semiconductor part; a gate electrode; an interlayer insulating film electrically insulating the gate electrode and the second electrode on the front surface side of the semiconductor part; and a third semiconductor layer having: a first region in contact with the second semiconductor layer and the second electrode on the front surface side of the semiconductor part; and a second region provided between the interlayer insulating film and the second electrode in a second direction perpendicular to a first direction.
Inventor(s): Saya SHIMOMURA of Komatsu Ishikawa (JP) for kabushiki kaisha toshiba, Hiroaki KATOU of Nonoichi Ishikawa (JP) for kabushiki kaisha toshiba
IPC Code(s): H01L29/78, H01L29/40, H01L29/66
Abstract: according to one embodiment, a semiconductor device includes a first electrode, a second electrode, a first region, a second region, a third region, a first conductive portion, a second conductive portion, a gate electrode, a first insulating portion, a second insulating portion, a third insulating portion, and a fourth insulating portion. the second electrode has a first portion and a second portion extending from the first portion toward the first electrode. the first region is between the first electrode and the second electrode. the second region is between the first region and the second electrode. the third region is between the second semiconductor region and the second electrode. the first conductive portion is in the first semiconductor region. the gate electrode is between the second region and the second portion. the second conductive portion is between the first conductive portion and the gate electrode.
20240097045.SEMICONDUCTOR DEVICE_simplified_abstract_(kabushiki kaisha toshiba)
Inventor(s): Yuto ADACHI of Ibo Hyogo (JP) for kabushiki kaisha toshiba, Yoichi HORI of Himeji Hyogo (JP) for kabushiki kaisha toshiba, Makoto MIZUKAMI of Ibo Hyogo (JP) for kabushiki kaisha toshiba
IPC Code(s): H01L29/872, H01L29/06, H01L29/861
Abstract: a semiconductor device includes a first electrode, a first semiconductor layer of a first conductivity type located on the first electrode, a second semiconductor layer of a second conductivity type located on a portion of the first semiconductor layer, a metal layer located on the first and second semiconductor layers, a second electrode located on the metal layer, a bonding member connected to an upper surface of the second electrode, and a conductive member located between the second semiconductor layer and the metal layer. the metal layer has a schottky junction with the first semiconductor layer. the conductive member is made of a different material from the metal layer. an area ratio of the conductive member in a region directly under the bonding member is higher than an area ratio of the conductive member in a region other than the region directly under the bonding member.
Inventor(s): Kazuomi YOSHIMA of Yokohama Kanagawa (JP) for kabushiki kaisha toshiba, Yuta KANAI of Yokohama Kanagawa (JP) for kabushiki kaisha toshiba, Hirofumi YASUMIISHI of Kawasaki Kanagawa (JP) for kabushiki kaisha toshiba, Tetsuya SASAKAWA of Yokohama Kanagawa (JP) for kabushiki kaisha toshiba
IPC Code(s): H01M4/04, H01M4/66
Abstract: in a manufacturing method of an electrode structure of an embodiment, in a belt-like member in which an uncoated region not coated with an active material-containing layer is formed in one of long edges and its vicinity in a current collector, the active material-containing layer is rolled, and a tension in a longitudinal direction is applied to the belt-like member between a pulling unit pulling the belt-like member and a rolling unit rolling the active material-containing layer. in the method, the uncoated region is pushed by a projection projecting to an outer peripheral side in a roller between the rolling unit and the pulling unit, thereby enlarging the uncoated region in the longitudinal direction. a projection length of the projection to the projection end is larger than the thickness of the rolled active material-containing layer.
Inventor(s): Hirofumi YASUMIISHI of Kawasaki Kanagawa (JP) for kabushiki kaisha toshiba, Keigo HOSHINA of Yokohama Kanagawa (JP) for kabushiki kaisha toshiba, Yasuyuki HOTTA of Ota Tokyo (JP) for kabushiki kaisha toshiba, Yumiko SEKIGUCHI of Kawasaki Kanagawa (JP) for kabushiki kaisha toshiba, Kazuomi YOSHIMA of Yokohama Kanagawa (JP) for kabushiki kaisha toshiba, Hayato SEKI of Kawasaki Kanagawa (JP) for kabushiki kaisha toshiba, Wataru UNO of Yokohama Kanagawa (JP) for kabushiki kaisha toshiba
IPC Code(s): H01M10/38, H01M4/485, H01M4/505, H01M4/62, H01M50/414, H01M50/431, H01M50/443, H01M50/446, H01M50/46
Abstract: an integrated sheet structure for a secondary battery, including a first mixture layer containing a first active material and a first binder, a second mixture layer containing a second active material and a second binder, and a third mixture layer located between the first mixture layer and the second mixture layer and containing solid particles and a third binder, in which the first mixture layer and the third mixture layer are bonded each other, and the second mixture layer and the third mixture layer are bonded each other.
Inventor(s): Yasunobu YAMASHITA of Tokyo (JP) for kabushiki kaisha toshiba, Keigo HOSHINA of Tokyo (JP) for kabushiki kaisha toshiba, Shinsuke MATSUNO of Tokyo (JP) for kabushiki kaisha toshiba
IPC Code(s): H01M10/52, H01M10/0525
Abstract: in general, according to one embodiment, a secondary battery includes a positive electrode, a negative electrode, an aqueous electrolyte, and a gas treatment structure. the gas treatment structure is configured to be capable of treating hydrogen gas using an electrical conduction between the gas treatment structure and the positive electrode.
Inventor(s): Taro FUKAYA of Tokyo (JP) for kabushiki kaisha toshiba, Asato KONDO of Yokohama Kanagawa (JP) for kabushiki kaisha toshiba, Yasuhiro HARADA of Isehara Kanagawa (JP) for kabushiki kaisha toshiba
IPC Code(s): H01M10/54, C01G33/00
Abstract: in general, according to one embodiment, a recycling method is provided. the method includes dispersing an electrode containing a niobium titanium oxide in water; separating the niobium titanium oxide from the electrode dispersed in the water; and applying a first heat treatment to the separated niobium titanium oxide.
Inventor(s): Yasunobu YAMASHITA of Tokyo (JP) for kabushiki kaisha toshiba, Kakuya UEDA of Kawasaki Kanagawa (JP) for kabushiki kaisha toshiba, Mitsuhiro OKI of Kawasaki Kanagawa (JP) for kabushiki kaisha toshiba, Yasuhiro HARADA of Isehara Kanagawa (JP) for kabushiki kaisha toshiba, Norio TAKAMI of Yokohama Kanagawa (JP) for kabushiki kaisha toshiba
IPC Code(s): H01M50/431, H01M4/48, H01M10/42
Abstract: in general, according to one embodiment, a nonaqueous electrolyte battery is provided. the nonaqueous electrolyte battery includes an electrode group, including a positive electrode, a negative electrode, and a separator. the separator includes at least one metal-element containing portion containing a metal element. the at least one metal-element containing portion is provided on a surface of the separator in contact with the negative electrode. the at least one metal-element containing portion contains at least one selected from a group consisting of a metal, a metallic oxide, and a metallic fluoride. an area of the at least one metal-element containing portion is in a range of 0.3 mmto 3.2 mm.
20240097302.DIGITAL ISOLATOR_simplified_abstract_(kabushiki kaisha toshiba)
Inventor(s): Minoru NAGATA of Yokohama Kanagawa (JP) for kabushiki kaisha toshiba
IPC Code(s): H01P1/36, H03K3/037, H03K19/20
Abstract: a digital isolator includes: an edge detection circuit configured to output a first detection signal and a second detection signal; a driving buffer circuit configured to output a first edge signal and a second edge signal; an isolation element configured to output a first edge signal and a second edge signal; a receiving inverter circuit configured to output a first reception signal and a second reception signal; a latch circuit configured to latch data based on the pulse of the first received signal and the pulse of the second received signal, and to output an output signal to an output terminal according to the data; a switch circuit configured to switch a state of conduction between the reference potential and the first output and a state of conduction between the reference potential and the second output; and a control circuit configured to control a switching operation.
20240097303.ISOLATOR_simplified_abstract_(kabushiki kaisha toshiba)
Inventor(s): Jia LIU of Yokohama Kanagawa (JP) for kabushiki kaisha toshiba, Yusuke IMAIZUMI of Kawasaki Kanagawa (JP) for kabushiki kaisha toshiba, Minoru TAKIZAWA of Sagamihara Kanagawa (JP) for kabushiki kaisha toshiba, Yoshinari TAMURA of Yokohama Kanagawa (JP) for kabushiki kaisha toshiba, Daijo CHIDA of Yokohama Kanagawa (JP) for kabushiki kaisha toshiba
IPC Code(s): H01P1/36, H01F17/00, H01F27/32
Abstract: according to one embodiment, an isolator includes a first coil, a second coil, a plate-shaped first magnet, and a first insulator. the second coil is aligned with the first coil along a first axis and faces the first coil. the first magnet is provided on a side of the second coil and faces the second coil, the side being opposite to a side where the first coil is located. the first magnet extends along a first plane intersecting the first axis. the first insulator seals the first coil, the second coil, and the first magnet.
Inventor(s): Yasuhiro KANEKIYO of Yokohama Kanagawa (JP) for kabushiki kaisha toshiba, Kenichirou OGAWA of Kawasaki Kanagawa (JP) for kabushiki kaisha toshiba, Tetsu SHIJO of Setagaya Tokyo (JP) for kabushiki kaisha toshiba
IPC Code(s): H02J7/00, H02J7/34
Abstract: according to one embodiment, a power supply/demand device includes a virtual synchronous inverter and a storage battery. the virtual synchronous inverter is connected to a power system. charging and discharging of the storage battery are controlled by the virtual synchronous inverter. the virtual synchronous inverter is connected to the power system in parallel with other inverters. the virtual synchronous inverter is capable of calculating a first standby time having any length and performing control of the storage battery corresponding to an operation instruction after a lapse of the first standby time, when receiving the operation instruction accompanied by output of power to the power system or input of power from the power system.
Inventor(s): Keigo HOSHINA of Yokohama Kanagawa (JP) for kabushiki kaisha toshiba, Hayato SEKI of Kawasaki Kanagawa (JP) for kabushiki kaisha toshiba, Shinsuke MATSUNO of Tokyo (JP) for kabushiki kaisha toshiba, Norio TAKAMI of Yokohama Kanagawa (JP) for kabushiki kaisha toshiba
IPC Code(s): H02J7/00, H01M10/42, H01M10/44
Abstract: in one embodiment, there is provided a charging method of a battery pack in which a plurality of aqueous battery cells are electrically connected in series. in this charging method, in a case where the battery pack reaches a reference voltage by a constant-current charging at a first charging rate, constant-current charging is performed on the battery pack at the second charging rate lower than the first charging rate and being from 0.01 c or more to 0.05 c or less. then, this constant-current charging at the second charging rate is continued until a charged electric charge amount from a start timing of the constant-current charging at the second charging rate reaches a reference electric charge amount set from 1% or more to 5% or less of the nominal capacity of the battery pack.
Inventor(s): Hiroki WATANABE of Tokyo (JP) for kabushiki kaisha toshiba, Takeshi UENO of Tokyo (JP) for kabushiki kaisha toshiba
IPC Code(s): H02M1/08, H02M7/5387
Abstract: in one embodiment, electronic circuitry includes a current output circuit configured to output a drive current to a switching element, a first detection circuit configured to detect a timing at which a voltage between output terminals of the switching element, and a control circuit configured to cause the current output circuit to start outputting a first drive current in accordance with a command signal that instructs switching operation of the switching element. the control circuit switches the drive current output from the current output circuit to a second drive current smaller than the first drive current based on the timing at which the voltage between the output terminals, the timing being detected by the first detection circuit.
20240097564.CHARGE PUMP CIRCUIT AND DRIVE DEVICE_simplified_abstract_(kabushiki kaisha toshiba)
Inventor(s): Mitsumasa SONODA of Yokohama Kanagawa (JP) for kabushiki kaisha toshiba
IPC Code(s): H02M3/07
Abstract: a charge pump circuit includes a first capacitor including a first end supplied for a voltage, and a second end; a second capacitor including a third end supplied for a pulse signal, and a fourth end coupled to a node; a third capacitor including a fifth end supplied for the pulse signal, and sixth end; a first transistor including a seventh end coupled to the second end, an eighth end coupled to the node, and a first gate; a second transistor including a ninth end coupled to the first end, a tenth end coupled to the node, and a second gate; and a circuit including a first terminal coupled to the node, a second terminal coupled to the sixth end, a third terminal coupled to the first gate, and a fourth terminal coupled to the second gate.
Inventor(s): Takehiro HARA of Yokohama Kanagawa (JP) for kabushiki kaisha toshiba
IPC Code(s): H02P6/18, H02K11/21, H02K11/27, H02K11/33, H02P6/30
Abstract: according to one embodiment, a motor control device includes a sensor, a detection circuit, and a controller. the sensor is at a position between a winding of a first phase and a winding of a second phase in a motor. the motor includes windings of three phases. the detection circuit detects when a magnitude relationship between an induced voltage amplitude of the first phase and an induced voltage amplitude of the second phase is switched. the controller performs based on a sensor signal from the sensor and a detection result sensor from the detection circuit.
20240097590.MOTOR CONTROLLER_simplified_abstract_(kabushiki kaisha toshiba)
Inventor(s): Yutaka YAMADA of Fuchu Tokyo (JP) for kabushiki kaisha toshiba, Koji SUZUKI of Fuchu Tokyo (JP) for kabushiki kaisha toshiba, Ken TANABE of Ota Tokyo (JP) for kabushiki kaisha toshiba
IPC Code(s): H02P23/16, H02P23/00
Abstract: a motor controller includes a first control circuit, a second control circuit, a determination circuit, and a command circuit. the first control circuit outputs a first control value based on a rule base from a command value of an angular velocity and a measured value of an angular velocity. the second control circuit outputs a second control value based on a learned model from the command value of the angular velocity and the measured value of the angular velocity. the determination circuit determines a state based on at least the second control value. the command circuit acquires and outputs a control command value from the first control value and the second control value based on a result determined by the determination circuit.
20240097671.SEMICONDUCTOR DEVICE_simplified_abstract_(kabushiki kaisha toshiba)
Inventor(s): Toru SUGIYAMA of Musashino Tokyo (JP) for kabushiki kaisha toshiba, Noriaki YOSHIKAWA of Inagi Tokyo (JP) for kabushiki kaisha toshiba, Yasuhiko KURIYAMA of Yokohama Kanagawa (JP) for kabushiki kaisha toshiba, Akira YOSHIOKA of Yokohama Kanagawa (JP) for kabushiki kaisha toshiba, Hitoshi KOBAYASHI of Yamato Kanagawa (JP) for kabushiki kaisha toshiba, Hung HUNG of Kawasaki Kanagawa (JP) for kabushiki kaisha toshiba, Yasuhiro ISOBE of Ota Tokyo (JP) for kabushiki kaisha toshiba, Tetsuya OHNO of Yokohama Kanagawa (JP) for kabushiki kaisha toshiba, Hideki SEKIGUCHI of Yokohama Kanagawa (JP) for kabushiki kaisha toshiba, Masaaki ONOMURA of Setagaya Tokyo (JP) for kabushiki kaisha toshiba
IPC Code(s): H03K17/16
Abstract: a semiconductor device includes a first transistor, a first drive circuit including a second transistor, and a second drive circuit including a third transistor. the second transistor and the third transistor are connected in series; and a connection node of the second and third transistors is connected to a gate electrode of the first transistor. the first transistor, the second transistor, and the third transistor are normally-off mos hemts formed in a first substrate that includes gan. the first drive circuit charges a parasitic capacitance of the first transistor. the second drive circuit discharges the parasitic capacitance of the first transistor.
Inventor(s): Takayuki TERAGUCHI of Kawasaki Kanagawa (JP) for kabushiki kaisha toshiba
IPC Code(s): H03K17/687
Abstract: according to an embodiment, an spnt-type high frequency switch includes a plurality of first mos transistors, second mos transistors, and a capacitor. the plurality of first mos transistors are connected in series between one of a plurality of rf terminals and an rf common terminal. the second mos transistors have ends each connected to adjacent first mos transistors among the first mos transistors. the capacitor is connected between ground and another end of a second mos transistor having one end connected to another end of a first mos transistor having one end connected to the one of the rf terminals among the first and second mos transistors.
Inventor(s): Takayuki TERAGUCHI of Kawasaki Kanagawa (JP) for kabushiki kaisha toshiba
IPC Code(s): H03K17/693
Abstract: according to one embodiment, a radio frequency switch of a single-pole-n-throw (spnt) type includes a first rf terminal, a second rf terminal, a single rf common terminal, first mos transistors, termination resistors, and second mos transistors. the first mos transistors are respectively provided between the first rf terminal and the rf common terminal and between the second rf terminal and the rf common terminal. each of the termination resistors is configured to be connected to the first rf terminal or the second rf terminal in a selected state where a corresponding one of the first mos transistors is in an off state. the second mos transistors are connected in parallel to the respective termination resistors, and each of the second mos transistors is configured to be controlled in a same manner as a corresponding one of the first mos transistors.
20240097684.LEVEL SHIFT CIRCUITRY_simplified_abstract_(kabushiki kaisha toshiba)
Inventor(s): Tetsuya NAKAMURA of Yokohama Kanagawa (JP) for kabushiki kaisha toshiba
IPC Code(s): H03K19/0185
Abstract: a level shift circuitry includes a first impedance, a second impedance, a first transistor, a second transistor, a current source, and a first capacitor. the first impedance and the second impedance have a first end connected to a positive-side power supply voltage. the first transistor has a control terminal and a first end connected to a second end of the first impedance. the second transistor has a control terminal, a first end connected to a second end of the second impedance, and a second end connected to a second end of the first transistor. the current source has a first end connected to the second end of the first transistor and a second end connected to a negative-side power supply voltage. the first capacitor has a first end connected to the second end of the second impedance and a second end.
Inventor(s): Takafumi SAKAMOTO of Machida Tokyo (JP) for kabushiki kaisha toshiba, Koji AKITA of Yokohama Kanagawa (JP) for kabushiki kaisha toshiba, Yuki YONEZAWA of Ayase Kanagawa (JP) for kabushiki kaisha toshiba
IPC Code(s): H04B17/345, H04B17/318
Abstract: according to one embodiment, an electronic apparatus includes a processing circuitry configured to estimate a position at which electromagnetic noise occurs based on propagation data in communication between a first wireless device located at a first position and second wireless devices located at second positions, and position information indicating the first position and the second positions.
20240097938.RING NETWORK_simplified_abstract_(kabushiki kaisha toshiba)
Inventor(s): Taiki SHINOHARA of Yokosuka Kanagawa (JP) for kabushiki kaisha toshiba, Hirohisa KUSANO of Mitaka Tokyo (JP) for kabushiki kaisha toshiba
IPC Code(s): H04L12/437
Abstract: according to one embodiment, a ring network includes a plurality of communication devices. each of the plurality of communication devices has first and second ethernet interfaces respectively connected to adjacent communication devices on one side and on the other side in the ring, and a host device that can transmit and receive data to and from other communication devices on the ring network using the first and second ethernet interfaces. the plurality of communication devices includes a first communication device that transmits, in a first time period, a first frame from its second ethernet interface in a clockwise direction and transmits a second frame from its first ethernet interface in a counterclockwise direction.
Inventor(s): Akiyuki TANIZAWA of Kanagawa (JP) for kabushiki kaisha toshiba, Takeshi CHUJOH of Kanagawa (JP) for kabushiki kaisha toshiba, Taichiro SHIODERA of Tokyo (JP) for kabushiki kaisha toshiba
IPC Code(s): H04N19/159, H04N19/105, H04N19/126, H04N19/136, H04N19/172, H04N19/176, H04N19/186, H04N19/463, H04N19/70, H04N19/94
Abstract: according to an embodiment, an encoding device includes an index setting unit and an encoding unit. the index setting unit generates a common index in which reference indices of one or more reference images included in a first index and a second index are sorted in a combination so as not to include a same reference image in accordance with a predetermined scanning order. the first index representing a combination of the one or more reference images referred to by a first reference image. the second index representing a combination of the one or more reference images referred to by a second reference image. the encoding unit encodes the common index.
Inventor(s): Tatsuhiko GOTO of Kawasaki Kanagawa (JP) for kabushiki kaisha toshiba, Osamu NISHIMURA of Kawasaki Kanagawa (JP) for kabushiki kaisha toshiba, Akihiko ENAMITO of Kawasaki Kanagawa (JP) for kabushiki kaisha toshiba
IPC Code(s): H04R3/00, G10K11/16
Abstract: according to one embodiment, a noise reduction system includes a microphone, a loudspeaker, and processing circuitry. the processing circuitry switches an operating mode between a control mode and a path characteristic measurement mode, includes a control filter that generates a control signal that causes the loudspeaker to output a control sound for reducing noise, based on a detection signal obtained by detecting a first sound including the noise with the microphone, measures a path characteristic including an acoustic characteristic between the loudspeaker and the microphone, and generates the control filter by using a measurement result of the path characteristic and a noise feature signal including a feature of the noise.
Inventor(s): Koji AKITA of Yokohama Kanagawa (JP) for kabushiki kaisha toshiba, Yuki YONEZAWA of Ayase Kanagawa (JP) for kabushiki kaisha toshiba, Tomoya TANDAI of Ota Tokyo (JP) for kabushiki kaisha toshiba
IPC Code(s): H04W72/02, H04W72/0446, H04W72/20
Abstract: according to one embodiment, an electronic apparatus is arranged at an interface between a first layer and a second layer in a base station, and includes a processor and a memory configured to store allocation information indicating a radio resource for a first control signal. the first layer is configured to transmit a physical layer signal to the second layer. the processor is configured to generate a second control signal based on the allocation information, generate a synthesis signal by adding the second control signal to the physical layer signal, and transmit the synthesis signal to the second layer.
KABUSHIKI KAISHA TOSHIBA patent applications on March 21st, 2024
- KABUSHIKI KAISHA TOSHIBA
- B01J19/24
- C25B1/04
- C25B1/23
- C25B9/19
- C25B15/021
- C25B15/08
- Kabushiki kaisha toshiba
- B60L8/00
- B60L53/60
- B60L53/64
- G06Q50/06
- H02J7/00
- C12Q1/00
- G01N27/414
- G01N33/00
- C25B11/093
- C25B11/031
- C25B13/02
- C25B11/056
- C25B11/063
- C25B11/091
- C25B15/02
- C25B15/027
- C25B1/27
- C25B3/26
- C25B9/23
- C25B9/65
- C25B15/029
- G01M99/00
- G01N21/25
- G01N21/29
- G01N21/31
- G06T5/00
- G06T5/10
- G06T5/20
- G06T7/00
- G01N29/07
- G01N29/12
- G01N29/14
- G01N29/04
- G01N29/44
- G01S7/481
- G01S17/08
- G01S13/34
- G01S7/35
- G01S13/88
- G01S13/89
- G01V3/12
- G01V8/00
- G01W1/10
- G01S13/95
- G01W1/02
- G01W1/14
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