International business machines corporation (20240222395). BACKSIDE-CONNECTING VIA WITH NANOSHEET SPACERS FOR TRANSISTORS simplified abstract

BACKSIDE-CONNECTING VIA WITH NANOSHEET SPACERS FOR TRANSISTORS

Organization Name

international business machines corporation

Inventor(s)

Oscar Van Der Straten of Guilderland Center NY (US)

Tsung-Sheng Kang of Ballston Lake NY (US)

Alexander Reznicek of Troy NY (US)

Koichi Motoyama of Clifton Park NY (US)

BACKSIDE-CONNECTING VIA WITH NANOSHEET SPACERS FOR TRANSISTORS - A simplified explanation of the abstract

This abstract first appeared for US patent application 20240222395 titled 'BACKSIDE-CONNECTING VIA WITH NANOSHEET SPACERS FOR TRANSISTORS

The semiconductor device array described in the patent application includes a backside power distribution network (BSPDN), a buried power rail (BPR) in electrical contact with the BSPDN, a device layer, and a backside-connecting via.

• The device layer consists of a first transistor, a second transistor, a first spacer, and a second spacer.
• The first transistor is in electrical contact with the first spacer, while the second transistor is in electrical contact with the second spacer.
• The first transistor neighbors the second transistor.
• The backside-connecting via is in electrical contact with the first transistor, the BPR, the first spacer, and the second spacer.

Potential Applications: - This technology could be used in the manufacturing of advanced semiconductor devices for various electronic applications. - It may find applications in the development of high-performance computing systems and integrated circuits.

Problems Solved: - The technology addresses the need for efficient power distribution and connectivity in semiconductor device arrays. - It improves the performance and reliability of electronic devices by enhancing power management.

Benefits: - Enhanced power distribution efficiency. - Improved performance and reliability of semiconductor devices. - Better connectivity and integration in electronic systems.

Commercial Applications: Title: Advanced Semiconductor Device Array Technology for High-Performance Computing This technology could be commercially applied in the production of advanced processors, memory chips, and other electronic components for high-performance computing systems. It has the potential to revolutionize the semiconductor industry by enabling the development of more efficient and powerful electronic devices.

Questions about the technology: 1. How does the backside power distribution network (BSPDN) improve the efficiency of power distribution in semiconductor device arrays? 2. What are the key advantages of using buried power rails (BPR) in semiconductor device arrays?

Original Abstract Submitted

embodiments are disclosed for a semiconductor device array and a method for fabricating the semiconductor device array. the semiconductor device array includes a backside power distribution network (bspdn), a buried power rail (bpr) in electrical contact with the bspdn, a device layer, and a backside-connecting via. the device layer includes a first transistor, a second transistor, a first spacer, and a second spacer. further, the first transistor is in electrical contact with the first spacer. additionally, the second transistor is in electrical contact with the second spacer. also, the first transistor neighbors the second transistor. further, the backside-connecting via is in electrical contact with the first transistor, the bpr, the first spacer, and the second spacer.