International business machines corporation (20240203990). STACKED CMOS DEVICES WITH TWO DIELECTRIC MATERIALS IN A GATE CUT simplified abstract

STACKED CMOS DEVICES WITH TWO DIELECTRIC MATERIALS IN A GATE CUT

Organization Name

international business machines corporation

Inventor(s)

Ruilong Xie of Niskayuna NY (US)

Kangguo Cheng of Schenectady NY (US)

Julien Frougier of Albany NY (US)

Chanro Park of Clifton Park NY (US)

Min Gyu Sung of Latham NY (US)

STACKED CMOS DEVICES WITH TWO DIELECTRIC MATERIALS IN A GATE CUT - A simplified explanation of the abstract

This abstract first appeared for US patent application 20240203990 titled 'STACKED CMOS DEVICES WITH TWO DIELECTRIC MATERIALS IN A GATE CUT

Simplified Explanation: A complementary field effect transistor (CFET) device is created on a semiconductor substrate with two transistors, one under the other. The device features a gate cut filled with two different dielectric materials, each adjacent to one of the transistors. These materials are chosen to enhance the electrical performance of both the NFET and PFET in the CFET device by applying stress to the channels of the transistors.

• The CFET device consists of two transistors, one stacked on top of the other.
• A gate cut filled with two dielectric materials is located next to the gate of the CFET device.
• The first dielectric material in the gate cut applies compressive stress to the channel of the first transistor (PFET) to improve its performance.
• The second dielectric material in the gate cut applies tensile stress to the channel of the second transistor (NFET) to enhance its performance.

Key Features and Innovation:

• CFET device with two transistors stacked on top of each other.
• Gate cut filled with two dielectric materials to improve NFET and PFET performance.
• Compressive stress applied to PFET channel by the first dielectric material.
• Tensile stress applied to NFET channel by the second dielectric material.

Potential Applications:

• Semiconductor devices
• Integrated circuits
• Electronics industry

Problems Solved:

• Enhancing the electrical performance of both NFET and PFET in a CFET device.
• Improving stress application to transistor channels for better performance.

Benefits:

• Improved electrical performance of NFET and PFET.
• Enhanced overall functionality of CFET devices.

Commercial Applications: Semiconductor manufacturers can utilize this technology to enhance the performance of their integrated circuits, leading to more efficient and reliable electronic devices in various industries.

Prior Art: Readers interested in prior art related to this technology can explore patents and research papers on CFET devices, stress application in transistors, and dielectric materials in semiconductor devices.

Frequently Updated Research: Researchers in the field of semiconductor technology are constantly exploring new ways to optimize the performance of transistors in integrated circuits, including the use of innovative stress application techniques like those described in this patent application.

Questions about CFET Devices: 1. What are the potential drawbacks of applying stress to transistor channels in CFET devices? 2. How do the dielectric materials in the gate cut affect the overall reliability of the CFET device?

Original Abstract Submitted

a complementary field effect transistor (cfet) device is formed on a semiconductor substrate. the cfet device has a first transistor that is under a second transistor. a filled gate cut is directly adjacent to the sidewall of the gate of the cfet device. the first dielectric material in the gate cut is adjacent to the first transistor. the second dielectric material in the gate cut is adjacent to the second transistor. the two dielectric materials in the gate cut are selected to improve the electrical performance of each of the nfet and the pfet in the cfet device. the first dielectric material can apply a compressive stress to the channels of the first transistor when the first transistor is a pfet to improve the electrical performance of the pfet. when the second transistor is an nfet, the second dielectric material applies a tensile stress to nfet to improve nfet performance.