International business machines corporation (20240202305). TWO-TRANSISTOR CHIP AND THREE-TRANSISTOR CHIP IDENTIFICATION BIT CELLS simplified abstract
Contents
TWO-TRANSISTOR CHIP AND THREE-TRANSISTOR CHIP IDENTIFICATION BIT CELLS
Organization Name
international business machines corporation
Inventor(s)
Kangguo Cheng of Schenectady NY (US)
Julien Frougier of Albany NY (US)
Ruilong Xie of Niskayuna NY (US)
Chanro Park of Clifton Park NY (US)
Min Gyu Sung of Latham NY (US)
TWO-TRANSISTOR CHIP AND THREE-TRANSISTOR CHIP IDENTIFICATION BIT CELLS - A simplified explanation of the abstract
This abstract first appeared for US patent application 20240202305 titled 'TWO-TRANSISTOR CHIP AND THREE-TRANSISTOR CHIP IDENTIFICATION BIT CELLS
Simplified Explanation: The patent application describes a method for programming an array of bit cells in a semiconductor structure to create a unique identification code using random gate dielectric failures.
- Random gate dielectric failures are utilized to generate a binary identification code.
- Applying different logic states based on the location of the gate dielectric failure (source-side or drain-side) creates unique codes.
- The thinness of the gate dielectric compared to a control dielectric thickness influences the failure rate.
- Failure is initiated by applying a voltage to both the thin gate dielectric and the control dielectric.
- A bit cell can consist of two or three transistors, such as field-effect transistors.
Potential Applications: 1. Semiconductor security systems 2. Anti-counterfeiting measures in electronic devices 3. Unique identification codes for integrated circuits
Problems Solved: 1. Ensuring secure identification codes in semiconductor structures 2. Preventing unauthorized access to sensitive information stored in semiconductor devices
Benefits: 1. Enhanced security features in semiconductor devices 2. Reliable identification codes for authentication purposes 3. Improved anti-counterfeiting measures in the electronics industry
Commercial Applications: Title: "Semiconductor Security System Using Random Gate Dielectric Failures" This technology could be applied in the development of secure identification systems for electronic devices, enhancing their anti-counterfeiting capabilities. The market implications include increased demand for secure semiconductor solutions in industries such as consumer electronics, automotive, and healthcare.
Prior Art: Prior research in the field of semiconductor security systems may include studies on gate dielectric failures and their potential applications in creating unique identification codes.
Frequently Updated Research: Researchers may be exploring new methods to enhance the reliability and efficiency of using gate dielectric failures for generating identification codes in semiconductor structures.
Questions about Semiconductor Security Systems Using Gate Dielectric Failures: 1. How does the thickness of the gate dielectric influence the failure rate in generating identification codes? 2. What are the potential limitations of using random gate dielectric failures for creating unique codes in semiconductor structures?
Original Abstract Submitted
methods and structure are provided for programming an array of bit cells to create a unique identification code for a semiconductor structure. random failure of a gate dielectric at a transistor is utilized to generate a binary identification code. a portion of the gate is located above a source and a portion is located above a drain, a first logic state can be applied where the gate dielectric fails source-side and a second logic state can be applied where the gate dielectric fails drain-side. the gate dielectric preferentially fails as a function of its thinness versus the thickness of a second gate dielectric of a second transistor which acts as a control for failure of the gate dielectric. failure is initiated based upon a voltage applied to both the thin gate dielectric and the thick dielectric. a bit cell can include two or three transistors, e.g., field effect transistors.
