International Business Machines Corporation patent applications on June 6th, 2024
Patent Applications by International Business Machines Corporation on June 6th, 2024
International Business Machines Corporation: 68 patent applications
International Business Machines Corporation has applied for patents in the areas of H01L29/775 (16), H01L29/423 (11), H01L29/66 (10), H01L29/06 (9), H01L29/42392 (8)
With keywords such as: data, device, layer, gate, user, source, based, semiconductor, include, and embodiment in patent application abstracts.
Patent Applications by International Business Machines Corporation
Inventor(s): Eloisa Bentivegna of Warrington (GB) for international business machines corporation, Krishnasuri Narayanam of BANGALORE (IN) for international business machines corporation, Christopher J. Vollmar of Mississauga (CA) for international business machines corporation
IPC Code(s): A63B71/06
Abstract: embodiments of the invention are directed to wireless sport scoring. aspects include detecting, by a sensor of a first user device, a scoring event between a first user and a second user and transmitting, by a wireless transmitter of the first user device, a signal indicating the scoring event to a scoring system. aspects also include recording, in a memory of the first user device, a record of the scoring event and transmitting, by a wired transmitter of the first user device, the record of the scoring event to the scoring system based on detecting a wired connection between the first user device and the scoring system.
Inventor(s): Sarbajit K. RAKSHIT of Kolkata (IN) for international business machines corporation, Sathya SANTHAR of Chennai (IN) for international business machines corporation, Sridevi KANNAN of Tamil Nadu (IN) for international business machines corporation
IPC Code(s): B64G1/24, B64G1/36, B64G1/40, B64G3/00
Abstract: embodiments herein describe maneuvering a spacecraft using a solar sail when sunlight is not available. smaller satellites may rely solely on solar sails in order to maneuver to different locations (e.g., different orbits) to adjust for orbital decay, avoid collisions with other satellites, or to avoid space junk. however, solar sails cannot rely on the sun when orbiting on the dark side of a planet (e.g., when in the earth's shadow). when a spacecraft should maneuver but the sun is not available as a power source, the embodiments herein describe identifying other spacecraft within line-of-sight (los) of the spacecraft and using these spacecraft to direct lasers (or reflecting sunlight if available) at the spacecraft to maneuver it to a desired path (e.g., a new orbit).
Inventor(s): Jasbir Singh Dhaliwal of Noida (IN) for international business machines corporation, Sanket Jain of Gurgaon (IN) for international business machines corporation, Jatinder S. Joshi of Gurgaon (IN) for international business machines corporation, Vivek Dabas of Delhi (IN) for international business machines corporation
IPC Code(s): G01C21/34, G06Q10/0835, G16H40/00
Abstract: a computer-implemented method for efficiently dispatching one or more autonomous vehicles to deliver medical supplies to a destination. the method determines a level of emergency and a disease condition at the destination via a user communication interface on the one or more autonomous vehicles. the method prioritizes dispatching the one or more autonomous vehicles based on the level of emergency and the disease condition at the destination. the method optimizes a route of the one or more autonomous vehicles to the destination. the method further integrates a plurality of available data sources across multiple locations, compares these data sources, and builds deep learning (dl) forecasting models to predict several different medicines required, corresponding to a distribution of the disease condition, across the multiple locations.
Inventor(s): Subhro Das of Cambridge MA (US) for international business machines corporation
IPC Code(s): G01D18/00
Abstract: using a first sensor device in a network of sensor devices, sensor data is measured. a second sensor device comprising a trusted sensor device is selected from the network of sensor devices. a gain matrix is updated. using the gain matrix, the sensor data, and a second parameter estimate received from the second sensor device, a first parameter estimate is updated. the first parameter estimate comprises an estimate of a parameter of a model representing the first sensor device. using the gain matrix, an estimation error covariance matrix and a cross-variance matrix are updated. using the updated first parameter estimate, second sensor data measured by the first sensor device is adjusted.
Inventor(s): David Michael Audette of Colchester VT (US) for international business machines corporation, Grant Wagner of Jericho VT (US) for international business machines corporation, Peter William Neff of Cambridge VT (US) for international business machines corporation, Jacob Louis Moore of Milton VT (US) for international business machines corporation, Melissa Keefe of Cortlandt Manor NY (US) for international business machines corporation
IPC Code(s): G01R1/067
Abstract: an ic device test probe has one or more clusters of a plurality of tapered probe tips that taper upon a taper plane that is orthogonal to a seating direction or force vector of the ic device test probe toward the ic device. each of the plurality of tapered probe tips is seated against one contact of the ic device. in this manner, the ic device test probe is seated against multiple contacts and may therefore apply test signal(s) to these contacts serially, simultaneously, or the like. the ic device test probe allows the seating to small pitch ic devices and associated testing thereof. this allows for electrical characterization of the ic device by the same test signal(s) through the ic device test probe and ultimately through multiple contacts. the forces associated with seating the ic device test probe against the ic device contacts is effectively spread across multiple contacts.
Inventor(s): Christian Compton of Austin TX (US) for international business machines corporation, Jeremy R. Fox of Georgetown TX (US) for international business machines corporation, Tushar Agrawal of West Fargo ND (US) for international business machines corporation, Sarbajit K. Rakshit of Kolkata (IN) for international business machines corporation
IPC Code(s): G05B19/418
Abstract: computer-implemented methods for managing noise in an industrial environment. aspects include obtaining a layout of the industrial environment, wherein the layout includes a plurality of machines and creating a digital representation of the industrial environment, wherein the digital twin for each of the plurality of machines. aspects also include simulating operation of the industrial environment based on the digital representation and performing a sound analysis of the industrial environment based on the simulation. based on a determination that a noise level identified by the sound analysis is expected to exceed a threshold level, aspects include identifying a maintenance recommendation for one of the plurality of machines based on the digital representation of the industrial environment.
Inventor(s): David Michael Shackelford of Tucson AZ (US) for international business machines corporation, Nadim P. Shehab of TUCSON AZ (US) for international business machines corporation, Alan George McClure of Sahuarita AZ (US) for international business machines corporation, KARL GUSTAV SIIK of Saltsjoe-Duvnaes (SE) for international business machines corporation, Jose Ricardo Fernandez of Cary NC (US) for international business machines corporation
IPC Code(s): G06F3/06
Abstract: a computer-implemented method for a mirror volume comparison is provided. the computer-implemented method includes executing asynchronous remote mirroring between a primary site and a secondary site, making a first flash copy of first data at the primary site, executing asynchronous remote copying of the first flash copy to a replica at the secondary site, making a second flash copy of second data at the secondary site and performing an on-demand compare of the replica with the second flash copy to verify an accuracy of the asynchronous remote mirroring.
Inventor(s): Sudipto Chakraborty of Plano TX (US) for international business machines corporation, Rajiv Joshi of Yorktown Heights NY (US) for international business machines corporation
IPC Code(s): G06F7/523, G06F7/50
Abstract: an apparatus includes a current-mode multiply-accumulate (mac) core with a plurality of parallel current carrying paths. each path is configured to carry a unit current based on a state of an input variable, a weight, and a configuration vector. the plurality of current carrying paths are arranged in groups, and each group has a summation line. also included are a plurality of current mode interfaces. each current mode interface of the plurality of current mode interfaces is coupled to a corresponding summation line of the plurality of summation lines. a plurality of current mode comparators are coupled to the plurality of current mode interfaces and configured to compare current on the corresponding one of the plurality of summation lines to a plurality of corresponding reference currents.
Inventor(s): Sthanikam Santhosh Kumar of Punganuru (IN) for international business machines corporation, Meena A of Bangalore (IN) for international business machines corporation, Supriya Devidutta of Bhubaneswar (IN) for international business machines corporation, Koosappa M of Bangalore (IN) for international business machines corporation, Manish Kumar Dash of Khallikote (IN) for international business machines corporation
IPC Code(s): G06F8/30
Abstract: mechanisms are provided for generating electronic data interchange mapping source code. a source code generator, comprising a machine learning trained neural network computer model, receives input data comprising a source document data structure in a first format and a destination document data structure in a second format, different from the first format. the source code generator processes the input data to generate a source code sequence output vector. a source code is generated that maps contents of source documents in the first format to contents of destination documents in the second format based on the source code sequence output vector. the source code is output to a computing device for execution on other source documents that utilize the first format to thereby automatically generate corresponding destination documents in the second format.
Inventor(s): Xiao Ling CHEN of Changping District (CN) for international business machines corporation, Si Yu CHEN of Beijing (CN) for international business machines corporation, Juliet CANDEE of Brewster NY (US) for international business machines corporation, Yan Fei QIN of Beijing (CN) for international business machines corporation, Hao WU of Beijing (CN) for international business machines corporation, Wen Bin HAN of Beijing (CN) for international business machines corporation
IPC Code(s): G06F8/61, G06F9/54
Abstract: computer implemented method, systems, and computer program products include program code executing on a processor(s) obtain a first container comprising image layers, wherein the image layers include a base image layer and one or more image layers. the program code determines dependencies between the image layers. the program code obtains a request for an application where at least one image layer of the one or more image layers comprises features of the application. the program code identifies, based on the dependencies, at least one additional image layer related to the at least one image layer. the program code generates and deploys a second container, where image layers of the second container consist of the at least one image layer, the at least one additional image layer related to the at least one image layer, and the base layer.
Inventor(s): Jacob Ryan Jepperson of St. Paul MN (US) for international business machines corporation, Zachary A. Silverstein of Georgetown TX (US) for international business machines corporation, Jeremy R. Fox of Georgetown TX (US) for international business machines corporation, Spencer Thomas Reynolds of Austin TX (US) for international business machines corporation
IPC Code(s): G06F8/65, G06Q20/36
Abstract: a computer hardware system includes a machine learning engine and a hardware processor configured to perform the following executable operations. a stake in a software product is converted into feature development tokens to be stored in the digital wallet. a description of a plurality of proposed product features for the software product and previously-stored within a blockchain are forwarded to a usage user via a usage user portal. a plurality of the feature development tokens are allocated, using the usage user portal, to a selected one of the proposed product features. the digital wallet and the blockchain are updated based upon the allocating. an objective analysis is performed on the plurality of proposed product features using the machine learning engine. the blockchain is updated based upon a delivered one of the plurality of the proposed product features.
Inventor(s): Lei Gao of Xian (CN) for international business machines corporation, Jin Wang of Xian (CN) for international business machines corporation, A PENG ZHANG of Xian (CN) for international business machines corporation, Kai Li of Xian (CN) for international business machines corporation, Matthew Wayne Howard of Racine MN (US) for international business machines corporation
IPC Code(s): G06F8/71
Abstract: an embodiment for an improved method of automated version management for machine learning pipeline development is provided. the embodiment may compute a quality value of a target machine learning pipeline at a predetermined regular interval and automatically save updated versions of the target machine learning pipeline. the embodiment may extract a series of key features from detected versions of the target machine learning pipeline and cluster the detected versions of the target machine learning model pipeline by the extracted series of key features. the embodiment may identify a highest-quality version within each of a series of generated clusters. the embodiment may compute similarity scores for subsets of versions within each of the series of generated clusters. the embodiment may generate and output to a user, a visual representation of the series of generated clusters including version quality data and version similarity data.
Inventor(s): Abhishek Malvankar of White Plains NY (US) for international business machines corporation, Alaa S. Youssef of Valhalla NY (US) for international business machines corporation, Diana Jeanne Arroyo of Austin TX (US) for international business machines corporation, Asser Nasreldin Tantawi of Somers NY (US) for international business machines corporation
IPC Code(s): G06F9/455, G06F9/48
Abstract: disclosed embodiments provide techniques for compute job allocation in a virtualized computing environment. a first list of compute jobs that are currently executing in a virtualized environment is obtained. for each job in the first list, a job description file is obtained. an entity extraction process is performed on the job description file to extract a plurality of job entities. multiple clusters are created that correspond to the compute jobs in the first list. a second list of compute jobs that are currently queued for execution is obtained. compute jobs in the second list are assigned to a cluster from the plurality of clusters, and the virtualized environment is reused for execution of a compute job from the second list based on the assigned cluster.
Inventor(s): Ye Fan of Xian (CN) for international business machines corporation, Chong Liu of Xian (CN) for international business machines corporation, Yang Yang of Xian (CN) for international business machines corporation, Juan Wu of Xi'an (CN) for international business machines corporation, Xu Lu of Xi'an (CN) for international business machines corporation, Jin Xu of Xian (CN) for international business machines corporation
IPC Code(s): G06F9/50, G06F3/06
Abstract: in an approach, a processor divides a set of data into at least two smaller data blocks. for each of the at least two smaller data blocks, a processor calculates an original value for a data distribution of a respective smaller data block, runs at least two different sampling methods against the respective smaller data block to produce at least two different sets of sample data for the respective smaller data block, calculates respective sampling values for the data distribution of each set of sample data, and selects a set of sample data of the at least two different sets of sample data that has the respective sampling value that is closest to the original value for the respective smaller data block. a processor merges each selected set of sample data for each smaller data block to form a final set of sample data.
Inventor(s): Sudheesh S. Kairali of Kozhikode (IN) for international business machines corporation, Sarbajit K. Rakshit of Kolkata (IN) for international business machines corporation
IPC Code(s): G06F9/50
Abstract: a system may include a memory and a processor in communication with the memory. the processor may be configured to perform operations. the operations may include acquiring historical data and identifying a pattern in the historical data. the operations may include predicting a predicted task request based on the historical data and the pattern such that the predicted task request anticipates a task request. the operations may include calculating predicted resource requirements for the predicted task request and allocating resources for the predicted task request. the operations may include receiving the task request, assigning the allocated resources to the task request, and deploying the allocated resources for the task request.
Inventor(s): Neelamadhav Gantayat of Bangalore (IN) for international business machines corporation, Renuka Sindhgatta Rajan of Bengaluru (IN) for international business machines corporation, Avirup Saha of Kolkata (IN) for international business machines corporation, Sampath Dechu of Acton MA (US) for international business machines corporation
IPC Code(s): G06F11/00, G06F11/34
Abstract: scheduling it maintenance based on key performance indicators (kpis) includes receiving current information technology (it) data corresponding to an it system and current process data corresponding to a process implemented with the it system. a suffix and time prediction model generates a suffix prediction of a likely sequence of suffixes given a prefix of the process and a time prediction of time remaining to complete the likely sequence of suffixes, wherein the suffix and time predictions are based on based on the it data and current process data; a load on each of step of the process is determined based on the suffix and time prediction; one or more kpi metrics of the process is determined based on the load of each step. an it maintenance schedule output is generated based on the one or more kpi metrics.
20240184755.CAPSULE MIGRATION_simplified_abstract_(international business machines corporation)
Inventor(s): Brent Philip Eicher of Mooresville NC (US) for international business machines corporation
IPC Code(s): G06F16/21, G06F16/26
Abstract: embodiments of the present invention provide computer-implemented methods, computer program products and computer systems. for example, embodiments of the present invention can, in response to receiving a request, analyze one or more components of a network. embodiments of the present invention can predict an optimal migration path for the one or more components of the network based, at least in part on an opportunity rating for each respective component of the network. embodiments of the present invention can then generate one or more recommendations based on the predicted optimal migration path of the one or more components.
Inventor(s): SHUHO KIDOKORO of Ichikawa (JP) for international business machines corporation, YOJIRO ADACHI of Yokohama-shi (JP) for international business machines corporation, Tomoyuki Kawamukoh of Chiba-shi (JP) for international business machines corporation, Tomokazu Ohtsu of Sakura-shi (JP) for international business machines corporation
IPC Code(s): G06F16/215, G06F16/2458, G06F16/28
Abstract: according to an aspect, a computer-implemented method includes collecting statistics of an original database and collecting statistics of a sampling database that includes a subset of the original database. the statistics of the original database are periodically updated. the statistics of the original database and the statistics of the sampling database are periodically compared to determine whether the sampling database is within a predetermined threshold of the original database. in response to determining that the sampling database is not within the predetermined threshold of the original database, an update to the sampling database is initiated.
Inventor(s): Shailesh Chandra Jamloki of Noida (IN) for international business machines corporation, Girish V. Mattur of Bangalore (IN) for international business machines corporation
IPC Code(s): G06F16/27, G06F16/22, G06F16/25
Abstract: an approach is provided for detecting a data discrepancy in a replication pipeline. during a live data replication process that includes moving logical records in the replication pipeline from a source database to a target database via component(s), a raw record is read from a log entry. a logical record is obtained by converting the raw record. the logical record is moved in the replication pipeline so that a next component receives the logical record. responsive to obtaining or receiving the logical record, metadata is updated in sorted hashmaps. a data discrepancy is detected between the obtained logical record and the moved logical record by analyzing the updated metadata.
Inventor(s): Jennifer I. Bennett of Rochester MN (US) for international business machines corporation, William J Green of Cary NC (US) for international business machines corporation, Jeremy Miner of Cary NC (US) for international business machines corporation, Carolina Garcia Delgado of Zapopan (MX) for international business machines corporation
IPC Code(s): G06F21/78, G06F1/3234
Abstract: digital data stored on a data storage device is secured by rendering the data storage device inoperable. an insulating tab can be coupled to a battery where the insulating tab is positioned between an electric output for the battery and a power circuit for the data storage device. the insulating tab can be positioned between the data storage device and a structure, such that when the structure is compromised to access the storage device, the insulating tab is decoupled from the battery and an electric output at a voltage level is delivered by the battery to the storage device via the power circuit. the voltage level renders the storage device inoperable by providing an overvoltage to one or more electrical components of the storage device.
Inventor(s): Victor N. KRAVETS of Bangalore (IN) for international business machines corporation, Gi-Joon NAM of Chappaqua NY (US) for international business machines corporation, Alexey Y. LVOV of Congers NY (US) for international business machines corporation, Ashish JAITLY of Bangalore (IN) for international business machines corporation
IPC Code(s): G06F30/33
Abstract: a method includes receiving a circuit design and a specification for the circuit design and determining a first hypothesized change to the circuit design. making the first hypothesized change to the circuit design produces a first changed circuit design. the method also includes determining a first counterexample input that causes the first changed circuit design to produce an output that departs from the specification and determining a second hypothesized change to the circuit design based at least in part on the first hypothesized change. making the second hypothesized change to the circuit design produces a second changed circuit design. the method further includes, in response to determining that the second changed circuit design has no counterexample input that causes the second changed circuit design to produce an output that departs from the specification, making the second hypothesized change to the circuit design.
Inventor(s): K. Paul Muller of Wappingers Falls NY (US) for international business machines corporation, Luiz C. Alves of Hopewell Junction NY (US) for international business machines corporation, William J. Clarke of Poughkeepsie NY (US) for international business machines corporation, Steven R. Carlough of Poughkeepsie NY (US) for international business machines corporation
IPC Code(s): G06F30/392
Abstract: a method for bit line alignment during the design of an integrated circuit is provided. aspects include receiving a chip design for the integrated circuit and receiving an intended orientation of the integrated circuit. aspects also include identifying one or more elements of the chip design that include word lines that are oriented in a substantially gravitational direction and modifying the chip design to perform one or more of rotating the one or more elements such that the word lines are no longer oriented in a substantially gravitational direction and rotating the one or more elements such that the word lines are oriented in a direction substantially perpendicular to the gravitational direction. aspects further include causing the fabrication of the integrated circuit based on the modified chip design.
Inventor(s): James William Murdock, IV of Amawalk NY (US) for international business machines corporation, Radha Mohan De of Howrah (IN) for international business machines corporation, Sneha Srinivasan of San Jose CA (US) for international business machines corporation, Mary Diane Swift of Rochester NY (US) for international business machines corporation, Caesar Chatterjee of Kolkata (IN) for international business machines corporation
IPC Code(s): G06F40/186, G06F40/30, G06V30/412
Abstract: various systems and methods are presented regarding automatically generating a document for a particular topic, and further utilizing an algorithm to automatically identify information in a resource that pertains to the topic. the document can be a purpose-specific document, created by a template configured to combine data fields to build the document. each data field can be subject-matter specific with an associated algorithm. the algorithm can be trained to recognize and extract content that potentially meets the subject matter of the data field. the data field can be populated with the content. subsequent editing of the content populating the data field can be monitored to determine an effectiveness of the algorithm to identify data of interest in the data repository. in the event of low success, the algorithm can be retrained. further, the document can be regenerated if an algorithm is retrained, new information added to the repository, etc.
Inventor(s): Muntasir Wahed of Blacksburg VA (US) for international business machines corporation, Daniel Gruhl of San Jose CA (US) for international business machines corporation
IPC Code(s): G06F40/47, G06F40/237, G06F40/30
Abstract: disclosed herein are methods, systems, and computer program products for selecting an artificial intelligence (ai) model. aspects include receiving, by a multi-armed bandit agent, candidate entities from multiple set expansion models and selecting a subset of the candidate entities for a first set expansion task, wherein a first candidate entity of the selected subset of candidate entities is selected from a first model by a subject matter expert. aspects also include selecting, by the multi-armed bandit agent, based on the first candidate entity selected by the subject matter expert, the first model from the set expansion models for generating further candidate entities.
Inventor(s): Deepak Vijaykeerthy of Bangalore (IN) for international business machines corporation, Nishtha Madaan of Gurgaon (IN) for international business machines corporation, Swagatam Haldar of Kolkata (IN) for international business machines corporation, Aniya Aggarwal of NEW DELHI (IN) for international business machines corporation, Diptikalyan Saha of Bangalore (IN) for international business machines corporation
IPC Code(s): G06N3/045, G06N3/08
Abstract: using encoded representations of target model training data and a label corresponding to each portion of the target model training data, a proxy model to determine an uncertainty score corresponding to an output of a trained target model is trained. using the trained proxy model, a set of uncertainty scores is computed, each uncertainty score in the set of uncertainty scores corresponding to a portion of target model testing data in a set of target model testing data. a subset of the set of target model testing data is selected, the subset comprising a plurality of portions of target model testing data having an uncertainty score above a threshold uncertainty score. using the subset of the set of target model testing data, the trained target model.
Inventor(s): Takashi Ando of Eastchester NY (US) for international business machines corporation, Martin Michael Frank of Dobbs Ferry NY (US) for international business machines corporation, Timothy Mathew Philip of Albany NY (US) for international business machines corporation, Vijay Narayanan of New York NY (US) for international business machines corporation
IPC Code(s): G06N3/08, G06F3/06, G06N3/065
Abstract: systems, methods, and semiconductor devices for transfer learning are described. a semiconductor device can include a first non-volatile memory (nvm) and a second nvm. the first nvm can be configured to store weights of a first set of layers of a machine learning model. the weights of the first set of layers can be fixed. the second nvm can be configured to store weights of a second set of layers of the machine learning model. the weights of the second set of layers can be adjustable.
Inventor(s): Yash Vardhan Singh of Bangalore (IN) for international business machines corporation, Khushboo Tak of Bangalore (IN) for international business machines corporation, Parmar Yogeshbhai of Gujarat (IN) for international business machines corporation, Trapti Kalra of Gurgaon (IN) for international business machines corporation
IPC Code(s): G06N3/0895, G06N3/04
Abstract: a holistic approach to determining resource authenticity using similarity-based clustering of resource images. resource images are input to generate image embeddings for an embedding space including generated embeddings for known authentic and known counterfeit resources. similarity-based clustering processes identify outlier embeddings in the embedding space for determination of authenticity. a set of outlier embeddings for counterfeit resource images is the basis for creating new clusters representing previously unrecognized counterfeit resources.
Inventor(s): Don Joven Ravoy Agravante of Tokyo (JP) for international business machines corporation, Daiki Kimura of Midori-ku (JP) for international business machines corporation, Michiaki Tatsubori of Oiso (JP) for international business machines corporation
IPC Code(s): G06N3/092, G06F40/205, G06F40/30, G06N3/042
Abstract: mechanisms are provided for a model-based reinforcement learning (rl) computing system. a proprioception module receives a previous state of an environment and a previous action taken by an agent in the environment, and estimates a current state by using a transition model which receives a pair of state and action and produces a next state. the proprioception module modifies an estimate of the transition model so that the modified estimate of the transition model prevents a past invalid action from recurring in a corresponding state, where the past invalid action taken in the corresponding state is one that did not cause a change in state. the proprioception module passes the current state and the modified estimate of the transition model to a model-based rl computer model for generation of a next action to take in the environment.
Inventor(s): Malcolm Scott Carroll of Cranbury NJ (US) for international business machines corporation, Sami Rosenblatt of White Plains NY (US) for international business machines corporation, Abhinav Kandala of Yorktown Heights NY (US) for international business machines corporation
IPC Code(s): G06N10/20
Abstract: one or more systems, devices, computer program products and/or computer-implemented methods of use provided herein relate to determining estimated energy relaxation times of qubits. a system can comprise a memory configured to store computer executable components; and a processor configured to execute the computer executable components stored in the memory, wherein the computer executable components comprise a sampling component configured to sample a plurality of measurements of an energy relaxation time of a qubit at individual shifted qubit frequencies of a plurality of shifted qubit frequencies of the qubit; and an analysis component configured to perform an analysis, based on a protocol, to determine a correlation frequency-length between individual energy relaxation times measured at the individual shifted qubit frequencies.
Inventor(s): Hagai Aronowitz of Modiin (IL) for international business machines corporation, Itai Gat of Tel-Aviv (IL) for international business machines corporation
IPC Code(s): G06N20/00
Abstract: a computer-implemented method including: obtaining a pre-trained upstream machine learning model; fine-tuning the pre-trained upstream model for at least two downstream tasks, wherein the fine-tuning comprises: (a) training a target downstream model for a target downstream task, based on a dataset with labeling specific to the target downstream task, and (b) training a nuisance downstream model for a nuisance downstream task, based on a dataset with labeling of characteristics which are specific to the nuisance downstream task and are undesired for the target downstream task; and normalizing the undesired characteristics from the pre-trained upstream model, to prevent biasing of the target downstream model by the undesired characteristics.
Inventor(s): YADA ZHU of Irvington NY (US) for international business machines corporation, Zixuan Yuan of Edison NJ (US) for international business machines corporation, David Cox of Somerville MA (US) for international business machines corporation, Anna Wanda Topol of Clifton Park NY (US) for international business machines corporation
IPC Code(s): G06Q30/02, G06F40/126, G06F40/166, G06F40/30
Abstract: unsupervised cross-domain data augmentation techniques for long-text document based prediction and explanation are provided. in one aspect, a system for long-document based prediction includes: an encoder for creating embeddings of long-document texts with hierarchical sparse self-attention, and making predictions using the embeddings of the long-document texts; and a multi-source counterfactual augmentation module for generating perturbed long-document texts using unlabeled sentences from at least one external source to train the encoder. a method for long-document based prediction is also provided.
Inventor(s): William Bruce Nicol, II of Durham NC (US) for international business machines corporation, Lakshminarayanan Srinivasan of Cary NC (US) for international business machines corporation, Peter Yim of Raleigh NC (US) for international business machines corporation, John Handy Bosma of Leander TX (US) for international business machines corporation
IPC Code(s): G06Q30/0207, G06Q30/0211, G06Q30/0235
Abstract: a method, computer system, and a computer program product for store optimization is provided. the present invention may include monitoring a plurality of consumers for a physical store. the present invention may include receiving an alert. the present invention may include determining one or more incentives to offer the plurality of consumers based on the alert. the present invention may include applying the one or more incentives to a product inventor of the physical store.
Inventor(s): Martin G. Keen of Cary NC (US) for international business machines corporation, Makenzie Manna of Poughkeepsie NY (US) for international business machines corporation, Ivan Deleuze of Montpellier (FR) for international business machines corporation, Victor Tardieu of Montpellier (FR) for international business machines corporation
IPC Code(s): G06Q30/0601
Abstract: artificial intelligence (ai) is used to generate contextual wearable device recommendations to a user. data is received at a computer that characterizes a user's environment, wherein the user environment includes location data. a prediction is made of user activity. a prediction is made, with a computer, of user activity from the location data. predicting the user activity includes artificial intelligence analyzing the location data for comparison with activities from historical activity data for the user. a list of wearable devices that are present on the user are characterized by sensors for capability. at least one of the wearable devices is matched to the user activity. by employing artificial intelligence the computer wearable devices are matched by capability of their sensor to the user activity
Inventor(s): Shubhi Asthana of Santa Clara CA (US) for international business machines corporation, Bing Zhang of San Jose CA (US) for international business machines corporation, Pawan Raghunath Chowdhary of San Jose CA (US) for international business machines corporation, Taiga Nakamura of Sunnyvale CA (US) for international business machines corporation
IPC Code(s): G06Q30/06, G06F40/20, G06N3/04
Abstract: an embodiment for methods of processing invoices and purchase orders is provided. the embodiment may receive a set of invoices. the embodiment may cluster the set of invoices based on a series of invoice attributes. the embodiment may then utilize a multitask deep neural network model to split a generated cluster of invoices into subsets of invoices based on a series of invoice features. the embodiment may utilize a second deep neural network model to identify one or more prioritized subsets of invoices in the subsets of invoices that meet a purchase order match probability threshold. the embodiment may perform text mining on the one or more prioritized subsets of invoices to identify matching item-level services between individual invoices in the prioritized subset of invoices and a target purchase order. the embodiment may output matching invoices corresponding to the target purchase order.
Inventor(s): Jeremy R. Fox of Georgetown TX (US) for international business machines corporation, Michael Boone of Lutz FL (US) for international business machines corporation, Tushar Agrawal of West Fargo ND (US) for international business machines corporation, Sarbajit K. Rakshit of Kolkata (IN) for international business machines corporation
IPC Code(s): G06T19/00, B29C64/393, B33Y50/02
Abstract: a 3d model modification system may receive a 3d model and information on a physical object. the 3d model modification system may modify the 3d model to interface with the physical object and manufacture the 3d model into a 3d physical part.
Inventor(s): Simona Rabinovici-Cohen of Haifa (IL) for international business machines corporation, Ella Barkan of () for international business machines corporation, Tal Tlusty Shapiro of Zichron Yaacov (IL) for international business machines corporation
IPC Code(s): G06V10/774, G06N3/0464, G06V10/40, G06V10/762, G06V10/771, G06V10/776, G06V10/82
Abstract: an embodiment for generating balanced train-test splits for machine learning analysis. the embodiment may automatically extract low-level features and high-level features from a series of received datasets. the embodiment may automatically determine a series of impactful features for each of the received datasets correlating to a corresponding label. the embodiment may automatically select subsets of impactful features the embodiment may automatically cluster the received datasets to generate series of clusters, each of the generated series of clusters corresponding to one of the selected subsets of impactful features. the embodiment may automatically generate train-test split versions using datasets from each cluster in each of the generated series of clusters. the embodiment may automatically score each of the generated train-test split versions and select a highest-scoring train-test split version.
Inventor(s): Sudheesh S. Kairali of Kozhikode (IN) for international business machines corporation, Sarbajit K. Rakshit of Kolkata (IN) for international business machines corporation
IPC Code(s): G08G1/01, G06F30/20
Abstract: an embodiment for dynamically arranging vehicles on a smart crossing is provided. the embodiment may include receiving data relating to a maximum carrying capacity of a smart crossing having one or more sensors. the embodiment may also include predicting a current load carrying capacity of the smart crossing. the embodiment may further include identifying a number of vehicles traveling towards the smart crossing within a pre-defined distance of the smart crossing. the embodiment may also include identifying one or more specifications and a current arrangement of each vehicle. the embodiment may further include executing a digital twin simulation of a digital twin model of each vehicle driving across the smart crossing. the embodiment may also include in response to determining the current load carrying capacity is exceeded, assigning a priority level to each vehicle. the embodiment may further include predicting a modification of the current arrangement of each vehicle.
Inventor(s): Ashok Kumar Iyengar of Encinitas CA (US) for international business machines corporation, Trudy L. Hewitt of Cary NC (US) for international business machines corporation, Venkata Vishwanath Gadepalli of Apex NC (US) for international business machines corporation, Jeremy R. Fox of Georgetown TX (US) for international business machines corporation
IPC Code(s): G10L17/22, G10L13/027, G10L25/54
Abstract: a computer-implemented method, a computer system and a computer program product generate a query response in an environment based on predicted relationships between users. the method includes capturing a question with a device in the environment, where the question includes a speaking voice and is selected from a group consisting of: video data, audio data and text data. the method also includes identifying the speaker of the question based on the speaking voice. the method further includes determining a relationship between the question and each user interaction in a database of user interactions, where each user interaction is associated with a user. in addition, the method includes selecting a response from the database of user interactions based on the relationship. lastly, the method includes transmitting the response to the speaker of the question in the environment, where the transmission of the response uses a voice of the user.
Inventor(s): John S. Werner of Fishkill NY (US) for international business machines corporation, Brian Fernandez of Poughkeepsie NY (US) for international business machines corporation, Philip David Atwood of Poughkeepsie NY (US) for international business machines corporation, Abraham Mitchell of Saint Albans NY (US) for international business machines corporation
IPC Code(s): G11B27/00, H04N21/45, H04N21/845
Abstract: in an approach to playback speed adjustment, one or more computer processors extract metadata from a media file previously consumed by a user. one or more computer processors determine the metadata includes an eigenvector associated with each segment of the media file. one or more computer processors import data associated with actions taken by the user while the user consumed the media file. based on the data associated with the actions taken by the user while the user consumed the media file, one or more computer processors extract the eigenvector and an associated eigenvalue of each previously consumed segment of the media file from the data associated with actions taken by the user while the user consumed the media file. one or more computer processors add the eigenvector and the associated eigenvalue of each previously consumed segment of the media file to a user profile.
Inventor(s): Nicholas Anthony Lanzillo of Wynantskill NY (US) for international business machines corporation, Reinaldo Vega of Mahopac NY (US) for international business machines corporation, Takashi Ando of Eastchester NY (US) for international business machines corporation, David Wolpert of Poughkeepsie NY (US) for international business machines corporation
IPC Code(s): H01L21/768, H01L23/522, H01L23/528, H01L23/532
Abstract: a semiconductor interconnect structure and formation thereof. the semiconductor interconnect structure includes a skip via. the skip via includes a first skip via segment vertically connected to a second skip via segment. the first skip via segment has a first width and the second skip via segment has a second width.
Inventor(s): Tsung-Sheng Kang of Ballston Lake NY (US) for international business machines corporation, Tao Li of Slingerlands NY (US) for international business machines corporation, Ruilong Xie of Niskayuna NY (US) for international business machines corporation, Chih-Chao Yang of Glenmont NY (US) for international business machines corporation
IPC Code(s): H01L23/48, H01L29/06, H01L29/417, H01L29/66, H01L29/786
Abstract: a semiconductor structure includes a first backside power rail disposed on a portion of a sidewall and a bottom surface of a backside source/drain contact, a first sidewall spacer disposed on another sidewall of the backside source/drain contact, and a backside signal line disposed on the first sidewall spacer and separated from the backside source/drain contact.
Inventor(s): Oscar van der Straten of Guilderland Center NY (US) for international business machines corporation, Koichi Motoyama of Clifton Park NY (US) for international business machines corporation, Chih-Chao Yang of Glenmont NY (US) for international business machines corporation
IPC Code(s): H01L23/528, H01L21/768, H01L23/522, H01L23/532
Abstract: interconnect wire structures and techniques for fabrication thereof with uniform line profile and height are provided. in one aspect, a structure is provided that includes: a wafer; a first interlayer dielectric disposed on the wafer; a second interlayer dielectric disposed on the first interlayer dielectric; and an interconnect wire(s) embedded in the first interlayer dielectric and the second interlayer dielectric, where a first portion of a top half of the interconnect wire(s) has vertical sidewalls, and where a second portion of the top half of the interconnect wire(s) and a bottom half of the interconnect wire(s) have flared sidewalls. a first barrier layer and a (potentially different) second barrier layer can separate the bottom half and top half of the interconnect wire(s) from the first and second interlayer dielectrics. a method for forming the interconnect wire(s) is also provided.
Inventor(s): Ruilong Xie of Niskayuna NY (US) for international business machines corporation, Kisik Choi of Watervliet NY (US) for international business machines corporation, Reinaldo Vega of Mahopac NY (US) for international business machines corporation, Albert M. Chu of Nashua NH (US) for international business machines corporation, Nicholas Anthony Lanzillo of Wynantskill NY (US) for international business machines corporation, Lawrence A. Clevenger of Saratoga Springs NY (US) for international business machines corporation
IPC Code(s): H01L23/528, H01L21/8234, H01L27/088, H01L29/06, H01L29/417, H01L29/423, H01L29/66, H01L29/775
Abstract: one or more systems, devices, and/or methods of fabrication provided herein relate to reduced parasitic capacitance of power via bars. according to one embodiment, a semiconductor device can comprise a field-effect transistor (fet), and a power via bar coupled to a backside power rail, wherein the power via bar has greater height adjacent to a source and drain region of the field-effect transistor (fet) relative to a gate of the fet to mitigates parasitic capacitance within the device.
Inventor(s): Tao Li of Slingerlands NY (US) for international business machines corporation, Ruilong Xie of Niskayuna NY (US) for international business machines corporation
IPC Code(s): H01L23/528, H01L27/088, H01L29/417
Abstract: a microelectronic architecture including a logic device and a header gate transistor located adjacent to a first side of the logic device. the header gate transistor has a parallel orientation to the logic device, and the header gate transistor is connected to a vss source or a vdd source. aa footer gate transistor located adjacent to a second side of the logic device and the footer gate transistor has parallel orientation to the logic device. the first side and the second side are opposite sides of the logic device and the footer gate transistor is connected to a vss source or a vdd source. the footer gate transistor is connected to a different source than the header gate transistor and the logic device is connected to the vss source and the vdd source through either footer gate transistor and the header gate transistor.
Inventor(s): Bogdan Cezar Zota of Rueschlikon (CH) for international business machines corporation, Bernd W. Gotsmann of Horgen (CH) for international business machines corporation, Heinz Schmid of Horgen (CH) for international business machines corporation, Alan Molinari of Kilchberg (CH) for international business machines corporation, Lorenzo Rocchino of Zurich (CH) for international business machines corporation
IPC Code(s): H01L23/532, H01L21/8238, H01L23/522, H01L23/528
Abstract: described is an integrated circuit device comprising one or more interconnects. each interconnect of the one or more interconnects can be structured as a stack of layers including distinct topological layers, where each of the distinct topological layers can be a layer of topological material. any two successive layers of the distinct topological layers can be separated by one or more interfaces, each forming a boundary between two consecutive layers of the stack, where the two consecutive layers can be engineered to preserve topologically protected surface states of each of the any two successive layers of the distinct topological layers.
Inventor(s): Ruilong Xie of Niskayuna NY (US) for international business machines corporation, Julien Frougier of Albany NY (US) for international business machines corporation, Alexander Reznicek of Troy NY (US) for international business machines corporation, Sagarika Mukesh of Albany NY (US) for international business machines corporation
IPC Code(s): H01L27/06, H01L29/06, H01L29/423, H01L29/66, H01L29/775
Abstract: a semiconductor device is provided. the semiconductor device includes: a first nanosheet device including a plurality of active semiconductor layers, a first metal stack wrapping around the active semiconductor layers, and a first gate insulator layer between the active semiconductor layers and the first metal stack; and a second nanosheet device including a second metal contact, the first metal stack wrapping around the second metal contact, and a second gate insulator between the second metal contact and the first metal stack.
Inventor(s): Albert M. Chu of Nashua NH (US) for international business machines corporation, Junli Wang of Slingerlands NY (US) for international business machines corporation, Jay William Strane of Warwick NY (US) for international business machines corporation
IPC Code(s): H01L27/092, H01L29/423
Abstract: a semiconductor structure is presented having a first field effect transistor (fet) including a first device layer, a second fet including a second device layer, where the first device layer has a stepped portion with respect to the second device layer, and an electrical connection between a gate of the first fet and a gate of the second fet at the stepped portion of the first device layer. the first fet is stacked over the second fet. the second device layer is larger than the first device layer. the gate of the first fet is positioned above the first device layer having a stepped portion.
Inventor(s): Koichi Motoyama of Clifton Park NY (US) for international business machines corporation, Ruilong Xie of Niskayuna NY (US) for international business machines corporation, Julien Frougier of Albany NY (US) for international business machines corporation, Nicolas Jean Loubet of GUILDERLAND NY (US) for international business machines corporation, Kangguo Cheng of Schenectady NY (US) for international business machines corporation
IPC Code(s): H01L27/092, H01L21/285, H01L21/822, H01L21/8238, H01L29/06, H01L29/08, H01L29/417, H01L29/423, H01L29/45, H01L29/66, H01L29/775
Abstract: a stacked transistor structure including a top source drain region above a bottom source drain region, where a width of the bottom source drain region is greater than a width of the top source drain region, a bottom contact structure directly above and in electrical contact with the bottom source drain region, a metal silicide between the bottom source drain region and the bottom contact structure, the metal silicide having a width larger than a width of the bottom contact structure; a replacement spacer surrounding the bottom contact structure; and a top gate spacer separating the replacement spacer from a gate conductor.
Inventor(s): Ruilong Xie of Niskayuna NY (US) for international business machines corporation, Alexander Reznicek of Troy NY (US) for international business machines corporation, Daniel Schmidt of Niskayuna NY (US) for international business machines corporation, Tsung-Sheng Kang of Ballston Lake NY (US) for international business machines corporation
IPC Code(s): H01L29/06, H01L21/8234, H01L23/48, H01L29/08, H01L29/66, H01L29/775, H01L29/786
Abstract: embodiments are disclosed for a method for fabricating a semiconductor device. the method includes forming a recess under a region for a source/drain (s/d). the method further includes depositing a sacrificial placeholder liner conformally. additionally, the method includes performing a sacrificial material overfill. further, the method includes performing an etch back of the sacrificial material overfill. also, the method includes performing s/d epitaxial (epi) growth over a remaining placeholder sacrificial liner to generate an s/d epi for the s/d.
Inventor(s): Brent A. Anderson of Jericho VT (US) for international business machines corporation, Ruilong Xie of Niskayuna NY (US) for international business machines corporation, Albert M. Chu of Nashua NH (US) for international business machines corporation, Hemanth Jagannathan of Niskayuna NY (US) for international business machines corporation, Junli Wang of Slingerlands NY (US) for international business machines corporation
IPC Code(s): H01L29/06, H01L23/528, H01L27/092, H01L29/423, H01L29/78
Abstract: a semiconductor structure including a vertical semiconductor channel region, a bottom source drain region arranged on a substrate at a bottom of the vertical semiconductor channel region, a metal gate disposed around the vertical semiconductor channel region, where a first portion of the metal gate extends above the vertical semiconductor channel region, and a gate contact entirely above the vertical semiconductor channel region.
Inventor(s): Brent A. Anderson of Jericho VT (US) for international business machines corporation, Ruilong Xie of Niskayuna NY (US) for international business machines corporation, Albert M. Chu of Nashua NH (US) for international business machines corporation, Junli Wang of Slingerlands NY (US) for international business machines corporation
IPC Code(s): H01L29/06, H01L29/423, H01L29/78
Abstract: a semiconductor structure including a vertical semiconductor channel region, a bottom source drain region arranged on a substrate below the vertical semiconductor channel region, and a metal gate disposed around the vertical semiconductor channel region, where a first end of the vertical semiconductor channel region is aligned with a first end of the metal gate.
Inventor(s): Jin Ping Han of Yorktown Heights NY (US) for international business machines corporation, Jianshi Tang of Elmsford NY (US) for international business machines corporation, Kevin K. Chan of Staten Island NY (US) for international business machines corporation, Ahmet Serkan Ozcan of Los Altos CA (US) for international business machines corporation
IPC Code(s): H01L29/40, H01L29/49, H01L29/51, H01L29/66, H01L29/786, H10K10/46
Abstract: a method of making a mobile ion regulated device includes stacking a dielectric layer on a substrate. mobile ions are placed within the dielectric layer. an electrode layer is provided on the dielectric layer. the mobile ions are directed to a designated area of the dielectric layer.
Inventor(s): Ruilong Xie of Niskayuna NY (US) for international business machines corporation, Min Gyu Sung of Latham NY (US) for international business machines corporation, Chanro Park of Clifton Park NY (US) for international business machines corporation, Kangguo Cheng of Schenectady NY (US) for international business machines corporation, Julien Frougier of Albany NY (US) for international business machines corporation
IPC Code(s): H01L29/417, H01L21/28, H01L21/8238, H01L23/528, H01L27/092, H01L29/06, H01L29/423, H01L29/66, H01L29/775
Abstract: a microelectronic structure including a first nano device that includes a plurality of first transistors and the plurality of first transistors includes at least one first source/drain. a second nano device includes a plurality of second transistors and the second nano device is oriented parallel to the first nano device. the plurality of second transistors includes at least two second source/drains. a gate cut located between the first nano device and the second nano device. a source/drain contact connected to the at least one first source/drain and is connected to at least one of the second source/drains. a portion of the source/drain contact extends parallel to the first nano device and the second nano device.
Inventor(s): Julien Frougier of Albany NY (US) for international business machines corporation, Sung Dae Suk of Watervliet NY (US) for international business machines corporation, Ruilong Xie of Niskayuna NY (US) for international business machines corporation, Christopher J. Waskiewicz of Rexford NY (US) for international business machines corporation, Veeraraghavan S. Basker of Fremont CA (US) for international business machines corporation
IPC Code(s): H01L29/423, H01L29/06, H01L29/08, H01L29/417, H01L29/66, H01L29/775, H01L29/786
Abstract: a semiconductor structure includes a first gate-all-around device disposed on a first region of a substrate and a second gate-all-around device disposed on a second region of the substrate. the first gate-all-around device includes a first metal gate stack surrounding a first channel layer. the first metal gate stack is separated from a first source/drain region by a dielectric inner spacer disposed on opposite sides of the first metal gate stack. the second gate-all-around device includes a second metal gate stack surrounding a second channel layer. the second metal gate stack is separated from a second source/drain region by an epitaxial layer disposed on opposite sides of the second metal gate stack.
Inventor(s): Ruqiang Bao of Niskayuna NY (US) for international business machines corporation, Effendi Leobandung of Stormville NY (US) for international business machines corporation
IPC Code(s): H01L29/423, H01L21/8238, H01L29/08, H01L29/786
Abstract: semiconductor devices having gate all around transistors with dual channels, one channel type for p-channel field-effect transistors (pfets) and another channel type for n-channel field-effect transistors (nfets) are provided. in one aspect, a semiconductor device includes: a wafer; and at least a first transistor and a second transistor on the wafer, where the first and second transistors each includes multiple channels, and where the multiple channels of the first transistor include first portions and second portions with the first portions having (e.g., si) cores and a (e.g., sige) ciadding layer fully surrounding the cores. alternatively, an anneal can be performed to convert the cores/cladding layer into uniform (e.g., sige). a method of fabricating the present semiconductor devices is also provided.
Inventor(s): Ruqiang Bao of Niskayuna NY (US) for international business machines corporation, Dechao Guo of Niskayuna NY (US) for international business machines corporation, Junli Wang of Slingerlands NY (US) for international business machines corporation
IPC Code(s): H01L29/423, H01L25/07, H01L29/66, H01L29/775, H01L29/786
Abstract: bonded stacked fets with individually tunable gate dielectrics are provided. in one aspect, a stacked fet device includes: a bottom transistor disposed on a wafer; and a top transistor bonded on top of the bottom transistor via a bonding layer, where the bottom transistor includes a stack of first active layers, a first gate dielectric disposed on the first active layers, and a first gate electrode disposed on the first gate dielectric, where the top transistor includes a stack of second active layers, a second gate dielectric disposed on the second active layers, and a second gate electrode disposed on the second gate dielectric, and where the first gate dielectric has at least one of a different composition and a different thickness from the second gate dielectric. a method of forming the present stacked fet devices is also provided.
Inventor(s): Ruqiang Bao of Niskayuna NY (US) for international business machines corporation, Effendi Leobandung of Stormville NY (US) for international business machines corporation, Eric Miller of Albany NY (US) for international business machines corporation
IPC Code(s): H01L29/66, H01L21/8238, H01L29/423, H01L29/775, H01L29/786
Abstract: semiconductor devices having separate (i.e., non-overlapping) gate all around replacement metal gates are provided. in one aspect, a semiconductor device includes: a wafer; and at least a first transistor of a first polarity (e.g., a pfet) and a second transistor of a second polarity (e.g., an nfet) on the wafer, where a gate electrode of the first transistor and a gate electrode of the second transistor have a single pair of vertically adjoining sidewalls. the workfunction-setting metals employed in the gate electrodes of the first and second transistors can vary, as can the composition, thickness, etc. of the gate dielectric that is present beneath the gate electrodes. a method of fabricating the present semiconductor devices is also provided.
Inventor(s): Layne A. Berge of Rochester MN (US) for international business machines corporation, Matthew Doyle of Chatfield MN (US) for international business machines corporation, Kyle Schoneck of Rochester MN (US) for international business machines corporation, Thomas W. Liang of Rochester MN (US) for international business machines corporation, John R. Dangler of Rochester MN (US) for international business machines corporation, Matthew A. Walther of Rochester MN (US) for international business machines corporation, Jason J. Bjorgaard of Rochester MN (US) for international business machines corporation, Trevor Timpane of Rochester MN (US) for international business machines corporation
IPC Code(s): H01P1/20, H01P3/06, H01P11/00
Abstract: one or more devices and/or methods provided herein relate to a method for fabricating a filtering electronic device having a co-integrated impedance modification element and signal transmission line. an electronic structure can comprise a signal transmission line, and an impedance modification element adjacent to and external to the signal transmission line, wherein the impedance modification element comprises a structure having differentiated sections, along the signal transmission line, that provide corresponding differentiated impedances. in an embodiment, the impedance modification element can comprise a plurality of impedance sub-elements spaced apart from one another along and adjacent to the signal transmission line to facilitate the different impedances.
Inventor(s): Christopher J. Vollmar of Mississauga (CA) for international business machines corporation, Adriana Pellegrini Furnielis of Valinhos (BR) for international business machines corporation, Sarvesh S. Patel of Pune (IN) for international business machines corporation, Frank N. Lee of Sunset Hills MO (US) for international business machines corporation, Abhishek Jain of Baraut (IN) for international business machines corporation, Joseph W. Dain of Tucson AZ (US) for international business machines corporation, Daniel DE SOUZA CASALI of Elmhurst NY (US) for international business machines corporation
IPC Code(s): H04L9/40, H04L9/08
Abstract: computer-implemented methods for management of data collection devices. aspects include creating a cluster of data collection devices and a distributed meta-key manager for the cluster and providing an authentication key for each data collection device to access the distributed meta-key manager. aspects also include collecting and storing data by one or more of the data collection devices and periodically perform a quorum check for each data collection device of the cluster. aspects further include updating an operational mode of each data collection device based on the quorum check and offloading the stored data from a data collection device based on successful verification of the stored data and the operational mode of the data collection device.
Inventor(s): Sen Wang of BEIJING (CN) for international business machines corporation, Mei Liu of Beijing (CN) for international business machines corporation, Si Bo Niu of Beijing (CN) for international business machines corporation, WEN YI GAO of Beijing (CN) for international business machines corporation, Zong Xiong ZX Wang of Beijing (CN) for international business machines corporation, Guoxiang Zhang of Beijing (CN) for international business machines corporation, Xiao Yi Tian of Beijing (CN) for international business machines corporation, XIAN WEI ZHANG of BEIJING (CN) for international business machines corporation
IPC Code(s): H04L9/40, H04L9/32
Abstract: aspects of the invention include systems and methods configured to prevent masquerading service attacks. a non-limiting example computer-implemented method includes sending, from a first server in a cloud environment, a communication request comprising an application programming interface (api) key and a first server identifier to an identity and access management (iam) server of the cloud environment. the api key can be uniquely assigned by the iam server to a first component of the first server. the first server receives a credential that includes a token for the first component and sends the credential to a second server. the second server sends the credential, a second server identifier, and an identifier for a second component of the second server to the iam server. the second server receives an acknowledgment from the iam server and sends the acknowledgment to the first server.
Inventor(s): IOSIF VIOREL ONUT of Ottawa (CA) for international business machines corporation, Julien Cassagne of Montreal (CA) for international business machines corporation, Ettore Merlo of Montreal (CA) for international business machines corporation, Guy Jourdan of Ottawa (CA) for international business machines corporation, Cheng-Ta Lee of Cumming GA (US) for international business machines corporation
IPC Code(s): H04L9/40, G06F8/41
Abstract: aspects of the invention include techniques for correlating distinct phishing campaigns by identifying shared modus operandi. a non-limiting example method includes building, from a source code, an abstract syntax tree and building, from the abstract syntax tree, a decloaked abstract syntax tree. the method includes removing payload data from the decloaked abstract syntax tree to define an obfuscation pattern. the obfuscation pattern is compared to a plurality of predetermined obfuscation patterns. the method includes correlating, based on the comparison, the source code to one or more phishing kits.
Inventor(s): Sudheesh S. Kairali of Koshikode (IN) for international business machines corporation, Vijay Kalangumvathakkal of Pathanamthitta (IN) for international business machines corporation, Ashish Kumar Thakur of Asansol (IN) for international business machines corporation, Jagdish Kumar of Pune (IN) for international business machines corporation, Sarbajit K. Rakshit of Kolkata (IN) for international business machines corporation
IPC Code(s): H04L67/51, G06F9/50, G06F11/07
Abstract: intelligent microservice timeout management is provided. it is determined whether a threshold level of predictability has been attained for a microservice chain corresponding to a current transaction requested by a user. it is determined whether the current transaction is predicted to result in a fast-forwarded fa�ade timeout based on a total of historic execution times of microservices in the microservice chain for data size and data condition exceeding a total of configured timeouts of the microservices in the microservice chain in response to determining that the threshold level of predictability has been attained for the microservice chain. a timeout is presented at an entry point microservice into the microservice chain to terminate the current transaction prior to executing the microservice chain for the current transaction saving time and resources in response to determining that the current transaction is predicted to result in the fast-forwarded fa�ade timeout.
Inventor(s): Suman Patra of Kolkata (IN) for international business machines corporation, NEIL DELIMA of Scarborough (CA) for international business machines corporation, Hunter Medney of Durham NC (US) for international business machines corporation
IPC Code(s): H04L67/62, H04L67/50
Abstract: intelligently facilitating content data for a user to consume by utilizing edge computing. in some instances, an intelligent virtual agent is used to collect user data (including scheduling data, historical data, location data, type of content that the user consumes, and the like). this collected user data is used to predict, in part, the time and location where the user is likely to consume this content. based on this predicted time and location, the content that the user is likely to consume is forwarded to an edge gateway so that this content is readily available to the user.
Inventor(s): Min Gyu Sung of Latham NY (US) for international business machines corporation, Kangguo Cheng of Schenectady NY (US) for international business machines corporation, Ruilong Xie of Niskayuna NY (US) for international business machines corporation, Chanro Park of Clifton Park NY (US) for international business machines corporation, Julien Frougier of Albany NY (US) for international business machines corporation
IPC Code(s): H10B12/00, H01L23/48
Abstract: a semiconductor structure having a high cell density is provided in which a frontside dynamic access memory (dram) is located on a frontside of a semiconductor substrate, and a backside dram is located on a backside of the semiconductor substrate. peripheral transistors can be located on the frontside of the semiconductor substrate and at a same level as frontside transistors of the frontside dram.
Inventor(s): Shravana Kumar Katakam of Lehi UT (US) for international business machines corporation, Ashim Dutta of Clifton Park NY (US) for international business machines corporation, Chih-Chao Yang of Glenmont NY (US) for international business machines corporation
IPC Code(s): H10N50/01, G11C11/16, H01L23/522, H10B61/00, H10N50/10, H10N50/80
Abstract: a semiconductor device including a magnetic tunnel junction (mtj) stack and an upper word line of the mtj stack surrounding vertical side surfaces of the mtj stack. a semiconductor device including a magnetic tunnel junction (mtj) stack and an upper word line for the mtj stack surrounding vertical side surfaces and an upper surface of a reference layer of the mtj stack. a method including forming a forming a magnetic tunnel junction (mtj) stack and forming a dielectric encapsulation layer surrounding vertical side surfaces of a top electrode, a free layer, a tunneling barrier, a reference layer and a bottom electrode of the mtj stack.
Inventor(s): Chanro Park of Clifton Park NY (US) for international business machines corporation, Koichi Motoyama of Clifton Park NY (US) for international business machines corporation, Hsueh-Chung Chen of Cohoes NY (US) for international business machines corporation, Yann Mignot of Slingerlands NY (US) for international business machines corporation, Daniel Worledge of San Jose CA (US) for international business machines corporation
IPC Code(s): H10N50/01, G11C11/16, H10B61/00, H10N50/80
Abstract: a memory structure including a magnetic tunnel junction (mtj) structure and a top electrode that are both formed without utilizing ion beam etching is provided. the mtj structure, which includes a lower magnetic stack, a tunnel barrier layer and an upper magnetic stack, is pyramidal shaped, and end portions of the lower magnetic stack of the mtj structure are devoid of the tunnel barrier layer and the upper magnetic stack.
Inventor(s): Oscar van der Straten of Guilderland Center NY (US) for international business machines corporation, Chih-Chao Yang of Glenmont NY (US) for international business machines corporation
IPC Code(s): H01L43/02, H01L27/22, H01L43/12
Abstract: a semiconductor structure with a magnetic tunnel junction (mtj) pillar for a magnetoresistive random-access memory (mram) device, where each material layer of the mtj pillar resides on a lower material layer of the mtj pillar with a different width. embodiments of the present invention provide a top electrode with a tapered shape. embodiments of the present invention also provide a dielectric encapsulation layer around the reference layer and around the free layer. the dielectric encapsulation material surrounding a sidewall of the reference layer is composed of a different dielectric encapsulation material than the dielectric encapsulation around the sidewall of the free layer.
Inventor(s): Timothy Mathew Philip of Albany NY (US) for international business machines corporation, Injo Ok of Albany NY (US) for international business machines corporation, JIN PING HAN of Yorktown Heights NY (US) for international business machines corporation, Ching-Tzu Chen of Ossining NY (US) for international business machines corporation, Kevin W. Brew of Niskayuna NY (US) for international business machines corporation
IPC Code(s): H10N70/00, H10B63/00
Abstract: a computer memory device includes a bottom electrode, a top electrode, and a memory component arranged between the top electrode and the bottom electrode. the memory component is made of a dielectric solid-state material and is in direct contact with the top electrode and the bottom electrode. the computer memory device further includes a proximity heater configured to increase a temperature of a portion of the memory component. the computer memory device further includes a layer of dielectric material in direct contact with the proximity heater. the layer of dielectric material is in direct contact with one of the bottom electrode and the top electrode.
International Business Machines Corporation patent applications on June 6th, 2024
- International Business Machines Corporation
- A63B71/06
- International business machines corporation
- B64G1/24
- B64G1/36
- B64G1/40
- B64G3/00
- G01C21/34
- G06Q10/0835
- G16H40/00
- G01D18/00
- G01R1/067
- G05B19/418
- G06F3/06
- G06F7/523
- G06F7/50
- G06F8/30
- G06F8/61
- G06F9/54
- G06F8/65
- G06Q20/36
- G06F8/71
- G06F9/455
- G06F9/48
- G06F9/50
- G06F11/00
- G06F11/34
- G06F16/21
- G06F16/26
- G06F16/215
- G06F16/2458
- G06F16/28
- G06F16/27
- G06F16/22
- G06F16/25
- G06F21/78
- G06F1/3234
- G06F30/33
- G06F30/392
- G06F40/186
- G06F40/30
- G06V30/412
- G06F40/47
- G06F40/237
- G06N3/045
- G06N3/08
- G06N3/065
- G06N3/0895
- G06N3/04
- G06N3/092
- G06F40/205
- G06N3/042
- G06N10/20
- G06N20/00
- G06Q30/02
- G06F40/126
- G06F40/166
- G06Q30/0207
- G06Q30/0211
- G06Q30/0235
- G06Q30/0601
- G06Q30/06
- G06F40/20
- G06T19/00
- B29C64/393
- B33Y50/02
- G06V10/774
- G06N3/0464
- G06V10/40
- G06V10/762
- G06V10/771
- G06V10/776
- G06V10/82
- G08G1/01
- G06F30/20
- G10L17/22
- G10L13/027
- G10L25/54
- G11B27/00
- H04N21/45
- H04N21/845
- H01L21/768
- H01L23/522
- H01L23/528
- H01L23/532
- H01L23/48
- H01L29/06
- H01L29/417
- H01L29/66
- H01L29/786
- H01L21/8234
- H01L27/088
- H01L29/423
- H01L29/775
- H01L21/8238
- H01L27/06
- H01L27/092
- H01L21/285
- H01L21/822
- H01L29/08
- H01L29/45
- H01L29/78
- H01L29/40
- H01L29/49
- H01L29/51
- H10K10/46
- H01L21/28
- H01L25/07
- H01P1/20
- H01P3/06
- H01P11/00
- H04L9/40
- H04L9/08
- H04L9/32
- G06F8/41
- H04L67/51
- G06F11/07
- H04L67/62
- H04L67/50
- H10B12/00
- H10N50/01
- G11C11/16
- H10B61/00
- H10N50/10
- H10N50/80
- H01L43/02
- H01L27/22
- H01L43/12
- H10N70/00
- H10B63/00
- H01L29/42392
