International Business Machines Corporation patent applications on June 13th, 2024
Patent Applications by International Business Machines Corporation on June 13th, 2024
International Business Machines Corporation: 71 patent applications
International Business Machines Corporation has applied for patents in the areas of G06N20/00 (6), H01L21/768 (5), H01L23/528 (5), H01L23/522 (4), H10N50/01 (3) G06N20/00 (3), H01L23/5226 (3), G06F11/079 (2), H01L43/12 (2), H01L23/5286 (2)
With keywords such as: layer, data, user, computer, based, device, provided, object, structure, and semiconductor in patent application abstracts.
Patent Applications by International Business Machines Corporation
Inventor(s): Tiberiu Suto of Franklin NY (US) for international business machines corporation, Martin G. Keen of Cary NC (US) for international business machines corporation, Jeremy R. Fox of Georgetown TX (US) for international business machines corporation, Sarbajit K. Rakshit of Kolkata (IN) for international business machines corporation
IPC Code(s): B60W60/00, B60W50/00
CPC Code(s): B60W60/0015
Abstract: provided is a computer-implemented method, system, and computer program product for predicting data insufficiency related to performing autonomous vehicle actions and dynamically mitigating the data insufficiency by collecting external data from additional data sources. a processor may direct, for an autonomous vehicle, an action in response to external data. the processor may collect contextual data about an environment in which the autonomous vehicle is operating. the processor may predict, based in part on the collected contextual data, an insufficiency of external data for performing the action. in response to the predicting, the processor may direct collection of additional external data from a second data source.
Inventor(s): Emmanuel Yashchin of Yorktown Heights NY (US) for international business machines corporation, Nianjun Zhou of Chappaqua NY (US) for international business machines corporation, Anuradha Bhamidipaty of Yorktown Heights NY (US) for international business machines corporation, Dhavalkumar C. Patel of White Plains NY (US) for international business machines corporation, Arun Kwangil Iyengar of Yorktown Heights NY (US) for international business machines corporation, Shrey Shrivastava of White Plains NY (US) for international business machines corporation
IPC Code(s): G01W1/10, G06N7/01
CPC Code(s): G01W1/10
Abstract: an embodiment for identifying influential disturbances is provided. the embodiment may automatically receive a set of service records including disturbance-related probability values corresponding to the disturbance-revealing events, and wherein one or more service records are mislabeled or have no label relating to an associated disturbance. the embodiment may generate baselines for a series of relevant sub-regions associated with the service records, and normalize daily summaries of disturbance probabilities for each of the relevant sub-regions. the embodiment may automatically identify subsets of service records corresponding to a series of newly-discovered disturbances by using the disturbance-related probability values and a series of associated features to identify deviations from normal non-disturbance event distributions. the embodiment may automatically identify and output a series of influential disturbances, the series of influential disturbances including newly-discovered disturbances for which a series of generated impact scores are above a predetermined threshold.
Inventor(s): Barnim Alexander Janta-Polczynski of Shefford (CA) for international business machines corporation
IPC Code(s): G02B6/12, H01L21/56, H01L25/00, H01L25/16, H01L25/18
CPC Code(s): G02B6/12004
Abstract: heterogeneous package structures comprising photonic components are provided. for example, an exemplary package structure comprises at least one electronic device, at least one photonic device, at least one bridge interconnect device, and at least one optical waveguide device. the at least one bridge interconnect device is configured to electrically connect the at least one electronic device to the at least one photonic device. the at least one optical waveguide device is optically coupled to the at least one photonic device to implement an optical bus for routing optical signals in the package structure. the at least one photonic device is configured to implement an electro-optical interface between the at least one electronic device and the optical bus.
Inventor(s): Sarbajit K. Rakshit of Kolkata (IN) for international business machines corporation, Manikandan Padmanaban of Chennal (IN) for international business machines corporation, Jagabondhu Hazra of Bangalore (IN) for international business machines corporation
IPC Code(s): G05B19/4155
CPC Code(s): G05B19/4155
Abstract: an approach for adjusting an inclination angle of a mirror to maximize power output of an adjacent solar panel and shadow-effect energy generator (seg). the approach retrieves data associated with a solar irradiance profile and a seg shadow profile. the approach predicts an irradiance profile based on the data. the approach predicts a shadow contrast ratio based on the data. the approach predicts a seg shadow profile based on the data. the approach calculates optimized control parameters associated with a mirror based on the irradiance profile, the shadow contrast ratio and the seg shadow profile. the approach adjusts the mirror inclination angle based on the optimized control parameters.
Inventor(s): Jaime JALOMA of Austin TX (US) for international business machines corporation, Mark ROGERS of Round Rock TX (US) for international business machines corporation, Arnold FLORES of Round Rock TX (US) for international business machines corporation, Mysore S. SRINIVAS of Austin TX (US) for international business machines corporation
IPC Code(s): G06F3/06
CPC Code(s): G06F3/061
Abstract: a system and methods are provided for implementing a selected segment size of a shared memory object in a paged-segmented operating system. a user selected shared memory object autonomic promotion feature enables a selected segment size of a shared memory object for a user application. a paged-segmented operating system receiving a request for a shared memory object of a user application, accesses the user selected shared memory object autonomic promotion feature to identify a user selection. an identified user selection is evaluated with secondary criteria for the request shared memory object for the user application and a segment size is set. the operating system creates a shared memory object with the set segment size for the user application. enabling shared memory objects to be supported by a large segment size reduces the number of segments used for a single shared memory object and application performance can be significantly improved.
Inventor(s): Lokesh Mohan Gupta of Tucson AZ (US) for international business machines corporation, Matthew J. Kalos of Tucson AZ (US) for international business machines corporation, Matthew G. Borlick of Tucson AZ (US) for international business machines corporation, Beth Ann Peterson of Tucson AZ (US) for international business machines corporation, Kevin J. Ash of Tucson AZ (US) for international business machines corporation, Kyler A. Anderson of Sahuarita AZ (US) for international business machines corporation
IPC Code(s): G06F3/06
CPC Code(s): G06F3/064
Abstract: a computer-implemented method for managing tracks in a cache is provided. the computer-implemented method includes instantiating cache control blocks to each manage operations for one of the tracks and instantiating a bytemap corresponding to each of the cache control blocks. each bytemap includes an active bit indicating whether the one of the tracks for which the corresponding cache control block manages operations is active and additional bits indicating additional characteristics of the one of the tracks for which the corresponding cache control block manages operations.
Inventor(s): Stefano Ambrogio of San Jose CA (US) for international business machines corporation, Pritish Narayanan of San Jose CA (US) for international business machines corporation
IPC Code(s): G06F7/544, G06F17/18
CPC Code(s): G06F7/5443
Abstract: systems and methods for compensating multiply and accumulate (mac) operations are described. a processor can send an input vector to a first portion of a memory device. the first portion can store synaptic weights of a trained artificial neural network (ann). the processor can read a first result of a mac operation performed on the input vector and the synaptic weights stored in the first portion. the processor can send an inverse of the input vector to a second portion of the memory device. the processor can read a second result of a mac operation performed on the inverse of the input vector and an inverse of synaptic weights stored in the second portion. the processor can combine the first result and the second result to generate a final result. the final result can be a compensated version of the first result.
Inventor(s): Juan Cruz Benito of Salamanca (ES) for international business machines corporation, Ismael Faro Sertage of Chappaqua NY (US) for international business machines corporation, Francisco Jose Martin Fernandez of Ridgefield CT (US) for international business machines corporation
IPC Code(s): G06F8/51, G06F8/33, G06N10/60
CPC Code(s): G06F8/51
Abstract: one or more systems, devices, computer program products and/or computer-implemented methods of use provided herein relate to a process to port code while adapting the code for a configuration of a target system. a system can comprise a memory that stores computer executable components, and a processor that executes the computer executable components stored in the memory, wherein the computer executable components can comprise an identification component that identifies a configuration of a target system on which a translated source code is to be executed, and a translation component that translates, based on a constraint defining the configuration, an original source code into the translated source code. in one or more embodiments, the translated source code can comprise a code language not comprised by the original source code and/or can be modified to align with the constraint, which can be of a hardware and/or software configuration.
Inventor(s): Kuo-Liang CHOU of New Taipei City (TW) for international business machines corporation, Zhan Peng HUO of Beijing (CN) for international business machines corporation, Jun ZHU of Shanghai (CN) for international business machines corporation, Yu Zui YOU of Beijing (CN) for international business machines corporation, Xuan FENG of Beijing (CN) for international business machines corporation, Jun HAO of Beijing (CN) for international business machines corporation
IPC Code(s): G06F8/71
CPC Code(s): G06F8/71
Abstract: processing within a container-based computing environment is facilitated by standardizing container identification processing. the process includes, for a container being provided from a container image, extracting multiple layer files from the container image and using natural language processing to determine frequency of occurrence of software components in the multiple layer files of the container image. further, the process includes generating a container name for the container using the determined frequency of occurrence of software components in the multiple layer files of the container image. the method further includes providing the container for the container-based computing environment using the container image and the generated container name. the generated container name facilitates processing within the container-based computing environment by being based, at least in part, on the frequency of occurrence of software components in the multiple layer files of the container image.
Inventor(s): Avirup Saha of Kolkata (IN) for international business machines corporation, Renuka Sindhgatta Rajan of Bengaluru (IN) for international business machines corporation, Neelamadhav Gantayat of Bangalore (IN) for international business machines corporation, Sampath Dechu of Acton MA (US) for international business machines corporation, Ravi Shankar Arunachalam of Bangalore (IN) for international business machines corporation, Sachindra Joshi of Gurgaon (IN) for international business machines corporation
IPC Code(s): G06F11/00, G06F9/54
CPC Code(s): G06F11/004
Abstract: predicting the impact of an information technology (it) failure includes detecting a computer-generated indication of the failure. responsive to determining that the it failure is a previously unseen it failure, operations of a computer-implemented unseen event handler can be invoked. the unseen event handler can map the previously unseen it failure to a previously seen it failure based on a similarity score generated by a computer-implemented similarity scorer, wherein the similarity score is based on a unified process-it topology. a machine learning model can generate an it failure impact prediction and recommendation based on the mapping, wherein the machine learning model also is based on the unified process-it topology. an output of the it failure prediction and recommendation can be generated.
Inventor(s): AMAR SHAH of Pune (IN) for international business machines corporation, AJAY PONNAPPAN of BANGALORE (IN) for international business machines corporation, Dominic John Storey of Eastleigh (GB) for international business machines corporation, James Jose of Bangalore (IN) for international business machines corporation
IPC Code(s): G06F11/07
CPC Code(s): G06F11/079
Abstract: an approach for reducing backend system calls. the approach determines if a client request, comprising a backend system call, has timed out. if the client request has timed out, then the approach generates a unique identity associated with the client request. the approach creates a fault message indicating a timeout of the client request. the approach inserts the unique identity into the fault message. the approach sends the fault message to the client as a response to the request. the approach creates a data structure comprising the unique identity, a timeout value, and a message buffer. the approach inserts the data structure into a message queue. subsequently, a client sending a next request containing the unique identity can receive a response, from a slow responding backend server, after the timeout of the previous request without incurring the expense and overhead of another backend system call.
Inventor(s): Shu Jun Tang of Beijing (CN) for international business machines corporation, Jia Lin Wang of Beijing (CN) for international business machines corporation, Qi Han Zheng of Beijing (CN) for international business machines corporation, Yi Fan Wu of Beijing (CN) for international business machines corporation, Jing Jing Wei of Beijing (CN) for international business machines corporation, Zhi Li Guan of Beijing (CN) for international business machines corporation, Yang Kang of Beijing (CN) for international business machines corporation
IPC Code(s): G06F11/07
CPC Code(s): G06F11/079
Abstract: a computer-implemented method, system and computer program product for identifying a root cause of failures in a ci/cd pipeline. tags for tasks, templates and/or variables of the operator and the ci/cd pipeline are extracted. code of the tagged tasks, templates and/or variables of the operator are mapped with the code of the tagged tasks, templates and/or variables of the cl/cd pipeline forming mappings. additionally, code of the tagged tasks, templates and/or variables between the roles of the operator are mapped forming mappings. upon receiving a notification of a failure in the cl/cd pipeline, a root cause of the failure is identified by searching such mappings for a mapped role or task in relation to the role or task involving the software product which failed in the ci/cd pipeline and searching the log file of the operator for an error in connection with such mapped role or task.
Inventor(s): Jing Yan ZZ Zhang of BEIJING (CN) for international business machines corporation, Chu Yun Tong of BEIJING (CN) for international business machines corporation, Wan Feng of BEIJING (CN) for international business machines corporation, Wen Wen Guo of BEIJING (CN) for international business machines corporation, Miao Liu of BEIJING (CN) for international business machines corporation, Bing Qian of BEIJING (CN) for international business machines corporation
IPC Code(s): G06F11/36
CPC Code(s): G06F11/3676
Abstract: an example operation may include one or more of storing log files via a data store, comparing a test log file from the data store which is generated from tests performed on source code in a test environment to a productive log file from the data store that is generated by executing the source code in a productive environment, identifying one or more components of the source code that are not covered by the tests based on the comparison, and generating a visualization which includes identifiers of the one or more components that are not covered by the tests and display the visualization via a user interface.
20240193100.Heap Protection System_simplified_abstract_(international business machines corporation)
Inventor(s): Joran S.C. Siu of Thornhill (CA) for international business machines corporation, Alper Buyuktosunoglu of White Plains NY (US) for international business machines corporation, Richard H. Boivie of Monroe CT (US) for international business machines corporation, Tong Chen of Yorktown Heights NY (US) for international business machines corporation
IPC Code(s): G06F12/14, G06F12/02
CPC Code(s): G06F12/1441
Abstract: a computer implemented method handles object references. a computer system determines whether an object reference fetched by a load instruction has an expected value for heap protection for a heap in response to receiving the load instruction for execution. the computer system generates an event in response to the object reference not being the expected value, wherein the event is used to manage the object reference. according to other illustrative embodiments, a computer system and a computer program product for managing object references are provided. as a result, the illustrative embodiments can prevent a load instruction from loading an invalid object reference that does not point to a memory location in a heap.
Inventor(s): Yuan Gao of Beijing (CN) for international business machines corporation, Xiao Min Zhao of Beijing (CN) for international business machines corporation, Shuang Li of Beijing (CN) for international business machines corporation, Hao Wu of Beijing (CN) for international business machines corporation
IPC Code(s): G06F16/23, G06F16/2453
CPC Code(s): G06F16/2379
Abstract: method, computer program product, and computer system are provided. a plurality of query activities are captured from one or more monitored databases. the query activities are persisted into a graph-enabled database repository. the plurality of query activities are classified into a plurality of workload rules based on there being a correlations between the plurality of query activities. a plurality of components of a total execution time of each query in a workload rule is analyzed. one or more problematic queries is identified based on the analyzing.
Inventor(s): Shashank Mujumdar of Nagpur (IN) for international business machines corporation, Ruhi Sharma Mittal of Bangalore (IN) for international business machines corporation, Nitin Gupta of Saharanpur (IN) for international business machines corporation, Hima Patel of Bangalore (IN) for international business machines corporation
IPC Code(s): G06F16/2457, G06F16/28
CPC Code(s): G06F16/24573
Abstract: a method, computer program, and computer system are provided for collecting and annotating data based on user preference. unlabeled data corresponding to one or more entries within a dataset is received. pseudo-labeled data is generated based on the unlabeled data. based on one or more quality metrics, each entry from among the pseudo-labeled data is determining to be included within a final dataset. a user is prompted for annotations corresponding to entries of the pseudo-labeled data included within the final dataset. a determination is made as to whether additional data is needed based on comparing the final dataset to the one or more quality metrics, and the additional information is collected if the final dataset does not meet the quality metrics.
Inventor(s): Kunal Sawarkar of Franklin Park NJ (US) for international business machines corporation
IPC Code(s): G06F16/33, G06F40/10, G06N20/00
CPC Code(s): G06F16/3344
Abstract: a method and system of generating inferential text are provided. the method includes ingesting a data set that includes at least one structured hierarchical or multidimensional table for a particular domain. the method includes processing the ingested data set that includes the at least one structured hierarchical or multidimensional table for the particular domain by applying a generated machine learning model. the method includes generating inferential natural language text based on applying the machine learning model. the method includes outputting the generated inferential natural language text in a sequence format.
Inventor(s): Kelley Anders of East New Market MD (US) for international business machines corporation, Jonathan D. Dunne of Dungarvan (IE) for international business machines corporation
IPC Code(s): G06F40/35, G06F40/166, G06F40/20, H04L51/216
CPC Code(s): G06F40/35
Abstract: according to one embodiment, a method, computer system, and computer program product for explaining discourse is provided. the embodiment may include monitoring a conversation. the embodiment may also include deriving a conversation alignment model based on the conversation. the embodiment may further include identifying a misalignment in the conversation. the embodiment may also include taking an action to align the conversation based on the conversation alignment model.
Inventor(s): LIN PAN of Jersey City NJ (US) for international business machines corporation, Haode Qi of Cambridge MA (US) for international business machines corporation, Ladislav Kunc of Cambridge MA (US) for international business machines corporation, Saloni Potdar of Jersey City NJ (US) for international business machines corporation
IPC Code(s): G06F40/58
CPC Code(s): G06F40/58
Abstract: a method, computer system, and a computer program product for training a machine learning model are provided. a machine learning model may be split into a lower portion and an upper portion. the lower portion includes at least one layer. the upper portion includes at least one layer. the lower portion may be pre-trained via a generator task and via alternating between inputting of monolingual text data and multilingual text data. the upper portion may be pre-trained via a discriminator task. the pre-trained lower portion may be joined to the pre-trained upper portion to form a trained multilingual machine learning model.
Inventor(s): Jiri Navratil of Cortlandt Manor NY (US) for international business machines corporation, Karthikeyan Shanmugam of Bengaluru (IN) for international business machines corporation, Naoki Abe of Rye NY (US) for international business machines corporation, Youssef Mroueh of New York NY (US) for international business machines corporation, Mattia Rigotti of Basel (CH) for international business machines corporation, Inkit Padhi of White Plains NY (US) for international business machines corporation
IPC Code(s): G06N3/08
CPC Code(s): G06N3/08
Abstract: an embodiment for generating causal association rankings for candidate events within a window of candidate events using dynamic deep neural network generated embeddings. the embodiment may automatically receive a window of candidate events including events of a first type preceding one or more target events of interest. the embodiment may automatically generate contrastive windows of candidate events, each of the contrastive windows of candidate events of the first type corresponding to a different dropped candidate event from the received window of candidate events. the embodiment may automatically identify matching historical windows of events having resulting embeddings that are close in distance to the embeddings corresponding to the embeddings of the contrastive windows and calculate a first score for each match. the embodiment may automatically identify matching incident windows and calculate a corresponding second score. the embodiment may use the first and second scores to generate casual association rankings.
Inventor(s): Ambrish Rawat of Dublin (IE) for international business machines corporation, Killian Levacher of Dublin (IE) for international business machines corporation, Giulio Zizzo of Dublin (IE) for international business machines corporation, Ngoc Minh Tran of Dublin (IE) for international business machines corporation
IPC Code(s): G06N3/088, G06N3/045
CPC Code(s): G06N3/088
Abstract: a method, computer system, and computer program product are provided for training a federated generative adversarial network (gan) using private data. the method is carried out at an aggregator system having a generator and a discriminator, wherein the aggregator system is in communication with multiple participant systems each having a local feature extractor and a local discriminator. the method includes: receiving, from a feature extractor at a participant system, a set of features for input to the discriminator at the aggregator system, wherein the features include features extracted from private data that is private to the participant system; and receiving, from one or more local discriminators of the participant systems, discriminator parameter updates to update the discriminator at the aggregator system, wherein the local discriminators are trained at the participant systems.
Inventor(s): ANNA PAOLA CARRIERI of Manchester (GB) for international business machines corporation, LAURA-JAYNE GARDINER of Wirral (GB) for international business machines corporation
IPC Code(s): G06N5/022
CPC Code(s): G06N5/022
Abstract: a method, computer program product, and computer system are provided for domain knowledge-based evaluation of machine learning models for a target subject. the method accesses a model explanation of each of a plurality of machine learning models for a target subject, where a model explanation includes a set of identified important features. the method receives a domain expert input including a set of known important features for the target subject. the method compares the domain expert input with the plurality of model explanations to evaluate consensus based on at least some of the known important features concurring with at least some of the identified important features of the model explanations and outputs a score of the machine learning models with the score including the evaluated consensus.
Inventor(s): Nathan Andrew Phelps of Durham NC (US) for international business machines corporation, Ryan Anderson of Kensington CA (US) for international business machines corporation, Ashok Kumar Iyengar of Encinitas CA (US) for international business machines corporation, Kavitha Bade of Durham NC (US) for international business machines corporation, Joseph Andrew Pearson of Brookhaven GA (US) for international business machines corporation, Troy Fine of Sutter Creek CA (US) for international business machines corporation
IPC Code(s): G06N5/04
CPC Code(s): G06N5/04
Abstract: a computer-implemented method, according to one embodiment, includes deploying a policy to edge devices in an edge computing environment. the method further includes analyzing, using an artificial intelligence (ai) reasoning model, the policy to understand an intent of deploying the policy. the analyzing includes discounting a weight value assigned to data points that are determined to not apply to a current decision of a first of the edge devices. the method further includes causing the policy to be altered based on the analysis. a computer program product, according to another embodiment, includes a computer readable storage medium having program instructions embodied therewith. the program instructions are readable and/or executable by a computer to cause the computer to perform the foregoing method.
Inventor(s): Ismail Yunus Akhalwaya of Emmarentia (ZA) for international business machines corporation, Kenneth Clarkson of Madison NJ (US) for international business machines corporation, Lior Horesh of North Salem NY (US) for international business machines corporation, Mark Squillante of Greenwich CT (US) for international business machines corporation, Shashanka Ubaru of Ossining NY (US) for international business machines corporation, Vasileios Kalantzis of White Plains NY (US) for international business machines corporation
IPC Code(s): G06N10/00, G06F17/11, G06N20/00
CPC Code(s): G06N10/00
Abstract: techniques and a system to facilitate estimation of a quantum phase, and more specifically, to facilitate estimation of an expectation value of a quantum state, by utilizing a hybrid of quantum and classical methods are provided. in one example, a system is provided. the system can comprise a memory that stores computer executable components and a processor that executes the computer executable components stored in the memory. the computer executable components can include an encoding component and a learning component. the encoding component can encode an expectation value associated with a quantum state. the learning component can utilize stochastic inference to determine the expectation value based on an uncollapsed eigenvalue pair.
Inventor(s): Chi Nan of XIAN (CN) for international business machines corporation, Xiang Yu Yang of XIAN (CN) for international business machines corporation, Yong Wang of XIAN (CN) for international business machines corporation, Deng Xin Luo of XIAN (CN) for international business machines corporation, Zhi Yong Jia of XIAN (CN) for international business machines corporation, Yu Ying YY Wang of XIAN (CN) for international business machines corporation
IPC Code(s): G06N20/00
CPC Code(s): G06N20/00
Abstract: a method, computer program, and computer system are provided for performing multiple machine learning tasks through a shared framework. data corresponding to a plurality of predetermined machine learning tasks is received. one or more steps of the machine learning tasks associated with the received data is performed on the received data by a shared backbone of a machine learning model. the predetermined plurality of machine learning tasks is completed on the received data by a plurality of sub-networks associated with each of the plurality of predetermined machine learning tasks.
Inventor(s): Shweta Vohra of Bangalore (IN) for international business machines corporation, Madhusmita Patil of Hyderabad (IN) for international business machines corporation, Atul Misra of Bangalore (IN) for international business machines corporation, William A. Brown of Raleigh NC (US) for international business machines corporation, Scott E. Schneider of Rolesville NC (US) for international business machines corporation
IPC Code(s): G06N20/00
CPC Code(s): G06N20/00
Abstract: an approach is provided for upgrading containerized applications in cluster(s) in a container orchestration system. state information about the containerized applications is identified and analyzed. based on the state information, an upgrade path for an upgrade of the containerized applications is determined. using an artificial intelligence (ai) based container orchestration platform upgrade engine that employs continuous learning for upgrading data and algorithmic models to upgrade containers, a recommendation is generated that the upgrade be a full upgrade or a partial upgrade. a confirmation of the full upgrade or the partial upgrade is received from a user. components for the full upgrade or the partial upgrade are created. using the upgrade path and based on the full upgrade or the partial upgrade, the upgrade is performed.
Inventor(s): Martin Wistuba of Dublin (IE) for international business machines corporation, Tejaswini Pedapati of White Plains NY (US) for international business machines corporation
IPC Code(s): G06N20/00, G06F21/55
CPC Code(s): G06N20/00
Abstract: various embodiments are provided for accelerating machine learning in a computing environment by one or more processors in a computing system. selected data may be received for training machine learning pipelines. each of the machine learning pipelines may be scored according to one or more learning curves while training on selected data. completion of the training on the selected data may be permitted for those of the machine learning pipelines having a score greater than a selected threshold. the training on the selected data may be terminated, prior to completion, on those of the machine learning pipelines having a score less than a selected threshold.
Inventor(s): Al Chakra of Apex NC (US) for international business machines corporation, Alejandro Aguilar Esteban of Watertown MA (US) for international business machines corporation, Alexander David Burke of Littleton MA (US) for international business machines corporation, Mingqing(Mindy) Li of San Jose CA (US) for international business machines corporation
IPC Code(s): G06Q10/0631
CPC Code(s): G06Q10/06313
Abstract: a method, computer system, and a computer program product for event-related item tracking are provided. a first computer receives from an event database associated with personal information management software a reminder of an upcoming event for a first user. the first computer retrieves an electronic list of items needed by the first user for the upcoming event. the first computer retrieves, from a location database, location information of a first item from the electronic list of items. the location database was generated using image information of the first item. the first computer transmits the electronic list of items and the location information of the first item for presentation to the first user.
Inventor(s): Robert Paul Lukasik of New York NY (US) for international business machines corporation, Christopher F. Ackermann of Fairfax VA (US) for international business machines corporation, Jeremy R. Fox of Georgetown TX (US) for international business machines corporation, Jennifer M. Hatfield of San Francisco CA (US) for international business machines corporation
IPC Code(s): G06Q10/06, G06F40/20, G06K9/62
CPC Code(s): G06Q10/0633
Abstract: a system implements a method that comprises receiving end user information of end users to produce synthesized user research data, storing the synthesized user research data in a knowledge corpus, and segmenting the end users into one or more end user segments based on end user roles or end user categories. for each end user segment, a persona is generated, each representing a composite of end users in a respective end user segment. the method further comprises training each persona with training data from the synthesized user research data of the end users in the respective end user segment, and generating a dialog engine for each persona based on the training. an avatar is connected to each persona, and each avatar is made accessible for dialog with metaverse users in the metaverse, which is a 3d virtual reality environment.
Inventor(s): Fearghal O'Donncha of Aran Islands (IE) for international business machines corporation, Paulito Palmes of Dublin (IE) for international business machines corporation, Albert Akhriev of Dublin (IE) for international business machines corporation, Amadou Ba of Navan (IE) for international business machines corporation
IPC Code(s): G06Q10/06
CPC Code(s): G06Q10/0639
Abstract: in an approach for a virtual assistant career mentor that provides a user with personalized career recommendations, a processor identifies a position a user wishes to achieve in a request for a personalized career recommendation. a processor compares a user profile of the user to a marketplace profile for the position to determine whether there are one or more gaps in the user profile that would prevent the user from achieving the position. responsive to determining there is a gap in the user profile, a processor assigns the user a task to address the gap in the user profile. a processor generates a performance score using a reinforcement learning model. responsive to updating the user profile with the performance score, a processor generates a recommendation using machine learning, wherein the recommendation includes a series of actions the user may take to achieve the position identified and an appropriate timeline.
Inventor(s): Igor S. Ramos of Round Rock TX (US) for international business machines corporation, Angelo Danducci, II of Austin TX (US) for international business machines corporation, Kimberly J. Taft of Round Rock TX (US) for international business machines corporation, Devon E. Mensching of Austin TX (US) for international business machines corporation
IPC Code(s): G06Q30/018
CPC Code(s): G06Q30/0185
Abstract: a method, computer system, and a computer program product for product verification is provided. the present invention may include encoding a unique identifier for a product. the present invention may include storing the unique identifier in a shared library. the present invention may include determining a bio-tagging composition for the product. the present invention may include monitoring the product using the bio-tagging composition.
Inventor(s): Martin G. Keen of Cary NC (US) for international business machines corporation, Zachary A. Silverstein of Georgetown TX (US) for international business machines corporation, Melanie Dauber of Oceanside NY (US) for international business machines corporation, John M. Ganci, JR. of Raleigh NC (US) for international business machines corporation
IPC Code(s): G06Q30/04, G06F9/48, G06F11/32
CPC Code(s): G06Q30/04
Abstract: by analyzing activity monitoring data, a task pattern comprising a set of one or more tasks is derived. the task pattern is identified as a candidate task pattern responsive to determining that a completion variability in the task pattern is above a threshold amount. by analyzing performance data of a system used in performing the candidate task pattern, an optimum time at which to perform the candidate task pattern is identified. responsive to detecting commencement of performance, at a time earlier than the optimum time, the candidate task pattern is delayed. the candidate task pattern is performed at the optimum time.
Inventor(s): Hamid Majdabadi of OTTAWA (CA) for international business machines corporation, Jeremy R. Fox of Georgetown TX (US) for international business machines corporation, Peng Hui Jiang of Beijing (CN) for international business machines corporation, Su Liu of Austin TX (US) for international business machines corporation
IPC Code(s): G06Q40/08
CPC Code(s): G06Q40/08
Abstract: a computer-implemented method for recommending a best driver to get best vehicle rental and insurance costs. the method builds a framework of a group of multiple driving candidates to select from to be a driver of a rental vehicle. the method further determines a driving score based on the collected set of data and generates an aggregate ranking of each of the multiple driving candidates based on the driving score. the method further computes an insurance cost for each of the multiple driving candidates based on the driving score and calculates a vehicle rental and insurance cost for each of the multiple driving candidates, based on the driving score. the method further ranks each of the multiple driving candidates based on the respective calculated vehicle rental cost and insurance cost and recommends a highest ranked candidate as the best driver to receive the best vehicle rental and insurance costs.
Inventor(s): Yuan Yuan DING of Shanghai (CN) for international business machines corporation, Yi Chen ZHONG of Shanghai (CN) for international business machines corporation, Jing ZHANG of Shanghai (CN) for international business machines corporation, Yang LIU of Zhong Xin City (CN) for international business machines corporation, Ziyi JIANG of Shanghai (CN) for international business machines corporation, Ting Ting CAO of Beijing (CN) for international business machines corporation
IPC Code(s): G06T7/136, G06T5/00
CPC Code(s): G06T7/136
Abstract: techniques for skin-condition visualization using machine learning. a color image depicting facial skin of a subject is retrieved. a monochromatic version of the color image is generated. candidate instances of one or more skin conditions are segmented from the monochromatic version based on a segmentation threshold and using a machine learning model. a polarized version of the color image is generated, and based on the polarized version, the candidate instances are filtered. one or more simulation images are generated based on the filtered candidate instances.
Inventor(s): Tiberiu Suto of Franklin NY (US) for international business machines corporation, Jeremy R. Fox of Georgetown TX (US) for international business machines corporation, Tushar Agrawal of West Fargo ND (US) for international business machines corporation, Sarbajit K. Rakshit of Kolkata (IN) for international business machines corporation
IPC Code(s): G06T11/00, G06F3/01
CPC Code(s): G06T11/00
Abstract: techniques are described with respect to a system, method, and computer product for visualizing real world sentiments of an inanimate object. an associated method includes receiving sensor data from a plurality of sensors associated with the inanimate object, the sensor data tracking one or more conditions of the inanimate object; analyzing the sensor data to determine a status of a real world sentiment associated with the inanimate object; and based on the determination, generating, an augmented reality based visualization associated with the inanimate object, the augmented reality based visualization including at least one indicator of the status. the method further including generating a feedback associated with the inanimate object including the at least one indicator for a user; and transmitting the feedback to a wearable device of the user.
Inventor(s): Wen Pei Yu of Xian (CN) for international business machines corporation, Xiao Ming Ma of X'ian (CN) for international business machines corporation, Xue Ying Zhang of X'ian (CN) for international business machines corporation, Si Er Han of X'ian (CN) for international business machines corporation, Jing James Xu of X'ian (CN) for international business machines corporation, Jing Xu of X'ian (CN) for international business machines corporation, Jun Wang of X'ian (CN) for international business machines corporation
IPC Code(s): G06T11/20, G06N20/00
CPC Code(s): G06T11/206
Abstract: in an approach for post-modeling data visualization and analysis, a processor presents a first visualization of a training dataset in a first plot. responsive to receiving a selection of a data group of the training dataset to analyze, a processor identifies three or fewer key model features of the data group of the training dataset. a processor ascertains a representative record of each key model feature of the three or fewer key model features using a local interpretable model-agnostic explanation technique. a processor presents a second visualization of the three or fewer key model features and the representative record of each key model feature in a second plot.
Inventor(s): Sudheesh S. Kairali of Kozhikode (IN) for international business machines corporation, Sarbajit K. Rakshit of Kolkata (IN) for international business machines corporation
IPC Code(s): G06T19/00, G02B27/01, G06T13/40, G06V10/74
CPC Code(s): G06T19/006
Abstract: provided is a computer-implemented method, system, and computer program product for displaying augmented reality (ar) visualization of a user action on an identified and/or recognized object. a processor may determine, for a user, an object interest level for each object of a plurality of known objects. the processor may detect one or more objects in an environment. the processor may identify, based on the object interest level, a first object of the one or more objects in the environment that is similar to at least one object of the plurality of known objects. the processor may determine, based on properties of the first object and the object interest level, an action for interacting with the first object. the processor may display, using an ar display, an avatar performing the determined action for interacting with the first object.
Inventor(s): Ang Yi of Beijing (CN) for international business machines corporation, Jing Zhang of Beijing (CN) for international business machines corporation, Hai Cheng Wang of Beijing (CN) for international business machines corporation, Jun Hong Zhao of ShangDi (CN) for international business machines corporation, Rajesh M. Desai of San Jose CA (US) for international business machines corporation, Yang Zhong Li of Beijing (CN) for international business machines corporation, Ye Chen of Beijing (CN) for international business machines corporation
IPC Code(s): G06V30/412, G06V10/26, G06V10/74, G06V10/75, G06V30/413, G06V30/414
CPC Code(s): G06V30/412
Abstract: computer implemented methods, systems, and computer program products include program code executing on a processor(s) that merges a document comprising multiple pages into a single document image. the program code processes the single document image to identify structural elements and textual content. the program code compares the structural elements of the single document image to other structural elements of a group of document templates stored in a database to identify a subset of the group of documents templates with a threshold number of similarities to the single document image. the program code generates, from the single document image, a graph structure representing the document, where the graph structure comprises visual information and connections related to the structural elements and concepts comprising the textual content. the program code uses the structure to identify a document template that is a closest match to the document.
Inventor(s): Lowell Thomason of Byron MN (US) for international business machines corporation, Bradley Smoley of Rochester MN (US) for international business machines corporation, Jessica Wandrey of Kasson MN (US) for international business machines corporation, Mark E. Maresh of Oro Valley AZ (US) for international business machines corporation, Richard Burton Finch of New Paltz NY (US) for international business machines corporation
IPC Code(s): G08B21/18, G08B21/10
CPC Code(s): G08B21/182
Abstract: dynamically coordinating interactive fence zones and alerts includes receiving, by one or more processors, location data corresponding to a first object. a virtual fence location and a virtual fence type are determined for the first object based on the received location data, and a first virtual fence is then established surrounding the first object. a plurality of parameters associated with the first virtual fence is received by the one or more processors, and a rule table is generated based on the received plurality of parameters associated with the first virtual fence. data regarding a virtual fence boundary of the first virtual fence is received by the one or more processors, and based on the received data meeting a first rule of the rule table, an alert is sent to a user device.
Inventor(s): Swagatam Haldar of Kolkata (IN) for international business machines corporation, Diptikalyan Saha of Bangalore (IN) for international business machines corporation, Deepak Vijaykeerthy of Bangalore (IN) for international business machines corporation, Aniya Aggarwal of New Delhi (IN) for international business machines corporation, Nishtha Madaan of Gurgaon (IN) for international business machines corporation
IPC Code(s): G10L15/01, G06N3/08, G10L15/18, G10L15/32, G10L25/18
CPC Code(s): G10L15/01
Abstract: one or more systems, devices, computer program products and/or computer-implemented methods of use provided herein relate to a process to facilitate testing a cascaded pipeline. a system can comprise a memory that stores computer executable components, and a processor that executes the computer executable components stored in the memory, wherein the computer executable components can comprise an input component, a cascaded pipeline, and an evaluation component. the input component can receive a test case associated with a label from labeled speech data represented by waveform. the evaluation component can feed the test case to the cascaded pipeline to obtain an output of the cascaded pipeline. the evaluation component can evaluate a robustness of the cascaded pipeline by comparing the output of the cascaded pipeline and the label. the cascaded pipeline can include a first model and a second model, and the first model can be different than the second model.
Inventor(s): Praveen Venkateswaran of Cambridge MA (US) for international business machines corporation, Nigel Steven Fernandez of Sunderland MA (US) for international business machines corporation, Yara Rizk of Cambridge MA (US) for international business machines corporation, Vatche Isahagian of Belmont MA (US) for international business machines corporation, Vinod Muthusamy of Austin TX (US) for international business machines corporation
IPC Code(s): G10L15/18, G10L15/06, G10L15/22
CPC Code(s): G10L15/1815
Abstract: according to one embodiment, a method, computer system, and computer program product for software agent synthesis is provided. the present invention may include generating one or more training examples from historical data and software agents; training, using the on the one or more training examples, a language model to synthesize a software agent based on a natural language input from a user; monitoring, using one or more input devices, for one or more natural language user inputs; responsive to identifying one or more natural language user inputs, synthesizing, using the trained language model, one or more software agents based on the one or more natural language user inputs; execute the one or more new software agents to carry out one or more tasks invoked by the one or more natural language user inputs.
Inventor(s): Willie L. Scott, II of Austin TX (US) for international business machines corporation
IPC Code(s): G10L15/26, G10L25/03, H04N21/488
CPC Code(s): G10L15/26
Abstract: according to one embodiment, a method, computer system, and computer program product for generating captions is provided. the present invention may include capturing input audio comprising audiovisual content; processing the input audio to extract an input rate of speech, input word timings, and input word predictions; generating one or more new audio files by altering the input rate of speech of the input audio to fall within a pre-determined range; processing the one or more new audio files to extract new word timings and a new word predictions; creating a mapping that pairs the input word timings with corresponding new word timings; selecting a word prediction for each paired input word timing and new word timing based on the mapping; and integrating the selected word predictions into the audiovisual content for display.
Inventor(s): Takashi Ando of Eastchester NY (US) for international business machines corporation, Reinaldo Vega of Mahopac NY (US) for international business machines corporation, David Wolpert of Poughkeepsie NY (US) for international business machines corporation, Nicholas Anthony Lanzillo of Wynantskill NY (US) for international business machines corporation
IPC Code(s): G11C11/22, H10B53/30
CPC Code(s): G11C11/221
Abstract: a capacitive memory cell includes an electrode, a tunneling barrier layer in direct contact with the electrode, a charge trapping layer in direct contact with the tunneling barrier layer, a ferroelectric layer in direct contact with the charge trapping layer, and another electrode in direct contact with the ferroelectric layer.
Inventor(s): Niina Haiminen of Tampere (FI) for international business machines corporation, Laxmi Parida of Mohegan Lake NY (US) for international business machines corporation, Filippo Utro of Pleasantville NY (US) for international business machines corporation
IPC Code(s): G16B5/00, C12Q1/04, G16B45/00
CPC Code(s): G16B5/00
Abstract: topological data analysis is used to detect general nestedness in microbial communities through the generation and application of filtration matrices and persistent homology barcodes. from a starting point of an input matrix with 1s and 0s, a filtration matrix is generated with a mathematical function, such as a jaccard similarity, overlap coefficient, or a min(com1/sum(1)) computation. the persistent homology of the filtration matrix is then calculated in at least two dimensions using a mathematical function, such as a simplicial complex, a cubical complex, an alpha complex, a c�ech complex, or a vietris-rips complex, that is displayed in a barcode that provides a visualization of the nestedness within the microbial community. p-values for the microbial community nestedness can be calculated by comparing the shape and length of the persistent homology barcodes for the input matrix against persistent homology barcodes for a completely randomized input matrix.
Inventor(s): Ruilong Xie of Niskayuna NY (US) for international business machines corporation, Kisik Choi of Watervliet NY (US) for international business machines corporation, Nicolas Jean Loubet of GUILDERLAND NY (US) for international business machines corporation, Theodorus E. Standaert of Clifton Park NY (US) for international business machines corporation
IPC Code(s): H01L21/768, H01L21/28, H01L21/8234, H01L21/8238, H01L23/528, H01L23/535, H01L27/06, H01L27/088, H01L29/06, H01L29/66, H01L29/786
CPC Code(s): H01L21/76897
Abstract: a semiconductor device is provided. the semiconductor device includes source/drain (s/d) epitaxy, a gate stack adjacent to the s/d epitaxy, a semiconductor layer underlying the gate stack and including a semiconductor material surrounded by an inner spacer, an etch stop layer underlying the semiconductor layer, back trench s/d epitaxy and a self-aligned backside contact. the backside trench s/d epitaxy contacts the s/d epitaxy and is insulated from the semiconductor material by the inner spacer. the self-aligned backside contact contacts the backside trench s/d epitaxy and is insulated from the semiconductor material by the etch stop layer.
Inventor(s): Mukta Ghate Farooq of Hopewell Junction NY (US) for international business machines corporation, Keiji Matsumoto of Yokohama-shi (JP) for international business machines corporation, John Knickerbocker of Monroe NY (US) for international business machines corporation
IPC Code(s): H01L23/31, H01L23/29, H01L23/48
CPC Code(s): H01L23/3192
Abstract: a semiconductor structure includes a first back-end-of-line region coupled to a first side of a front-end-of-line region, a second back-end-of-line region coupled to a second side of the front-end-of-line region, and a thermally conducting region at least partially surrounding a perimeter of the front-end-of-line region, the first back-end-of-line region and the second back-end-of-line region.
Inventor(s): Brent William Yardley of Hillsboro OR (US) for international business machines corporation, Theron Lee Lewis of Rochester MN (US) for international business machines corporation, James D. Bielick of Pine Island MN (US) for international business machines corporation, Curtis Eugene Larsen of Eden Valley MN (US) for international business machines corporation, Karl Stathakis of Owatonna MN (US) for international business machines corporation
IPC Code(s): H01L23/367, H01L21/48
CPC Code(s): H01L23/367
Abstract: mounting a heat sink to an electrical component by applying a thermal interface material on at least one of a surface of one of the electrical component and the heat sink, wherein the heat sink includes a heat pedestal including an interface surface with an apex having at least one curvature extending therethrough. the heat sink contacts the electrical component through the thermal interface material. the apex of the interface surface is an element of the heat sink closest to the electrical component. the interface surface that includes the apex and the at least one curvature cause the thermal interface material to flow during the contacting so that any space between the heat sink and the electrical component is filled with thermal interface material and is substantially free of voids.
Inventor(s): Ruilong Xie of NIskayuna NY (US) for international business machines corporation, Nicholas Anthony Lanzillo of Wynantskill NY (US) for international business machines corporation, Koichi Motoyama of Clifton Park NY (US) for international business machines corporation, Lawrence A. Clevenger of Saratoga Springs NY (US) for international business machines corporation, Hosadurga Shobha of Niskayuna NY (US) for international business machines corporation, Huai Huang of Clifton Park NY (US) for international business machines corporation, Chih-Chao Yang of Glenmont NY (US) for international business machines corporation
IPC Code(s): H01L23/522, H01L21/768, H01L23/528
CPC Code(s): H01L23/5226
Abstract: a semiconductor device includes a first metallization layer; a second metallization layer formed on the first metallization layer; a third metallization layer formed on the second metallization layer; a super via extending from the first metallization layer to the third metallization layer; and an inner spacer layer formed on sidewalls of the super via from the second metallization layer to the first metallization layer.
Inventor(s): Ruilong Xie of Niskayuna NY (US) for international business machines corporation, Koichi Motoyama of Clifton Park NY (US) for international business machines corporation, Nicholas Anthony Lanzillo of Wynantskill NY (US) for international business machines corporation, Oleg Gluschenkov of Tannersville NY (US) for international business machines corporation
IPC Code(s): H01L23/522, H01L21/768, H01L23/528
CPC Code(s): H01L23/5226
Abstract: a semiconductor structure includes a first metallization layer having a first plurality of metal containing lines, and a second metallization layer located above the first metallization layer. the second metallization layer includes a second plurality of metal containing lines. a first group of the second plurality of metal containing lines is disposed within the first metallization layer. the first group of the second plurality of metal containing lines is isolated from the first metallization layer by a dielectric barrier layer.
Inventor(s): Koichi Motoyama of Clifton Park NY (US) for international business machines corporation, Oscar van der Straten of Guilderland Center NY (US) for international business machines corporation, Chih-Chao Yang of Glenmont NY (US) for international business machines corporation
IPC Code(s): H01L23/522, H01L21/768, H01L23/532
CPC Code(s): H01L23/5226
Abstract: dual-damascene fully-aligned via interconnects with divot fill are provided. in one aspect, an interconnect structure includes: a first interlayer dielectric disposed on a wafer; a metal line(s) embedded in the first interlayer dielectric, where a top surface of the metal line(s) is recessed below a top surface of the first interlayer dielectric; a second interlayer dielectric disposed on the first interlayer dielectric; a conductive via(s) embedded in the second interlayer dielectric and aligned with the metal line(s); a barrier layer along a bottom and a first portion of a sidewall of the metal line(s); and a protective dielectric layer along a second portion of the sidewall of the metal line(s), where the barrier layer and the protective dielectric layer fully separate the metal line(s) from the first interlayer dielectric. a metal cap can be disposed on the metal line(s). a method of fabricating an interconnect structure is also provided.
Inventor(s): Albert M. Chu of Nashua NH (US) for international business machines corporation, Nicholas Anthony Lanzillo of Wynantskill NY (US) for international business machines corporation, Albert M. Young of Fishkill NY (US) for international business machines corporation, Junli Wang of Slingerlands NY (US) for international business machines corporation, Brent A. Anderson of Jericho VT (US) for international business machines corporation, Ruilong Xie of Niskayuna NY (US) for international business machines corporation, Lawrence A. Clevenger of Saratoga Springs NY (US) for international business machines corporation, REINALDO VEGA of Mahopac NY (US) for international business machines corporation
IPC Code(s): H01L23/528, G06F30/392, G06F30/394, H01L23/522, H01L27/092
CPC Code(s): H01L23/5286
Abstract: a semiconductor structure is presented having a plurality of circuit rows, a plurality of first power rails positioned on front sides of the plurality of circuit rows, a plurality of second power rails positioned on back sides of the plurality of circuit rows, and power tap cells associated with each the plurality of circuit rows, wherein each of the power tap cells includes one or more power vias connecting at least one first power rail of the plurality of first power rails to at least one second power rail of the plurality the second power rails. in one instance, the plurality of second power rails are orthogonal to the plurality of first power rails. in another instance, the plurality of first power rails are horizontally offset from the plurality of second power rails. the one or more power vias include at least two or more different sized power vias.
Inventor(s): Alexander Reznicek of Troy NY (US) for international business machines corporation, Tsung-Sheng Kang of Ballston Lake NY (US) for international business machines corporation, Daniel Schmidt of Niskayuna NY (US) for international business machines corporation, Ruilong Xie of Niskayuna NY (US) for international business machines corporation
IPC Code(s): H01L23/528, H01L21/02, H01L23/485
CPC Code(s): H01L23/5286
Abstract: a semiconductor structure includes a lattice matched etch stop layer disposed on a silicon substrate layer. the lattice matched etch stop layer is lattice matched to the silicon substrate layer. the semiconductor structure further includes an epitaxial silicon layer disposed on the lattice matched etch stop layer, a front-end-of-the-line device layer disposed on the epitaxial silicon layer, a back-end-of-the-line device layer disposed on the front-end-of-the-line device layer, and a carrier wafer disposed on the back-end-of-the-line device layer.
Inventor(s): Ruqiang Bao of Niskayuna NY (US) for international business machines corporation, Fee Li Lie of Albany NY (US) for international business machines corporation, Michael P. Belyansky of Halfmoon NY (US) for international business machines corporation, Matt Malley of Averill Park NY (US) for international business machines corporation
IPC Code(s): H01L27/06, H01L21/768, H01L23/00, H01L23/48
CPC Code(s): H01L27/0688
Abstract: a multi-layer stacked semiconductor device includes a first integrated circuit device and a bonding insulator layer formed upon the first integrated circuit device. the bonding insulator layer includes an insulating material layer and an etch stop layer. the semiconductor device also includes a second integrated circuit device formed over the first integrated circuit device in a stacked configuration. the semiconductor device also includes a bonding insulator layer formed between the second integrated circuit device and the insulating material layer. the insulating material layer and the bonding insulator layer are bonded adjacent to one another.
Inventor(s): Min Gyu Sung of Latham NY (US) for international business machines corporation, Julien Frougier of Albany NY (US) for international business machines corporation, Ruilong Xie of Niskayuna NY (US) for international business machines corporation, Chanro Park of Clifton Park NY (US) for international business machines corporation, Juntao Li of Cohoes NY (US) for international business machines corporation
IPC Code(s): H01L27/092, H01L21/02, H01L21/8238, H01L29/06, H01L29/423, H01L29/66, H01L29/775
CPC Code(s): H01L27/092
Abstract: a semiconductor device includes a first nanosheet field effect transistor (pet) having a first gate stack arranged on a substrate. a second nanosheet fet is arranged on the substrate adjacent to the first nanosheet fet. the second fet includes a second gate stack, wherein a top of the first gate stack and a top of the second gate stack have different heights.
Inventor(s): Albert M. Chu of Nashua NH (US) for international business machines corporation, Brent A. Anderson of Jericho VT (US) for international business machines corporation, Nicholas Anthony Lanzillo of Wynantskill NY (US) for international business machines corporation, Reinaldo Vega of Mahopac NY (US) for international business machines corporation, Lawrence A. Clevenger of Saratoga Springs NY (US) for international business machines corporation, Ruilong Xie of Niskayuna NY (US) for international business machines corporation
IPC Code(s): H01L27/118
CPC Code(s): H01L27/11807
Abstract: a semiconductor structure comprising a first circuit row and a second circuit row adjacent the first circuit row. the first circuit row comprises a first circuit cell and a second circuit cell, the first circuit cell having a first cell height greater than a first row height of the first circuit row, the second circuit cell having a second cell height different than the first cell height. the second circuit row comprises a third circuit cell, the third circuit cell having a third cell height less than a second row height of the second circuit row. the first circuit cell in the first circuit row is at least partially aligned with the third circuit cell in the second circuit row.
Inventor(s): Ruilong Xie of Niskayuna NY (US) for international business machines corporation, Tao Li of Slingerlands NY (US) for international business machines corporation, Nicholas Alexander POLOMOFF of Hopewell Junction NY (US) for international business machines corporation, Chih-Chao Yang of Glenmont NY (US) for international business machines corporation
IPC Code(s): H01L27/12
CPC Code(s): H01L27/124
Abstract: a first backside power rail directly below and connected to a first source-drain epitaxy region of a positive field effect transistor (p-fet) region via a first backside contact vertically aligned with the first source-drain epitaxy region, the first backside power rail directly contacts an upper horizontal surface of the first backside contact and the first backside power rail directly contacts a vertical side surface of the first backside contact. forming a first backside power rail directly below and connected to a first source-drain epitaxy region of a positive field effect transistor (p-fet) region via a first backside contact vertically aligned with the first source-drain epitaxy region, where the first backside power rail directly contacts an upper horizontal surface of the first backside contact and the first backside power rail directly contacts a vertical side surface of the first backside contact.
Inventor(s): Genevieve Antoinette Kane of Albany NY (US) for international business machines corporation, Manasa Medikonda of Albany NY (US) for international business machines corporation, Md Nabil Azad of Malta NY (US) for international business machines corporation, Shravana Kumar Katakam of Lehi UT (US) for international business machines corporation, Nicholas Latham of Albany NY (US) for international business machines corporation, Indira Seshadri of Niskayuna NY (US) for international business machines corporation, Tao Li of Slingerlands NY (US) for international business machines corporation
IPC Code(s): H01L27/12
CPC Code(s): H01L27/1248
Abstract: a semiconductor device includes a first transistor comprising a first gate region, and a second transistor comprising a second gate region. the second transistor is stacked on the first transistor in a staggered configuration. a dielectric bonding layer is between the first transistor and the second transistor, and a gate cut portion is along a side of the first gate region and a side of the second gate region. a gate contact is connected to at least one of the first gate region and the second gate region.
Inventor(s): Sarbajit K. Rakshit of Kolkata (IN) for international business machines corporation, Jagabondhu Hazra of Bangalore (IN) for international business machines corporation, Manikandan Padmanaban of Chennai (IN) for international business machines corporation, Marc Henri Coq of Hopewell Junction NY (US) for international business machines corporation
IPC Code(s): H02S20/30, G01B5/24, H01L31/02, H02S10/10, H02S40/30, H10N30/30
CPC Code(s): H02S20/30
Abstract: an approach for adjusting an inclination angle and a raindrop impact angle of a solar panel to maximize power output. the approach predicts an impact angle of a plurality of raindrops on an inclined solar panel. the approach predicts solar irradiance striking the inclined solar panel. the approach calculates an optimal solar panel inclination angle and an optimal solar panel radial angle based on maximizing power output. the approach adjusts the solar panel inclination angle and solar panel radial angle based on the optimal solar panel inclination angle and an optimal solar panel radial angle.
Inventor(s): Abram L Falk of Port Chester NY (US) for international business machines corporation, Chi Xiong of Yorktown Heights NY (US) for international business machines corporation, Ryan Daniel Schilling of New York NY (US) for international business machines corporation, Jason S. Orcutt of Katonah NY (US) for international business machines corporation
IPC Code(s): H04B10/70, G02F1/35, G02F1/355, G02F1/365, H01S3/094, H10N60/83
CPC Code(s): H04B10/70
Abstract: devices and/or methods provided herein relate to providing conversion of photons between an optical domain and a microwave domain. an electronic structure can comprise a resonator assembly comprising a microwave resonator and an optical resonator, an optical pump waveguide that transmits an optical pump input to the resonator assembly, and an optical signal waveguide, separate from the optical pump waveguide, that transmits an optical signal relative to the resonator assembly. the electronic structure further can comprise a microwave signal waveguide that transmits a microwave signal relative to the resonator assembly. the optical pump waveguide can comprise a delay portion that delays receipt of the optical pump input to the resonator assembly through the optical pump waveguide to a time after reduction of a majority of decoherence of the resonator assembly caused by scattering of a portion of the optical pump input, which portion does not enter the optical pump waveguide.
Inventor(s): Atsushi ABE of Ebina (JP) for international business machines corporation, Tsuyoshi Miyamura of Yokohama-shi (JP) for international business machines corporation, KOHEI TAGUCHI of Yokohama (JP) for international business machines corporation, KENJI MIKUNI of Inzai-shi (JP) for international business machines corporation, Tsuyoshi Kamenoue of Adachi-ku (JP) for international business machines corporation
IPC Code(s): H04L9/08
CPC Code(s): H04L9/0822
Abstract: provided are a computer program product, system, and method for managing access to tape cartridges at a tape archival service provider. a determination is made as to whether a non-volatile memory of the tape cartridge stores a key encryption key comprising an encrypted user encryption key associated with a user. in response to determining that the non-volatile memory of the tape cartridge stores the key encryption key, the key encryption key is decrypted to produce the user encryption key. the user encryption key, resulting from the decrypting, is provided to an encryption engine of the tape drive to encrypt plain-text data read from the tape medium in the tape cartridge with the user encryption key to return to a read request.
Inventor(s): SUDHEESH S. KAIRALI of KOZHIKODE (IN) for international business machines corporation, SARBAJIT K. RAKSHIT of KOLKATA (IN) for international business machines corporation
IPC Code(s): H04L9/40
CPC Code(s): H04L63/0414
Abstract: a method for protecting data from a user that traverses through a chain of microservices include retrieving information identifying the chain of microservices associated with a user identifier of the user and a time when the user provided data to the chain of microservices. a level of confidentiality stored in association with the user identifier and with the time is retrieved. one or more security measures corresponding to the stored level of confidentiality are implemented for each microservice of the chain of microservices during the time.
Inventor(s): Krishnan Sugavanam of Mahopac NY (US) for international business machines corporation, ARIS GKOULALAS-DIVANIS of Waltham MA (US) for international business machines corporation, Sophie Batchelder of Cambridge MA (US) for international business machines corporation, Uri Kartoun of Cambridge MA (US) for international business machines corporation
IPC Code(s): H04L9/40
CPC Code(s): H04L63/0876
Abstract: according to one embodiment, a method, computer system, and computer program product for user authentication. the embodiment may include receiving, at an authentication server, respective multiple location coordinates from first and second registered devices. storing, on the authentication server, respective moving windows comprising registered, device specific, last n location coordinates from the first and the second registered devices. receiving a request to access the authentication server via the first registered device. the request comprises log-in credentials of a user and a first hash value calculated at the first registered device. computing, at the authentication server, a second hash value using a set of the last n location coordinates from each of the respective moving windows. comparing the first hash value and the second hash value. in response to the first and the second hash values being equal, and the log-in credentials being verified, granting access to the authentication server.
Inventor(s): Frederico Araujo of Mahopac NY (US) for international business machines corporation, Teryl Paul Taylor of Danbury CT (US) for international business machines corporation
IPC Code(s): H04L9/40
CPC Code(s): H04L63/1416
Abstract: an approach is disclosed that receives system events corresponding to event occurrences that occur at an information handling system. the system events are combined into a set of one or more coalesced events, wherein the combining is based on a root node associated with the system events. the coalesced events are then transmitted to a security information and event management (siem) system.
Inventor(s): Brent A. Anderson of Jericho VT (US) for international business machines corporation, Albert M. Chu of Nashua NH (US) for international business machines corporation, Carl Radens of LaGrangeville NY (US) for international business machines corporation, Ruilong Xie of Niskayuna NY (US) for international business machines corporation
IPC Code(s): H10B10/00
CPC Code(s): H01L27/1108
Abstract: a semiconductor structure is provided that includes a stacked transistor including at least one transistor stacked over another transistor and a non-stacked transistor integrated on a same wafer. both the stacked transistor and the non-stacked transistor include frontside and backside interconnects.
Inventor(s): Min Gyu Sung of Latham NY (US) for international business machines corporation, Julien Frougier of Albany NY (US) for international business machines corporation, Ruilong Xie of Niskayuna NY (US) for international business machines corporation, Chanro Park of Clifton Park NY (US) for international business machines corporation, Juntao Li of Cohoes NY (US) for international business machines corporation, Soon-Cheon Seo of Glenmont NY (US) for international business machines corporation, Takashi Ando of Eastchester NY (US) for international business machines corporation, Chen Zhang of Guilderland NY (US) for international business machines corporation, Heng Wu of Santa Clara CA (US) for international business machines corporation
IPC Code(s): H10B63/00
CPC Code(s): H01L27/2436
Abstract: a semiconductor structure including a one-transistor one-capacitor (1t1r) device is provided that includes an embedded resistive random access memory (reram) having a width larger than 1 gate pitch, that is present in a frontside or the backside of the structure, a frontside contact structure electrically connected to a source region of the transistor of the 1t1r device and a backside contact structure electrically connected to a drain region of the transistor of the 1t1r device.
Inventor(s): Alexander Reznicek of Troy NY (US) for international business machines corporation, Bahman Hekmatshoartabari of White Plains NY (US) for international business machines corporation, Praneet Adusumilli of Somerset NJ (US) for international business machines corporation, Fabio Carta of Pleasantville NY (US) for international business machines corporation
IPC Code(s): H10B63/00, H10N70/00, H10N70/20
CPC Code(s): H01L27/2445
Abstract: a phase change memory device or a reram device is integrated with a pair of bipolar junction transistors, the pair of bipolar junction transistors being arranged in a sziklai darlington transistor configuration. a small unit cell footprint is obtained by pairing a vertical bipolar junction transistor with a lateral bipolar junction transistor, the memory device being electrically connected to the collector of the lateral bipolar junction transistor.
Inventor(s): Bogdan Cezar Zota of Rueschlikon (CH) for international business machines corporation, Kirsten Emilie Moselund of Rueschlikon (CH) for international business machines corporation, Peter Mueller of Zurich (CH) for international business machines corporation
IPC Code(s): H10N50/01, H10N50/80, H10N50/85
CPC Code(s): H01L43/12
Abstract: a method for forming a semiconductor structure comprising isolated coupled quantum dots defining a physical spin qubit is disclosed. the method comprises structuring the doped silicon layer using an sio substrate with a source area structure, a linear structure extending from the source area, gate structures extending vertically to a main extension direction of the linear structure, covering the structures with an oxide, removing the oxide at a lateral end of the linear structure, laterally etching back the linear structure between the blanket oxide and the soi isolator, epitaxial filling the hollow template with a first semiconductor material different from the silicon, continuing the epitaxial and laterally filling the hollow template with an alternating sequence of lateral thin layers of a second and a third semiconductor material, and continuing the epitaxial filling the hollow template with the first semiconductor material until an end of the hollow template is reached.
Inventor(s): Matthias Georg Gottwald of Ridgefield CT (US) for international business machines corporation, Guohan Hu of Yorktown Heights NY (US) for international business machines corporation, Stephen L. Brown of Carmel NY (US) for international business machines corporation, Alexander Reznicek of Troy NY (US) for international business machines corporation
IPC Code(s): H10N50/01, G11C11/16, H01F10/32, H10B61/00, H10N50/10, H10N50/80, H10N50/85
CPC Code(s): H01L43/12
Abstract: a semiconductor device that includes a substrate, a crystalline bottom electrode layer on an upper side of the semiconductor substrate, a conductive crystalline metal layer above the crystalline bottom electrode layer, and a conductive oxide layer above the conductive crystalline metal layer. the conductive oxide layer has a low resistance. the semiconductor device also includes a magnetic tunnel junction (mtj) above the conductive crystalline metal layer, the mtj including a tunnel barrier layer, a free layer on a first side of the tunnel barrier layer and a reference layer on a second side of the tunnel barrier layer opposite the first side.
Inventor(s): Koichi Motoyama of Clifton Park NY (US) for international business machines corporation, Oscar van der Straten of Guilderland Center NY (US) for international business machines corporation, Jennifer Church of Albany NY (US) for international business machines corporation, Chih-Chao Yang of Glenmont NY (US) for international business machines corporation
IPC Code(s): H10N50/80, G11C11/16, H10B61/00, H10N50/01
CPC Code(s): H01L43/02
Abstract: a magnetic tunnel junction (mtj) stack with a hammerhead profile, including vertically aligned layers of a top electrode, a free layer, a tunneling barrier, a reference layer and a bottom electrode, where the bottom electrode and the reference layer each include a first width, and the top electrode, the free layer and the tunneling barrier, each include a second width greater than the first width. forming vertically aligned layers of a bottom electrode and a reference layer on the bottom electrode, of a magnetic tunnel junction (mtj), where the bottom electrode, the reference layer and the hard mask, each include a first width, and separately forming vertically aligned layers of a tunneling barrier, a free layer and a top electrode on the free layer, where the tunneling barrier, the free layer and the top electrode each include a second width, where the second width is greater than the first width.
Inventor(s): Matthew Joseph BrightSky of Armonk NY (US) for international business machines corporation, Cheng-Wei Cheng of White Plains NY (US) for international business machines corporation, Guy M. Cohen of Westchester NY (US) for international business machines corporation, Robert L. Bruce of White Plains NY (US) for international business machines corporation, Asit Ray of Baldwin NY (US) for international business machines corporation, Wanki Kim of Chappaqua NY (US) for international business machines corporation
IPC Code(s): H01L47/00
CPC Code(s): H01L45/1246
Abstract: an electronic device includes a first electrode, a second electrode, and a memory component configured to store a resistive state. the memory component includes a layered region arranged in direct contact with the first electrode and a bulk region arranged in direct contact with the second electrode. the layered region includes a plurality of first layers made of a first material and a plurality of second layers made of a second material alternatingly arranged with one another. the first material is a phase-change material and the second material is a non-phase-change material. the bulk region is a continuous mass made of a third material that is different than the first material and the second material, and the bulk region is in direct contact with at least two of the first layers and at least one of the second layers of the layered region.
Inventor(s): Bogdan Cezar Zota of Rueschlikon (CH) for international business machines corporation, Kirsten Emilie Moselund of Rueschlikon (CH) for international business machines corporation, Peter Mueller of Rueschlikon (CH) for international business machines corporation
IPC Code(s): H10N99/00
CPC Code(s): H10N99/05
Abstract: a method for forming a semiconductor structure comprising quantum dots with self-aligned gate structures is disclosed. the method comprises structuring a doped silicon-on-isolator to build a source area, a linear structure extending from the source area having at least two distinct broadened areas, a first and a second gate structure simultaneously by a single lithography process; covering the structures with a blanket oxide layer, forming an opening in the blanket oxide layer at a lateral end of the linear structure, etching back the linear structure and the at least two distinct broadened areas below the blanket oxide until the source area is reached, and filling the hollow template with a semiconductor material different to the silicon such that the at least two broadened areas build quantum dot areas.
International Business Machines Corporation patent applications on June 13th, 2024
- International Business Machines Corporation
- B60W60/00
- B60W50/00
- CPC B60W60/0015
- International business machines corporation
- G01W1/10
- G06N7/01
- CPC G01W1/10
- G02B6/12
- H01L21/56
- H01L25/00
- H01L25/16
- H01L25/18
- CPC G02B6/12004
- G05B19/4155
- CPC G05B19/4155
- G06F3/06
- CPC G06F3/061
- CPC G06F3/064
- G06F7/544
- G06F17/18
- CPC G06F7/5443
- G06F8/51
- G06F8/33
- G06N10/60
- CPC G06F8/51
- G06F8/71
- CPC G06F8/71
- G06F11/00
- G06F9/54
- CPC G06F11/004
- G06F11/07
- CPC G06F11/079
- G06F11/36
- CPC G06F11/3676
- G06F12/14
- G06F12/02
- CPC G06F12/1441
- G06F16/23
- G06F16/2453
- CPC G06F16/2379
- G06F16/2457
- G06F16/28
- CPC G06F16/24573
- G06F16/33
- G06F40/10
- G06N20/00
- CPC G06F16/3344
- G06F40/35
- G06F40/166
- G06F40/20
- H04L51/216
- CPC G06F40/35
- G06F40/58
- CPC G06F40/58
- G06N3/08
- CPC G06N3/08
- G06N3/088
- G06N3/045
- CPC G06N3/088
- G06N5/022
- CPC G06N5/022
- G06N5/04
- CPC G06N5/04
- G06N10/00
- G06F17/11
- CPC G06N10/00
- CPC G06N20/00
- G06F21/55
- G06Q10/0631
- CPC G06Q10/06313
- G06Q10/06
- G06K9/62
- CPC G06Q10/0633
- CPC G06Q10/0639
- G06Q30/018
- CPC G06Q30/0185
- G06Q30/04
- G06F9/48
- G06F11/32
- CPC G06Q30/04
- G06Q40/08
- CPC G06Q40/08
- G06T7/136
- G06T5/00
- CPC G06T7/136
- G06T11/00
- G06F3/01
- CPC G06T11/00
- G06T11/20
- CPC G06T11/206
- G06T19/00
- G02B27/01
- G06T13/40
- G06V10/74
- CPC G06T19/006
- G06V30/412
- G06V10/26
- G06V10/75
- G06V30/413
- G06V30/414
- CPC G06V30/412
- G08B21/18
- G08B21/10
- CPC G08B21/182
- G10L15/01
- G10L15/18
- G10L15/32
- G10L25/18
- CPC G10L15/01
- G10L15/06
- G10L15/22
- CPC G10L15/1815
- G10L15/26
- G10L25/03
- H04N21/488
- CPC G10L15/26
- G11C11/22
- H10B53/30
- CPC G11C11/221
- G16B5/00
- C12Q1/04
- G16B45/00
- CPC G16B5/00
- H01L21/768
- H01L21/28
- H01L21/8234
- H01L21/8238
- H01L23/528
- H01L23/535
- H01L27/06
- H01L27/088
- H01L29/06
- H01L29/66
- H01L29/786
- CPC H01L21/76897
- H01L23/31
- H01L23/29
- H01L23/48
- CPC H01L23/3192
- H01L23/367
- H01L21/48
- CPC H01L23/367
- H01L23/522
- CPC H01L23/5226
- H01L23/532
- G06F30/392
- G06F30/394
- H01L27/092
- CPC H01L23/5286
- H01L21/02
- H01L23/485
- H01L23/00
- CPC H01L27/0688
- H01L29/423
- H01L29/775
- CPC H01L27/092
- H01L27/118
- CPC H01L27/11807
- H01L27/12
- CPC H01L27/124
- CPC H01L27/1248
- H02S20/30
- G01B5/24
- H01L31/02
- H02S10/10
- H02S40/30
- H10N30/30
- CPC H02S20/30
- H04B10/70
- G02F1/35
- G02F1/355
- G02F1/365
- H01S3/094
- H10N60/83
- CPC H04B10/70
- H04L9/08
- CPC H04L9/0822
- H04L9/40
- CPC H04L63/0414
- CPC H04L63/0876
- CPC H04L63/1416
- H10B10/00
- CPC H01L27/1108
- H10B63/00
- CPC H01L27/2436
- H10N70/00
- H10N70/20
- CPC H01L27/2445
- H10N50/01
- H10N50/80
- H10N50/85
- CPC H01L43/12
- G11C11/16
- H01F10/32
- H10B61/00
- H10N50/10
- CPC H01L43/02
- H01L47/00
- CPC H01L45/1246
- H10N99/00
- CPC H10N99/05
