Intel corporation (20240303343). PARTITIONING OF PROCESSOR SOCKETS simplified abstract

PARTITIONING OF PROCESSOR SOCKETS

Organization Name

intel corporation

Inventor(s)

Yi Zeng of Shanghai (CN)

Russell J. Wunderlich of Livermore CO (US)

Janusz Jurski of Beaverton OR (US)

Lumin Zhang of Shanghai (CN)

Kasper Wszolek of Gdansk (PL)

Jeanne Guillory of Reseda CA (US)

Ching Yu Lo of Taipei (TW)

Teresa C. Herrick of Folsom CA (US)

Richard Marian Thomaiyar of Trichy (IN)

PARTITIONING OF PROCESSOR SOCKETS - A simplified explanation of the abstract

This abstract first appeared for US patent application 20240303343 titled 'PARTITIONING OF PROCESSOR SOCKETS

The patent application described herein pertains to multiple processor sockets connected to processors and first circuitry. The first circuitry can configure the multiple processor sockets in two different modes of operation.

• In the first mode of operation, the multiple processor sockets are configured to operate with a single memory address space and share interfaces.
• In the second mode of operation, the interfaces accessible to the multiple processor sockets are configured to provide isolated communications to processor sockets in different partitions. Additionally, the multiple processor sockets are configured to operate in independent memory address spaces.

Potential Applications: - Data centers - High-performance computing systems - Server architectures

Problems Solved: - Efficient resource utilization - Enhanced system flexibility - Improved data processing capabilities

Benefits: - Increased system performance - Enhanced scalability - Improved data security

Commercial Applications: Title: "Enhanced Processor Socket Configuration for Improved System Performance" This technology can be utilized in data centers, server farms, and cloud computing environments to optimize system performance and resource allocation.

Questions about the technology: 1. How does this technology improve data processing capabilities in high-performance computing systems? 2. What are the key advantages of configuring multiple processor sockets to operate in independent memory address spaces?

Original Abstract Submitted

examples described herein relate to multiple processor sockets comprising processors connected thereto and first circuitry. the first circuitry is to: based on a first mode of operation: configure the multiple processor sockets to operate with a single memory address space and share interfaces and based on a second mode of operation: configure the interfaces accessible to the multiple processor sockets to provide isolated communications to processor sockets in different partitions and configure the multiple processor sockets to operate in independent memory address spaces.