Intel corporation (20240250043). CHIPLET FIRST ARCHITECTURE FOR DIE TILING APPLICATIONS simplified abstract
Contents
CHIPLET FIRST ARCHITECTURE FOR DIE TILING APPLICATIONS
Organization Name
Inventor(s)
Srinivas Pietambaram of Chandler AZ (US)
Deepak Kulkarni of Chandler AZ (US)
Rahul Manepalli of Chandler AZ (US)
Xiaoying Guo of Chandler AZ (US)
CHIPLET FIRST ARCHITECTURE FOR DIE TILING APPLICATIONS - A simplified explanation of the abstract
This abstract first appeared for US patent application 20240250043 titled 'CHIPLET FIRST ARCHITECTURE FOR DIE TILING APPLICATIONS
The abstract of this patent application describes electronic packages and methods of forming them. The electronic package includes a mold layer with embedded dies, with one die positioned between the other dies and the mold layer's second surface.
- Electronic package with mold layer and embedded dies
- First dies are coplanar with the mold layer's first surface
- Second die positioned between first dies and mold layer's second surface
Potential Applications: - Consumer electronics - Automotive electronics - Industrial equipment
Problems Solved: - Efficient packaging of electronic components - Improved thermal management - Enhanced durability and reliability
Benefits: - Compact design - Enhanced performance - Cost-effective manufacturing
Commercial Applications: Title: Advanced Electronic Packaging Technology for Various Industries This technology can be used in various industries such as consumer electronics, automotive, and industrial equipment, offering compact design, improved performance, and cost-effective manufacturing solutions.
Questions about Electronic Packaging Technology: 1. How does this technology improve thermal management in electronic devices? 2. What are the potential cost savings associated with using this advanced packaging technology?
Frequently Updated Research: Researchers are continually exploring new materials and manufacturing techniques to further enhance the performance and reliability of electronic packages. Stay updated on the latest advancements in this field to leverage the benefits of cutting-edge technology.
Original Abstract Submitted
embodiments disclosed herein include electronic packages and methods of forming such electronic packages. in an embodiment, the electronic package comprises a mold layer having a first surface and a second surface opposite the first surface, and a plurality of first dies embedded in the mold layer. in an embodiment, each of the plurality of first dies has a surface that is substantially coplanar with the first surface of the mold layer. in an embodiment, the electronic package further comprises a second die embedded in the mold layer. in an embodiment, the second die is positioned between the plurality of first dies and the second surface of the mold layer.
