Intel corporation (20240232122). DISAGGREGATED DIE WITH INPUT/OUTPUT (I/O) TILES simplified abstract
Contents
DISAGGREGATED DIE WITH INPUT/OUTPUT (I/O) TILES
Organization Name
Inventor(s)
Andrew Paul Collins of Chandler AZ (US)
Mahesh Krishnappayya Kumashikar of Bangalore (IN)
Srikanth Nimmagadda of Bangalore (IN)
DISAGGREGATED DIE WITH INPUT/OUTPUT (I/O) TILES - A simplified explanation of the abstract
This abstract first appeared for US patent application 20240232122 titled 'DISAGGREGATED DIE WITH INPUT/OUTPUT (I/O) TILES
The patent application describes a microelectronic assembly consisting of a substrate, a first die connected to the substrate, and a second die connected to the substrate adjacent to the first die.
- The first die has four edges, while the second die has six edges, with the fifth edge aligned with the first edge of the first die.
- The first die contains a processor die, while the second die contains an input/output (I/O) die.
- The second die extends beyond the third edge of the first die, creating a specific configuration for communication between the two dies.
Potential Applications: This technology could be used in various microelectronic devices that require efficient communication between different components. It may find applications in consumer electronics, telecommunications equipment, and industrial control systems.
Problems Solved: This innovation addresses the need for improved connectivity and communication between different dies in a microelectronic assembly. It optimizes the layout and placement of dies to enhance overall performance and functionality.
Benefits: Enhanced communication efficiency between processor and I/O components. Improved overall performance and reliability of microelectronic devices. Optimized design for compact and space-efficient assemblies.
Commercial Applications: Title: Enhanced Microelectronic Assembly for Improved Communication. This technology could be valuable in the development of advanced smartphones, tablets, networking devices, and IoT gadgets. It may have implications in the semiconductor industry, driving innovation in microelectronic design and manufacturing processes.
Prior Art: Readers interested in exploring prior art related to this technology could start by researching advancements in microelectronic packaging and die-to-die communication technologies.
Frequently Updated Research: Stay updated on the latest research in microelectronic assembly techniques, die stacking technologies, and advancements in semiconductor packaging methods.
Questions about Microelectronic Assembly: 1. How does this technology improve communication efficiency between different dies in a microelectronic assembly? 2. What are the potential implications of this innovation in the semiconductor industry?
Original Abstract Submitted
embodiments may relate to a microelectronic assembly including a substrate; a first die electrically coupled to the substrate, wherein the first die includes a first edge, a second edge, a third edge opposite the first edge, and a fourth edge opposite the second edge; and a second die electrically coupled to the substrate adjacent to the second edge of the first die and communicatively coupled to the first die, wherein the second die includes a fifth edge and a sixth edge opposite the fifth edge, and wherein the fifth edge of the second die is substantially aligned with the first edge of the first die and the sixth edge of the second die extends beyond the third edge of the first die, where the first die includes a processor die and the second die includes an input/output (i/o) die.
