Intel corporation (20240222346). ARCHITECTURES FOR MEMORY ON INTEGRATED CIRCUIT DEVICE PACKAGES simplified abstract
Contents
ARCHITECTURES FOR MEMORY ON INTEGRATED CIRCUIT DEVICE PACKAGES
Organization Name
Inventor(s)
Jenny Shio Yin Ong of Bayan Lepas (MY)
Kooi Chi Ooi of Bukit Gambir (MY)
Jackson Chung Peng Kong of Penang (MY)
ARCHITECTURES FOR MEMORY ON INTEGRATED CIRCUIT DEVICE PACKAGES - A simplified explanation of the abstract
This abstract first appeared for US patent application 20240222346 titled 'ARCHITECTURES FOR MEMORY ON INTEGRATED CIRCUIT DEVICE PACKAGES
Simplified Explanation: The patent application describes an apparatus consisting of two packages, with one package having a mold layer with a recess and a metal redistribution layer, and the other package having a plurality of devices and an integrated circuit device connected through solder bumps.
- The apparatus includes two packages coupled together, with one package having a mold layer with a recess and a metal redistribution layer.
- The second package contains a plurality of devices adjacent to the recess and an integrated circuit device connected to both packages through solder bumps.
- The recess in the mold layer has a smaller thickness compared to the overall thickness of the mold layer.
- The integrated circuit device is securely connected to both packages through the solder bumps.
- The innovation allows for efficient and reliable connection between the integrated circuit device and the two packages.
Potential Applications: 1. Semiconductor packaging industry. 2. Electronics manufacturing. 3. Integrated circuit design.
Problems Solved: 1. Ensuring secure connection between integrated circuit devices and packages. 2. Efficient redistribution of metal layers in semiconductor packaging.
Benefits: 1. Improved reliability in semiconductor packaging. 2. Enhanced performance of integrated circuit devices. 3. Simplified manufacturing processes.
Commercial Applications: The technology can be utilized in the production of advanced electronic devices, such as smartphones, tablets, and computers, to enhance their performance and reliability.
Prior Art: Researchers can explore prior patents related to semiconductor packaging, integrated circuit design, and metal redistribution layers to understand the existing technology landscape.
Frequently Updated Research: Researchers can stay updated on advancements in semiconductor packaging, integrated circuit design, and metal redistribution layers through academic journals and industry conferences.
Questions about Semiconductor Packaging: 1. How does the thickness of the recess in the mold layer impact the overall performance of the integrated circuit device? 2. What are the key factors to consider when designing solder bumps for connecting integrated circuit devices to packages?
Original Abstract Submitted
an apparatus is provided which comprises: a first package, a second package coupled with the first package, the second package comprising a mold layer having a recess on a first mold surface, a first plurality of devices adjacent to the recess and a metal redistribution layer (rdl) coupled to a second mold surface opposite the first mold surface, wherein the mold layer includes a first thickness, wherein the recess includes a second thickness, and wherein the second thickness is less than the first thickness, and an integrated circuit device coupled with both the second package at the recess and with the first package through a plurality of solder bumps. other embodiments are also disclosed and claimed.
