Intel corporation (20240220446). METHODS, SYSTEMS, AND APPARATUSES FOR DYNAMIC SIMULTANEOUS MULTI-THREADING (SMT) SCHEDULING TO MAXIMIZE PROCESSOR PERFORMANCE ON HYBRID PLATFORMS simplified abstract

METHODS, SYSTEMS, AND APPARATUSES FOR DYNAMIC SIMULTANEOUS MULTI-THREADING (SMT) SCHEDULING TO MAXIMIZE PROCESSOR PERFORMANCE ON HYBRID PLATFORMS

Organization Name

intel corporation

Inventor(s)

Deepak Samuel Kirubakaran of Hillsboro OR (US)

Rajshree Chabukswar of Sunnyvale CA (US)

Zhongsheng Wang of Camas WA (US)

Russell Fenger of Beaverton OR (US)

Asit Kumar Verma of Bangalore (IN)

DK Deepika of Secunderabad (IN)

Yevgeni Sabin of Haifa (IL)

Daniel J. Rogers of Folsom CA (US)

Cameron T. Rieck of Portland OR (US)

METHODS, SYSTEMS, AND APPARATUSES FOR DYNAMIC SIMULTANEOUS MULTI-THREADING (SMT) SCHEDULING TO MAXIMIZE PROCESSOR PERFORMANCE ON HYBRID PLATFORMS - A simplified explanation of the abstract

This abstract first appeared for US patent application 20240220446 titled 'METHODS, SYSTEMS, AND APPARATUSES FOR DYNAMIC SIMULTANEOUS MULTI-THREADING (SMT) SCHEDULING TO MAXIMIZE PROCESSOR PERFORMANCE ON HYBRID PLATFORMS

Simplified Explanation: The patent application describes techniques for implementing dynamic simultaneous multi-threading (SMT) scheduling on a hybrid processor platform.

• A hardware processor includes a first plurality of physical processor cores of a first type and a second plurality of physical processor cores of a second type.
• Each core of the second type implements a plurality of logical processor cores of the second type.
• The processor includes circuitry to determine the number of logical processor cores to be used by a set of threads of a foreground application and disable specific logical cores accordingly.

Key Features and Innovation:

• Implementation of dynamic simultaneous multi-threading (SMT) scheduling on a hybrid processor platform.
• Utilization of different types of physical processor cores to optimize performance based on application requirements.
• Adaptive disabling of logical processor cores based on thread usage to enhance efficiency.

Potential Applications: The technology can be applied in:

• High-performance computing systems
• Data centers
• Cloud computing environments

Problems Solved:

• Efficient resource allocation in hybrid processor platforms
• Optimization of processor core utilization based on application demands

Benefits:

• Improved performance and resource utilization
• Enhanced efficiency in handling multi-threaded applications
• Flexibility in adapting to varying workload requirements

Commercial Applications: Potential commercial uses include:

• Server systems for data centers
• Workstations for intensive computing tasks
• Cloud computing services

Prior Art: Prior research in dynamic scheduling algorithms for multi-core processors and hybrid computing systems can provide insights into similar technologies.

Frequently Updated Research: Stay updated on advancements in dynamic scheduling algorithms for hybrid processor platforms to leverage the latest innovations in multi-threading optimization.

Questions about Dynamic SMT Scheduling: 1. How does dynamic simultaneous multi-threading scheduling improve processor performance? 2. What are the key differences between static and dynamic scheduling algorithms in hybrid processor platforms?

Original Abstract Submitted

techniques for implementing dynamic simultaneous multi-threading (smt) scheduling on a hybrid processor platforms are described. in certain examples, a hardware processor includes a first plurality of physical processor cores of a first type to implement a plurality of logical processor cores of the first type; a second plurality of physical processor cores of a second type, wherein each core of the second type is to implement a plurality of logical processor cores of the second type; and circuitry to: determine if a set of threads of a foreground application is to use more than a lower threshold (e.g., a threshold number (e.g., one) of logical processor cores) and less than or equal to an upper threshold (e.g., a total number of the first plurality of physical processor cores of the first type and the second plurality of physical processor cores of the second type), and disable a second logical core of a physical processor core of the second type, and not disable a first logical core of the physical processor core of the second type, in response to a determination that the set of threads of the foreground application is to use more than the lower threshold number of logical processor cores and less than or equal to the upper threshold (e.g., the total number of the first plurality of physical processor cores of the first type and the second plurality of physical processor cores of the second type).