Intel corporation (20240213989). System and method for testing a phase noise or jitter of a phase-locked loop simplified abstract
Contents
System and method for testing a phase noise or jitter of a phase-locked loop
Organization Name
Inventor(s)
Marc Jan Georges Tiebout of Finkenstein (AT)
Edwin Thaller of Faak am See (AT)
Kameran Azadet of San Ramon CA (US)
System and method for testing a phase noise or jitter of a phase-locked loop - A simplified explanation of the abstract
This abstract first appeared for US patent application 20240213989 titled 'System and method for testing a phase noise or jitter of a phase-locked loop
The patent application describes a system and method for testing or determining the phase noise and/or jitter of a phase-locked loop (PLL).
- The system includes a first PLL that generates a clock signal based on a reference clock signal.
- A mixer mixes the first clock signal with a second clock signal.
- An analog-to-digital converter (ADC) converts the output of the mixer to digital data.
- A processing circuit processes the digital data to determine the phase noise or jitter of the first PLL and generates an output indicating the phase noise or jitter.
- The system may also include a second PLL that generates the second clock signal based on the reference clock signal.
Potential Applications: - Testing and measuring phase noise and jitter in phase-locked loops. - Quality control in PLL manufacturing processes. - Research and development in telecommunications and signal processing.
Problems Solved: - Accurately measuring and analyzing phase noise and jitter in PLLs. - Improving the performance and stability of PLLs. - Enhancing the overall reliability of clock signal generation systems.
Benefits: - Increased precision in phase noise and jitter analysis. - Enhanced functionality and efficiency of PLLs. - Facilitates the optimization of clock signal generation processes.
Commercial Applications: Title: "Advanced Phase Noise and Jitter Analysis System for PLLs" This technology can be utilized in industries such as telecommunications, aerospace, defense, and semiconductor manufacturing for improving the performance and reliability of clock signal generation systems.
Questions about the technology: 1. How does the system differentiate between phase noise and jitter in the PLL? 2. What are the key parameters that the processing circuit analyzes to determine the phase noise and jitter levels accurately?
Original Abstract Submitted
a system and method for testing or determining a phase noise and/or jitter of a phase locked loop (pll). the system includes a first pll configured to generate a first clock signal based on a reference clock signal, a first buffer for providing the reference clock signal to the first pll, a mixer configured to mix the first clock signal with a second clock signal, an analog-to-digital converter (adc) configured to convert an output of the mixer to digital data, and a processing circuit configured to process the digital data to determine a phase noise or jitter of the first pll and generate an output indicative of the phase noise or jitter of the first pll. the system may include a second pll configured to generate the second clock signal based on the reference clock signal, and a second buffer for providing the reference clock signal to the second pll.
