Intel corporation (20240211332). TECHNIQUES TO SUSTAIN ERROR INFORMATION FOR CRASH DATA ERROR HARVESTING simplified abstract

TECHNIQUES TO SUSTAIN ERROR INFORMATION FOR CRASH DATA ERROR HARVESTING

Organization Name

intel corporation

Inventor(s)

Divya Gupta of Hillsboro OR (US)

Shubhada Pugaonkar of Portland OR (US)

Raed Al-omari of Round Rock TX (US)

Mariecel Torres-young of Portland OR (US)

Ayman G. Abdo of Lake Oswego OR (US)

John R. Ayers of Portland OR (US)

Chih-Cheh Chen of Portland OR (US)

Wilfredo Figueroa Martinez of Hillsboro OR (US)

Girish Chandrasekaran of Hillsboro OR (US)

TECHNIQUES TO SUSTAIN ERROR INFORMATION FOR CRASH DATA ERROR HARVESTING - A simplified explanation of the abstract

This abstract first appeared for US patent application 20240211332 titled 'TECHNIQUES TO SUSTAIN ERROR INFORMATION FOR CRASH DATA ERROR HARVESTING

Simplified Explanation: The patent application describes techniques for collecting and providing error-related information for a multi-die system-on-a-chip (SoC) computing system following a critical or catastrophic error.

Key Features and Innovation:

• Circuitry on a first die receives an indication of a critical or catastrophic error and stores error-related information to a volatile memory at the first die.
• The volatile memory is arranged to continually maintain power during a global reset of the SoC.
• The circuitry can provide the stored error-related information to a requestor following the global reset of the SoC.

Potential Applications: This technology can be applied in various industries where critical errors in computing systems need to be quickly identified and addressed.

Problems Solved: The technology addresses the need for efficient collection and provision of error-related information in multi-die SoC computing systems following critical errors.

Benefits:

• Quick identification and resolution of critical errors in computing systems.
• Enhanced reliability and performance of multi-die SoC systems.
• Improved maintenance and troubleshooting processes.

Commercial Applications: Potential commercial applications include data centers, telecommunications, automotive systems, and industrial automation where reliable computing systems are crucial.

Prior Art: Prior art related to this technology may include patents or research papers on error handling mechanisms in computing systems.

Frequently Updated Research: Stay updated on advancements in error handling mechanisms in multi-die SoC computing systems to enhance the efficiency and reliability of the technology.

Questions about Multi-Die SoC Computing Systems: 1. How does the technology ensure the stored error-related information is securely provided to the requestor? 2. What are the potential challenges in implementing this technology in large-scale computing systems?

Original Abstract Submitted

examples include techniques to collecting and providing error related information for a multi-die system-on-a-chip (soc) computing system following a critical or catastrophic error. examples include circuitry on a first die that is configured to receive an indication of a critical or catastrophic error and cause error related information to be stored to a volatile memory at the first die that is arranged to continually maintain power during a global reset of the soc. the circuitry can also be configured to provide the stored error related information to a requestor following the global reset of the soc.