Intel corporation (20240194608). LOW Z-HEIGHT, GLASS-REINFORCED PACKAGE WITH EMBEDDED BRIDGE simplified abstract
Contents
LOW Z-HEIGHT, GLASS-REINFORCED PACKAGE WITH EMBEDDED BRIDGE
Organization Name
Inventor(s)
Rahul Manepalli of Chandler AZ (US)
Srinivas Pietambaram of Chandler AZ (US)
Brandon Marin of Gilbert AZ (US)
Suddhasattwa Nad of Chandler AZ (US)
Jeremy Ecton of Gilbert AZ (US)
LOW Z-HEIGHT, GLASS-REINFORCED PACKAGE WITH EMBEDDED BRIDGE - A simplified explanation of the abstract
This abstract first appeared for US patent application 20240194608 titled 'LOW Z-HEIGHT, GLASS-REINFORCED PACKAGE WITH EMBEDDED BRIDGE
Simplified Explanation:
The patent application describes an integrated circuit (IC) package that includes multiple IC dies with different metallization features separated by a glass layer. Through vias connect the metallization features of the different dies, while package metallization within a dielectric material is coupled to the IC dies and terminates at package interconnect interfaces.
- The IC package includes multiple IC dies with different metallization features.
- A glass layer separates the IC dies, with through vias connecting the metallization features.
- Package metallization within a dielectric material is coupled to the IC dies and terminates at package interconnect interfaces.
Potential Applications: The technology can be applied in various electronic devices requiring multiple IC dies to be integrated within a single package, such as smartphones, tablets, and computers.
Problems Solved: The technology addresses the challenge of integrating multiple IC dies with different metallization features in a compact and efficient manner.
Benefits: - Improved integration of multiple IC dies within a single package. - Enhanced connectivity between different metallization features. - Compact design for electronic devices.
Commercial Applications: The technology can be utilized in the semiconductor industry for manufacturing advanced electronic devices with improved performance and compact designs.
Prior Art: Researchers can explore prior patents related to integrated circuit packaging, glass layer integration, and through via technology to understand the evolution of this innovation.
Frequently Updated Research: Researchers are continuously exploring advancements in integrated circuit packaging, materials science, and semiconductor technology to enhance the performance and efficiency of electronic devices.
Questions about Integrated Circuit Package Technology: 1. What are the key challenges in integrating multiple IC dies with different metallization features? 2. How does the use of through vias improve connectivity between the metallization features of different IC dies?
Original Abstract Submitted
an integrated circuit (ic) package comprises a first ic die having first metallization features, a second ic die having second metallization features, and a third ic die having third metallization features. a glass layer is between the third ic die and both of the first ic die and the second ic die. a plurality of first through vias extend through the glass layer, coupling the third metallization features with first ones of the first metallization features and with first ones of the second metallization features. a plurality of second through vias extend through the glass layer. a dielectric material is around the third die and a package metallization is within the dielectric material. the package metallization is coupled to at least one of the first, second, or third ic die, and terminating at a plurality of package interconnect interfaces.
