Intel corporation (20240193109). APPARATUS AND METHOD TO REDUCE MEMORY POWER CONSUMPTION IN A MEMORY PHY IN A MEMORY CONTROLLER simplified abstract

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APPARATUS AND METHOD TO REDUCE MEMORY POWER CONSUMPTION IN A MEMORY PHY IN A MEMORY CONTROLLER

Organization Name

intel corporation

Inventor(s)

Michelle M. Wigton of Timnath CO (US)

Kambiz R. Munshi of Westford MA (US)

Zhongyao Linda Gu of Acton MA (US)

Mohammad M. Rashid of San Jose CA (US)

Victor Lau of Marlborough MA (US)

Jing Ling of Milpitas CA (US)

APPARATUS AND METHOD TO REDUCE MEMORY POWER CONSUMPTION IN A MEMORY PHY IN A MEMORY CONTROLLER - A simplified explanation of the abstract

This abstract first appeared for US patent application 20240193109 titled 'APPARATUS AND METHOD TO REDUCE MEMORY POWER CONSUMPTION IN A MEMORY PHY IN A MEMORY CONTROLLER

Simplified Explanation

Memory power consumption is reduced without increasing latency of memory read access by disabling certain circuits when inactive. The memory controller sends signals to the PHY to transition the memory from a low power state to an active power state.

  • Reduces power consumption without latency increase
  • Disables receiver bias circuitry and clock network in PHY when inactive
  • Memory controller sends command-based signals to enable PHY circuits
  • First signal sent before any command, second signal sent synchronous with read command

Key Features and Innovation

  • Reduction of memory power consumption without latency increase
  • Disabling receiver bias circuitry and clock network in PHY when inactive
  • Command-based signals from memory controller to enable PHY circuits

Potential Applications

This technology can be applied in various electronic devices that use memory modules, such as smartphones, tablets, laptops, and servers.

Problems Solved

  • Reduced power consumption in memory modules
  • Efficient management of power states in memory devices

Benefits

  • Extended battery life in portable devices
  • Improved energy efficiency in electronic devices
  • Enhanced overall performance of memory modules

Commercial Applications

  • "Reduced Power Consumption Memory Technology for Electronic Devices"
  • Potential commercial uses in consumer electronics, data centers, and IoT devices
  • Market implications include increased demand for energy-efficient memory solutions

Prior Art

There may be prior art related to power management techniques in memory devices, PHY circuits, and memory controllers. Researchers can explore patents, academic papers, and industry publications for more information.

Frequently Updated Research

Researchers are constantly exploring new ways to improve power efficiency in memory devices and enhance the performance of memory controllers and PHY circuits.

Questions about Memory Power Consumption Technology

How does this technology impact the overall performance of electronic devices?

This technology improves energy efficiency and extends battery life in electronic devices, leading to enhanced overall performance.

What are the potential challenges in implementing this technology in memory modules?

Implementing this technology may require coordination between memory controllers and PHY circuits, as well as ensuring compatibility with existing memory architectures.


Original Abstract Submitted

memory power consumption is reduced without increasing latency of memory read access. when inactive, power consumption is reduced in a phy in a memory controller by disabling receiver bias circuitry and a clock network in the phy. the memory controller sends two command-based signals to the phy to enable the phy to enable the receiver bias circuitry and the clock network in the phy to transition the memory from a low power state to an active power state prior to or at the time of receiving command from the memory controller. a first command-based signal is an early command indication signal that is sent before any command. the second command-based signal is a read indication signal that is sent synchronous with every read command. upon receiving these signals, the phy enables the clock network and receiver bias circuitry.

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