Intel corporation (20240188212). PACKAGE SUBSTRATE ARCHITECTURES WITH IMPROVED COOLING simplified abstract
Contents
- 1 PACKAGE SUBSTRATE ARCHITECTURES WITH IMPROVED COOLING
- 1.1 Organization Name
- 1.2 Inventor(s)
- 1.3 PACKAGE SUBSTRATE ARCHITECTURES WITH IMPROVED COOLING - A simplified explanation of the abstract
- 1.4 Simplified Explanation
- 1.5 Potential Applications
- 1.6 Problems Solved
- 1.7 Benefits
- 1.8 Potential Commercial Applications
- 1.9 Possible Prior Art
- 1.10 Original Abstract Submitted
PACKAGE SUBSTRATE ARCHITECTURES WITH IMPROVED COOLING
Organization Name
Inventor(s)
Mohammad Mamunur Rahman of Gilbert AZ (US)
Brandon Christian Marin of Gilbert AZ (US)
Srinivas V. Pietambaram of Chandler AZ (US)
Suddhasattwa Nad of Chandler AZ (US)
Rahul Manepalli of Chandler AZ (US)
PACKAGE SUBSTRATE ARCHITECTURES WITH IMPROVED COOLING - A simplified explanation of the abstract
This abstract first appeared for US patent application 20240188212 titled 'PACKAGE SUBSTRATE ARCHITECTURES WITH IMPROVED COOLING
Simplified Explanation
The integrated circuit package substrate described in the abstract includes a core layer and multiple build-up layers, each consisting of a dielectric and metal. The substrate also features a cavity that spans across different build-up layers.
- The integrated circuit package substrate comprises a core layer and multiple build-up layers.
- Each build-up layer is made up of a dielectric and metal.
- The substrate includes a cavity that extends through different build-up layers.
Potential Applications
The technology described in this patent application could be applied in the manufacturing of advanced integrated circuit packages, such as microprocessors, memory modules, and other electronic devices that require high-density packaging solutions.
Problems Solved
This technology solves the problem of efficiently integrating cavities within integrated circuit package substrates, allowing for more compact and complex designs without sacrificing performance or reliability.
Benefits
The benefits of this technology include increased packaging density, improved signal integrity, enhanced thermal management, and overall cost-effectiveness in the production of integrated circuit packages.
Potential Commercial Applications
The technology has potential commercial applications in the semiconductor industry, particularly in the development of high-performance computing devices, telecommunications equipment, and consumer electronics.
Possible Prior Art
One possible prior art in this field is the use of through-silicon vias (TSVs) in integrated circuit packaging to enable vertical interconnects between different layers of the substrate. However, the specific configuration of a cavity spanning multiple build-up layers as described in this patent application may be a novel approach.
=== What materials are used in each build-up layer of the integrated circuit package substrate? The build-up layers consist of a dielectric material and metal.
=== How does the cavity connect different portions of the integrated circuit package substrate? The cavity connects different portions of the substrate through at least one layer other than the first and second build-up layers.
Original Abstract Submitted
in one embodiment, an integrated circuit package substrate includes a core layer and a plurality of build-up layers on the core layer, each build-up layer comprising a dielectric and metal. the package substrate also includes a cavity, wherein a first portion of the cavity is defined in a first build-up layer, a second portion of the cavity is defined in a second build-up layer, and a third portion of the cavity connects the first portion with the second portion through at least one layer other than first build-up layer and the second build-up layer.
