Intel corporation (20240187012). ANALOG-TO-DIGITAL CONVERTER SYSTEM, RECEIVER, BASE STATION, MOBILE DEVICE AND METHOD FOR ANALOG-TO-DIGITAL CONVERSION simplified abstract
Contents
- 1 ANALOG-TO-DIGITAL CONVERTER SYSTEM, RECEIVER, BASE STATION, MOBILE DEVICE AND METHOD FOR ANALOG-TO-DIGITAL CONVERSION
- 1.1 Organization Name
- 1.2 Inventor(s)
- 1.3 ANALOG-TO-DIGITAL CONVERTER SYSTEM, RECEIVER, BASE STATION, MOBILE DEVICE AND METHOD FOR ANALOG-TO-DIGITAL CONVERSION - A simplified explanation of the abstract
- 1.4 Simplified Explanation
- 1.5 Potential Applications
- 1.6 Problems Solved
- 1.7 Benefits
- 1.8 Potential Commercial Applications
- 1.9 Possible Prior Art
- 1.10 Original Abstract Submitted
ANALOG-TO-DIGITAL CONVERTER SYSTEM, RECEIVER, BASE STATION, MOBILE DEVICE AND METHOD FOR ANALOG-TO-DIGITAL CONVERSION
Organization Name
Inventor(s)
Matteo Camponeschi of Villach (AT)
Kannan Rajamani of Basking Ridge NJ (US)
Martin Clara of Santa Clara CA (US)
ANALOG-TO-DIGITAL CONVERTER SYSTEM, RECEIVER, BASE STATION, MOBILE DEVICE AND METHOD FOR ANALOG-TO-DIGITAL CONVERSION - A simplified explanation of the abstract
This abstract first appeared for US patent application 20240187012 titled 'ANALOG-TO-DIGITAL CONVERTER SYSTEM, RECEIVER, BASE STATION, MOBILE DEVICE AND METHOD FOR ANALOG-TO-DIGITAL CONVERSION
Simplified Explanation
The abstract describes a patent application for an analog-to-digital converter (ADC) system that includes a first signal path with a time-interleaved ADC, a correction circuit, a second signal path with a second ADC and a combiner circuit, and an equalizer to generate an equalized output signal.
- The ADC system includes a first signal path with a time-interleaved ADC consisting of multiple sub-ADCs.
- Circuitry in the first signal path outputs activity data indicating which sub-ADC is active.
- A correction circuit generates digital correction data based on the activity data.
- A second signal path runs in parallel to the first, with a second ADC and a combiner circuit that modifies the second digital data using the correction data.
- An equalizer adjusts equalization parameters based on the modified second digital data to generate an equalized output signal.
Potential Applications
The technology described in this patent application could be applied in various fields such as telecommunications, medical imaging, and instrumentation where high-speed and accurate analog-to-digital conversion is required.
Problems Solved
This technology solves the problem of inaccuracies and errors in analog-to-digital conversion by using a correction circuit to adjust the output data based on the activity of the sub-ADCs in a time-interleaved ADC system.
Benefits
The benefits of this technology include improved accuracy and precision in analog-to-digital conversion, increased speed of data processing, and enhanced performance in high-frequency signal processing applications.
Potential Commercial Applications
- High-speed data acquisition systems
- Wireless communication devices
- Radar and sonar systems
Possible Prior Art
One possible prior art for this technology could be the use of time-interleaved ADCs in high-speed data acquisition systems or communication devices.
What are the limitations of this technology in terms of scalability and integration with other systems?
The scalability of this technology may be limited by the complexity of the time-interleaved ADC system and the need for precise synchronization between the sub-ADCs. Integration with other systems may also pose challenges due to the specific equalization parameters required for optimal performance.
How does this technology compare to existing ADC systems in terms of speed and accuracy?
This technology offers improved speed and accuracy compared to traditional ADC systems by utilizing a time-interleaved ADC with multiple sub-ADCs and a correction circuit to enhance the output data quality.
Original Abstract Submitted
an analog-to-digital converter (adc) system is provided. the adc system includes a first signal path. the first signal path includes a first adc configured to generate first digital data based on an input signal. the first adc is a time-interleaved adc including a plurality of sub-adcs. the first signal path further includes circuitry configured to output activity data indicating at least which of the plurality of sub-adcs is currently active. the adc system further includes a correction circuit configured to output digital correction data based on the activity data. further, the adc system includes a second signal path coupled in parallel to the first signal path. the second signal path includes a second adc configured to generate second digital data based on the input signal and a combiner circuit configured to generate modified second digital data by combining the second digital data and the correction data. the adc system further includes an equalizer configured to generate an equalized output signal of the adc system based on the first digital data. the equalizer is configured to adjust, based on the modified second digital data, at least one equalization parameter used for generating the equalized output signal of the adc system.
