Intel corporation (20240186403). DUAL METAL GATE STRUCTURES FOR ADVANCED INTEGRATED CIRCUIT STRUCTURE FABRICATION simplified abstract

DUAL METAL GATE STRUCTURES FOR ADVANCED INTEGRATED CIRCUIT STRUCTURE FABRICATION

Organization Name

intel corporation

Inventor(s)

Jeffrey S. Leib of Beaverton OR (US)

Jenny Hu of Santa Clara CA (US)

Anindya Dasgupta of Portland OR (US)

Michael L. Hattendorf of Portland OR (US)

Christopher P. Auth of Portland OR (US)

DUAL METAL GATE STRUCTURES FOR ADVANCED INTEGRATED CIRCUIT STRUCTURE FABRICATION - A simplified explanation of the abstract

This abstract first appeared for US patent application 20240186403 titled 'DUAL METAL GATE STRUCTURES FOR ADVANCED INTEGRATED CIRCUIT STRUCTURE FABRICATION

Simplified Explanation

The patent application is related to advanced integrated circuit structure fabrication, specifically focusing on the 10 nanometer node and smaller integrated circuit structures. The structure described includes a semiconductor substrate with a semiconductor fin protruding from an n well region, surrounded by a trench isolation layer. A gate dielectric layer and a conductive layer containing titanium, nitrogen, and oxygen are present over the semiconductor fin, with a p-type metal gate layer on top.

• Semiconductor substrate with semiconductor fin protruding from n well region
• Trench isolation layer surrounding the semiconductor fin
• Gate dielectric layer over the semiconductor fin
• Conductive layer with titanium, nitrogen, and oxygen over the gate dielectric layer
• P-type metal gate layer over the conductive layer

Potential Applications

The technology described in this patent application could be applied in the manufacturing of advanced integrated circuits for various electronic devices, such as smartphones, computers, and IoT devices.

Problems Solved

This technology addresses the challenges of fabricating smaller integrated circuit structures with improved performance and efficiency, meeting the demands of modern electronic devices.

Benefits

The benefits of this technology include enhanced functionality, increased speed, reduced power consumption, and overall improved performance of integrated circuits.

Potential Commercial Applications

The technology has potential commercial applications in the semiconductor industry for the production of high-performance integrated circuits for consumer electronics, automotive systems, and other technological applications.

Possible Prior Art

One possible prior art in this field is the use of different materials and techniques for fabricating integrated circuit structures, such as alternative gate dielectric materials or metal gate layers.

What are the limitations of this technology in terms of scalability and mass production?

One limitation of this technology could be the complexity of the fabrication process and the cost associated with implementing it on a large scale. Additionally, the compatibility of the materials used with existing manufacturing processes may need to be considered for mass production.

How does this technology compare to similar patents or innovations in the field of integrated circuit structure fabrication?

This technology appears to offer improvements in terms of performance, efficiency, and scalability compared to similar patents or innovations in the field. The use of specific materials and layers in the structure could provide unique advantages in integrated circuit fabrication.

Original Abstract Submitted

embodiments of the disclosure are in the field of advanced integrated circuit structure fabrication and, in particular, 10 nanometer node and smaller integrated circuit structure fabrication and the resulting structures. in an example, an integrated circuit structure includes a semiconductor substrate comprising an n well region having a semiconductor fin protruding therefrom. a trench isolation layer is on the semiconductor substrate around the semiconductor fin, wherein the semiconductor fin extends above the trench isolation layer. a gate dielectric layer is over the semiconductor fin. a conductive layer is over the gate dielectric layer over the semiconductor fin, the conductive layer comprising titanium, nitrogen and oxygen. a p-type metal gate layer is over the conductive layer over the semiconductor fin.