Intel corporation (20240186228). INTEGRATED CIRCUIT PACKAGE ARCHITECTURES WITH CORE AND/OR BUILD-UP LAYERS COMPRISING SPIN-ON GLASS (SOG) simplified abstract

INTEGRATED CIRCUIT PACKAGE ARCHITECTURES WITH CORE AND/OR BUILD-UP LAYERS COMPRISING SPIN-ON GLASS (SOG)

Organization Name

intel corporation

Inventor(s)

Haobo Chen of Chandler AZ (US)

Bohan Shan of Chandler AZ (US)

Kyle J. Arrington of Gilbert AZ (US)

Yiqun Bai of Chandler AZ (US)

Kristof Darmawikarta of Chandler AZ (US)

Gang Duan of Chandler AZ (US)

Jeremy D. Ecton of Gilbert AZ (US)

Hongxia Feng of Chandler AZ (US)

Xiaoying Guo of Chandler AZ (US)

Ziyin Lin of Chandler AZ (US)

Brandon Christian Marin of Gilbert AZ (US)

Bai Nie of Chandler AZ (US)

Srinivas V. Pietambaram of Chandler AZ (US)

Dingying Xu of Chandler AZ (US)

INTEGRATED CIRCUIT PACKAGE ARCHITECTURES WITH CORE AND/OR BUILD-UP LAYERS COMPRISING SPIN-ON GLASS (SOG) - A simplified explanation of the abstract

This abstract first appeared for US patent application 20240186228 titled 'INTEGRATED CIRCUIT PACKAGE ARCHITECTURES WITH CORE AND/OR BUILD-UP LAYERS COMPRISING SPIN-ON GLASS (SOG)

Simplified Explanation

The integrated circuit package substrate described in the abstract includes a core layer with metal vias, a dielectric material with silicon, oxygen, and boron or phosphorus, and build-up layers with metal vias connected to the core layer.

• The core layer of the substrate contains metal vias that electrically connect two opposite sides.
• The dielectric material in the core layer consists of silicon, oxygen, and either boron or phosphorus.
• The build-up layers on top of the core layer also contain metal vias that are electrically connected to the core layer's metal vias.

Potential Applications

The technology described in this patent application could be used in the manufacturing of advanced integrated circuit packages for various electronic devices, such as smartphones, computers, and IoT devices.

Problems Solved

This technology solves the problem of efficiently connecting different layers within an integrated circuit package substrate, improving the overall performance and reliability of the electronic device.

Benefits

The benefits of this technology include enhanced electrical connectivity, improved signal transmission, and increased overall functionality of the integrated circuit package substrate.

Potential Commercial Applications

One potential commercial application of this technology is in the semiconductor industry for the production of high-performance integrated circuit packages. Another application could be in the development of advanced electronic devices with increased processing power and efficiency.

Possible Prior Art

One possible prior art for this technology could be the use of metal vias in integrated circuit packages to improve electrical connectivity and signal transmission. Additionally, the integration of different materials in the dielectric layer may have been explored in previous patents or research studies.

== What are the manufacturing processes involved in producing this integrated circuit package substrate? The manufacturing processes involved in producing this integrated circuit package substrate may include deposition of the dielectric material, formation of metal vias, stacking and bonding of the core layer and build-up layers, and testing for electrical connectivity and reliability.

== How does the composition of the dielectric material impact the performance of the integrated circuit package substrate? The composition of the dielectric material, specifically the presence of silicon, oxygen, and boron or phosphorus, can affect the electrical properties, thermal conductivity, and overall reliability of the integrated circuit package substrate. Further research and testing may be needed to fully understand the impact of the dielectric material composition on performance.

Original Abstract Submitted

in one embodiment, an integrated circuit package substrate includes a core layer comprising a dielectric material and a plurality of metal vias within the core layer. the dielectric material includes silicon, oxygen, and at least one of boron or phosphorus. the metal vias electrically couple a first side of the core layer and a second side of the core layer opposite the first side. the package substrate further includes a plurality of build-up layers on the core layer, the build-up layers comprising metal vias electrically connected to the metal vias of the core layer.