Intel corporation (20240186227). INTEGRATED CIRCUIT PACKAGE ARCHITECTURES WITH CORE AND/OR BUILD-UP LAYERS COMPRISING SPIN-ON GLASS (SOG) simplified abstract

INTEGRATED CIRCUIT PACKAGE ARCHITECTURES WITH CORE AND/OR BUILD-UP LAYERS COMPRISING SPIN-ON GLASS (SOG)

Organization Name

intel corporation

Inventor(s)

Haobo Chen of Chandler AZ (US)

Bohan Shan of Chandler AZ (US)

Kyle J. Arrington of Gilbert AZ (US)

Kristof Darmawikarta of Chandler AZ (US)

Gang Duan of Chandler AZ (US)

Jeremy D. Ecton of Gilbert AZ (US)

Hongxia Feng of Chandler AZ (US)

Xiaoying Guo of Chandler AZ (US)

Ziyin Lin of Chandler AZ (US)

Brandon Christian Marin of Gilbert AZ (US)

Srinivas V. Pietambaram of Chandler AZ (US)

Dingying Xu of Chandler AZ (US)

INTEGRATED CIRCUIT PACKAGE ARCHITECTURES WITH CORE AND/OR BUILD-UP LAYERS COMPRISING SPIN-ON GLASS (SOG) - A simplified explanation of the abstract

This abstract first appeared for US patent application 20240186227 titled 'INTEGRATED CIRCUIT PACKAGE ARCHITECTURES WITH CORE AND/OR BUILD-UP LAYERS COMPRISING SPIN-ON GLASS (SOG)

Simplified Explanation

The integrated circuit package substrate described in the abstract includes a core layer with metal vias electrically coupling two sides of the layer, and a build-up layer on one side of the core layer with metal vias within a dielectric material connected to the core layer vias.

• Core layer with metal vias electrically coupling two sides
• Build-up layer on one side with metal vias in dielectric material
• Dielectric material includes silicon, oxygen, boron, or phosphorus

Potential Applications

The technology described in this patent application could be used in various electronic devices and systems requiring high-density interconnections, such as smartphones, tablets, computers, and other consumer electronics.

Problems Solved

This technology solves the problem of achieving reliable and efficient electrical connections in integrated circuit packages with complex layouts and high interconnect densities.

Benefits

The benefits of this technology include improved electrical performance, increased reliability, and enhanced signal integrity in electronic devices and systems.

Potential Commercial Applications

The technology could be commercialized by semiconductor companies, electronics manufacturers, and suppliers of integrated circuit packaging solutions for a wide range of consumer and industrial applications.

Possible Prior Art

One possible prior art for this technology could be the use of similar dielectric materials in integrated circuit packaging, but with different configurations or materials compositions.

What are the environmental implications of using this technology?

The environmental implications of using this technology are not addressed in the provided information. However, it would be important to consider the materials used in the substrate and their impact on the environment during manufacturing and disposal.

How does this technology compare to existing solutions in terms of cost-effectiveness?

The cost-effectiveness of this technology compared to existing solutions is not discussed in the abstract. Further analysis would be needed to determine the cost implications of implementing this integrated circuit package substrate compared to other available options.

Original Abstract Submitted

in one embodiment, an integrated circuit package substrate includes a core layer comprising a plurality of metal vias electrically coupling a first side of the core layer and a second side of the core layer opposite the first side. the package substrate further includes a build-up layer on the first side of the core layer, the build-up layer comprising metal vias within a dielectric material and electrically connected to the metal vias of the core layer. the dielectric material includes silicon, oxygen, and at least one of boron or phosphorus.