Intel corporation (20240176941). PRINTED CIRCUIT BOARD PIN FIELD SIGNAL ROUTING simplified abstract

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PRINTED CIRCUIT BOARD PIN FIELD SIGNAL ROUTING

Organization Name

intel corporation

Inventor(s)

Xiaoning Ye of Portland OR (US)

Jorge A. Alvarez of Zapopan (MX)

Jose de Jesus Jauregui Ruelas of Guadalajara (MX)

Vijaya K. Kunda of Portland OR (US)

Hong-Yi Luoh of Portland OR (US)

Yanwu Wang of Suzhou (CN)

Chunfei Ye of Lacey WA (US)

PRINTED CIRCUIT BOARD PIN FIELD SIGNAL ROUTING - A simplified explanation of the abstract

This abstract first appeared for US patent application 20240176941 titled 'PRINTED CIRCUIT BOARD PIN FIELD SIGNAL ROUTING

Simplified Explanation

Signal lines in a printed circuit board layout are modified to reduce line impedance and improve signal integrity by extending the widths of the signal lines in the pin field.

  • Signal lines are extended in the pin field to make use of available routing space between pads and adjacent signal lines.
  • The signal line extension is a subtractive approach, where extensions causing design rule violations are subtracted out.
  • The edge of a signal line is extended to keep-out regions associated with pads in the pin field.

Potential Applications

This technology can be applied in various electronic devices and systems where signal integrity is crucial, such as high-speed data transmission systems, telecommunications equipment, and computer hardware.

Problems Solved

1. Reduced line impedance leading to improved signal integrity. 2. Optimization of routing space in the pin field for better signal performance.

Benefits

1. Enhanced signal quality and reduced signal interference. 2. Increased reliability and performance of electronic devices. 3. Efficient use of available routing space for signal lines.

Potential Commercial Applications

Optimizing signal lines in printed circuit board layouts can benefit companies involved in the design and manufacturing of electronic devices, telecommunications equipment, and computer hardware. This technology can help improve the performance and reliability of their products, leading to a competitive edge in the market.

Possible Prior Art

One possible prior art could be the use of differential signaling techniques to improve signal integrity in printed circuit board layouts. Another could be the use of impedance matching techniques to reduce signal interference in electronic devices.

Unanswered Questions

How does this technology compare to existing methods of signal line optimization in printed circuit board layouts?

This article does not provide a direct comparison with existing methods of signal line optimization in printed circuit board layouts. It would be beneficial to understand the advantages and disadvantages of this technology compared to other approaches currently used in the industry.

What are the potential challenges or limitations of implementing this technology in practical applications?

The article does not address the potential challenges or limitations of implementing this technology in practical applications. It would be important to consider factors such as cost, complexity, and compatibility with existing design processes when introducing this innovation in real-world scenarios.


Original Abstract Submitted

signal lines in the pin field of a printed circuit board layout are modified to reduce line impedance and improve signal integrity. the widths of signal lines are extended in the pin field to take full advantage of the available routing space between pads and adjacent signal lines. the signal line extension can be considered a subtractive approach in that the signal lines are extended to occupy the available muting space, with signal line extensions that would otherwise cause design rule violations being subtracted out. the edge of a signal line is extended to a keep-out region associated with a centerline that extends through a plurality of pads arranged in a line and located adjacent to the signal line. the edge of the signal line is also extended to keep-out regions associated with pads in the pin fields.