Intel corporation (20240129104). GENERIC SYNTHESIZABLE CIRCUIT COUNTERMEASURE AGAINST HARDWARE SCA simplified abstract

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GENERIC SYNTHESIZABLE CIRCUIT COUNTERMEASURE AGAINST HARDWARE SCA

Organization Name

intel corporation

Inventor(s)

Jason M. Fung of Portland OR (US)

Debayan Das of Hillsboro OR (US)

Sayak Ray of San Jose CA (US)

Rana Elnaggar of San Jose CA (US)

Majid Sabbagh of Santa Clara CA (US)

GENERIC SYNTHESIZABLE CIRCUIT COUNTERMEASURE AGAINST HARDWARE SCA - A simplified explanation of the abstract

This abstract first appeared for US patent application 20240129104 titled 'GENERIC SYNTHESIZABLE CIRCUIT COUNTERMEASURE AGAINST HARDWARE SCA

Simplified Explanation

The abstract describes an apparatus, system, and method for protecting a component from an observation attack, specifically a cryptography component, using a power balancing circuit with a ring oscillator, time-to-digital converter (TDC), and a controller circuit.

  • The power balancing circuit includes a ring oscillator connected to a power supply.
  • A TDC monitors an electrical parameter of the power drawn by the cryptography component and provides data indicative of the parameter.
  • The controller circuit adjusts the number of inverters of the ring oscillator drawing power from the supply based on the data.

Potential Applications

This technology could be applied in various industries where secure communication and data protection are critical, such as cybersecurity, financial services, and government agencies.

Problems Solved

This innovation addresses the issue of protecting a cryptography component from observation attacks, ensuring the security and integrity of sensitive information and data.

Benefits

- Enhanced security for cryptography components - Real-time monitoring of power consumption - Dynamic adjustment of power usage based on monitoring data

Potential Commercial Applications

"Enhancing Data Security in Financial Services with Power Balancing Circuit Technology"

Possible Prior Art

One possible prior art could be the use of power analysis attacks to extract cryptographic keys from devices by monitoring power consumption patterns. This technology aims to prevent such attacks by dynamically adjusting power usage.

Unanswered Questions

How does the power balancing circuit impact the overall performance of the cryptography component?

The article does not delve into the potential effects of the power balancing circuit on the performance metrics of the cryptography component. It would be interesting to explore whether there are any trade-offs in terms of speed or efficiency.

Are there any limitations or constraints in implementing this technology in different types of cryptography components?

The article does not discuss any potential limitations or constraints that may arise when implementing this technology in various types of cryptography components. It would be valuable to understand if there are specific requirements or adaptations needed for different systems.


Original Abstract Submitted

an apparatus, system, and method for protecting a component from an observation attack are provided. a power balancing circuit configured to protect a cryptography component can include a ring oscillator electrically connected to a power supply, a time-to-digital converter (tdc) electrically connected to monitor an electrical parameter of the electrical power drawn by the cryptography component and provide data indicative of the electrical parameter, and a controller circuit configured to adjust a number of inverters of the ring oscillator drawing power from the power supply based on the data.