Intel corporation (20240105584). BURIED VIA THROUGH FRONT-SIDE AND BACK-SIDE METALLIZATION LAYERS WITH OPTIONAL CYLINDRICAL MIM CAPACITOR simplified abstract

BURIED VIA THROUGH FRONT-SIDE AND BACK-SIDE METALLIZATION LAYERS WITH OPTIONAL CYLINDRICAL MIM CAPACITOR

Organization Name

intel corporation

Inventor(s)

Abhishek Anil Sharma of Portland OR (US)

Tahir Ghani of Portland OR (US)

Anand Murthy of Portland OR (US)

Wilfred Gomes of Portland OR (US)

Sagar Suthram of Portland OR (US)

Pushkar Ranade of San Jose CA (US)

BURIED VIA THROUGH FRONT-SIDE AND BACK-SIDE METALLIZATION LAYERS WITH OPTIONAL CYLINDRICAL MIM CAPACITOR - A simplified explanation of the abstract

This abstract first appeared for US patent application 20240105584 titled 'BURIED VIA THROUGH FRONT-SIDE AND BACK-SIDE METALLIZATION LAYERS WITH OPTIONAL CYLINDRICAL MIM CAPACITOR

Simplified Explanation

The abstract describes an integrated circuit (IC) die with multiple front-side and back-side metallization layers, as well as a vertical metallization structure connecting these layers.

• The IC die includes a first front-side metallization layer and one or more additional front-side metallization layers.
• It also has a first back-side metallization layer and one or more additional back-side metallization layers.
• The first front-side metallization layer is close to the first back-side metallization layer.
• A vertical metallization structure is formed through at least the first front-side and back-side metallization layers, connecting structures on different layers.

Potential Applications

This technology could be used in various electronic devices, such as smartphones, tablets, and computers, to improve performance and connectivity.

Problems Solved

This innovation solves the problem of efficiently connecting different metallization layers in an IC die, allowing for more complex and compact designs.

Benefits

The benefits of this technology include increased functionality, improved signal transmission, and potentially reduced manufacturing costs.

Potential Commercial Applications

This technology could be valuable in the semiconductor industry for producing advanced ICs with enhanced performance and reliability.

Possible Prior Art

One possible prior art could be the use of through-silicon vias (TSVs) in semiconductor devices to vertically connect different layers, although this technology may offer unique advantages.

How does this technology impact power consumption in electronic devices?

This article does not address the potential effects of this technology on power efficiency in electronic devices.

What are the environmental implications of using this technology in manufacturing processes?

The environmental impact of implementing this technology in semiconductor manufacturing is not discussed in this article.

Original Abstract Submitted

an integrated circuit (ic) die includes a plurality of front-side metallization layers including a first front-side metallization layer and one or more additional front-side metallization layers, a plurality of back-side metallization layers formed on the plurality front side metallization layers including a first back-side metallization layer and one or more additional back-side metallization layers, wherein the first front-side metallization layer is proximate to the first back-side metallization layer, and a vertical metallization structure formed through at least the first front-side metallization layer and the first back-side metallization layer, wherein the vertical metallization structure electrically connects a first metallization structure on one of the one or more additional front-side metallization layers to a second metallization structure on one of the one or more additional back-side metallization layers. other embodiments are disclosed and claimed.