Intel Corporation patent applications published on September 28th, 2023

Summary of the patent applications from Intel Corporation on September 28th, 2023

Intel Corporation has recently filed several patents related to various technologies and innovations. These patents cover a wide range of areas, including heat sink cooling efficiency, computer systems, electronic packages, communication devices, wireless stations, signal identification, augmented computing, secure wireless connections, WLAN stream classification, and wireless communication stations.

In terms of heat sink cooling efficiency, Intel has developed an apparatus that improves the flow of immersion bath liquid through the spaces between fins and across the base of a heat sink. This apparatus includes a flow enhancement structure that enhances the flow of the liquid, potentially improving the cooling efficiency of the heat sink.

For computer systems, Intel has designed a printed circuit board assembly (PCBA) with two surfaces, each housing a computer processor module. These modules are connected through an electrical path that goes through the thickness of the PCBA, enabling efficient communication between the processors.

In the field of electronic packages, Intel has developed a printed circuit board (PCB) made of a combination of glass weave, resin, and metal organic frameworks (MOFs) embedded in the resin. This innovative PCB is connected to a package substrate, and a die is connected to the package substrate, enabling efficient electronic packaging.

In the realm of communication devices, Intel has created a device that can establish a connection with peripheral devices when disconnected from an external communication device. It determines the connectability of the external device based on radio signals received from it and encodes a message to be sent to the peripheral devices, instructing them to perform high duty cycle advertising using Bluetooth communication protocol.

In the wireless station domain, Intel has developed processors that determine when data needs to be transferred and what type of data it is. If the data is of high priority, the processors send a signal indicating this and create a dedicated connection with a network device to transfer the data efficiently.

Intel has also developed a system that can determine and identify different communication signals by analyzing their characteristics, such as waveform. This system uses statistical and/or Cyclostationary Signal Processing algorithms to identify each signal as a communication signal with a specific protocol. It can also identify rogue devices that do not follow the expected protocol and take appropriate actions.

In the field of augmented computing, Intel has introduced the concept of compute control client (Comp CC) and compute control function (Comp CF) at the user equipment (UE) side, and compute service function (Comp SF) at the network side. These functions handle computing-related control and user traffic in 6G networks.

For establishing secure wireless connections, Intel has developed a process where devices determine a method for connection establishment based on exchanged messages. They then pair and create a secure key for communication, which is used to encrypt peer-to-peer communication between the devices.

In the domain of WLAN stream classification, Intel has developed apparatuses equipped with processing circuitry that can encode and decode stream classification service (SCS) request and response frames. These frames contain specific subfields indicating LinkID and SCSID, enabling efficient stream classification in a wireless local area network.

Lastly, Intel has developed an Enhanced Directional Multi-Gigabit (DMG) wireless communication station that can determine Orthogonal Frequency Division Multiplexing (OFDM) Training (TRN) sequences and generate OFDM TRN waveforms for transmission over a channel bandwidth, improving wireless communication efficiency.

Notable applications:

• Improved heat sink cooling efficiency through enhanced liquid flow.
• Efficient communication between computer processor modules through a printed circuit board assembly.
• Innovative electronic packaging with a combination of glass weave, resin, and metal organic frameworks.
• Connection establishment and communication enhancement for peripheral devices.
• Efficient data transfer and connection establishment in wireless stations.
• Signal identification and rogue device detection through waveform analysis.
• Augmented computing capabilities for 6G networks.
• Secure wireless connections through key generation and encryption.
• Stream classification in wireless local area networks.
• Enhanced wireless communication through improved training sequences and waveforms.

Patent applications for Intel Corporation on September 28th, 2023

AGITATION MONITORING SYSTEM FOR PLATING PROCESS (17702839)

Inventor Adrian BAYRAKTAROGLU

Brief explanation

The abstract describes a monitoring system designed for a plating process. The system includes a monitoring device that has a metrology component, which collects data on the intensity of agitation in a plating equipment. This data is then transferred to a process control station for further analysis and control of the plating process.

Abstract

The present disclosure is directed to a monitoring system for a plating process using a monitoring device including a metrology component for collecting agitation intensity data on at least one agitation component within a plating equipment and transferring the collected agitation intensity data to a process control station.

WAFER LEVEL ELECTRON BEAM PROBER (17701323)

Inventor Xianghong Tong

Brief explanation

The abstract describes wafer level electron beam prober systems, devices, and techniques used for testing fabricated device structures. These systems involve contacting one side of a die on a wafer with a probe to send test signals to the die. Simultaneously, electron beam imaging is performed on the same side of the die while the test signals are being provided.

Abstract

Wafer level electron beam prober systems, devices, and techniques, are described herein related to providing wafer level testing for fabricated device structures. Such wafer level testing contacts a first side of a die of a wafer with a probe to provide test signals to the die under test and performs e-beam imaging of the first side of the die while the test signals are provided to the die under test.

OPPORTUNISTIC BATTERY CHARGING WITH A PROGRAMMABLE POWER ADAPTER (17705012)

Inventor Udaya Natarajan

Brief explanation

The abstract describes techniques and mechanisms for charging a battery using a programmable power adapter. A charger circuit is connected between the power adapter and the battery, and bypass circuitry allows for bypassing the charger circuit when needed. A controller circuit determines the state of charge of the battery and selects a power delivery scheme, which includes the operational mode of the power adapter and the activation state of the switch circuit. The controller then configures the power delivery scheme by transitioning the power adapter to the operational mode. In one embodiment, the operational mode is based on communication compatible with the USB standard protocol.

Abstract

Techniques and mechanisms for opportunistically charging a battery with a programmable power adapter. In an embodiment, a charger circuit is to be coupled between the programmable power adapter and a load circuit which is coupled to the battery. Bypass circuitry is coupled to selectively enable a bypassing of the charger circuit. Based on a state of charge of the battery, a controller circuit identifies a power delivery scheme which includes both an operational mode of the programmable power adapter, and an activation state of the switch circuit. The controller configures the identified power delivery scheme by signaling that the programmable power adapter is to be transitioned to the operational mode. In another embodiment, the operational mode is based on communications which are compatible with a Universal Serial Bus (USB) standard protocol.

SAVING AND RESTORING CONFIGURATION AND STATUS INFORMATION WITH REDUCED LATENCY (17682032)

Inventor Deepak Rameshkumar Tanna

Brief explanation

The abstract describes an apparatus that includes several components. These components include a port circuit, a save restore memory, and a configuration network. The port circuit receives a configuration write from a source circuit and sends it to a first node of the configuration network and to the save restore memory. The save restore memory is used to store information about various control and status registers (CSRs). The configuration network is connected to multiple nodes, each of which has at least one CSR. The abstract also mentions that there are other embodiments of this apparatus that are described and claimed.

Abstract

In one embodiment, an apparatus includes: a port circuit to receive a configuration write from a source circuit; a save restore memory coupled to the port circuit to store information of a plurality of control and status registers (CSRs); and a configuration network coupled to the port circuit, the configuration network coupled to a plurality of nodes, each of the plurality of nodes comprising at least one CSR. The port circuit may be configured to send the configuration write to a first node of the plurality of nodes and to the save restore memory. Other embodiments are described and claimed.

FACILITATING IMPROVED USE OF STOCHASTIC ASSOCIATIVE MEMORY (18040145)

Inventor Dipanjan Sengupta

Brief explanation

This abstract describes a method for improving the use of a stochastic associative memory (SAM). The method involves generating a hash code for data to be stored in the SAM and comparing it with centroids of clusters of data already stored in the SAM. The closest cluster is selected, and if the number of hash codes stored in the SAM exceeds a threshold, a controller is queried for cluster sizes. Based on the query, it is determined that one of the clusters has an unbalanced size, and a different cluster is selected to associate with a number of hash codes corresponding to the unbalanced cluster.

Abstract

Methods, apparatus, systems, and articles of manufacture are disclosed to facilitate improved use of stochastic associative memory. Example instructions cause at least one processor to: generate a hash code for data to be stored in a stochastic associative memory (SAM); compare the hash code with centroids of clusters of data stored in the SAM; select a first one of the clusters corresponding to a first one of the centroids that is closest to the hash code; determine whether a selected number of hash codes stored in the SAM exceeds a threshold; in response to the selected number exceeding the threshold: query a controller for sizes of the clusters; and determine, based on the query, that a second one of the clusters includes an unbalanced size; and select a third one of the clusters to associate with a second number of hash codes corresponding to the second one of the clusters.

RESERVATION OF MEMORY IN MULTIPLE TIERS OF MEMORY (18084258)

Inventor Slawomir PUTYRSKI

Brief explanation

The abstract describes a memory controller in a multi-tiered memory system. The memory controller allocates a portion of the near memory to a requester based on a received request. It can send read and write commands to the multi-tiered memory system to access and store data. The near memory is connected to the memory controller through a memory interface, while the far memory is connected via a network.

Abstract

Examples described herein relate to a memory controller, when connected to at least one memory device in a multi-tiered memory system comprising a near memory and far memory, is to allocate a region of the near memory to a requester based on receipt of a request. In some examples, the memory controller includes circuitry to transmit at least one memory read command and address information to the multi-tiered memory system to read data from the multi-tiered memory system and circuitry to transmit at least one memory write command and address information to the multi-tiered memory system to write data to the multi-tiered memory system, wherein the near memory comprises at least one memory connected to the memory controller via a memory interface and the far memory comprises at least one memory connected to the memory controller via a network.

PRECISE LONGITUDINAL MONITORING OF MEMORY OPERATIONS (18327474)

Inventor Ahmad YASIN

Brief explanation

This abstract describes a processor that has a memory subunit and an execution engine unit. The memory subunit has a status register and is responsible for monitoring load operations. When a load operation is selected, the processor determines its re-order buffer identifier and sends it to the memory subsystem. The memory subunit then stores information about the status of the load operation in the status register.

Additionally, the processor has logic that detects when a load operation is retired. When this happens, memory information is stored in memory-related fields of a memory buffer record. This memory information includes auxiliary information and access latency information. One of these pieces of information, either the auxiliary information or the access latency information, includes the status information from the status register, which is stored in a specific field of the memory-related fields.

Abstract

A processor includes a memory subunit that includes a status register and an execution engine unit to: randomly select a load operation to monitor; determine a re-order buffer identifier of the load operation; and transmit the re-order buffer identifier to the memory subsystem. Responsive to receipt of the re-order buffer identifier, the first memory subunit is to store a piece of information, related to a status of the load operation, in the status register. The processor also includes logic to, responsive to detection of retirement of the load operation, store memory information in memory-related fields of a record of a memory buffer. The memory information includes auxiliary information (AUX) and access latency information, wherein one of the auxiliary information or the access latency information includes the piece of information, from the status register, stored in a particular field of the memory-related fields.

METHODS AND APPARATUS TO PERFORM AN ENHANCED S3 PROTOCOL TO UPDATE FIRMWARE WITH A BOOT SCRIPT UPDATE (18040146)

Inventor Di Zhang

Brief explanation

The abstract describes a method for updating firmware using an enhanced S3 protocol. The method involves a management agent storing a firmware update in memory and requesting the operating system (OS) to enter a sleep state called S3. When the OS enters the sleep state, it triggers an interrupt. The basic input/output system (BIOS) then updates a Boot Script based on the firmware update and wakes up the OS using a wake vector.

Abstract

Methods, apparatus, systems, and articles of manufacture perform an enhanced S3 protocol to update firmware with a Boot Script update are disclosed. An example apparatus includes a management agent to store a firmware update into memory; and request an operating system (OS) to enter into an S3 sleep state; the OS to, in response to the request from the management agent, enter into the S3 sleep state and trigger an interrupt; and a basic input/output system (BIOS) to, in response to the interrupt from the OS update a Boot Script according to the firmware update; and wake up the OS with a wake vector.

METHODS AND APPARATUS TO PERFORM A PSEUDO-S3 PROTOCOL TO UPDATE FIRMWARE AND/OR ACTIVATE NEW FIRMWARE WITH A WARM RESET (18040147)

Inventor Mohan Kumar

Brief explanation

The abstract describes a method and system for updating firmware and activating new firmware using a pseudo-S3 protocol. The system includes an ACPI component that triggers a pseudo-sleep event when a firmware update is identified. It also initiates a power button event, which prompts the operating system to prepare for sleep mode. The BIOS component then performs a warm reset in response to the OS preparing for sleep, updating the firmware according to the firmware update. Finally, the BIOS transmits a wake vector to the OS to resume normal operation.

Abstract

Methods, apparatus, systems, and articles of manufacture to perform a pseudo-S3 protocol to update firmware and/or activate new firmware with a warm reset are disclosed. An example apparatus includes an advanced configuration and power interface (ACPI) to: initiate a pseudo-sleep event in response to identifying a firmware update; and assert a power button event, the power button event to cause an operating system (OS) to prepare to enter into a sleep state; a basic input/output system (BIOS) to: initiate a warm reset in response to the OS preparing to enter the sleep state, the warm reset to update firmware according to the firmware update; and transmit a wake vector to the OS to continue operation.

PROCESSOR HARDWARE AND INSTRUCTIONS FOR VECTORIZED FUSED AND-XOR (17703194)

Inventor Andrew H. Reinders

Brief explanation

The abstract describes a method that involves fetching an encoded instruction, decoding it, and executing it. The instruction is a vectorized AND-XOR operation that takes inputs from different sources and performs a computation to generate an updated value. The result is then stored in a register file.

Abstract

A method comprises fetching, by fetch circuitry, an encoded vectorized AND-XOR instruction comprising an opcode, a first source identifier, a second source identifier, a third source identifier, and a destination identifier, decoding, by decode circuitry, the decoded vectorized AND-XOR instruction to generate a decoded vectorized AND-XOR instruction, and executing, by execution circuitry, the decoded vectorized AND-XOR instruction to retrieve operands representing a product coefficient at an index position from the first source, a coefficient of a first polynomial from the second source, and a coefficient of a second polynomial from the third source, perform, in an atomic fashion, a vectorized AND-XOR operation to generate updated value of the product coefficient, and store the product coefficient of the output polynomial in a register file accessible to the execution circuitry.

SYSTEMS, APPARATUS, ARTICLES OF MANUFACTURE, AND METHODS FOR DATA DRIVEN NETWORKING (18189813)

Inventor Roya Doostnejad

Brief explanation

The abstract describes a device called an edge compute device that can adjust its computing resources based on the demand of its location. It has interface circuitry, programmable circuitry, and instructions to configure the compute resources. When the device changes location, it can detect the change and reconfigure its resources based on the new location's demand.

Abstract

Systems, apparatus, articles of manufacture, and methods are disclosed. An example edge compute device disclosed herein includes interface circuitry, machine readable instructions, and programmable circuitry to execute the machine readable instructions to configure compute resources of the edge compute device based on a first resource demand associated with a first location of the edge compute device, detect a change in location of the edge compute device to a second location, and in response to detection of the change in location, reconfigure the compute resources of the edge compute device based on a second resource demand associated with the second location.

REGISTER REPLAY STATE MACHINE (18326918)

Inventor Xueyan Wang

Brief explanation

The abstract describes a method for a processor unit to enter into a management operating mode. Register operations are stored in a dedicated buffer and executed when the processor unit needs to enter this mode. These operations can be stored during system startup or added during system runtime. The operations can save the processor unit's state when entering the management mode and restore it when exiting. In systems with multiple processor units, these operations can cause one unit to execute management instructions while others enter an idle mode.

Abstract

Register operations to cause a processor unit to enter into a management operating mode are stored in a dedicated buffer in the processor unit and are executed by the processor unit when the processor unit is to enter into a management operating mode. The register operations can be stored in the buffer during computing system startup or by out-of-band provisioning during computing system runtime. The register operations can save a state of the processor unit as part of entering the management operating mode and restore the state when the processor unit exits the management operation mode. In computing systems comprising multiple processor units, the register operations can cause one of the processor units to execute management operating mode instructions and one or more other processor units to enter into an idle mode while the processor units are in the management operating mode.

DEVICE, SYSTEM AND METHOD FOR PROVIDING A HIGH AFFINITY SNOOP FILTER (17705015)

Inventor Leon Polishuk

Brief explanation

The abstract describes techniques and mechanisms for efficiently accessing cached data. It introduces a cache coherency engine that includes a snoop filter, which stores entries corresponding to lines in one or more caches. The snoop filter has multiple sets, each capable of representing a line in a first cache's set. In another embodiment, multiple caches each have a first set, and each set in the snoop filter represents a line in the respective first sets of the multiple caches.

Abstract

Techniques and mechanisms for efficiently providing access to cached data. In an embodiment, a cache coherency engine comprises circuitry to provide a snoop filter which stores entries each corresponding to a respective line of one or more caches. The one or more caches comprise a first cache which includes a first set, and the snoop filter includes a first plurality of sets which are each configured to be available to represent a line of the first set. In another embodiment, the one or more caches comprise multiple caches which each comprise a respective first set, wherein, for each set of the first plurality of sets, any line in the multiple caches which is to be represented by that each set is to be a line in the respective first sets of the multiple caches.

CHIPLET ARCHITECTURE FOR LATE BIND SKU FUNGIBILITY (17702271)

Inventor Mark C. Davis

Brief explanation

The abstract describes a modular parallel processor that consists of an active base die and multiple chiplets. The active base die contains hardware logic, interconnect logic, and slots for the chiplets. The chiplets are stacked on top of the active base die and can be easily swapped out during assembly. There are two types of chiplets: hardware logic chiplets with different functional units, and memory chiplets with different memory devices. The chiplets are connected to each other through the interconnect logic within the active base die.

Abstract

Described herein is a modular parallel processor comprising an active base die including hardware logic, interconnect logic, and a plurality of chiplet slots and a plurality of chiplets vertically stacked on the active base die and coupled with the plurality of chiplet slots of the active base die. The plurality of chiplets is interchangeable during assembly of the modular parallel processor and include a group of hardware logic chiplets having a plurality of different functional units and a group of memory chiplets having a plurality of different memory devices. The hardware logic chiplets and the memory chiplets interconnect via the interconnect logic within the active base die.

INTERFACE BRIDGE BETWEEN INTEGRATED CIRCUIT DIE (18327043)

Inventor Jeffrey Erik Schulz

Brief explanation

This abstract describes a communication bridge between two integrated circuit dies. The first die has programmable logic fabric, while the second die supports the first die. The bridge allows the two dies to communicate with each other using chip-to-chip interconnects. The bridge implements source-synchronous communication, using a data receive clock from the second die to the first die.

Abstract

An interface bridge to enable communication between a first integrated circuit die and a second integrated circuit die is disclosed. The two integrated circuit die may be connected via chip-to-chip interconnects. The first integrated circuit die may include programmable logic fabric. The second integrated circuit die may support the first integrated circuit die. The first integrated circuit die and the secondary integrated circuit die may communicate with one another via the chip-to-chip interconnects using an interface bridge. The first and second component integrated circuits may include circuitry to implement the interface bridge, which may provide source-synchronous communication using a data receive clock from the second integrated circuit die to the first integrated circuit die.

CHIPLET ARCHITECTURE CHUNKING FOR UNIFORMITY ACROSS MULTIPLE CHIPLET CONFIGURATIONS (17702235)

Inventor Mark C. Davis

Brief explanation

This abstract describes a modular parallel processor that is made up of multiple chiplets. These chiplets are tested to determine their characteristics, such as the number of functional units or power consumption. The chiplet slots on the base chiplet die can be configured to be populated by one or more chunks of chiplets, each with a predetermined value. This value can be the total number of functional execution cores or a collective power metric for the chunk.

Abstract

Described herein is a modular parallel processor and associated manufacturing method in which the parallel processor is assembled from multiple chiplets that populate multiple chiplet slots of an active base chiplet die. The multiple chiplets are tested to determine characteristics of the chiplet, such as a number of functional units or a power consumption metric for the chiplet. The multiple chiplet slots can be configured to be populated by one or more chunks of multiple chiplets, where each chunk has a pre-determined collective value. The pre-determined collective value can be a total number of functional execution cores within a chunk or a collective power metric for the chunk.

MODULAR PERIPHERY TILE FOR INTEGRATED CIRCUIT DEVICE (18327045)

Inventor Chee Hak Teh

Brief explanation

The abstract describes a system or method that can improve the scalability of integrated circuit systems by separating the peripheral intellectual property (IP) circuitry into modular tiles. These tiles can be installed as separate modules, allowing for easier scalability and variation in the product. The system includes a first die with programmable fabric circuitry and a second die with the periphery IP tile. The periphery IP tile is separated from the programmable fabric die and connected to the first die through a modular interface.

Abstract

Systems or methods of the present disclosure may improve scalability (e.g., component scalability, product variation scalability) of integrated circuit systems by disaggregating periphery intellectual property (IP) circuitry into modular periphery IP tiles that can be installed as modules. Such an integrated circuit system may include a first die that includes programmable fabric circuitry and a second die that includes a periphery IP tile. The periphery IP tile may be disaggregated from the programmable fabric die and may be communicatively coupled to the first die via a modular interface.

COMPRESSION USING A FLAT MAPPING IN VIRTUAL ADDRESS SPACE (17702301)

Inventor Vidhya Krishnan

Brief explanation

This abstract describes a graphics processor that has a processing resource, a codec, and circuitry. The processing resource performs processing operations, while the codec compresses and decompresses data related to these operations. The circuitry calculates a metadata address for a compressed surface, which is where the data associated with a processing operation is stored. This metadata address is based on a mapping between the address of the compressed surface and the metadata address in virtual memory. The circuitry also configures the codec to access the compressed surface using the compression metadata.

Abstract

Described herein is a graphics processor comprising a processing resource configured to perform processing operations, a codec configured to compress and decompress data associated with the processing operations, and circuitry configured to calculate a metadata address for a compressed surface based on a flat virtual memory address mapping between the address of the compressed surface and the metadata address. The compressed surface is to store data associated with a processing operation to be performed by the processing resource and the metadata address is a virtual address that stores compression metadata for the compressed surface. The circuitry can configure the codec to access the compressed surface based on the compression metadata.

DISPLAY VIRTUALIZATION (17827305)

Inventor David Cowperthwaite

Brief explanation

The abstract describes a graphics processor that includes a display controller with hardware display virtualization. The graphics processor has a system interface with two virtual interfaces, a render engine for graphics rendering operations, and a display engine with hardware display virtualization. The render engine can perform different rendering operations based on commands received through the virtual interfaces. The display engine can present the output of these rendering operations on separate physical display planes associated with each virtual interface.

Abstract

Described herein is a partitional graphics processor including a display controller including hardware display virtualization. One embodiment provides a graphics processor comprising a system interface including a first virtual interface and a second virtual interface, a render engine to perform graphics rendering operations, and a display engine including hardware display virtualization. The render engine is configured to perform a first rendering operation in response to a command received via the first virtual interface and a second rendering operation in response to a command received via the second virtual interface. The display engine configured to present output of the first rendering operation via a first physical display plane that is associated with the first virtual interface and present output of the second rendering operation via a second physical display plane that is associated with the second virtual interface.

REGISTRATION METROLOGY TOOL USING DARKFIELD AND PHASE CONTRAST IMAGING (17705436)

Inventor Deepan KISHORE KUMAR

Brief explanation

The abstract describes a system for inspecting and measuring the accuracy of registration and detecting defects on EUV masks and semiconductor wafers. The system uses darkfield and phase contrast imaging techniques to capture images of low contrast features. It also includes brightfield imaging capabilities. The system provides analyzed data on registration errors and surface defects.

Abstract

The present disclosure is directed to an inspection system for registration metrology and defect detection using darkfield and phase contrast imaging optical systems. The present system includes a transmitted light mode and diffracted light mode to enable imaging of low contrast features on blank EUV masks and semiconductor wafers. In an aspect, this system combines the optics for darkfield and phase contrast imaging, and may also include the optics for brightfield imaging, to provide analyzed data on registration errors and surface defects.

DEEP LEARNING FOR DENSE SEMANTIC SEGMENTATION IN VIDEO WITH AUTOMATED INTERACTIVITY AND IMPROVED TEMPORAL COHERENCE (18131650)

Inventor Anthony Rhodes

Brief explanation

The abstract discusses techniques for automatically dividing video frames into distinct regions of objects and background. This is done by using a segmentation convolutional neural network (CNN) on various inputs such as the current and previous video frames, an indicator frame for the object of interest, a motion frame, and multiple feature frames. These inputs are processed to generate potential segmentations, and one of these segmentations is chosen as the final segmentation for the current video frame.

Abstract

Techniques related to automatically segmenting video frames into per pixel dense object of interest and background regions are discussed. Such techniques include applying a segmentation convolutional neural network (CNN) to a CNN input including a current video frame, a previous video frame, an object of interest indicator frame, a motion frame, and multiple feature frames each including features compressed from feature layers of an object classification convolutional neural network as applied to the current video frame to generate candidate segmentations and selecting one of the candidate segmentations as a final segmentation of the current video frame.

ENHANCING HIERARCHICAL DEPTH BUFFER CULLING EFFICIENCY VIA MASK ACCUMULATION (18189873)

Inventor Saikat Mandal

Brief explanation

This abstract describes a technique to enhance the efficiency of coarse depth testing in computer graphics. It introduces a method that involves tracking the history of source fragments being tested against a destination tile. In cases where a combination of partial fragments adds up to full coverage, the technique utilizes the most conservative source far depth value instead of the previous destination far depth value. However, if the combination only results in partial coverage, the previous destination far depth value is retained.

Abstract

Embodiments described herein provide for a technique to improve the culling efficiency of coarse depth testing. One embodiment provides for a graphics processor that is configured to perform a method to track a history of source fragments that are tested against a destination tile. When a combination of partial fragments sum to full coverage, the most conservative source far depth value is used instead of the previous destination far depth value. When the combination sums to partial coverage, the previous destination far depth value is retained.

TECHNOLOGIES FOR CURRENT BIASING FOR MEMORY CELLS (17703921)

Inventor Jonathan Y. Wang

Brief explanation

The abstract describes techniques for biasing memory cells in a way that ensures they function properly. In this approach, a source follower is used to set a specific voltage on a bitline of the memory cell. To limit the current flowing through the source follower, a current mirror is placed in series with it. If the source follower cannot provide enough current, an additional feedback transistor is activated to supply the required amount. In some cases, the current flowing through the feedback transistor is copied to a current mirror, which is then used to determine the state of the memory cell.

Abstract

Techniques for current biasing for memory cells are disclosed. In the illustrative embodiment, a source follower sets a voltage on a bitline of a memory cell. The current through the source follower is limited by a current mirror in series with the source follower. When additional current is required that the source follower cannot supply, a feedback transistor is activated to provide additional current. Additionally, in some embodiments, the current through the feedback transistor is copied to a current mirror, and the copied current is used to sense the state of the memory cell.

IMPLANTATION THROUGH AN ETCH STOP LAYER (17656366)

Inventor Moshe Dolejsi

Brief explanation

This abstract describes an integrated circuit that consists of multiple layers of dielectric material. The first layer contains either an interconnect feature or a device. Above this layer is a second layer also made of dielectric material, with a third layer in between. The third layer can serve as an etch stop layer, liner layer, or barrier layer. Within the first and third layers, there is an impurity present. The impurity has a detectable implant depth profile, meaning it is distributed at different depths within the first and third layers.

Abstract

An integrated circuit includes a first layer comprising dielectric material. One or both of an interconnect feature and a device are within the dielectric material of the first layer. The integrated circuit further includes a second layer above the first layer, where the second layer includes dielectric material. A third layer is between the first layer and the second layer. In an example, the third layer can be, for example, an etch stop layer or a liner layer or barrier layer. In an example, an impurity is within the first layer and the third layer. In an example, the impurity has a detectable implant depth profile such that a first distribution of the impurity is within the first layer and a second distribution of the impurity is within the third layer.

ALIGNED PITCH-QUARTERED PATTERNING FOR LITHOGRAPHY EDGE PLACEMENT ERROR ADVANCED RECTIFICATION (18205456)

Inventor Charles H. WALLACE

Brief explanation

The abstract describes a method of improving the accuracy of lithography in semiconductor fabrication. It involves using a specific patterning technique called aligned pitch-quartered patterning. The process includes forming multiple layers of hardmask on a semiconductor substrate and applying a special type of polymer called segregated di-block co-polymer. By selectively removing certain parts of the polymer, a patterned hardmask is created, which is then used to create semiconductor fins on the substrate. Some of these fins are subsequently removed. Overall, this method aims to enhance the precision and quality of semiconductor structures.

Abstract

Aligned pitch-quartered patterning approaches for lithography edge placement error advanced rectification are described. For example, a method of fabricating a semiconductor structure includes forming a first patterned hardmask on a semiconductor substrate. A second hardmask layer is formed on the semiconductor substrate. A segregated di-block co-polymer is formed on the first patterned hardmask and on the second hardmask layer. Second polymer blocks are removed from the segregated di-block co-polymer. A second patterned hardmask is formed from the second hardmask layer and a plurality of semiconductor fins is formed in the semiconductor substrate using first polymer blocks as a mask. A first fin of the plurality of semiconductor fins is removed. Subsequent to removing the first fin, a second fin of the plurality of semiconductor fins is removed.

PACKAGE LAYERS FOR STRESS MONITORING AND METHOD (17705878)

Inventor Jan Proschwitz

Brief explanation

The abstract describes a semiconductor package that consists of layers of a certain material. It also includes an integrated circuit (IC) that is attached to the package substrate through multiple vias. The package also contains an interface layer made of a different material, which is sealed off from exposure to air. This interface material can be a nonconductive material that is sensitive to moisture. It can be located within the package substrate or between the IC and the package substrate. The abstract mentions that there are other systems, apparatuses, and methods described as well.

Abstract

A semiconductor package comprises a package substrate comprised of comprised of layers of a first material. The semiconductor package includes an integrated circuit (IC) attached to the substrate at a first surface of the IC through a plurality of vias. The semiconductor package includes at least one interface layer comprised of an interface material different from the first material and sealed from exposure to air. The interface material can comprise a moisture-sensitive nonconductive material and can be disposed within the package substrate or between the first surface of the IC and the package substrate, among other locations. Other systems, apparatuses and methods are described.

SUBSTRATE FOR IMPROVED HEAT DISSIPATION AND METHOD (17703400)

Inventor Carlton Hanna

Brief explanation

The abstract describes a semiconductor package that is made up of a package substrate, which is a layer of dielectric material. This substrate includes a portion of diamond dust material, which consists of tiny particles of diamond dust. The semiconductor package also has electrical connections that are connected through the layers of the package substrate.

Abstract

A semiconductor package comprises a package substrate comprised of at least a first layer of dielectric material including a portion of diamond dust material. The diamond dust material is comprised of diamond dust particles. The semiconductor package includes at least one electrical connection coupled through layers of the package substrate.

PACKAGING ARCHITECTURE WITH EDGE RING ANCHORING (17583485)

Inventor Xavier Francois Brun

Brief explanation

The abstract describes a microelectronic assembly that includes an interposer, a package substrate, an integrated circuit die, and an edge ring. The interposer has two faces, with the package substrate attached to one face and the integrated circuit die attached to the other face. The interposer also has a core made of a first dielectric material and a redistribution layer (RDL) made of a second dielectric material. The edge ring consists of a metal trace that runs along the outer edge of the interposer and is in contact with the second dielectric material. Additionally, there are multiple metal vias that pass through the RDL and are in contact with the metal trace.

Abstract

A microelectronic assembly is provided, comprising: an interposer having a first face and a second face opposite to the first face; a package substrate coupled to the first face; an integrated circuit die coupled to the second face; and an edge ring in the interposer. The interposer comprises a core comprising a first dielectric material and a redistribution layer (RDL), the RDL being on the first face or the second face, the RDL comprising a second dielectric material different from the first dielectric material, and the edge ring comprises: a metal trace in contact with the second dielectric material, the metal trace being along a periphery of the interposer, and a plurality of metal vias through the RDL, the plurality of metal vias in contact with the metal trace.

AIRGAPS USED IN BACKEND MEMORY STRUCTURES (17704410)

Inventor Miriam R. Reshotko

Brief explanation

This abstract describes techniques for creating memory structures with airgaps in the interconnect region above semiconductor devices. These airgaps are placed between conductive features, such as wordlines, to reduce parasitic capacitance. The interconnect region consists of multiple layers, with the first layer containing wordlines with airgaps between them. The second layer includes memory cells positioned over the corresponding wordlines, and the third layer consists of a second conductive layer (bitline) that extends over the memory cells. The presence of airgaps between the wordlines allows for a tighter arrangement of memory cells and reduces overall energy consumption among the memory cells.

Abstract

Techniques are provided herein for forming backend memory structures with airgaps in an interconnect region above semiconductor devices. The airgaps may be provided between conductive features, such as wordlines, to reduce parasitic capacitance. An interconnect region above a plurality of semiconductor devices includes any number of interconnect layers. A first interconnect layer includes first conductive layers (e.g., wordlines) extending in a first direction with airgaps between adjacent first conductive layers. A second interconnect layer over the first interconnect layer includes at least portions of memory cells over corresponding first conductive layers. A third interconnect layer over the second interconnect layer includes a second conductive layer (e.g., bitline) extending in a second direction over one or more of the at least portions of memory cells. The presence of airgaps between the first conductive layers allows for a tighter pitch between memory cells and reduced total energy consumption among the memory cells.

SIZE AND EFFICIENCY OF DIES (18202136)

Inventor Mathew J. MANUSHAROW

Brief explanation

The abstract describes an integrated circuit package that consists of multiple components. These components include two integrated circuit dies, an organic substrate, a multi-die interconnect bridge (EMIB), and a termination resistor. The first and second integrated circuit dies are connected to the organic substrate, which also contains the embedded EMIB. The termination resistor is specifically associated with a circuit in the first integrated circuit die and is located within the EMIB embedded in the organic substrate.

Abstract

An integrated circuit package is disclosed. The integrated circuit package includes a first integrated circuit die, a second integrated circuit die, an organic substrate, wherein both the first integrated circuit die and the second integrated circuit die are connected to the organic substrate, a multi-die interconnect bridge (EMIB) embedded within the organic substrate, and a termination resistor associated with a circuit in the first integrated circuit die, wherein the termination resistor is located within the multi-die interconnect bridge embedded within the organic substrate.

BGA STIFFENER ATTACHMENT WITH LOW EOLIFE ADHESIVE STRENGTH AT HIGH SOLDER JOINT STRESS AREA GENERATED FROM ENABLING LOAD (17703768)

Inventor Phil GENG

Brief explanation

The abstract describes an electronic package that includes a package substrate and a die connected to the substrate. The package also includes a stiffener, which is a ring with corner regions and beams. The corner regions have a certain thickness, while the beams have a greater thickness.

Abstract

Embodiments disclosed herein include an electronic package. In an embodiment, the electronic package comprises a package substrate, and a die coupled to the package substrate. In an embodiment, the electronic package further comprises a stiffener on the package substrate surrounding the die. In an embodiment, the stiffener is a ring with one or more corner regions and one or more beams. In an embodiment, each beam is between a pair of corner regions, and the one or more corner regions have a first thickness and the one or more beams have a second thickness that is greater than the first thickness.

GAN 3D POWER BLOCK (17706454)

Inventor Ahmed ABOU-ALFOTOUH

Brief explanation

The abstract describes a device called a coupled inductor, which consists of two inductors. The first inductor is connected to the second inductor. The device also includes two switches, one connected to the first inductor and the other connected to the second inductor. These switches are made of a combination of gallium and nitrogen.

Abstract

Embodiments disclosed herein include a coupled inductor. In an embodiment, the coupled inductor comprises a first inductor and a second inductor. In an embodiment, the first inductor can be coupled to the first inductor. In an embodiment, the coupled inductor further comprises a first switch coupled to the first inductor, where the first switch comprises gallium and nitrogen, and a second switch coupled to the second inductor, where the second switch comprises gallium and nitrogen.

BACKSIDE PROCESSING OF FINS IN FIN BASED TRANSISTOR DEVICES (17656490)

Inventor Tao Chu

Brief explanation

This abstract describes an integrated circuit that consists of multiple components. It includes two sets of source and drain regions, each connected by a fin structure. The fin structure has an upper region and a lower region. On top and on the sides of the upper region, there is a gate structure. The key difference between the two sets is that the lower region of the first set has a different vertical height compared to the lower region of the second set, with a minimum difference of 2 nanometers.

Abstract

An integrated circuit includes a first source region, a first drain region, a first fin having (i) a first upper region laterally between the first source region and the first drain region and (ii) a first lower region below the first upper region, and a first gate structure on at least top and side surfaces of the first upper region. The integrated circuit further includes a second source region, a second drain region, a second fin having (i) a second upper region laterally between the second source region and the second drain region and (ii) a second lower region below the second upper region, and a second gate structure on at least top and side surfaces of the second upper region. In an example, a first vertical height of the first lower region is different from a second vertical height of the second lower region by at least 2 nanometers (nm).

REPLACEMENT METAL GATES TO ENHANCE TRANSISTOR STRAIN (18204231)

Inventor Mark T. BOHR

Brief explanation

The abstract describes that the present invention involves devices and techniques related to strain in NMOS and PMOS transistors. It does not provide any exaggerated claims or a specific title for the invention.

Abstract

Some embodiments of the present invention include apparatuses and methods relating to NMOS and PMOS transistor strain.

GATE-ALL-AROUND INTEGRATED CIRCUIT STRUCTURES HAVING BACKSIDE CONTACT WITH ENHANCED AREA RELATIVE TO EPITAXIAL SOURCE (17706218)

Inventor Joseph D'SILVA

Brief explanation

The abstract describes a type of integrated circuit structure called gate-all-around, which has a backside contact that enhances the area of the epitaxial source or drain region. The structure consists of two vertical arrangements of nanowires, with a gate stack placed over them. At the ends of each vertical arrangement, there are epitaxial source or drain structures. Beneath one of these structures, there is a conductive structure that is in contact with it. The conductive structure covers the entire bottom of the epitaxial source or drain structure and may also cover a portion of its sides.

Abstract

Gate-all-around integrated circuit structures having backside contact with enhanced area relative to an epitaxial source or drain region are described. For example, an integrated circuit structure includes a first vertical arrangement of nanowires and a second vertical arrangement of nanowires. A gate stack is over the first and second vertical arrangements of nanowires. First epitaxial source or drain structures are at ends of the first vertical arrangement of nanowires. Second epitaxial source or drain structures are at ends of the second vertical arrangement of nanowires. A conductive structure is vertically beneath and in contact with one of the first epitaxial source or drain structures. The conductive structure is along an entirety of a bottom of the one of the first epitaxial source or drain structures, and the conductive structure can also be along a portion of sides of one of the first epitaxial source or drain structures.

TRANSISTOR GATE STACKS WITH THICK HYSTERETIC ELEMENTS (17702593)

Inventor Abhishek A. Sharma

Brief explanation

This abstract describes a new type of transistor gate-channel arrangement that includes a thick hysteretic element. The gate stack of the transistor includes multiple layers, including a thick hysteretic element, an interface layer, a gate electrode material, and a channel material. The interface layer is a dielectric material with a high dielectric constant and is thinner than 3 nanometers. This new arrangement improves gate control and allows for the use of thick hysteretic elements without sacrificing transistor performance.

Abstract

Disclosed herein are transistor gate-channel arrangements with transistor gate stacks that include thick hysteretic elements (i.e., hysteretic elements having a thickness of at least 10-15 nanometers, e.g., between 55 and 100 nanometers), and related methods and devices. Transistor gate stacks disclosed herein include a multilayer gate insulator having a thick hysteretic element and an interface layer, where the thick hysteretic element is between the interface layer and a gate electrode material, and the interface layer is between the thick hysteretic element and a channel material of a transistor. The interface layer may be a dielectric material with an effective dielectric constant of at least 20 and/or be a dielectric material that is thinner than about 3 nanometers. Such an interface layer may help improve gate control and allow use of thick hysteretic elements while maintaining transistor performance in terms of, e.g., gate leakage, carrier mobility, and subthreshold swing.

LOW RADIATION HIGH SYMMETRY INDUCTOR (17704050)

Inventor Run LEVINGER

Brief explanation

The abstract describes a circuitry that consists of two S-shaped windings arranged in a figure-8 shape. The circuitry has four terminals - two for positive signals and two for negative signals. When a current flows through the windings, a magnetic flux is concentrated at the intersection of the windings.

Abstract

A circuitry including a first S-shaped winding and a second S-shaped winding configured to form a figure-8 inductive structure; a first terminal coupled to a first end of the first S-shaped winding and a second terminal coupled to a first end of the second S-shaped winding, wherein the first terminal is configured to receive a first positive signal and the second terminal is configured to receive a first negative signal; a third terminal coupled to a second end of the first S-shaped winding and a fourth terminal coupled to a second end of the second S-shaped winding, wherein the third terminal is configured to receive a second negative signal and the fourth terminal is configured to receive a second positive signal; wherein a magnetic flux is concentrated at an intersection of the first S-shaped winding and the second S-shaped winding when a first current flows through them.

HIGH PRECISION SCALABLE PACKAGING ARCHITECTURE BASED ON RADIO FREQUENCY SCANNING (17700819)

Inventor Georgios Dogiamis

Brief explanation

This abstract describes a microelectronic assembly that consists of multiple transceiver modules, each with an antenna and a printed circuit board (PCB). These transceiver modules are separated from a reflector module by a space. The reflector module includes a substrate with two sides, an antenna-array on one side, and two integrated circuit (IC) dies on the other side. The first IC die contains radio frequency (RF) switches that can operate within a wide range of electromagnetic frequencies, while the second IC die contains memory cell arrays and digital logic circuits.

Abstract

Embodiments of a microelectronic assembly comprise a plurality of transceiver modules, each transceiver module including a first antenna; a printed circuit board (PCB); and a reflector module coupled to the PCB and separated from the plurality of transceiver modules by a space. The reflector module comprises: a substrate having a first side and an opposing second side, the first side being proximate to the plurality of transceiver modules, an antenna-array on the first side of the substrate, the antenna-array including a plurality of second antennas; a first integrated circuit (IC) die on the second side of the substrate; and a second IC die on the second side of the substrate. The first IC die comprises radio frequency (RF) switches configured to operate at electromagnetic frequencies between 20 kHz and 1 THz, and the second IC die comprises memory cell arrays and digital logic circuits.

LOW PROFILE IMPEDANCE-TUNABLE AND CROSS-TALK CONTROLLED HIGH SPEED HYBRID SOCKET INTERCONNECT (17703730)

Inventor Emad S. AL-MOMANI

Brief explanation

The abstract describes the invention of sockets and socket architectures. These sockets are made up of a substrate, which is a material or surface on which something is placed. The substrate has an opening through it, and an elastomeric pin is inserted into this opening. The elastomeric pin is electrically conductive, meaning it can carry an electric current.

Abstract

Embodiments disclosed herein include sockets and socket architectures. In an embodiment, a socket comprises a substrate. In an embodiment, an opening is provided through the substrate. In an embodiment, an elastomeric pin inserted into the opening. In an embodiment, the elastomeric pin is electrically conductive.

NON-CONTACT POWER RECEIVER APPARATUS (18191329)

Inventor Chun-Kil Jung

Brief explanation

The abstract describes a non-contact power transmission apparatus that can accurately identify the type of object placed on its charging deck. It only allows power transmission and data communication when a compatible non-contact power receiving apparatus is detected. This ensures efficient power transmission and enables accurate monitoring of the receiver's state. The power transmission apparatus measures the power supplied to the non-contact power receiving apparatus and controls the output power of the wireless power signal from two different cores. This allows for stable charging even if the receiving apparatus is moved on the power transmission apparatus. Overall, this technology improves the reliability of non-contact charging systems and enhances the competitiveness of related products like portable terminals and battery packs.

Abstract

A non-contact power transmission apparatus accurately determines the kind of object that is placed on the charging deck of the non-contact power transmission apparatus, and, only when a non-contact power receiving apparatus is placed on the power transmission apparatus, allows power transmission and data communication to take place, thereby accurately determining the state of the receiver side and efficiently controlling the transmission of power. In the power transmission apparatus, the power supplied to the non-contact power receiving apparatus is measured, and the output power of the wireless power signal output from two different cores is controlled, thereby allowing the charging operation to be stably conducted even if the non-contact power receiving apparatus is moved anywhere on the power transmission apparatus. The power transmission apparatus improves both the reliability of operation of the non-contact charging system, and the competitiveness of related products, such as portable terminals, battery packs and the like.

VOLTAGE REGULATOR DRIVERS AND CONVERTER STAGES (17704950)

Inventor Nicolas Butzen

Brief explanation

The abstract discusses the use of power driver circuits to provide higher voltage capabilities. It suggests that using a single transistor may not be sufficient, so a secondary stacked transistor voltage driver is introduced. This secondary driver is driven using time-shifted control signals to reduce any negative effects. 

To improve the performance of a continuous capacitive voltage regulator, a switching schema is used to interleave the cells. This helps to optimize the regulation process.

The abstract also mentions a multi-stage approach, which includes fixed-ratio or multi-ratio capacitive voltage converter stages. The final stage is switched out of phase from the preceding stages and includes a continuously scalable capacitive converter. This approach allows for more efficient voltage conversion.

Abstract

Power driver circuits may be used to provide higher voltage capabilities beyond what may managed by a single transistor. To reduce or eliminate effects associated with a stacked transistor voltage driver, a secondary stacked transistor voltage driver may be separated from a primary stacked transistor voltage driver, where the secondary driver is driven using time-shifted control signals. A switching schema may be used to interleave the several cells of a single continuous capacitive voltage regulator. A multi-stage approach may include both a number of fixed-ratio or multi-ratio capacitive voltage converter stages and final stage that is switched out of phase from the preceding stages, where the final stage includes a continuously scalable capacitive converter.

DISTRIBUTED RADIOHEAD SYSTEM (DRS) AND CLOCKING, CALIBRATION, AND SYNCHRONIZATION FOR DRS (18041804)

Inventor Rotem BANIN

Brief explanation

This abstract describes a communication device that has two radiohead circuits. The first circuit is responsible for transmitting signals in two different configurations, while the second circuit is responsible for receiving those signals. The device also includes processors that analyze the received signals and determine the best configuration for the first circuit based on certain signal parameters.

Abstract

In various aspects of this disclosure, a communication device is provided. The communication device may include a first radiohead circuit including a first transceiver chain configured to transmit a first radio frequency signal associated with a first transmission configuration and to transmit a second radio frequency signal associated with a second transmission configuration a second radiohead circuit comprising a second transceiver chain configured to receive the first radio frequency signal and the second radio frequency signal, and one or more processors configured to determine a first signal parameter associated with the first radio frequency signal received at the second transceiver chain and a second signal parameter associated with the second radio frequency signal received at the second transceiver chain, and to determine a preferred transmission configuration for the first transceiver chain by using the first signal parameter and the second signal parameter.

LINK PERFORMANCE PREDICTION USING SPATIAL LINK PERFORMANCE MAPPING (18023699)

Inventor Jonas Svennebring

Brief explanation

This abstract describes a method for determining the current and future path of a mobile device based on radio signals between the device and a base station. The future path is predicted using the current path, and a link performance prediction is generated based on the future path and a base station coverage map. The link performance prediction indicates the expected quality of the radio link between the mobile device and the base station in the future.

Abstract

In one embodiment, a current path of a mobile device is determined based on radio signals between the mobile device and a base station, which indicates a sequence of positions of the mobile device over a current time window. A future path of the mobile device is then predicted based on the current path, which indicates a sequence of predicted future positions of the mobile device over a future time window. A link performance prediction (LPP) is then generated for the mobile device based on the future path of the mobile device and a base station coverage map. The base station coverage map indicates a radio signal quality across a base station coverage area, which is represented as a three-dimensional (3D) coordinate space. Moreover, the LPP indicates a predicted performance of a radio link between the mobile device and the base station during the future time window.

APPARATUS, SYSTEM AND METHOD OF COMMUNICATING A PHYSICAL LAYER PROTOCOL DATA UNIT (PPDU) INCLUDING A TRAINING FIELD (17972200)

Inventor Artyom Lomayev

Brief explanation

This abstract describes various apparatuses, devices, systems, and methods for communicating a PPDU (Physical Protocol Data Unit) that includes a training field. Specifically, it discusses an Enhanced Directional Multi-Gigabit (DMG) wireless communication station that can determine Orthogonal Frequency Division Multiplexing (OFDM) Training (TRN) sequences in the frequency domain based on the number of 2.16 Gigahertz (GHz) channels in a channel bandwidth. It can then generate OFDM TRN waveforms in the time domain based on these sequences and an OFDM TRN mapping matrix. Finally, it can transmit an OFDM mode transmission of the EDMG PPDU over the channel bandwidth, including the TRN field based on the generated OFDM TRN waveforms.

Abstract

Some demonstrative embodiments include apparatuses, devices, systems and methods of communicating a PPDU including a training field. For example, an Enhanced Directional Multi-Gigabit (DMG) (EDMG) wireless communication station may be configured to determine one or more Orthogonal Frequency Division Multiplexing (OFDM) Training (TRN) sequences in a frequency domain based on a count of one or more 2.16 Gigahertz (GHz) channels in a channel bandwidth for transmission of an EDMG PPDU including a TRN field; generate one or more OFDM TRN waveforms in a time domain based on the one or more OFDM TRN sequences, respectively, and based on an OFDM TRN mapping matrix, which is based on a count of the one or more transmit chains; and transmit an OFDM mode transmission of the EDMG PPDU over the channel bandwidth, the OFDM mode transmission comprising transmission of the TRN field based on the one or more OFDM TRN waveforms.

SCS ID MAPPINGS TO MLD LINKS (17953074)

Inventor Laurent Cariou

Brief explanation

This abstract describes methods, devices, and computer media for identifying a stream classification service (SCS) in a wireless local area network (WLAN) with multiple links. The apparatuses discussed are non-access points or stations of a multi-link device (MLD). These apparatuses are equipped with processing circuitry that can encode a SCS request frame, which includes a quality of service (QoS) element. The QoS element contains a subfield called LinkID that indicates a specific LinkID. The SCS request frame also includes a subfield called SCSID, which indicates a SCSID to be associated with the LinkID. The processing circuitry can also decode a SCS response frame from another MLD, which indicates whether the LinkID is mapped to the SCSID.

Abstract

Methods, apparatuses, and computer readable media for stream classification service (SCS) identification to multi-link device (MLD) link in wireless local area network (WLAN) are disclosed. Apparatuses of a non-access point (AP) or station (STA) of a MLD are disclosed, where the apparatuses comprise processing circuitry configured to: encode for transmission, to a second MLD, a stream classification service (SCS) request frame, the SCS comprising a quality of service (QoS) element, the QoS element comprising a link identification (LinkID) subfield indicating a LinkID, where the SCS request frame comprises a SCS identification (ID)(SCSID) subfield, the SCSID subfield indicating a SCSID to be mapped to the LinkID and further configured to decode, from the second MLD, a SCS response frame to the SCS request frame, the SCS request frame indicating whether the LinkID is mapped to the SCSID.

APPARATUS, SYSTEM, AND METHOD OF PEER-TO-PEER (P2P) COMMUNICATION (18091023)

Inventor Emily H. Qi

Brief explanation

The abstract describes a process for establishing a secure wireless connection between two devices. The first device determines a method for establishing the connection based on messages exchanged with the second device. Once the method is determined, the first device pairs with the second device and creates a secure key for communication. This key is then used to encrypt peer-to-peer communication between the two devices.

Abstract

For example, a first wireless communication device may be configured to determine a negotiated bootstrapping mechanism based on a first message-exchange including Peer-to-Peer (P2P) messages exchanged with a second wireless communication device; to pair the first wireless communication device with the second wireless communication device according to the negotiated bootstrapping mechanism; to derive a Pairwise Master Key Security Association (PMKSA) based on a second message-exchange with the second wireless communication device, e.g., after pairing with the second wireless communication device; and to determine an encryption key according to a third message exchange with the second wireless communication device based on the PMKSA. For example, the encryption key may be configured to encrypt a P2P communication with the second wireless communication device.

COMPUTING WORKLOAD MANAGEMENT IN NEXT GENERATION CELLULAR NETWORKS (18007898)

Inventor Zongrui DING

Brief explanation

The abstract discusses the concept of augmented computing as a service or network capability for 6G networks. It mentions the operation of a compute control client (Comp CC) at the user equipment (UE) side, and a compute control function (Comp CF) and compute service function (Comp SF) at the network side. These functions are referred to as "compute plane" functions and are responsible for handling computing-related control and user traffic.

Abstract

Various embodiments generally may relate to the field of wireless communications. For example, some embodiments may relate to enabling augmented computing as a service or network capability for sixth-generation (6G) networks. For example, some embodiments may be directed to the operation of a compute control client (Comp CC) at the UE side, and a compute control function (Comp CF) and compute service function (Comp SF) at the network side, which are referred to herein as “compute plane” functions to handle computing related control and user traffic.

DETECTION OF LTE ENB AND UE EMITTERS USING SIGNAL PROCESSING ALGORITHMS FOR FEATURE RECOGNITION (17705611)

Inventor Maya Mani

Brief explanation

The abstract describes an apparatus and system that can determine and identify different communication signals. It does this by analyzing the characteristics of the received signals, such as their waveform. Statistical and/or Cyclostationary Signal Processing algorithms are used to analyze these characteristics and identify each signal as a communication signal with a specific protocol. The system uses various techniques like autocorrelation, spectral correlation, and power Cepstrum to identify the signal based on its periodic characteristics in the frequency domain. Additionally, the system can also identify rogue devices that do not follow the expected protocol and take appropriate actions.

Abstract

An apparatus and system for determining and identifying communication signals are described. Characteristics of the waveform for received signals are determined. Statistical and/or Cyclostationary Signal Processing algorithms are used on the characteristics to identify each signals as a communication signal having a particular protocol. Autocorrelation, spectral correlation, and power Cepstrum, among others, are used to identify the signal using periodic characteristics of the waveform in the frequency domain. Rogue devices that do not adhere to the protocol are identified and actions taken accordingly.

WIRELESS COMMUNICATION SYSTEMS (18173100)

Inventor Anshu AGARWAL

Brief explanation

The abstract describes a wireless station that has processors. These processors are responsible for determining when data needs to be transferred and what type of data it is. If the data is determined to be a priority data type, the processors will send a signal indicating this. They will then receive a confirmation signal in response. Based on this confirmation, the processors will create a dedicated connection with a network device and instruct the data to be transferred through this connection.

Abstract

A wireless station may include one or more processors. The one or more processors may determine data is to be transferred. The one or more processors may also determine a data type of the data corresponds to a priority data type. In addition, the one or more processors may provide a data type signal indicating the data type corresponds to the priority data type. Further, the one or more processors may receive a data type confirmation signal in response to the data type signal. The one or more processors may create a dedicated bearer with a network device based on the data type confirmation signal. The one or more processors may also instruct the data to be transferred via the dedicated bearer.

METHODS AND DEVICES TO ESTABLISH AND MAINTAIN CONNECTIONS WITH MULTIPLE COMMUNICATION DEVICES (18161894)

Inventor Harish MITTY

Brief explanation

This abstract describes a communication device that can establish a connection with peripheral devices when it gets disconnected from an external communication device. It can determine if the external device is connectable based on radio signals received from it. If it is connectable, the device encodes a message to be sent to the peripheral devices, instructing them to perform a high duty cycle advertising using Bluetooth communication protocol.

Abstract

A communication device may include a processor configured to establish a connection with one or more peripheral devices in response to a disconnection from an external communication device, determine that the external communication device is connectable based on radio communication signals received from the external communication device, and encode a message to be transmitted to the one or more peripheral devices in response to the determination that the external communication device is connectable, wherein the message is configured to cause the one or more peripheral devices to perform a high duty cycle advertising in accordance with a Bluetooth communication protocol.

METAL ORGANIC FRAMEWORKS (MOFS) FILLER FOR ENABLING LOW CTE AND LOW DIELECTRIC CONSTANT PCB (17703704)

Inventor Yang JIAO

Brief explanation

The abstract describes an electronic package that includes a printed circuit board (PCB) made of a combination of glass weave, resin, and metal organic frameworks (MOFs) embedded in the resin. The PCB is connected to a package substrate, and a die is connected to the package substrate.

Abstract

Embodiments disclosed herein include an electronic package. In an embodiment, the electronic package comprises a printed circuit board (PCB), where the PCB comprises a glass weave, a resin, and metal organic frameworks (MOFs) disposed within the resin. In an embodiment, a package substrate is coupled to the PCB, and a die is coupled to the package substrate.

MIRROR-CORE MOUNTING MULTIPLE COMPUTER PROCESSOR MODULES FOR MINIMIZED TRACE LENGTH (17703717)

Inventor Carl WILLIAMS

Brief explanation

The abstract describes a computer system that includes a printed circuit board assembly (PCBA) with two surfaces. On one surface, there is a computer processor module, and on the other surface, there is another computer processor module. These two modules are connected through an electrical path that goes through the thickness of the PCBA.

Abstract

Embodiments disclosed herein include a computer system. In an embodiment, the computer system comprises a printed circuit board assembly (PCBA) with a first surface and a second surface opposite from the first surface. In an embodiment, a first computer processor module is coupled to the first surface of the PCBA, and a second computer processor module is coupled to the second surface of the PCBA. In an embodiment, the first computer processor module is communicatively coupled to the second computer processor module through an electrical path that passes through a thickness of the PCBA.

FLOW ENHANCEMENT STRUCTURE FOR IMMERSION COOLED ELECTRONIC SYSTEMS (18203904)

Inventor Liguang DU

Brief explanation

The abstract describes an apparatus that is designed to improve the flow of immersion bath liquid through the spaces between fins and across the base of a heat sink. This apparatus includes a flow enhancement structure that helps to enhance the flow of the liquid, potentially improving the cooling efficiency of the heat sink.

Abstract

An apparatus is described that includes a flow enhancement structure to enhance a flow of immersion bath liquid specifically through space between fins of a heat sink and/or across a base of a heat sink.