Intel Corporation patent applications published on September 21st, 2023

METHOD AND APPARATUS FOR REMOVING LASER DEBOND RESIDUE FROM SUBSTRATE (17698024)

Abstract

A method includes forming a solvent on a stage, and placing, on the solvent formed on the stage, a bottom surface of a substrate on which a residue is formed, so that the residue moves away from the bottom surface of the substrate into the solvent. The method further includes removing the substrate from the solvent into which the residue is moved.

Inventor

Jeremy ECTON

NON-DESTRUCTIVE GAP METROLOGY (17696980)

Abstract

The present disclosure is directed to a metrology system having 3-dimensional sensors for thickness measurements of semiconductor elements, and methods for taking the thickness measurements. In an aspect, the 3-dimensional sensor may be a single or dual 3-dimensional profiler that may scan across the top and bottom surfaces of an element to obtain a thickness measurement. In another aspect, the method may be used to measure a gap between elements that have assembled together.

Inventor

Jianyong MO

ON-CHIP DIGITALLY CONTROLLED ERROR RATE-LOCKED LOOP FOR ERROR RESILIENT EDGE ARTIFICIAL INTELLIGENCE (17695158)

Abstract

Embodiments herein relate to a neural network processor in a control loop, where the control loop sets an optimum supply voltage for the processor based on a measured error count or rate of the neural network. For example, if the measured error count is greater than a target level or range, the supply voltage can be increased. If the measured error count is below the target level or range, the supply voltage can be decreased. The error rate can be measured by providing an error detection circuit for one or more monitored nodes/processing units of a neural network. The error detection circuit can receive the same input data as the associated monitored processing unit, but operates on only a portion of the input data.

Inventor

Hechen WANG

GRANULAR GPU DVFS WITH EXECUTION UNIT PARTIAL POWERDOWN (18185008)

Abstract

Described herein, in one embodiment, are techniques to facilitate the partial powerdown of sub-components of an execution unit or other graphics processing resource based on the workload to be executed. In another embodiment, granular dynamic voltage and frequency scaling is enabled in which the voltage and frequency of groups of processing resources within a graphics processor can be separately scaled.

Inventor

Kenneth Daxer

FUSED MULTIPLE MULTIPLICATION AND ADDITION-SUBTRACTION INSTRUCTION SET (17695554)

Abstract

An embodiment of an apparatus comprises decode circuitry to decode a single instruction, the single instruction to include respective fields for one or more source operands, one or more destination operands, and an opcode, the opcode to indicate execution circuitry is to perform a fused multiple multiplication and addition-subtraction operation, and execution circuitry to execute the decoded instruction according to the opcode to retrieve data from one or more locations indicated by the one or more source operands, to perform the fused multiple multiplication and addition-subtraction indicated by the opcode on four or more arguments indicated by the retrieved data to produce one or more results. Other embodiments are disclosed and claimed.

Inventor

Fabian Boemer

INSTRUCTION AND LOGIC FOR SYSTOLIC DOT PRODUCT WITH ACCUMULATE (18307088)

Abstract

Embodiments described herein provided for an instruction and associated logic to enable GPGPU program code to access special purpose hardware logic to accelerate dot product operations. One embodiment provides for a graphics processing unit comprising a fetch unit to fetch a single instruction for execution, a decode unit to decode the single instruction into a decoded instruction, wherein the decoded instruction is to cause the graphics processing unit to perform a set of parallel dot product operations on elements of input matrices, and a systolic dot product unit to execute the decoded instruction across one or more parallel processor lanes using multiple systolic layers associated with multiple pipeline stages. The multiple pipeline stages include one or more sets of interconnected multipliers and adders to compute multiple concurrent dot products.

Inventor

SUBRAMANIAM MAIYURAN

MULTIPLE OPERATION FUSED ADDITION AND SUBTRACTION INSTRUCTION SET (17695533)

Abstract

An embodiment of an apparatus comprises decode circuitry to decode a single instruction, the single instruction to include respective fields for one or more source operands, one or more destination operands, and an opcode, the opcode to indicate execution circuitry is to perform a fused addition and subtraction operation, and execution circuitry to execute the decoded instruction according to the opcode to retrieve data from one or more locations indicated by the one or more source operands, to perform the fused addition and subtraction operation indicated by the opcode on three or more arguments indicated by the retrieved data to produce one or more results. Other embodiments are disclosed and claimed.

Inventor

Fabian Boemer

DEVICE VIRTUALIZATION IN A CONFIDENTIAL COMPUTING ENVIRONMENT (18200458)

Abstract

Examples described herein relate to a trusted and secure emulated device. The emulated device can be assigned to a service based on attestation of a hardware platform of the emulated device, assignment of the emulated device to a trust domain, and attestation of a device configuration associated with the emulated device.

Inventor

Kapil SOOD

APPARATUS AND METHOD FOR SCHEDULING INFERENCE TASKS (17699058)

Abstract

Apparatus and method for scheduling inference tasks. For example, one embodiment of an apparatus comprises: a plurality of compute units (CUs) to execute inferencing routines, an inferencing routine comprising a plurality of phases, at least one CU comprising execution circuitry configurable to operate in a single instruction multiple data (SIMD) mode or a single instruction multiple thread (SIMT) mode; and dispatching hardware logic to determine whether a current phase of an inferencing routine is to be executed in the SIMD mode or the SIMT mode, and to dispatch instructions of the current phase for execution by the execution circuitry of a CU in accordance with the SIMD mode or the SIMT mode, respectively.

Inventor

PAWEL MAJEWSKI

LOAD STORE BANK AWARE THREAD SCHEDULING TECHNIQUES (17699992)

Abstract

Bank aware thread scheduling and early dependency clearing techniques are described herein. In one example, bank aware thread scheduling involves arbitrating and scheduling threads based on the cache bank that is to be accessed by the instructions to avoiding bank conflicts. Early dependency clearing involves clearing dependencies for cache loads in a scoreboard before the data is loaded. In early dependency clearing for loads, delays in operation can be reduced by clearing dependencies before data is required from the cache.

Inventor

Abhishek R. APPU

HARD PARTITIONING VIA INTRA-SOC COMPOSITION (17827346)

Abstract

Described herein is a partitional graphics processor having multiple hard partitions with separate software execution and fault domains. One embodiment provides a graphics processor comprising a system interface and a plurality of graphics processing resources coupled with the system interface. The plurality of graphics processing resources is configurable to be partitioned into a plurality of isolated device partitions, each isolated device partition configured for fault isolation and independent concurrent execution of workloads associated with a plurality of clients, and the system interface is configured to present each of the plurality of isolated device partitions as a virtual function.

Inventor

David Cowperthwaite

SYSTEM, APPARATUS AND METHOD FOR PROVIDING HARDWARE STATE FEEDBACK TO AN OPERATING SYSTEM IN A HETEROGENEOUS PROCESSOR (18322636)

Abstract

In one embodiment, a processor includes a power controller having a resource allocation circuit. The resource allocation circuit may: receive a power budget for a first core and at least one second core and scale the power budget based at least in part on at least one energy performance preference value to determine a scaled power budget; determine a first maximum operating point for the first core and a second maximum operating point for the at least one second core based at least in part on the scaled power budget; determine a first efficiency value for the first core based at least in part on the first maximum operating point for the first core and a second efficiency value for the at least one second core based at least in part on the second maximum operating point for the at least one second core; and report a hardware state change to an operating system scheduler based on the first efficiency value and the second efficiency value. Other embodiments are described and claimed.

Inventor

Praveen Kumar Gupta

FLEXIBLE PARTITIONING OF GPU RESOURCES (17827373)

Abstract

Described herein is a partitionable graphics processor having a plurality of flexibly partitioned processing resources. One embodiment provides a graphics processor comprising a plurality of processing resources configurable to be flexibly partitioned into a plurality of resource partitions and circuitry to compose multiple graphics processor device partitions from the plurality of resource partitions. The multiple graphics processor device partitions are configurable to be asymmetrically composed of different types of functional units.

Inventor

David Cowperthwaite

APPARATUS AND METHOD FOR HARDWARE-ACCELERATED TEXTURE LOOKUP AND INTERPOLATION (17699067)

Abstract

Embodiments of the invention include acceleration hardware for performing texture lookups and for interpolation for textures backed by hashed memory layouts. In particular, on a texel fetch, a special texture addressing mode allows integer texel coordinates to be hashed and combined with dedicated hardware, to arrive at a pseudo-random memory address for each texel within the memory block allocated to back the respective sampled texture.

Inventor

TOBIAS ZIRR

CACHE STREAMING APPARATUS AND METHOD FOR DEEP LEARNING OPERATIONS (17699062)

Abstract

A cache streaming apparatus and method for machine learning. For example, one embodiment of an apparatus comprises: a plurality of compute units to perform machine learning operations; a cache subsystem comprising a hierarchy of cache levels, at least some of the cache levels shared by two or more of the plurality of compute units; and data streaming hardware logic to stream machine learning data in and out of the cache subsystem based on the machine learning operations, the data streaming hardware logic to load data into the cache subsystem from memory before the data is needed by a first portion of the machine learning operations and to ensure that results produced by the first portion of machine learning operations are maintained in the cache subsystem until used by a second portion of the machine learning operations.

Inventor

Prasoonkumar SURTI

TECHNIQUES FOR COMMAND BUS TRAINING TO A MEMORY DEVICE (18134920)

Abstract

Techniques for command bus training to a memory device includes triggering a memory device to enter a first or a second command bus training mode, outputting a command/address (CA) pattern via a command bus and compressing a sampled CA pattern returned from the memory device based on whether the memory device was triggered to be in the first or the second command bus training mode.

Inventor

Christopher P. MOZAK

SCALABLE I/O VIRTUALIZATION INTERRUPT AND SCHEDULING (17832305)

Abstract

Embodiments described herein provide techniques to facilitate scalable interrupts and workload submission for a virtualized graphics processor. The techniques include memory-based interrupt reporting and shared work queue submission for multiple software domains.

Inventor

David Puffer

Programmable Spatial Array for Matrix Decomposition (18017077)

Abstract

Programmable spatial array processing circuitry may be programmable to perform multiple different types of matrix decompositions. The programmable spatial array processing circuitry may include an array of processing elements. When programmed with a first instructions, the array performs a first type of matrix decomposition. When programmed with second instructions, the array performs a second type of matrix decomposition. Individual processing elements of the programmable spatial array processing circuitry may avoid having individual instruction memories. Instead, there may be an instruction memory that provides a portion of the first instructions or a portion of the second instructions sequentially to one processing element of a row of processing elements to sequentially propagate to other processing elements of the row of processing elements.

Inventor

Long Jiang

ROLLBACK OF PROCESSOR MICROCODE UPDATES IN RUNTIME WITHOUT SYSTEM REBOOT (17695817)

Abstract

Techniques for updates and rollbacks of firmware patches in a computing system during runtime are provided. A processor includes one or more intellectual property (IP) blocks; a secure patch memory to store a first firmware patch in a primary patch region and a second firmware patch in a secondary patch region; a processing core to execute a first patch commit instruction; and a security controller to send the second firmware patch to the one or more IP blocks, set the secondary patch region to the primary patch region when the first patch commit instruction indicates the second firmware patch is valid, and get the first firmware patch from the primary patch region and send the first firmware patch to the one or more IP blocks when the first patch commit instruction indicates the second firmware patch is invalid.

Inventor

Pratim Bose

TECHNOLOGIES FOR FILTERING MEMORY ACCESS TRANSACTIONS RECEIVED FROM ONE OR MORE I/O DEVICES (18200543)

Abstract

Technologies for secure I/O include a compute device having a processor, a memory, an input/output (I/O) device, and a filter logic. The filter logic is configured to receive a first key identifier from the processor, wherein the first key identifier is indicative of a shared memory range includes a shared key identifier range to be used for untrusted I/O devices and receive a transaction from the I/O device, wherein the transaction includes a second key identifier and a trust device ID indicator associated with the I/O device. The filter logic is further configured to determine whether the transaction is asserted with the trust device ID indicator indicative of whether the I/O device is assigned to a trust domain and determine, in response to a determination that the transaction is not asserted with the trust device ID indicator, whether the second key identifier matches the first key identifier.

Inventor

Luis Kida

ENABLING SECURE STATE-CLEAN DURING CONFIGURATION OF PARTIAL RECONFIGURATION BITSTREAMS ON FPGA (18300622)

Abstract

An apparatus to facilitate enabling secure state-clean during configuration of partial reconfiguration bitstreams on accelerator devices is disclosed. The apparatus includes a security engine to perform, as part of a PR configuration sequence for a new partial reconfiguration (PR) persona corresponding to a PR bitstream, a first clear operation to clear previously-set persona configuration bits in the region; perform, as part of the PR configuration sequence subsequent to the first clear operation, a set operation to set new persona configuration bits in the region; and perform, as part of the PR configuration sequence, a second clear operation to clear memory blocks of the region that became unfrozen subsequent to the set operation.

Inventor

Alpa Trivedi

PROCESSOR ARRAY FOR PROCESSING SPARSE BINARY NEURAL NETWORKS (18201291)

Abstract

An apparatus is described. The apparatus includes a circuit to process a binary neural network. The circuit includes an array of processing cores, wherein, processing cores of the array of processing cores are to process different respective areas of a weight matrix of the binary neural network. The processing cores each include add circuitry to add only those weights of an i layer of the binary neural network that are to be effectively multiplied by a non zero nodal output of an i−1 layer of the binary neural network.

Inventor

Ram KRISHNAMURTHY

MULTI-RENDER PARTITIONING (17827444)

Abstract

Described herein is a partitionable graphics processor having multiple render front ends. The partitions of the graphics processor maintain render functionality when partitioned and enable fault isolation and independent multi-client rendering.

Inventor

Hema Chand Nalluri

NODE PREFETCHING IN A WIDE BVH TRAVERSAL WITH A STACK (17699059)

Abstract

Apparatus and method for prefetching node data. For example, one embodiment of an apparatus comprises: ray tracing acceleration hardware to manage active ray tracing stack allocations within a traversal stack; and stack management hardware logic to issue a prefetch operation comprising an indication of bounding volume hierarchy (BVH) node data to be prefetched and an indication of a cache level, wherein responsive to performing the prefetch operation, the BVH node data is to be prefetched to the indicated cache level.

Inventor

Sven Woop

APPARATUS AND METHOD FOR BIASED BVH TRAVERSAL PATH (17699066)

Abstract

Apparatus and method for a biased BVH traversal path. For example, one embodiment of an apparatus comprises: ray tracing traversal hardware logic to traverse a ray through nodes of a bounding volume hierarchy (BVH); and stack management hardware logic to push and pop entries on a traversal stack, each entry corresponding to a node of the BVH, wherein the ray tracing traversal hardware logic is to determine an order in which to push entries to the traversal stack based on both a first intersection value corresponding to a closest intersection point between the ray and a BVH node and a farthest intersection value between the ray and the BVH node. In addition, the ray traversal hardware logic may determine the order in which to push the entries to the traversal stack further based on a probability density value corresponding to a probability of a ray hitting geometry inside of the BVH.

Inventor

Joshua Barczak

LOCAL MEMORY TRANSLATION TABLE (17849106)

Abstract

Embodiments described herein provide techniques to facilitate access to local memory of a graphics processor by a guest software domain. The guest software domain can access the local memory via an address translation system that includes a local memory translation table.

Inventor

David Puffer

LOCAL MEMORY TRANSLATION TABLE ACCESSED AND DIRTY FLAGS (17849165)

Abstract

Embodiments described herein provide techniques to facilitate access to local memory of a graphics processor by a guest software domain. The guest software domain can access the local memory via an address translation system that includes a local memory translation table. In one embodiment, accessed and/or dirty bits are enabled in the local memory translation table, which may be used to accelerate the GPU local memory portion of VM Migration for a VM that includes a vGPU.

Inventor

David Puffer

APPARATUS AND METHODS FOR THREE-DIMENSIONAL POSE ESTIMATION (18000389)

Abstract

Apparatus and methods for three-dimensional pose estimation are disclosed herein. An example apparatus includes an image synchronizer to synchronize a first image generated by a first image capture device and a second image generated by a second image capture device, the first image and the second image including a subject; a two-dimensional pose detector to predict first positions of keypoints of the subject based on the first image and by executing a first neural network model to generate first two-dimensional data and predict second positions of the keypoints based on the second image and by executing the first neural network model to generate second two-dimensional data; and a three-dimensional pose calculator to generate a three-dimensional graphical model representing a pose of the subject in the first image and the second image based on the first two-dimensional data, the second two-dimensional data, and by executing a second neural network model.

Inventor

Shandong Wang

APPARATUS AND METHOD FOR ACCELERATING BVH BUILDS BY MERGING BOUNDING BOXES (17699060)

Abstract

Apparatus and method for accelerating bounding box merge operations. For example, one embodiment of an apparatus comprises: ray tracing acceleration hardware to be used to determine ray traversal results when traversing a ray through a bounding volume hierarchy (BVH), the BVH comprising a plurality of axis-aligned bounding boxes (AABBs); and a bounding box (BB) merge accelerator coupled to one or more execution units and coupled to a local memory in which to store a group of the AABBs, the BB merge accelerator, in response to the one or more EUs, to determine a second AABB to merge with a first AABB in accordance with a specified distance function.

Inventor

Carsten BENTHIN

APPARATUS AND METHOD FOR ACCELERATION DATA STRUCTURE RE-BRAIDING WITH CAMERA POSITION (17699064)

Abstract

Apparatus and method for camera-aware BVH re-braiding. For example, one embodiment of an apparatus comprises: ray tracing acceleration hardware to be used to determine ray traversal results when traversing a ray through a bounding volume hierarchy (BVH); and BVH processing hardware logic to modify the BVH to reduce spatial overlap between one or more BVH subtrees based on a detected camera position to produce a modified BVH.

Inventor

Carsten BENTHIN

OUT-OF-DISTRIBUTION DETECTION USING A NEURAL NETWORK (18325436)

Abstract

Features extracted from one or more layers of a trained deep neural network (DNN) are used to detect out-of-distribution (OOD) data, such as anomalies. An OOD detection process includes transforming a feature output from a layer of the DNN from a relatively high-dimensional feature space to a lower-dimensional space, and then performing a reverse transformation back to the higher-dimensional feature space, resulting in a reconstructed feature. A feature reconstruction error is calculated based on a difference between the reconstructed feature and the original feature output from the DNN. The OOD detection process may further include calculating a score based on the feature reconstruction error and generating a visual representation of the feature reconstruction error.

Inventor

Ibrahima Ndiour

GENERATION AND TRANSMISSION OF VULNERABLE ROAD USER AWARENESS MESSAGES (17916731)

Abstract

The present disclosure is related to Intelligent Transport Systems (ITS), and in particular, to Vulnerable Road User (VRU) basic services (VBS) of a VRU ITS Station (ITS-S). Different arrangements and configurations of the VBS within the facilities layer of an ITS-S are described. Also described are different rules and/or conditions for VRU Awareness Message (VAM) formats, VAM generation and coding, and VAM dissemination.

Inventor

Satish C. JHA

AERIAL VEHICLE, DEVICE TO DETERMINE A TARGET LOCATION, STATIC BASE STATION DEVICE AND DOCKING STATION FOR A VEHICLE (17975653)

Abstract

Various aspects of this disclosure provide an aerial vehicle. The aerial vehicle may include a flight controller configured to control flight components of the aerial vehicle, and a radio access network base station radio head configured to allocate one or more radio resources for one more radio communication terminal devices to operate a radio cell in accordance with a mobile radio wide area network technology.

Inventor

Kedar VISWANATHAN

MICROELECTRONIC ASSEMBLIES INCLUDING STIFFENERS AROUND INDIVIDUAL DIES (17699139)

Abstract

Disclosed herein are microelectronic assemblies, as well as related apparatuses and methods. In some embodiments, a microelectronic assembly may include a substrate; a lid surrounding an individual die, wherein the lid includes a planar portion and two or more sides extending from the planar portion, and wherein the individual die is electrically coupled to the substrate by interconnects; and a material surrounding the interconnects and coupling the two or more sides of the lid to the substrate.

Inventor

Pouya Talebbeydokhti

MICROELECTRONIC STRUCTURE INCLUDING CONDUCTIVE POLYMER IN TRENCHES OF A CORE SUBSTRATE, AND METHOD OF MAKING SAME (17699031)

Abstract

A microelectronic structure and a method of forming same. The microelectronic structure includes: a core substrate including one of a glass material or an organic material, and defining a plurality of trenches therein; electrically conductive vias extending within the trenches, the vias to provide electrical coupling through the core substrate to semiconductor packages to be attached to the core substrate, individual ones of the vias including: a trench liner adjacent walls of a corresponding one of the plurality of trenches, the trench liner including an electrically conductive polymer material having double carbon bonds; and a metal structure on the trench liner.

Inventor

Shayan Kaviani

MICROELECTRONIC ASSEMBLIES INCLUDING STIFFENERS (17698322)

Abstract

Disclosed herein are microelectronic assemblies, as well as related apparatuses and methods. In some embodiments, a microelectronic assembly may include a substrate having a first surface and an opposing second surface; a die electrically coupled to the second surface of the substrate; and a stiffener attached to the first surface of the substrate configured to mitigate warpage of the die.

Inventor

Mohan Prashanth Javare Gowda

MICROELECTRONIC ASSEMBLIES INCLUDING STIFFENERS (17698365)

Abstract

Disclosed herein are microelectronic assemblies, as well as related apparatuses and methods. In some embodiments, a microelectronic assembly may include a substrate; and a microelectronic subassembly electrically coupled to the substrate by interconnects, the microelectronic subassembly including an interposer having a surface; a first die electrically coupled to the surface of the interposer; a second die electrically coupled to the surface of the interposer; and a stiffener ring coupled to the surface of the interposer along the perimeter of the interposer.

Inventor

Abdallah Bacha

MICROELECTRONIC ASSEMBLIES INCLUDING STIFFENERS (17698430)

Abstract

Disclosed herein are microelectronic assemblies, as well as related apparatuses and methods. In some embodiments, a microelectronic assembly may include a substrate, including a core and a stiffener in the core, wherein the stiffener is along a perimeter of the core; and a die electrically coupled to the substrate.

Inventor

Abdallah Bacha

BUMPING FOR LIQUID METAL SOCKET INTERCONNECTS (17696162)

Abstract

In one embodiment, an integrated circuit apparatus comprises a substrate that includes electrical contacts on a first side of the substrate to couple the substrate to an integrated circuit die, a passivation layer on a second side of the substrate opposite the first side, metal pads on the second side of the substrate and within openings defined by the passivation layer, and solder bumps on the metal pads. The solder bumps are a material that is resistant to Gallium-based liquid metal embrittlement.

Inventor

Jiaqi Wu

MICROELECTRONIC ASSEMBLIES INCLUDING NANOWIRE AND SOLDER INTERCONNECTS (17699209)

Abstract

Disclosed herein are microelectronic assemblies, as well as related apparatuses and methods. In some embodiments, a microelectronic assembly may include a die having a first conductive contact on a surface; a substrate having a second conductive contact on a surface; and an interconnect electrically coupling the first conductive contact of the die and the second conductive contact of the substrate, wherein the interconnect includes a portion of a nanowire on the second conductive contact and an intermetallic compound (IMC) surrounding at least a portion of the nanowire on the second conductive contact.

Inventor

Bernd Waidhas

METHOD OF ATOMIC DIFFUSION HYBRID BONDING AND APPARATUS MADE FROM SAME (17699024)

Abstract

A microelectronic assembly and a method of forming same. The assembly includes: first and second microelectronic structures; and an interface layer between the two microelectronic structures including dielectric portions in registration with dielectric layers of each of the microelectronic structures, and electrically conductive portions in registration with electrically conductive structures of each of the microelectronic structures, wherein the dielectric portions include an oxide of a metal, and the electrically conductive portions include the metal.

Inventor

Jay Prakash Gupta

PACKAGING ARCHITECTURE WITH THERMALLY CONDUCTIVE INTEGRATED CIRCUIT BRIDGE (17698282)

Abstract

Embodiments of a microelectronic assembly comprises a first layer, a second layer and a third layer in a stack; a package substrate in the first layer, the package substrate comprising a metallic via structure; a first integrated circuit (IC) die surrounded by an organic dielectric material in the second layer, the first IC die coupled to the package substrate; a second IC die in the third layer, the second IC die coupled to the first IC die; and a third IC die in the third layer, the third IC die coupled to the first IC die. An electrically conductive pathway in the first IC die electrically couples the third IC die and the second IC die, and the first IC die is coupled to the package substrate with a thermally conductive material in contact with the metallic via structure in the package substrate.

Inventor

Bernd Waidhas

PASSIVE ELECTRICAL COMPONENTS IN MOLD METAL LAYERS OF A MULTI-DIE COMPLEX (17698928)

Abstract

In one embodiment, a multi-die complex includes a mold material, first and second integrated circuit dies within the mold material, and one or more metal layers within the mold material. One or more passive electrical components, e.g., an inductor, a capacitor, or RF shielding, are formed at least partially within the metal layers.

Inventor

Andrew P. Collins

MICROELECTRONIC STRUCTURE INCLUDING ACTIVE BASE SUBSTRATE WITH THROUGH VIAS BETWEEN A TOP DIE AND A BOTTOM DIE SUPPORTED ON AN INTERPOSER (17699028)

Abstract

A microelectronic component and a method of forming same. The microelectronic component includes: a first substrate having first through vias therein, the first substrate including silicon or glass; a first layer on a front surface of the first substrate and including one or more first dies coupled to the first through vias; a second substrate on a front surface of first layer and having second through vias therein and including silicon or glass; a second layer on a front surface of the second substrate, the first layer between the first substrate and the second substrate, the second layer including one or more second dies coupled to the second through vias; and electrically conductive structures on a back surface of the first substrate coupled to the first through vias.

Inventor

Nitin A. Deshpande

FABRICATION OF GATE-ALL-AROUND INTEGRATED CIRCUIT STRUCTURES HAVING PRE-SPACER-DEPOSITION WIDE CUT GATES WITH EXTENSIONS (17695738)

Abstract

Gate-all-around integrated circuit structures having pre-spacer-deposition wide cut gates with extensions are described. For example, an integrated circuit structure includes a first vertical arrangement of horizontal nanowires and a second vertical arrangement of horizontal nanowires. A first gate stack is over the first vertical arrangement of horizontal nanowires, and a second gate stack is over the second vertical arrangement of horizontal nanowires. An end of the second gate stack is spaced apart from an end of the first gate stack by a gap. A first dielectric gate spacer is along an end of the first gate stack in the gap. A second dielectric gate spacer is along an end of the second gate stack in the gap. A dielectric material is between and in lateral contact with the first dielectric gate spacer and the second dielectric gate spacer.

Inventor

Leonard P. GULER

METHODS OF INTEGRATING MULTIPLE GATE DIELECTRIC TRANSISTORS ON A TRI-GATE (FINFET) PROCESS (18140931)

Abstract

Two or more types of fin-based transistors having different gate structures and formed on a single integrated circuit are described. The gate structures for each type of transistor are distinguished at least by the thickness or composition of the gate dielectric layer(s) or the composition of the work function metal layer(s) in the gate electrode. Methods are also provided for fabricating an integrated circuit having at least two different types of fin-based transistors, where the transistor types are distinguished by the thickness and composition of the gate dielectric layer(s) and/or the thickness and composition of the work function metal in the gate electrode.

Inventor

Curtis TSAI

INDUCTORS FOR HYBRID BONDING INTERCONNECT ARCHITECTURES (17698939)

Abstract

In one embodiment, an apparatus includes a first integrated circuit die with metal bonding pads that are co-planar with an external surface of the die and a second integrated circuit die with metal bonding pads that are co-planar with an external surface of the die. The first and second integrated circuit dies are coupled together such that their external surfaces are in contact and the metal pads of the first integrated circuit die are in direct contact with respective metal pads of the second integrated circuit die. The apparatus also includes an inductor formed at least partially by the metal pads of the first integrated circuit die and the metal pads of the second integrated circuit die.

Inventor

Qiang Yu

PARTIAL GATE CUT STRUCTURES IN AN INTEGRATED CIRCUIT (17697129)

Abstract

Techniques are provided herein to form an integrated circuit having any number of partial gate cut structures between adjacent semiconductor devices. Neighboring semiconductor devices each include a semiconductor region extending between a source region and a drain region, and a gate structure extending over the semiconductor regions of the neighboring semiconductor devices. In some such examples, a partial gate cut structure is present between a given pair of neighboring semiconductor devices. The partial gate cut structure acts as a dielectric pillar between the semiconductor structures that allows the conductive gate layer (from the gate structure) to extend above and/or below it such that the gates of each of the semiconductor devices remain electrically coupled together. The gate cut structure itself removes a portion of the gate layer from between the semiconductor devices, thus reducing parasitic capacitance.

Inventor

Leonard P. Guler

INTEGRATED CIRCUIT STRUCTURES WITH DEEP VIA STRUCTURE (17696115)

Abstract

Integrated circuit structures having deep via structures, and methods of fabricating integrated circuit structures having deep via structures, are described. For example, an integrated circuit structure includes a plurality of horizontally stacked nanowires. A gate structure is over the plurality of horizontally stacked nanowires. An epitaxial source or drain structure is at an end of the plurality of horizontally stacked nanowires. A conductive trench contact structure is vertically over the epitaxial source or drain structure. A conductive via is vertically beneath and extends into the conductive trench contact structure. The conductive via has a first width beneath the epitaxial source or drain structure less than a second width laterally adjacent to the epitaxial source or drain structure.

Inventor

Leonard P. Guler

FABRICATION OF GATE-ALL-AROUND INTEGRATED CIRCUIT STRUCTURES HAVING PRE-SPACER-DEPOSITION WIDE CUT GATES WITH NON-MERGED SPACERS (17695739)

Abstract

Gate-all-around integrated circuit structures having pre-spacer-deposition wide cut gates with non-merged spacers are described. For example, an integrated circuit structure includes a first vertical arrangement of horizontal nanowires and a second vertical arrangement of horizontal nanowires. A first gate stack is over the first vertical arrangement of horizontal nanowires, and a second gate stack is over the second vertical arrangement of horizontal nanowires. An end of the second gate stack is spaced apart from an end of the first gate stack by a gap. A first dielectric gate spacer is along an end of the first gate stack in the gap. A second dielectric gate spacer is along an end of the second gate stack in the gap. A dielectric liner is in lateral contact with and completely surrounded by the first dielectric gate spacer and the second dielectric gate spacer.

Inventor

Leonard P. GULER

DOUBLE-SIDED ULTRA SLIM MODULE CONNECTOR (18202194)

Abstract

A back-to-back ultra-slim module (USM) includes an inline USM (USMi) connector and a top mount USM (USMt) connector. The back-to-back USM assembly can be made as a double-sided module to allow a stacked module configuration to save system area. The stacked module has a USMi module inline with the system board on one side of the system board, and a USMt module vertically offset from the other side of the system board. The stacked module can have a thermal layer between the USMi module and the USMt module.

Inventor

Amarjeet KUMAR

QUADRATURE CHIRP GENERATION (17695868)

Abstract

A system may include a digital front end (DFE). The DFE may be configured to generate a command signal. The system may also include a sweeper. The sweeper may be configured to generate an intermediate in-phase signal, an intermediate quadrature signal, and a LO signal based on the command signal. In addition, the system may include a mixer. The mixer may be configured to generate a mixed in-phase signal based on the intermediate in-phase signal and the LO signal. The mixer may also be configured to generate a mixed quadrature signal based on the intermediate quadrature signal and the LO signal. Further, the system may include an amplifier. The amplifier may be configured to generate an in-phase signal based on the mixed in-phase signal and an amplification setting. The amplifier may also be configured to generate a quadrature signal based on the mixed quadrature signal and the amplification setting.

Inventor

Evgeny SHUMAKER

MICRO-PHOTONICS PARALLEL DATA TRANSMISSION FABRIC AND INTERCONNECT (17700043)

Abstract

A system enables optical communication with direct conversion of the electrical signal into an optical signal with an array of optical sources. The use of the array of optical sources can eliminate the need for a large serializer/deserializer (SERDES). With an array of optical sources, the optical communication can occur at lower power and lower frequency per optical source, with multiple parallel optical sources combining to provide a signal.

Inventor

Joshua B. FRYMAN

NETWORK INTERFACE DEVICE-BASED COMPUTATIONS (18200342)

Abstract

Examples described herein relate to a network interface device. The network interface device can include circuitry that is to: receive a first packet comprising a first packet header and a first packet payload; receive multiple subsequent packets comprising multiple packet headers for respective multiple subsequent packets; update at least one of the multiple packet headers; and construct egress packets. In some examples, the egress packets include respective one of the multiple packet headers and the first packet payload.

Inventor

Helia A. NAEIMI

METHODS AND APPARATUS FOR PERFORMANCE SCALING WITH PARALLEL PROCESSING OF SLIDING WINDOW MANAGEMENT ON MULTI-CORE ARCHITECTURE (18003267)

Abstract

Methods, apparatus, and articles of manufacture have been disclosed for performance scaling with parallel processing of sliding window management on multi-core architecture. An example apparatus includes at least one memory, instructions in the apparatus, and processor circuitry to at least one of execute or instantiate the instructions to partition a packet flow into two or more sub flows based on a packet flow distribution configuration, the two or more sub flows associated respectively with two or more sliding windows that are able to slide in parallel, provide the two or more sub flows to a buffer to schedule distribution of the two or more sub flows, dequeue the two or more sub flows from the buffer to one or more hardware cores, and transmit the two or more sub flows to a destination device.

Inventor

Surekha Peri

APPLICATION-LEVEL NETWORK QUEUEING (18201068)

Abstract

There is disclosed in one example a network interface card (NIC), comprising: an ingress interface to receive incoming traffic; a plurality of queues to queue incoming traffic; an egress interface to direct incoming traffic to a plurality of server applications; and a queuing engine, including logic to: uniquely associate a queue with a selected server application; receive an incoming network packet; determine that the selected server application may process the incoming network packet; and assign the incoming network packet to the queue.

Inventor

Anil Vasudevan

EDGE-CENTRIC TECHNIQUES AND TECHNOLOGIES FOR MONITORING ELECTRIC VEHICLES (18090029)

Abstract

The present disclosure is generally related to connected vehicles, computer-assisted and/or autonomous driving vehicles, Internet of Vehicles (IoV), Intelligent Transportation Systems (ITS), and Vehicle-to-Everything (V2X) technologies, and in particular, to technologies and techniques of a road usage monitoring (RUM) service for monitoring road usage of electric vehicles. The RUM service can be implemented or operated by individual electric vehicles, infrastructure nodes, edge compute nodes, cloud computing services, electric vehicle supply equipment, and/or combinations thereof. Additional RUM aspects may be described and/or claimed.

Inventor

Arvind Merwaday

WIRELESS LOCAL AREA NETWORK ENHANCEMENTS FOR ACCESS TRAFFIC STEERING SWITCHING SPLITTING (17922947)

Abstract

Some embodiments may relate to incorporating RAN measurements when determining traffic distribution for access traffic steering switching splitting (ATSSS) systems. Other embodiments may be disclosed and/or claimed.

Inventor

Meghashree Dattatri KEDALAGUDDE

WIRELESS COMMUNICATION SYSTEMS (17699332)

Abstract

A wireless station may include one or more processors. The wireless station may receive a no wireless fidelity (WiFi) signal indicating a parameter. The wireless station may also provide a scan signal comprising a scan list indicating a WiFi frequency band that a cellular modem is to scan for a WiFi signal based on the parameter. In addition, the wireless station may provide a mode signal based on the no WiFi signal. The mode signal may indicate that a WiFi modem is to enter a low power mode. Further, the wireless station may receive a detect signal indicating that the cellular modem detected the WiFi signal within the WiFi frequency band. The wireless station may provide a wake-up signal configured to cause the WiFi modem to enter an operational mode, the wake-up signal indicating a frequency of the detected WiFi signal.

Inventor

Sajal Kumar DAS

FREQUENCY DOMAIN AGGREGATED PPDU (FA-PPDU) COMPRISING MULTIPLE PHY TYPES (18201252)

Abstract

An access point station (AP) generates a trigger frame (TF) for transmission to two or more non-AP stations (STAs) or groups of STAs. The trigger frame may allocate resource units (RUs) for a trigger-based (TB) transmission to the two or more STAs. The AP may encode the trigger frame to include a Common Info field followed by one or more Special User Info fields. The Common Info field and the one or more Special User Info fields and may be encoded to solicit (i.e., trigger) a trigger-based (TB) Frequency Aggregated Physical layer Protocol Data Unit (PPDU) (FA-PPDU) that includes more than one PPDU of at least two different physical layer (PHY) types from the two or more STAs or groups of STAs. The different PHY types may include high-efficiency (HE), Extremely High Throughput (EHT), Ultra-High Rate (UHR), and UHR+. Accordingly, an AP can trigger a FA-PPDU that includes TB PPDUs of different PHY types.

Inventor

Juan Fang

INTEGRATED CIRCUIT PACKAGES HAVING REDUCED Z-HEIGHT (17699211)

Abstract

Disclosed herein are microelectronic assemblies, as well as related apparatuses and methods. For example, in some embodiments, a microelectronic assembly may include a substrate having a surface including a first cavity; a first die at least partially nested in the first cavity and electrically coupled to the substrate; and a circuit board having a surface including a second cavity, wherein the surface of the substrate is electrically coupled to the surface of the circuit board, and wherein the first die extends at least partially into the second cavity in the circuit board.

Inventor

Jan Proschwitz