Intel Corporation patent applications published on October 5th, 2023
Summary of the patent applications from Intel Corporation on October 5th, 2023
- Intel Corporation has recently filed patents for technologies enabling the scalable readout of spin qubits, integrating superconducting and semiconducting components on a single chip.
- The patents also include an integrated circuit die consisting of layers of magnetoelectric material and monolayer transition metal dichalcogenide, with a magnet placed between them for perpendicular magnetic anisotropy.
- Another patent involves an integrated circuit device with transistors using different types of metallization, including recessed jumper metallization for local connections and reducing the height of SRAM bit-cells.
- Intel has also filed a patent for an apparatus with a bolt and three holes in different components, connected by spring elements, to pull a cooling mass and planar mechanical element closer to a circuit board.
- The organization has filed a patent for an electronic device with two server blades connected to a chassis, featuring a waveguide for communication between their microelectronic packages.
- Another patent describes an apparatus with a multi-slot add-in card having two stacked air movers generating different air flows for cooling.
- Intel has filed a patent for a technology using vias or plated through holes in a substrate to create capacitors, coated with conductive and dielectric materials.
- The patents also include techniques for communication between Non-RT RAN Intelligent Controller and Near-RT RIC, and a process where a UE generates a client identity element for registration and service access.
- Notable applications include scalable readout of spin qubits, improved memory cell height reduction, enhanced cooling apparatus, and efficient communication between RICs.
Contents
- 1 Patent applications for Intel Corporation on October 5th, 2023
- 1.1 MICROBUMP CLUSTER PROBING ARCHITECTURE FOR 2.5D AND 3D DIES (17709487)
- 1.2 TECHNOLOGIES FOR TESTING LIQUID METAL ARRAY INTERCONNECT PACKAGES (17709630)
- 1.3 IN-FIELD LATENT FAULT MEMORY AND LOGIC TESTING USING STRUCTURAL TECHNIQUES (17712100)
- 1.4 CONFIGURABLE BOUNDARY SCAN (17700982)
- 1.5 LASER TRANSMITTER COMPONENT, LIGHT DETECTION AND RANGING SYSTEM, AND COMPUTER READABLE MEDIUM (18165949)
- 1.6 APPARATUSES AND METHODS FOR INSPECTING EMBEDDED FEATURES (17706654)
- 1.7 DESIGNS OF THERMAL INSULATION FOR MICRO-RING RESONATOR (MRR) IN ON-CAVITY PIC (OCPIC) TO ACHIEVE EFFECTIVE THERMAL TUNING (17710690)
- 1.8 TEMPERATURE SENSOR TO ACHIEVE THERMAL STABILIZATION OF MICRO-RING RESONATOR (MRR) IN AN OPEN CAVITY PHOTONIC INTEGRATED CIRCUIT (OCPIC) (17710709)
- 1.9 SELF-DOCKING SELF-ALIGNED OPTICAL PCB CONNECTOR FOR SEMICONDUCTOR PACKAGES (17710669)
- 1.10 APPROACH TO PREVENT PLATING AT V-GROOVE ZONE IN PHOTONICS SILICON DURING BUMPING OR PILLARING (17710725)
- 1.11 UNDERCUT DESIGN WITH A BONDED BASE COVER FOR FRIENDLY ASSEMBLY AND EFFECTIVE THERMAL TUNING OF MICRO-RING RESONATOR (MRR) IN OPEN CAVITY PHOTONIC INTEGRATED CHIPS (OCPIC) (17710703)
- 1.12 ON-CAVITY PHOTONIC INTEGRATED CIRCUIT (OCPIC) TO ACHIEVE THE MOST UNDERCUT REAL ESTATE FOR EFFECTIVE THERMAL TUNING (17710716)
- 1.13 CONFIGURATION OF BASE CLOCK FREQUENCY OF PROCESSOR BASED ON USAGE PARAMETERS (18329492)
- 1.14 HYBRID COMPUTING DEVICE, APPARATUS AND SYSTEM (18196831)
- 1.15 SYSTEM, APPARATUS AND METHOD FOR DYNAMIC THERMAL DISTRIBUTION OF A SYSTEM ON CHIP (18296560)
- 1.16 COMPENSATING FOR HIGH HEAD MOVEMENT IN HEAD-MOUNTED DISPLAYS (18181615)
- 1.17 METHOD AND APPARATUS TO IMPLEMENT AN INTEGRATED CIRCUIT INCLUDING BOTH DYNAMIC RANDOM-ACCESS MEMORY (DRAM) AND STATIC RANDOM-ACCESS MEMORY (SRAM) (17711394)
- 1.18 PROVIDING FINE GRAIN ACCESS TO PACKAGE MEMORY (17708398)
- 1.19 SYNCHRONOUS MICROTHREADING (17712124)
- 1.20 SYNCHRONOUS MICROTHREADING (17712126)
- 1.21 NATIVE SUPPORT FOR EXECUTION OF GET EXPONENT, GET MANTISSSA, AND SCALE INSTRUCTIONS WITHIN A GRAPHICS PROCESSING UNIT VIA REUSE OF FUSED MULTIPLY-ADD EXECUTION UNIT HARDWARE LOGIC (18170696)
- 1.22 APPARATUSES, METHODS, AND SYSTEMS FOR 8-BIT FLOATING-POINT MATRIX DOT PRODUCT INSTRUCTIONS (18313026)
- 1.23 TECHNOLOGY TO SUPPORT BITMAP MANIPULATION OPERATIONS USING A DIRECT MEMORY ACCESS INSTRUCTION SET ARCHITECTURE (18326623)
- 1.24 CIRCUITRY AND METHODS FOR CAPABILITY INFORMED PREFETCHES (17712075)
- 1.25 FORWARD CONDITIONAL BRANCH EVENT FOR PROFILE-GUIDED-OPTIMIZATION (PGO) (17712018)
- 1.26 SYNCHRONOUS MICROTHREADING (17712118)
- 1.27 SYNCHRONOUS MICROTHREADING (17712120)
- 1.28 SYNCHRONOUS MICROTHREADING (17712122)
- 1.29 SYNCHRONOUS MICROTHREADING (17712129)
- 1.30 SYNCHRONOUS MICROTHREADING (17712130)
- 1.31 SYNCHRONOUS MICROTHREADING (17712127)
- 1.32 CIRCUITRY AND METHODS FOR INFORMING INDIRECT PREFETCHES USING CAPABILITIES (17712073)
- 1.33 CONTROL REGISTER SET TO FACILITATE PROCESSOR EVENT BASED SAMPLING (17708933)
- 1.34 VARIABLE-LENGTH INSTRUCTION STEERING TO INSTRUCTION DECODE CLUSTERS (17712139)
- 1.35 MULTICORE PROCESSOR WITH EACH CORE HAVING INDEPENDENT FLOATING POINT DATAPATH AND INTEGER DATAPATH (18312079)
- 1.36 Performance Monitoring Emulation in Translated Branch Instructions in a Binary Translation-Based Processor (17711770)
- 1.37 Systems and Methods for Java Virtual Machine Management (18329576)
- 1.38 SYNCHRONOUS MICROTHREADING (17712121)
- 1.39 FIRMWARE FIRST HANDLING OF A MACHINE CHECK EVENT (17711465)
- 1.40 PLATFORM AND PLATFORM COMPONENT DEBUG BY MULTIPLE DEBUGGING SYSTEMS (18332420)
- 1.41 DYNAMIC INCLUSIVE AND NON-INCLUSIVE CACHING POLICY (17708435)
- 1.42 TWO-STAGE CACHE PARTITIONING (17711471)
- 1.43 CIRCUITRY AND METHODS FOR IMPLEMENTING CAPABILITY-DIRECTED PREFETCHING (17712072)
- 1.44 CACHE ACCESS FABRIC (18207602)
- 1.45 CIRCUITRY AND METHODS FOR IMPLEMENTING MICRO-CONTEXT BASED TRUST DOMAINS (17709867)
- 1.46 METHOD OF RING ALLREDUCE PROCESSING (18250515)
- 1.47 POWER SUPPLY COMMUNICATIONS VIA A SHARED CHANNEL FOR PERFORMANCE MANAGEMENT (17711380)
- 1.48 PROVIDING ISOLATION IN VIRTUALIZED SYSTEMS USING TRUST DOMAINS (18131199)
- 1.49 APPARATUS AND METHOD TO IMPLEMENT HOMOMORPHIC ENCYPTION AND COMPUTATION WITH DRAM (17712097)
- 1.50 MACHINE LEARNING SPARSE COMPUTATION MECHANISM FOR ARBITRARY NEURAL NETWORKS, ARITHMETIC COMPUTE MICROARCHITECTURE, AND SPARSITY FOR TRAINING MECHANISM (18302889)
- 1.51 LOW RANK MATRIX COMPRESSION (18191565)
- 1.52 Providing Orthogonal Subarrays in A Dynamic Random Access Memory (17708448)
- 1.53 METHOD AND APPARATUS TO IMPLEMENT AN INTEGRATED CIRCUIT TO OPERATE BASED ON DATA ACCESS CHARACTERISTICS (17711286)
- 1.54 SRAM CELLS FOR LOW TEMPERATURE INTEGRATED CIRCUIT OPERATION (17711906)
- 1.55 EPITAXIAL LAYERS OF A TRANSISTOR ELECTRICALLY COUPLED WITH A BACKSIDE CONTACT METAL (17710942)
- 1.56 TECHNOLOGIES FOR DYNAMIC BIASING FOR MEMORY CELLS (17706943)
- 1.57 STROBOSCOPIC ELECTRON-BEAM SIGNAL IMAGE MAPPING (17711785)
- 1.58 DIRECT INJECTION FILLING DEVICE, SYSTEM, AND METHOD FOR LIQUID METAL INTERCONNECTS (17712090)
- 1.59 HEAT-ASSISTED DIE EJECTION SYSTEM (17709482)
- 1.60 INTEGRATED CIRCUIT INTERCONNECT STRUCTURES WITH A METAL CHALCOGENIDE LINER (17711892)
- 1.61 TECHNOLOGIES FOR LIQUID METAL MIXTURES FOR ELECTRICAL INTERCONNECTS (17710556)
- 1.62 GROOVED PACKAGE (17707536)
- 1.63 INTEGRATED CIRCUIT PACKAGES HAVING REDUCED Z-HEIGHT AND HEAT PATH (17700211)
- 1.64 PACKAGE STRUCTURES WITH PATTERNED DIE BACKSIDE LAYER (17710507)
- 1.65 DIE BACKSIDE FILM WITH OVERHANG FOR DIE SIDEWALL PROTECTION (17710670)
- 1.66 POROUS MESH STRUCTURES FOR THE THERMAL MANAGEMENT OF INTEGRATED CIRCUIT DEVICES (17709064)
- 1.67 HETEROGENEOUS PACKAGES HAVING THERMAL TOWERS (17708890)
- 1.68 TRANSISTOR-SCALE THERMOELECTRIC DEVICES FOR REFRIGERATION OF INTEGRATED CIRCUITS (17712054)
- 1.69 CHASSIS CUSTOMIZATION WITH HIGH THROUGHPUT ADDITIVE MANUFACTURED MODIFICATION STRUCTURES (17710658)
- 1.70 SINGLE CONDUCTIVITY TYPE DEVICES FOR LOW TEMPERATURE COMPUTATION (17711837)
- 1.71 MULTIPLE EPITAXIAL LAYER SOURCE AND DRAIN TRANSISTORS FOR LOW TEMPERATURE COMPUTATION (17711848)
- 1.72 SCALABLE ARCHITECTURE FOR MULTI-DIE SEMICONDUCTOR PACKAGES (17708417)
- 1.73 DUAL-SIDED TERMINAL DEVICE WITH SPLIT SIGNAL AND POWER ROUTING (17708968)
- 1.74 VIAS WITH VERTICALLY NON-UNIFORM OR DISCONTINUOUS STACK (17711008)
- 1.75 GLASS CORE SUBSTRATE PRINTED CIRCUIT BOARD FOR WARPAGE REDUCTION (17707183)
- 1.76 MODIFICATION OF SINX THIN FILM FOR IMPROVED ADHESION OF METAL-DIELECTRICS FOR HSIO PACKAGING (17707358)
- 1.77 PLASMA-INDUCED SURFACE FUNCTIONALIZATION OF SINX THIN FILM FOR IMPROVED ADHESION OF METAL-DIELECTRIC FOR HSIO (17707371)
- 1.78 STACKED VIA MODULATOR IN HIGH SPEED INTERCONNECT (17707342)
- 1.79 SUBSTRATE WITH LOW-PERMITTIVITY CORE AND BUILDUP LAYERS (17711749)
- 1.80 INTEGRATED CIRCUIT STRUCTURES WITH PRE-EPITAXIAL DEEP VIA STRUCTURE (17710817)
- 1.81 INTEGRATED CIRCUIT STRUCTURES WITH CONTOURED INTERCONNECTS (18329731)
- 1.82 METAL ROUTING THAT OVERLAPS NMOS AND PMOS REGIONS OF A TRANSISTOR (17710871)
- 1.83 INTEGRATED CIRCUITS WITH NARROW WIDTH INTERCONNECTS AND REDUCED RC DELAY (17711917)
- 1.84 BACKSIDE ELECTRICAL CONTACT FOR PMOS EPITAXIAL VOLTAGE SUPPLY (17710867)
- 1.85 SURFACE FUNCTIONALIZATION OF SINX THIN FILM BY WET ETCHING FOR IMPROVED ADHESION OF METAL-DIELECTRIC FOR HSIO (17707351)
- 1.86 HYBRID ETCH STOP LAYERS (17708051)
- 1.87 SPACER SELF-ALIGNED VIA STRUCTURES USING DIRECTED SELFASSEMBLY FOR GATE CONTACT OR TRENCH CONTACT (17710827)
- 1.88 GLASS BRIDGE FOR CONNECTING DIES (17707157)
- 1.89 MICROELECTRONIC STRUCTURE INCLUDING DIE BONDING FILM BETWEEN EMBEDDED DIE AND SURFACE OF SUBSTRATE CAVITY, AND METHOD OF MAKING SAME (17711978)
- 1.90 INTERPOSERS FOR SEMICONDUCTOR DEVICES (17708746)
- 1.91 GLASS SUBSTRATE PACKAGE WITH HYBRID BONDED DIE (17707708)
- 1.92 PACKAGE STRUCTURES WITH COLLAPSE CONTROL FEATURES (17710502)
- 1.93 ELECTRONIC DEVICE SUBSTRATE HAVING A PASSIVE ELECTRONIC COMPONENT (17707523)
- 1.94 HYBRID BONDING A DIE TO A SUBSTRATE WITH VIAS CONNECTING METAL PADS ON BOTH SIDES OF THE DIE (17709367)
- 1.95 PACKAGE STRUCTURES WITH NON-UNIFORM INTERCONNECT FEATURES (17710518)
- 1.96 NON-PLANAR PEDESTAL FOR THERMAL COMPRESSION BONDING (17711925)
- 1.97 BOND HEAD DESIGN FOR THERMAL COMPRESSION BONDING (17711926)
- 1.98 RIBBON SHIELD DEVICE AND METHOD (17707340)
- 1.99 THREE-DIMENSIONAL STACK COOLING WINGS (17709481)
- 1.100 MICRO-LED DISPLAY ARCHITECTURE FOR HIGH VOLUME MANUFACTURING (17710662)
- 1.101 THIN CLIENT FORM FACTOR ASSEMBLY (17707366)
- 1.102 METAL PCB FOR TOPSIDE POWER DELIVERY (17710753)
- 1.103 JUNCTION FIELD EFFECT TRANSISTORS FOR LOW VOLTAGE AND LOW TEMPERATURE OPERATION (17711854)
- 1.104 BURIED CHANNEL STRUCTURE INTEGRATED WITH NON-PLANAR STRUCTURES (18207065)
- 1.105 VERTICAL BIT DATA PATHS FOR INTEGRATED CIRCUITS (17710584)
- 1.106 INTEGRATED CIRCUIT STRUCTURES HAVING CONDUCTIVE STRUCTURES IN FIN ISOLATION REGIONS (17709378)
- 1.107 TECHNOLOGIES FOR LOW-LEAKAGE ON-CHIP CAPACITORS (17711736)
- 1.108 LAYERED 2D SEMICONDUCTORS (17709365)
- 1.109 GATE-ALL-AROUND INTEGRATED CIRCUIT STRUCTURES HAVING NECKED FEATURE (17700215)
- 1.110 INTEGRATED CIRCUIT STRUCTURES HAVING BACKSIDE GATE TIE-DOWN (17709374)
- 1.111 INTEGRATED CIRCUIT STRUCTURES WITH FULL-WRAP CONTACT STRUCTURE (17710837)
- 1.112 SOURCE OR DRAIN STRUCTURES WITH SELECTIVE SILICIDE CONTACTS THEREON (17710841)
- 1.113 ULTRA-SCALED TRANSISTOR DEVICES TO ENABLE CELL SIZE SCALING (17712057)
- 1.114 TRANSISTOR BACKSIDE ROUTING LAYERS WITH CONTACTS HAVING VARYING DEPTHS (17710873)
- 1.115 FABRICATION OF GATE-ALL-AROUND INTEGRATED CIRCUIT STRUCTURES HAVING ADDITIVE GATE STRUCTURES IN A TUB ARCHITECTURE (17693150)
- 1.116 INTEGRATED CIRCUIT STRUCTURES HAVING DIFFERENTIATED CHANNEL SIZING (17700002)
- 1.117 SELECTIVE PASSIVATION FOR EPI GROWTH IN PRESENCE OF METALLIC CONTACTS (17710791)
- 1.118 GATE SPACERS WITH ADJACENT UNIFORM EPITAXIAL MATERIAL (17711434)
- 1.119 TECHNOLOGIES FOR MAJORITY GATES (17711665)
- 1.120 NON-EPITAXIAL ELECTRICAL COUPLING BETWEEN A FRONT SIDE TRENCH CONNECTOR AND BACK SIDE CONTACTS OF A TRANSISTOR (17710857)
- 1.121 TRANSISTOR BODY-INDUCED BODY LEAKAGE MITIGATION AT LOW TEMPERATURE (17711887)
- 1.122 Liquid-Proof Edge Connector Designs for Immersion Cooling (18130404)
- 1.123 PACKAGE WITH MULTIPLE PHOTONIC INTEGRATED CIRCUIT DIES OPTICALLY COUPLED WITH EACH OTHER (17710881)
- 1.124 DEVICE, SYSTEM AND METHOD TO DETERMINE AN OPERATIONAL MODE OF A CONTINUOUS CAPACITIVE VOLTAGE REGULATOR (17711461)
- 1.125 DOMINO LOGIC CIRCUITRY WITH KEEPER TRANSISTORS ON BACKSIDE OF INTEGRATED CIRCUIT DIE (17711901)
- 1.126 DIGITAL TO ANALOG CONVERTER USING HIGH-INJECTION VELOCITY CHANNEL MATERIALS FOR LOW TEMPERATURE SIGNAL CONVERSION (17712047)
- 1.127 APPARATUS, SYSTEM AND METHOD OF TRANSMITTING A WIDEBAND RADIO FREQUENCY (RF) TRANSMIT (TX) SIGNAL (17710861)
- 1.128 APPARATUS, SYSTEM, AND METHOD OF TRANSMITTING A JOINT TRANSMISSION (18326704)
- 1.129 APPARATUS, SYSTEM AND METHOD OF VISIBLE LIGHT COMMUNICATION (VLC) (17710839)
- 1.130 SEPARATELY STORING ENCRYPTION KEYS AND ENCRYPTED DATA IN A HYBRID MEMORY (17708431)
- 1.131 COMMUNICATION DEVICE AND METHOD FOR RADIO COMMUNICATION (18160322)
- 1.132 METHODS AND APPARATUS TO DIRECT TRANSMISSION OF DATA BETWEEN NETWORK-CONNECTED DEVICES (18328214)
- 1.133 NETWORK INTERFACE DEVICE TO SELECT A TARGET SERVICE AND BOOT AN APPLICATION (18205984)
- 1.134 USER-PLANE APPARATUS FOR EDGE COMPUTING (18117679)
- 1.135 METHODS AND ARRANGEMENTS FOR LOW POWER WIRELESS NETWORKS (18117001)
- 1.136 APPARATUS, SYSTEM, AND METHOD OF CLIENT IDENTITY FOR USER EQUIPMENT (UE) SERVICE ACCESS (17710785)
- 1.137 A1 ENRICHMENT INFORMATION FOR USER EQUIPMENT (UE) PHYSICAL POSITIONING INFORMATION (18311508)
- 1.138 CAPACITOR IN A SUBSTRATE VIA (17710944)
- 1.139 MULTI SLOT ADD-IN CARD WITH FIRST AND SECOND COOLING AIR MOVERS AND EXTENDED HEAT SINK FINS (17711018)
- 1.140 PLATFORMS INCLUDING MICROELECTRONIC PACKAGES THEREIN COUPLED TO A CHASSIS, WHERE WAVEGUIDES COUPLE THE MICROELECTRONIC PACKAGES TO EACH OTHER AND USABLE IN A COMPUTING DEVICE (18331474)
- 1.141 COMPACT FORM FACTOR COOLING ASSEMBLY RETENTION SYSTEM (17711007)
- 1.142 RECESSED TRANSISTOR TERMINAL VIA JUMPERS (17711875)
- 1.143 SPIN-ORBIT READOUT USING TRANSITION METAL DICHALCOGENIDES AND PROXIMITIZED GRAPHENE (17709074)
- 1.144 TECHNOLOGIES FOR SCALABLE SPIN QUBIT READOUT (17695584)
Patent applications for Intel Corporation on October 5th, 2023
MICROBUMP CLUSTER PROBING ARCHITECTURE FOR 2.5D AND 3D DIES (17709487)
Inventor Jagat SHAKYA
TECHNOLOGIES FOR TESTING LIQUID METAL ARRAY INTERCONNECT PACKAGES (17709630)
Inventor Gregorio Roberto Murtagian
IN-FIELD LATENT FAULT MEMORY AND LOGIC TESTING USING STRUCTURAL TECHNIQUES (17712100)
Inventor Elik Haran
CONFIGURABLE BOUNDARY SCAN (17700982)
Inventor Rohini Krishnan
LASER TRANSMITTER COMPONENT, LIGHT DETECTION AND RANGING SYSTEM, AND COMPUTER READABLE MEDIUM (18165949)
Inventor Naresh SATYAN
APPARATUSES AND METHODS FOR INSPECTING EMBEDDED FEATURES (17706654)
Inventor Jacob CHESNA
DESIGNS OF THERMAL INSULATION FOR MICRO-RING RESONATOR (MRR) IN ON-CAVITY PIC (OCPIC) TO ACHIEVE EFFECTIVE THERMAL TUNING (17710690)
Inventor Chia-Pin CHIU
TEMPERATURE SENSOR TO ACHIEVE THERMAL STABILIZATION OF MICRO-RING RESONATOR (MRR) IN AN OPEN CAVITY PHOTONIC INTEGRATED CIRCUIT (OCPIC) (17710709)
Inventor Chia-Pin CHIU
SELF-DOCKING SELF-ALIGNED OPTICAL PCB CONNECTOR FOR SEMICONDUCTOR PACKAGES (17710669)
Inventor Eric MORET
APPROACH TO PREVENT PLATING AT V-GROOVE ZONE IN PHOTONICS SILICON DURING BUMPING OR PILLARING (17710725)
Inventor Santosh SHAW
UNDERCUT DESIGN WITH A BONDED BASE COVER FOR FRIENDLY ASSEMBLY AND EFFECTIVE THERMAL TUNING OF MICRO-RING RESONATOR (MRR) IN OPEN CAVITY PHOTONIC INTEGRATED CHIPS (OCPIC) (17710703)
Inventor Chia-Pin CHIU
ON-CAVITY PHOTONIC INTEGRATED CIRCUIT (OCPIC) TO ACHIEVE THE MOST UNDERCUT REAL ESTATE FOR EFFECTIVE THERMAL TUNING (17710716)
Inventor Chia-Pin CHIU
CONFIGURATION OF BASE CLOCK FREQUENCY OF PROCESSOR BASED ON USAGE PARAMETERS (18329492)
Inventor Vasudevan Srinivasan
HYBRID COMPUTING DEVICE, APPARATUS AND SYSTEM (18196831)
Inventor SAMEER SHARMA
SYSTEM, APPARATUS AND METHOD FOR DYNAMIC THERMAL DISTRIBUTION OF A SYSTEM ON CHIP (18296560)
Inventor Rolf Kuehnis
COMPENSATING FOR HIGH HEAD MOVEMENT IN HEAD-MOUNTED DISPLAYS (18181615)
Inventor Ravindra A. Babu
METHOD AND APPARATUS TO IMPLEMENT AN INTEGRATED CIRCUIT INCLUDING BOTH DYNAMIC RANDOM-ACCESS MEMORY (DRAM) AND STATIC RANDOM-ACCESS MEMORY (SRAM) (17711394)
Inventor Abhishek Anil SHARMA
PROVIDING FINE GRAIN ACCESS TO PACKAGE MEMORY (17708398)
Inventor Abhishek Anil Sharma
SYNCHRONOUS MICROTHREADING (17712124)
Inventor David B. SHEFFIELD
SYNCHRONOUS MICROTHREADING (17712126)
Inventor David B. SHEFFIELD
NATIVE SUPPORT FOR EXECUTION OF GET EXPONENT, GET MANTISSSA, AND SCALE INSTRUCTIONS WITHIN A GRAPHICS PROCESSING UNIT VIA REUSE OF FUSED MULTIPLY-ADD EXECUTION UNIT HARDWARE LOGIC (18170696)
Inventor Shuai Mu
APPARATUSES, METHODS, AND SYSTEMS FOR 8-BIT FLOATING-POINT MATRIX DOT PRODUCT INSTRUCTIONS (18313026)
Inventor Naveen Mellempudi
TECHNOLOGY TO SUPPORT BITMAP MANIPULATION OPERATIONS USING A DIRECT MEMORY ACCESS INSTRUCTION SET ARCHITECTURE (18326623)
Inventor Shruti Sharma
CIRCUITRY AND METHODS FOR CAPABILITY INFORMED PREFETCHES (17712075)
Inventor Scott D. Constable
FORWARD CONDITIONAL BRANCH EVENT FOR PROFILE-GUIDED-OPTIMIZATION (PGO) (17712018)
Inventor Ahmad YASIN
SYNCHRONOUS MICROTHREADING (17712118)
Inventor David B. SHEFFIELD
SYNCHRONOUS MICROTHREADING (17712120)
Inventor Shreesha SRINATH
SYNCHRONOUS MICROTHREADING (17712122)
Inventor David B. SHEFFIELD
SYNCHRONOUS MICROTHREADING (17712129)
Inventor David B. SHEFFIELD
SYNCHRONOUS MICROTHREADING (17712130)
Inventor David B. SHEFFIELD
SYNCHRONOUS MICROTHREADING (17712127)
Inventor David B. SHEFFIELD
CIRCUITRY AND METHODS FOR INFORMING INDIRECT PREFETCHES USING CAPABILITIES (17712073)
Inventor Scott D. Constable
CONTROL REGISTER SET TO FACILITATE PROCESSOR EVENT BASED SAMPLING (17708933)
Inventor Matthew Merten
VARIABLE-LENGTH INSTRUCTION STEERING TO INSTRUCTION DECODE CLUSTERS (17712139)
Inventor Muhammad Azeem
MULTICORE PROCESSOR WITH EACH CORE HAVING INDEPENDENT FLOATING POINT DATAPATH AND INTEGER DATAPATH (18312079)
Inventor ELMOUSTAPHA OULD-AHMED-VALL
Performance Monitoring Emulation in Translated Branch Instructions in a Binary Translation-Based Processor (17711770)
Inventor Sebastian Winkel
Systems and Methods for Java Virtual Machine Management (18329576)
Inventor Christopher Thomas Wilkinson
SYNCHRONOUS MICROTHREADING (17712121)
Inventor David B. SHEFFIELD
FIRMWARE FIRST HANDLING OF A MACHINE CHECK EVENT (17711465)
Inventor Sarathy Jayakumar
PLATFORM AND PLATFORM COMPONENT DEBUG BY MULTIPLE DEBUGGING SYSTEMS (18332420)
Inventor Aruni P. Nelson
DYNAMIC INCLUSIVE AND NON-INCLUSIVE CACHING POLICY (17708435)
Inventor Hanna Alam
TWO-STAGE CACHE PARTITIONING (17711471)
Inventor Philip Abraham
CIRCUITRY AND METHODS FOR IMPLEMENTING CAPABILITY-DIRECTED PREFETCHING (17712072)
Inventor Scott D. Constable
CACHE ACCESS FABRIC (18207602)
Inventor Leon POLISHUK
CIRCUITRY AND METHODS FOR IMPLEMENTING MICRO-CONTEXT BASED TRUST DOMAINS (17709867)
Inventor David M. Durham
METHOD OF RING ALLREDUCE PROCESSING (18250515)
Inventor Guokai Ma
POWER SUPPLY COMMUNICATIONS VIA A SHARED CHANNEL FOR PERFORMANCE MANAGEMENT (17711380)
Inventor Rob W. Sims
PROVIDING ISOLATION IN VIRTUALIZED SYSTEMS USING TRUST DOMAINS (18131199)
Inventor Ravi L. Sahita
APPARATUS AND METHOD TO IMPLEMENT HOMOMORPHIC ENCYPTION AND COMPUTATION WITH DRAM (17712097)
Inventor Abhishek Anil Sharma
MACHINE LEARNING SPARSE COMPUTATION MECHANISM FOR ARBITRARY NEURAL NETWORKS, ARITHMETIC COMPUTE MICROARCHITECTURE, AND SPARSITY FOR TRAINING MECHANISM (18302889)
Inventor Eriko Nurvitadhi
LOW RANK MATRIX COMPRESSION (18191565)
Inventor Tomer Bar-On
Providing Orthogonal Subarrays in A Dynamic Random Access Memory (17708448)
Inventor Abhishek Anil Sharma
METHOD AND APPARATUS TO IMPLEMENT AN INTEGRATED CIRCUIT TO OPERATE BASED ON DATA ACCESS CHARACTERISTICS (17711286)
Inventor Abhishek Anil SHARMA
SRAM CELLS FOR LOW TEMPERATURE INTEGRATED CIRCUIT OPERATION (17711906)
Inventor Abhishek Anil Sharma
EPITAXIAL LAYERS OF A TRANSISTOR ELECTRICALLY COUPLED WITH A BACKSIDE CONTACT METAL (17710942)
Inventor Clifford ONG
TECHNOLOGIES FOR DYNAMIC BIASING FOR MEMORY CELLS (17706943)
Inventor Yasir Mohsin Husain
STROBOSCOPIC ELECTRON-BEAM SIGNAL IMAGE MAPPING (17711785)
Inventor Xianghong Tong
DIRECT INJECTION FILLING DEVICE, SYSTEM, AND METHOD FOR LIQUID METAL INTERCONNECTS (17712090)
Inventor Sangeon Lee
HEAT-ASSISTED DIE EJECTION SYSTEM (17709482)
Inventor Chetan Harsha EDARA
INTEGRATED CIRCUIT INTERCONNECT STRUCTURES WITH A METAL CHALCOGENIDE LINER (17711892)
Inventor Abhishek Anil Sharma
TECHNOLOGIES FOR LIQUID METAL MIXTURES FOR ELECTRICAL INTERCONNECTS (17710556)
Inventor Gregorio Roberto Murtagian
GROOVED PACKAGE (17707536)
Inventor Georg SEIDEMANN
INTEGRATED CIRCUIT PACKAGES HAVING REDUCED Z-HEIGHT AND HEAT PATH (17700211)
Inventor Jan Proschwitz
PACKAGE STRUCTURES WITH PATTERNED DIE BACKSIDE LAYER (17710507)
Inventor Pilin Liu
DIE BACKSIDE FILM WITH OVERHANG FOR DIE SIDEWALL PROTECTION (17710670)
Inventor Xavier Brun
POROUS MESH STRUCTURES FOR THE THERMAL MANAGEMENT OF INTEGRATED CIRCUIT DEVICES (17709064)
Inventor Feras Eid
HETEROGENEOUS PACKAGES HAVING THERMAL TOWERS (17708890)
Inventor Vishnu Prasad
TRANSISTOR-SCALE THERMOELECTRIC DEVICES FOR REFRIGERATION OF INTEGRATED CIRCUITS (17712054)
Inventor Abhishek Anil Sharma
CHASSIS CUSTOMIZATION WITH HIGH THROUGHPUT ADDITIVE MANUFACTURED MODIFICATION STRUCTURES (17710658)
Inventor Akhilesh Rallabandi
SINGLE CONDUCTIVITY TYPE DEVICES FOR LOW TEMPERATURE COMPUTATION (17711837)
Inventor Abhishek Sharma
MULTIPLE EPITAXIAL LAYER SOURCE AND DRAIN TRANSISTORS FOR LOW TEMPERATURE COMPUTATION (17711848)
Inventor Abhishek Sharma
SCALABLE ARCHITECTURE FOR MULTI-DIE SEMICONDUCTOR PACKAGES (17708417)
Inventor Abhishek Anil Sharma
DUAL-SIDED TERMINAL DEVICE WITH SPLIT SIGNAL AND POWER ROUTING (17708968)
Inventor Bernd Waidhas
VIAS WITH VERTICALLY NON-UNIFORM OR DISCONTINUOUS STACK (17711008)
Inventor Payam AMIN
GLASS CORE SUBSTRATE PRINTED CIRCUIT BOARD FOR WARPAGE REDUCTION (17707183)
Inventor Carlton Hanna
MODIFICATION OF SINX THIN FILM FOR IMPROVED ADHESION OF METAL-DIELECTRICS FOR HSIO PACKAGING (17707358)
Inventor Rahul N. MANEPALLI
PLASMA-INDUCED SURFACE FUNCTIONALIZATION OF SINX THIN FILM FOR IMPROVED ADHESION OF METAL-DIELECTRIC FOR HSIO (17707371)
Inventor Yi YANG
STACKED VIA MODULATOR IN HIGH SPEED INTERCONNECT (17707342)
Inventor Jiwei SUN
SUBSTRATE WITH LOW-PERMITTIVITY CORE AND BUILDUP LAYERS (17711749)
Inventor Brandon Christian Marin
INTEGRATED CIRCUIT STRUCTURES WITH PRE-EPITAXIAL DEEP VIA STRUCTURE (17710817)
Inventor Leonard P. GULER
INTEGRATED CIRCUIT STRUCTURES WITH CONTOURED INTERCONNECTS (18329731)
Inventor Ebubekir Dogan
METAL ROUTING THAT OVERLAPS NMOS AND PMOS REGIONS OF A TRANSISTOR (17710871)
Inventor Sukru YEMENICIOGLU
INTEGRATED CIRCUITS WITH NARROW WIDTH INTERCONNECTS AND REDUCED RC DELAY (17711917)
Inventor Abhishek Anil Sharma
BACKSIDE ELECTRICAL CONTACT FOR PMOS EPITAXIAL VOLTAGE SUPPLY (17710867)
Inventor Clifford ONG
SURFACE FUNCTIONALIZATION OF SINX THIN FILM BY WET ETCHING FOR IMPROVED ADHESION OF METAL-DIELECTRIC FOR HSIO (17707351)
Inventor Yi YANG
HYBRID ETCH STOP LAYERS (17708051)
Inventor Deepyanti Taneja
SPACER SELF-ALIGNED VIA STRUCTURES USING DIRECTED SELFASSEMBLY FOR GATE CONTACT OR TRENCH CONTACT (17710827)
Inventor Leonard P. GULER
GLASS BRIDGE FOR CONNECTING DIES (17707157)
Inventor Carlton Hanna
MICROELECTRONIC STRUCTURE INCLUDING DIE BONDING FILM BETWEEN EMBEDDED DIE AND SURFACE OF SUBSTRATE CAVITY, AND METHOD OF MAKING SAME (17711978)
Inventor Ravindranath V. Mahajan
INTERPOSERS FOR SEMICONDUCTOR DEVICES (17708746)
Inventor Carlton Hanna
GLASS SUBSTRATE PACKAGE WITH HYBRID BONDED DIE (17707708)
Inventor Bernd WAIDHAS
PACKAGE STRUCTURES WITH COLLAPSE CONTROL FEATURES (17710502)
Inventor Wenhao Li
ELECTRONIC DEVICE SUBSTRATE HAVING A PASSIVE ELECTRONIC COMPONENT (17707523)
Inventor Numair Ahmed
HYBRID BONDING A DIE TO A SUBSTRATE WITH VIAS CONNECTING METAL PADS ON BOTH SIDES OF THE DIE (17709367)
Inventor Hongxia FENG
PACKAGE STRUCTURES WITH NON-UNIFORM INTERCONNECT FEATURES (17710518)
Inventor Zhaozhi Li
NON-PLANAR PEDESTAL FOR THERMAL COMPRESSION BONDING (17711925)
Inventor Michael Baker
BOND HEAD DESIGN FOR THERMAL COMPRESSION BONDING (17711926)
Inventor Michael Baker
RIBBON SHIELD DEVICE AND METHOD (17707340)
Inventor Prabhat Ranjan
THREE-DIMENSIONAL STACK COOLING WINGS (17709481)
Inventor Sonja Koller
MICRO-LED DISPLAY ARCHITECTURE FOR HIGH VOLUME MANUFACTURING (17710662)
Inventor Bhupendra KUMAR
THIN CLIENT FORM FACTOR ASSEMBLY (17707366)
Inventor Carlton Hanna
METAL PCB FOR TOPSIDE POWER DELIVERY (17710753)
Inventor Kyle ARRINGTON
JUNCTION FIELD EFFECT TRANSISTORS FOR LOW VOLTAGE AND LOW TEMPERATURE OPERATION (17711854)
Inventor Abhishek Sharma
BURIED CHANNEL STRUCTURE INTEGRATED WITH NON-PLANAR STRUCTURES (18207065)
Inventor Guannan LIU
VERTICAL BIT DATA PATHS FOR INTEGRATED CIRCUITS (17710584)
Inventor Dmitri Evgenievich Nikonov
INTEGRATED CIRCUIT STRUCTURES HAVING CONDUCTIVE STRUCTURES IN FIN ISOLATION REGIONS (17709378)
Inventor Leonard P. GULER
TECHNOLOGIES FOR LOW-LEAKAGE ON-CHIP CAPACITORS (17711736)
Inventor Sameer Shekhar
LAYERED 2D SEMICONDUCTORS (17709365)
Inventor Kirby MAXEY
GATE-ALL-AROUND INTEGRATED CIRCUIT STRUCTURES HAVING NECKED FEATURE (17700215)
Inventor Rishabh MEHANDRU
INTEGRATED CIRCUIT STRUCTURES HAVING BACKSIDE GATE TIE-DOWN (17709374)
Inventor Leonard P. GULER
INTEGRATED CIRCUIT STRUCTURES WITH FULL-WRAP CONTACT STRUCTURE (17710837)
Inventor Leonard P. GULER
SOURCE OR DRAIN STRUCTURES WITH SELECTIVE SILICIDE CONTACTS THEREON (17710841)
Inventor Dan S. LAVRIC
ULTRA-SCALED TRANSISTOR DEVICES TO ENABLE CELL SIZE SCALING (17712057)
Inventor Abhishek Anil Sharma
TRANSISTOR BACKSIDE ROUTING LAYERS WITH CONTACTS HAVING VARYING DEPTHS (17710873)
Inventor Shaun MILLS
FABRICATION OF GATE-ALL-AROUND INTEGRATED CIRCUIT STRUCTURES HAVING ADDITIVE GATE STRUCTURES IN A TUB ARCHITECTURE (17693150)
Inventor Dan S. LAVRIC
INTEGRATED CIRCUIT STRUCTURES HAVING DIFFERENTIATED CHANNEL SIZING (17700002)
Inventor Rishabh MEHANDRU
SELECTIVE PASSIVATION FOR EPI GROWTH IN PRESENCE OF METALLIC CONTACTS (17710791)
Inventor Sudipto NASKAR
GATE SPACERS WITH ADJACENT UNIFORM EPITAXIAL MATERIAL (17711434)
Inventor Stephen M. CEA
TECHNOLOGIES FOR MAJORITY GATES (17711665)
Inventor Hai Li
NON-EPITAXIAL ELECTRICAL COUPLING BETWEEN A FRONT SIDE TRENCH CONNECTOR AND BACK SIDE CONTACTS OF A TRANSISTOR (17710857)
Inventor Shaun MILLS
TRANSISTOR BODY-INDUCED BODY LEAKAGE MITIGATION AT LOW TEMPERATURE (17711887)
Inventor Abhishek Anil Sharma
Liquid-Proof Edge Connector Designs for Immersion Cooling (18130404)
Inventor Xiang Li
PACKAGE WITH MULTIPLE PHOTONIC INTEGRATED CIRCUIT DIES OPTICALLY COUPLED WITH EACH OTHER (17710881)
Inventor Eleanor Patricia Paras RABADAM
DEVICE, SYSTEM AND METHOD TO DETERMINE AN OPERATIONAL MODE OF A CONTINUOUS CAPACITIVE VOLTAGE REGULATOR (17711461)
Inventor Tamir Salus
DOMINO LOGIC CIRCUITRY WITH KEEPER TRANSISTORS ON BACKSIDE OF INTEGRATED CIRCUIT DIE (17711901)
Inventor Abhishek Anil Sharma
DIGITAL TO ANALOG CONVERTER USING HIGH-INJECTION VELOCITY CHANNEL MATERIALS FOR LOW TEMPERATURE SIGNAL CONVERSION (17712047)
Inventor Abhishek Sharma
APPARATUS, SYSTEM AND METHOD OF TRANSMITTING A WIDEBAND RADIO FREQUENCY (RF) TRANSMIT (TX) SIGNAL (17710861)
Inventor Elan Banin
APPARATUS, SYSTEM, AND METHOD OF TRANSMITTING A JOINT TRANSMISSION (18326704)
Inventor Laurent Cariou
APPARATUS, SYSTEM AND METHOD OF VISIBLE LIGHT COMMUNICATION (VLC) (17710839)
Inventor Jay Vishnu Gupta
SEPARATELY STORING ENCRYPTION KEYS AND ENCRYPTED DATA IN A HYBRID MEMORY (17708431)
Inventor Abhishek Anil Sharma
COMMUNICATION DEVICE AND METHOD FOR RADIO COMMUNICATION (18160322)
Inventor Markus Dominik Mueck
METHODS AND APPARATUS TO DIRECT TRANSMISSION OF DATA BETWEEN NETWORK-CONNECTED DEVICES (18328214)
Inventor Rony Ferzli
NETWORK INTERFACE DEVICE TO SELECT A TARGET SERVICE AND BOOT AN APPLICATION (18205984)
Inventor Patrick G. KUTCH
USER-PLANE APPARATUS FOR EDGE COMPUTING (18117679)
Inventor Yifan YU
METHODS AND ARRANGEMENTS FOR LOW POWER WIRELESS NETWORKS (18117001)
Inventor Thomas J. Kenney
APPARATUS, SYSTEM, AND METHOD OF CLIENT IDENTITY FOR USER EQUIPMENT (UE) SERVICE ACCESS (17710785)
Inventor Anshu Agarwal
A1 ENRICHMENT INFORMATION FOR USER EQUIPMENT (UE) PHYSICAL POSITIONING INFORMATION (18311508)
Inventor Dawei Ying
CAPACITOR IN A SUBSTRATE VIA (17710944)
Inventor Aslam HASWAREY
MULTI SLOT ADD-IN CARD WITH FIRST AND SECOND COOLING AIR MOVERS AND EXTENDED HEAT SINK FINS (17711018)
Inventor Jyotiba SURYAWANSHI
PLATFORMS INCLUDING MICROELECTRONIC PACKAGES THEREIN COUPLED TO A CHASSIS, WHERE WAVEGUIDES COUPLE THE MICROELECTRONIC PACKAGES TO EACH OTHER AND USABLE IN A COMPUTING DEVICE (18331474)
Inventor Telesphor Kamgaing
COMPACT FORM FACTOR COOLING ASSEMBLY RETENTION SYSTEM (17711007)
Inventor Shahin AMIRI
RECESSED TRANSISTOR TERMINAL VIA JUMPERS (17711875)
Inventor Clifford Ong
SPIN-ORBIT READOUT USING TRANSITION METAL DICHALCOGENIDES AND PROXIMITIZED GRAPHENE (17709074)
Inventor Punyashloka Debashis
TECHNOLOGIES FOR SCALABLE SPIN QUBIT READOUT (17695584)
Inventor Bishnu Prasad Patra