Intel Corporation patent applications published on December 28th, 2023
Summary of the patent applications from Intel Corporation on December 28th, 2023
Intel Corporation has recently filed several patents related to semiconductor structures, memory devices, integrated circuits, and network technologies. These patents aim to improve the performance, efficiency, and reliability of various electronic devices and systems.
One patent application describes a semiconductor structure that includes a substrate with circuitry and a semiconductor stack on top of it. The stack consists of a first electrically conductive layer made of metal, connected to the circuitry, and a second electrically conductive layer acting as a barrier to prevent intermixing between the metal and the substrate material during deposition. This structure enhances the overall performance and reliability of semiconductor devices.
Another patent application focuses on a structure that combines memory and power delivery in an integrated circuit. The structure includes nanowire-based transistors for processing power and dynamic random access memory (DRAM) devices for memory storage. This integration improves the efficiency and performance of the integrated circuit, making it suitable for various electronic devices and advanced technologies.
Additionally, Intel has filed patents for techniques such as low power wake-up signals for efficient communication in wireless networks, rate-proportional routing and network coding for integrated access and backhaul (IAB) networks, and cyber attack detection in cellular networks. These techniques address issues such as power consumption, network efficiency, and security, providing benefits such as improved performance, increased capacity, enhanced connectivity, and early detection of cyber threats.
Summary of Patents Filed by Intel Corporation:
- Semiconductor structure with a barrier layer to prevent intermixing during deposition. - Integrated circuit structure combining memory and power delivery. - SRAM devices with angled transistors for increased density. - Structure for integrated circuits with nanowires and inverters. - Cold plates for thermal management in printed circuit boards. - Low power wake-up signals for efficient communication in wireless networks. - Techniques for integrated access and backhaul (IAB) networks, including routing, topology optimization, and network coding. - Cyber attack detection in cellular networks.
Notable Applications:
- Semiconductor manufacturing, integrated circuit fabrication, and electronics industry. - Memory devices, smartphones, tablets, computers, data centers, and servers. - Artificial intelligence systems, autonomous vehicles, and advanced technologies. - Wireless communication networks, IoT networks, mobile networks, and rural broadband connectivity. - Enhancing security, protecting user data, improving reliability, and mitigating cyber threats.
Contents
- 1 Patent applications for Intel Corporation on December 28th, 2023
- 1.1 LIQUID METAL (LM) DISPENSING APPARATUS AND METHODS FOR DESIGN AND OPERATION OF SAME (17851968)
- 1.2 ROAD SURFACE FRICTION BASED PREDICTIVE DRIVING FOR COMPUTER ASSISTED OR AUTONOMOUS DRIVING VEHICLES (18242869)
- 1.3 TECHNOLOGIES FOR EXPANDED BEAM OPTICAL CONNECTOR (17849557)
- 1.4 AUTOMATICALLY OPEN LAPTOP HINGE (18036823)
- 1.5 PROCESSOR POWER MANAGEMENT (18339827)
- 1.6 DEVICE, METHOD AND SYSTEM FOR TRANSPARENTLY CHANGING A FREQUENCY OF AN INTERCONNECT FABRIC (18244748)
- 1.7 PERFORMING DISTRIBUTED PROCESSING USING DISTRIBUTED MEMORY (17850090)
- 1.8 SYSTEMS, APPARATUSES, AND METHODS FOR ADDITION OF PARTIAL PRODUCTS (18456699)
- 1.9 RECONFIGURABLE VECTOR PROCESSING IN A MEMORY (17850044)
- 1.10 IMPLICIT MEMORY CORRUPTION DETECTION FOR CONDITIONAL DATA TYPES (17848142)
- 1.11 AUTOMATIC FUSION OF ARITHMETIC IN-FLIGHT INSTRUCTIONS (17848284)
- 1.12 METHODS AND APPARATUS TO INSERT PROFILING INSTRUCTIONS INTO A GRAPHICS PROCESSING UNIT KERNEL (18463142)
- 1.13 DATA LOCALITY ENHANCEMENT FOR GRAPHICS PROCESSING UNITS (18339454)
- 1.14 METHODS AND APPARATUS TO PERFORM CLOUD-BASED ARTIFICIAL INTELLIGENCE OVERCLOCKING (18241062)
- 1.15 SYSTEMS, METHODS, AND APPARATUSES FOR HETEROGENEOUS COMPUTING (18207870)
- 1.16 TECHNOLOGIES FOR PROVIDING EFFICIENT POOLING FOR A HYPER CONVERGED INFRASTRUCTURE (18219557)
- 1.17 HIERARCHICAL CORE VALID TRACKER FOR CACHE COHERENCY (17852189)
- 1.18 SELECTIVE PROVISIONING OF SUPPLEMENTARY MICRO-OPERATION CACHE RESOURCES (17846688)
- 1.19 UNIFIED ADDRESS TRANSLATION FOR VIRTUALIZATION OF INPUT/OUTPUT DEVICES (18321490)
- 1.20 DEVICE, SYSTEM, AND METHOD FOR INSPECTING DIRECT MEMORY ACCESS REQUESTS (18035705)
- 1.21 MULTICORE SYNCHRONIZATION MECHANISM FOR TIME CRITICAL RADIO SYSTEMS (17851739)
- 1.22 CONTROL FLOW INTEGRITY TO PREVENT POTENTIAL LEAKAGE OF SENSITIVE DATA TO ADVERSARIES (17849351)
- 1.23 EFFICIENT CONVOLUTION IN MACHINE LEARNING ENVIRONMENTS (18322988)
- 1.24 METHOD AND SYSTEM OF IMAGE PROCESSING WITH INCREASED SUBJECTIVE QUALITY 3D RECONSTRUCTION (18030025)
- 1.25 METHODS AND APPARATUS FOR ASSISTED DATA REVIEW FOR ACTIVE LEARNING CYCLES (18457169)
- 1.26 SPUTTER TARGETS AND SOURCES FOR SELF-DOPED SOURCE AND DRAIN CONTACTS (17847625)
- 1.27 MULTI-PATHWAY ROUTING VIA THROUGH HOLE (17851999)
- 1.28 ORGANIC ADHESION PROMOTOR FOR DIELECTRIC ADHESION TO A COPPER TRACE (17848615)
- 1.29 TECHNOLOGIES FOR ISOLATED HEAT DISSIPATING DEVICES (18034133)
- 1.30 ELECTRICALLY CONDUCTIVE STRIPS ON A SIDE OF A MEMORY MODULE (17848607)
- 1.31 COPPER RINGS FOR BGA COUNT REDUCTION IN SMALL FORM FACTOR PACKAGES (17849352)
- 1.32 SINGLE LITHOGRAPHY METHODS FOR INTERCONNECT ARCHITECTURES (17846303)
- 1.33 PACKAGING ARCHITECTURE WITH ROUNDED TRACES FOR ON-PACKAGE HIGH-SPEED INTERCONNECTS (17847282)
- 1.34 SINX ADHESION PROMOTER WITH ADHESION HOLE FEATURES IN PACKAGING SUBSTRATE FOR RELIABILITY PERFORMANCE ENHANCEMENT (17852039)
- 1.35 HYPER DENSITY PACKAGE SUBSTRATE AND MEMORY COUPLED TO A MODIFIED SEMI-ADDITIVE PROCESS BOARD (17848630)
- 1.36 ASYMMETRICAL DIELECTRIC-TO-METAL ADHESION ARCHITECTURE FOR ELECTRONIC PACKAGES (17848053)
- 1.37 ELECTRICAL CONDUCTOR EXTENDING FROM A SURFACE OF A SUBSTRATE (17848643)
- 1.38 SILICON NITRIDE LAYER UNDER A COPPER PAD (17848624)
- 1.39 INTEGRATED CIRCUIT PACKAGES WITH SILVER AND SILICON NITRIDE MULTI-LAYER (17851957)
- 1.40 INTEGRATED CIRCUIT STRUCTURE WITH RECESSED SELF-ALIGNED DEEP BOUNDARY VIA (17850779)
- 1.41 SELECTIVE BOTTOMLESS GRAPHENE LINED INTERCONNECTS (17852028)
- 1.42 INTEGRATED CIRCUIT DEVICES WITH ANGLED TRANSISTORS AND ANGLED ROUTING TRACKS (18314875)
- 1.43 MICROELECTRONIC DIE WITH TWO DIMENSIONAL (2D) COMPLEMENTARY METAL OXIDE SEMICONDUCTOR DEVICES IN AN INTERCONNECT STACK THEREOF (17849207)
- 1.44 INTEGRATED CIRCUIT STRUCTURES HAVING MEMORY WITH BACKSIDE POWER DELIVERY (17851985)
- 1.45 MICROELECTRONIC ASSEMBLIES WITH ANCHOR LAYER AROUND A BRIDGE DIE (17848069)
- 1.46 INORGANIC-BASED EMBEDDED-DIE LAYERS FOR MODULAR SEMICONDUCTIVE DEVICES (18367285)
- 1.47 MICROELECTRONIC STRUCTURES INCLUDING BRIDGES (18462600)
- 1.48 PACKAGING ARCHITECTURE WITH TRENCH VIA ROUTING FOR ON-PACKAGE HIGH-SPEED INTERCONNECTS (17847257)
- 1.49 PACKAGING ARCHITECTURE WITH CAVITIES FOR EMBEDDED INTERCONNECT BRIDGES (17847407)
- 1.50 INTEGRATED CIRCUIT PACKAGE WITH PSEUDO-STRIPLINE ARCHITECTURE (17848059)
- 1.51 TECHNOLOGIES FOR OVERLAY METROLOGY MARKS (17847111)
- 1.52 SLOTTED STIFFENER FOR A PACKAGE SUBSTRATE (17848639)
- 1.53 STRESS-REDUCING DIELECTRIC-TO-METAL ADHESION ARCHITECTURE FOR ELECTRONIC PACKAGES (17847652)
- 1.54 DEVICE-TO-DEVICE COMMUNICATION SYSTEM, PACKAGES, AND PACKAGE SYSTEM (18253954)
- 1.55 PACKAGED SEMICONDUCTOR DIE WITH BUMPLESS DIE-PACKAGE INTERFACE FOR BUMPLESS BUILD-UP LAYER (BBUL) PACKAGES (18244689)
- 1.56 PACKAGE ARCHITECTURE WITH VERTICAL STACKING OF INTEGRATED CIRCUIT DIES HAVING PLANARIZED EDGES (17846086)
- 1.57 PACKAGE ARCHITECTURE WITH VERTICALLY STACKED BRIDGE DIES HAVING PLANARIZED EDGES (17846129)
- 1.58 PACKAGE ARCHITECTURE OF THREE-DIMENSIONAL INTERCONNECT CUBE WITH INTEGRATED CIRCUIT DIES HAVING PLANARIZED EDGES (17846153)
- 1.59 PACKAGING ARCHITECTURE WITH COAXIAL PILLARS FOR HIGH-SPEED INTERCONNECTS (17847434)
- 1.60 MICROELECTRONIC ASSEMBLIES INCLUDING SOLDER AND NON-SOLDER INTERCONNECTS (17848246)
- 1.61 PACKAGE ARCHITECTURE OF PHOTONIC SYSTEM WITH VERTICALLY STACKED DIES HAVING PLANARIZED EDGES (17846173)
- 1.62 PACKAGE ARCHITECTURE WITH VERTICAL STACKING OF INTEGRATED CIRCUIT DIES HAVING PLANARIZED EDGES AND MULTI-SIDE ROUTING (17846109)
- 1.63 SIGE:GAB SOURCE OR DRAIN STRUCTURES WITH LOW RESISTIVITY (17850782)
- 1.64 LOWER DEVICE ACCESS IN STACKED TRANSISTOR DEVICES (17847628)
- 1.65 SINGLE GATED 3D NANOWIRE INVERTER FOR HIGH DENSITY THICK GATE SOC APPLICATIONS (18244741)
- 1.66 GATE ALL AROUND TRANSISTORS ON ALTERNATE SUBSTRATE ORIENTATION (17847559)
- 1.67 SELF-ASSEMBLED MONOLAYER ON A DIELECTRIC FOR TRANSITION METAL DICHALCOGENIDE GROWTH FOR STACKED 2D CHANNELS (17850078)
- 1.68 STACKED SINGLE CRYSTAL TRANSITION-METAL DICHALCOGENIDE USING SEEDED GROWTH (17850623)
- 1.69 INTEGRATED CIRCUIT STRUCTURE WITH BACKSIDE POWER STAPLE (17850778)
- 1.70 2D LAYERED GATE OXIDE (17852016)
- 1.71 SELF-ALIGNED EMBEDDED SOURCE AND DRAIN CONTACTS (17851658)
- 1.72 FABRICATION OF GATE-ALL-AROUND INTEGRATED CIRCUIT STRUCTURES HAVING COMMON METAL GATES AND HAVING GATE DIELECTRICS WITH AN OPPOSITE POLARITY DIPOLE LAYER (17850769)
- 1.73 INTEGRATED CIRCUIT STRUCTURES HAVING AOI GATES WITH ROUTING ACROSS NANOWIRES (17851960)
- 1.74 GATE CUT AND FIN TRIM ISOLATION FOR ADVANCED INTEGRATED CIRCUIT STRUCTURE FABRICATION (18367292)
- 1.75 DIFFUSION CUT STRESSORS FOR STACKED TRANSISTORS (17809329)
- 1.76 MOBILITY IMPROVEMENT IN GATE ALL AROUND TRANSISTORS BASED ON SUBSTRATE ORIENTATION (17847555)
- 1.77 VARACTOR DEVICE WITH BACKSIDE ELECTRICAL CONTACT (17848660)
- 1.78 DEVICE, SYSTEM AND METHOD TO DELIVER POWER WITH PHASE CIRCUITS OF AN INTEGRATED CIRCUIT DIE (17851997)
- 1.79 AUTO PHASE SCALING FOR DYNAMIC VOLTAGE ID (17982318)
- 1.80 SYSTEMS, APPARATUS, ARTICLES OF MANUFACTURE, AND METHODS FOR PRIVATE NETWORK MOBILITY MANAGEMENT (18343586)
- 1.81 TECHNOLOGIES FOR ALLOCATING RESOURCES ACROSS DATA CENTERS (18238096)
- 1.82 CONCEPT FOR A TELEMETRY HUB FOR MICROSERVICES (17809297)
- 1.83 TECHNOLOGIES FOR PROTOCOL EXECUTION WITH AGGREGATION AND CACHING (18356587)
- 1.84 PACKET PROCESSING WITH REDUCED LATENCY (18243896)
- 1.85 SECURE STREAM PROTOCOL FOR SERIAL INTERCONNECT (18345278)
- 1.86 TECHNOLOGIES FOR ACCELERATED HTTP PROCESSING WITH HARDWARE ACCELERATION (18202408)
- 1.87 METHODS AND ARRANGEMENTS FOR SHORT BEACON FRAMES IN WIRELESS NETWORKS (18242998)
- 1.88 ADAPTIVE RESOLUTION OF POINT CLOUD AND VIEWPOINT PREDICTION FOR VIDEO STREAMING IN COMPUTING ENVIRONMENTS (18347278)
- 1.89 ADAPTIVE FOVEATED ENCODER AND GLOBAL MOTION PREDICTOR (18345880)
- 1.90 CYBER ATTACK DETECTION FUNCTION (18465766)
- 1.91 TECHNIQUES FOR INTEGRATED ACCESS AND BACKHAUL (IAB) NODES (18450318)
- 1.92 LOW POWER WAKE-UP SIGNAL WITH TWO PARTS IN TIME DOMAIN (18465698)
- 1.93 COLD PLATES FOR SECONDARY SIDE COMPONENTS OF PRINTED CIRCUIT BOARDS (18344308)
- 1.94 INTEGRATED CIRCUIT STRUCTURES HAVING INVERTERS WITH CONTACTS BETWEEN NANOWIRES (17851979)
- 1.95 STATIC RANDOM-ACCESS MEMORY DEVICES WITH ANGLED TRANSISTORS (18312847)
- 1.96 INTEGRATED CIRCUIT STRUCTURES HAVING MEMORY WITH BACKSIDE DRAM AND POWER DELIVERY (17851967)
- 1.97 LOGIC CIRCUITS USING VERTICAL TRANSISTORS WITH BACKSIDE SOURCE OR DRAIN REGIONS (18314862)
- 1.98 LARGE GRAIN AND HALOGEN-FREE SILICON CELL CHANNEL FOR 3D NAND STRING (18367319)
- 1.99 SEMICONDUCTOR STRUCTURE INCLUDING BARRIER LAYER BETWEEN ELECTRODE LAYER AND UNDERLYING SUBSTRATE (17850746)
Patent applications for Intel Corporation on December 28th, 2023
LIQUID METAL (LM) DISPENSING APPARATUS AND METHODS FOR DESIGN AND OPERATION OF SAME (17851968)
Main Inventor
Sangeon Lee
ROAD SURFACE FRICTION BASED PREDICTIVE DRIVING FOR COMPUTER ASSISTED OR AUTONOMOUS DRIVING VEHICLES (18242869)
Main Inventor
Yoshifumi Nishi
TECHNOLOGIES FOR EXPANDED BEAM OPTICAL CONNECTOR (17849557)
Main Inventor
Wesley B. Morgan
AUTOMATICALLY OPEN LAPTOP HINGE (18036823)
Main Inventor
Chunlin BAI
PROCESSOR POWER MANAGEMENT (18339827)
Main Inventor
Altug Koker
DEVICE, METHOD AND SYSTEM FOR TRANSPARENTLY CHANGING A FREQUENCY OF AN INTERCONNECT FABRIC (18244748)
Main Inventor
Chen Ranel
PERFORMING DISTRIBUTED PROCESSING USING DISTRIBUTED MEMORY (17850090)
Main Inventor
Abhishek Anil Sharma
SYSTEMS, APPARATUSES, AND METHODS FOR ADDITION OF PARTIAL PRODUCTS (18456699)
Main Inventor
Robert Valentine
RECONFIGURABLE VECTOR PROCESSING IN A MEMORY (17850044)
Main Inventor
Abhishek Anil Sharma
IMPLICIT MEMORY CORRUPTION DETECTION FOR CONDITIONAL DATA TYPES (17848142)
Main Inventor
David M. Durham
AUTOMATIC FUSION OF ARITHMETIC IN-FLIGHT INSTRUCTIONS (17848284)
Main Inventor
Kristof Du Bois
METHODS AND APPARATUS TO INSERT PROFILING INSTRUCTIONS INTO A GRAPHICS PROCESSING UNIT KERNEL (18463142)
Main Inventor
Konstantin Levit-Gurevich
DATA LOCALITY ENHANCEMENT FOR GRAPHICS PROCESSING UNITS (18339454)
Main Inventor
Christopher J. HUGHES
METHODS AND APPARATUS TO PERFORM CLOUD-BASED ARTIFICIAL INTELLIGENCE OVERCLOCKING (18241062)
Main Inventor
Xia Zhu
SYSTEMS, METHODS, AND APPARATUSES FOR HETEROGENEOUS COMPUTING (18207870)
Main Inventor
Rajesh M. SANKARAN
TECHNOLOGIES FOR PROVIDING EFFICIENT POOLING FOR A HYPER CONVERGED INFRASTRUCTURE (18219557)
Main Inventor
Mohan J. Kumar
HIERARCHICAL CORE VALID TRACKER FOR CACHE COHERENCY (17852189)
Main Inventor
Yedidya Hilewitz
SELECTIVE PROVISIONING OF SUPPLEMENTARY MICRO-OPERATION CACHE RESOURCES (17846688)
Main Inventor
Niranjan Soundararajan
UNIFIED ADDRESS TRANSLATION FOR VIRTUALIZATION OF INPUT/OUTPUT DEVICES (18321490)
Main Inventor
Utkarsh Y. Kakaiya
DEVICE, SYSTEM, AND METHOD FOR INSPECTING DIRECT MEMORY ACCESS REQUESTS (18035705)
Main Inventor
Kaijie Guo
MULTICORE SYNCHRONIZATION MECHANISM FOR TIME CRITICAL RADIO SYSTEMS (17851739)
Main Inventor
Kevin Kinney
CONTROL FLOW INTEGRITY TO PREVENT POTENTIAL LEAKAGE OF SENSITIVE DATA TO ADVERSARIES (17849351)
Main Inventor
Scott D. Constable
EFFICIENT CONVOLUTION IN MACHINE LEARNING ENVIRONMENTS (18322988)
Main Inventor
Dhawal Srivastava
METHOD AND SYSTEM OF IMAGE PROCESSING WITH INCREASED SUBJECTIVE QUALITY 3D RECONSTRUCTION (18030025)
Main Inventor
Zhengxu Huang
METHODS AND APPARATUS FOR ASSISTED DATA REVIEW FOR ACTIVE LEARNING CYCLES (18457169)
Main Inventor
Vinnam Kim
SPUTTER TARGETS AND SOURCES FOR SELF-DOPED SOURCE AND DRAIN CONTACTS (17847625)
Main Inventor
Ilya V. Karpov
MULTI-PATHWAY ROUTING VIA THROUGH HOLE (17851999)
Main Inventor
Suddhasattwa Nad
ORGANIC ADHESION PROMOTOR FOR DIELECTRIC ADHESION TO A COPPER TRACE (17848615)
Main Inventor
Yi YANG
TECHNOLOGIES FOR ISOLATED HEAT DISSIPATING DEVICES (18034133)
Main Inventor
Prabhakar SUBRAHMANYAM
ELECTRICALLY CONDUCTIVE STRIPS ON A SIDE OF A MEMORY MODULE (17848607)
Main Inventor
Min Suet LIM
COPPER RINGS FOR BGA COUNT REDUCTION IN SMALL FORM FACTOR PACKAGES (17849352)
Main Inventor
Kavitha NAGARAJAN
SINGLE LITHOGRAPHY METHODS FOR INTERCONNECT ARCHITECTURES (17846303)
Main Inventor
Yi Yang
PACKAGING ARCHITECTURE WITH ROUNDED TRACES FOR ON-PACKAGE HIGH-SPEED INTERCONNECTS (17847282)
Main Inventor
Cemil Geyik
SINX ADHESION PROMOTER WITH ADHESION HOLE FEATURES IN PACKAGING SUBSTRATE FOR RELIABILITY PERFORMANCE ENHANCEMENT (17852039)
Main Inventor
Jieying KONG
HYPER DENSITY PACKAGE SUBSTRATE AND MEMORY COUPLED TO A MODIFIED SEMI-ADDITIVE PROCESS BOARD (17848630)
Main Inventor
Kavitha NAGARAJAN
ASYMMETRICAL DIELECTRIC-TO-METAL ADHESION ARCHITECTURE FOR ELECTRONIC PACKAGES (17848053)
Main Inventor
Suddhasattwa Nad
ELECTRICAL CONDUCTOR EXTENDING FROM A SURFACE OF A SUBSTRATE (17848643)
Main Inventor
Telesphor KAMGAING
SILICON NITRIDE LAYER UNDER A COPPER PAD (17848624)
Main Inventor
Brandon C. MARIN
INTEGRATED CIRCUIT PACKAGES WITH SILVER AND SILICON NITRIDE MULTI-LAYER (17851957)
Main Inventor
Cemil S. Geyik
INTEGRATED CIRCUIT STRUCTURE WITH RECESSED SELF-ALIGNED DEEP BOUNDARY VIA (17850779)
Main Inventor
Mohit HARAN
SELECTIVE BOTTOMLESS GRAPHENE LINED INTERCONNECTS (17852028)
Main Inventor
Nita CHANDRASEKHAR
INTEGRATED CIRCUIT DEVICES WITH ANGLED TRANSISTORS AND ANGLED ROUTING TRACKS (18314875)
Main Inventor
Sagar Suthram
MICROELECTRONIC DIE WITH TWO DIMENSIONAL (2D) COMPLEMENTARY METAL OXIDE SEMICONDUCTOR DEVICES IN AN INTERCONNECT STACK THEREOF (17849207)
Main Inventor
Kevin P. O'Brien
INTEGRATED CIRCUIT STRUCTURES HAVING MEMORY WITH BACKSIDE POWER DELIVERY (17851985)
Main Inventor
Abhishek Anil SHARMA
MICROELECTRONIC ASSEMBLIES WITH ANCHOR LAYER AROUND A BRIDGE DIE (17848069)
Main Inventor
Benjamin T. Duong
INORGANIC-BASED EMBEDDED-DIE LAYERS FOR MODULAR SEMICONDUCTIVE DEVICES (18367285)
Main Inventor
Srinivas V. PIETAMBARAM
MICROELECTRONIC STRUCTURES INCLUDING BRIDGES (18462600)
Main Inventor
Omkar G. Karhade
PACKAGING ARCHITECTURE WITH TRENCH VIA ROUTING FOR ON-PACKAGE HIGH-SPEED INTERCONNECTS (17847257)
Main Inventor
Cemil Geyik
PACKAGING ARCHITECTURE WITH CAVITIES FOR EMBEDDED INTERCONNECT BRIDGES (17847407)
Main Inventor
Sameer Paital
INTEGRATED CIRCUIT PACKAGE WITH PSEUDO-STRIPLINE ARCHITECTURE (17848059)
Main Inventor
Eng Huat Goh
TECHNOLOGIES FOR OVERLAY METROLOGY MARKS (17847111)
Main Inventor
Martin N. Weiss
SLOTTED STIFFENER FOR A PACKAGE SUBSTRATE (17848639)
Main Inventor
Kavitha NAGARAJAN
STRESS-REDUCING DIELECTRIC-TO-METAL ADHESION ARCHITECTURE FOR ELECTRONIC PACKAGES (17847652)
Main Inventor
Yi Yang
DEVICE-TO-DEVICE COMMUNICATION SYSTEM, PACKAGES, AND PACKAGE SYSTEM (18253954)
Main Inventor
Tolga ACIKALIN
PACKAGED SEMICONDUCTOR DIE WITH BUMPLESS DIE-PACKAGE INTERFACE FOR BUMPLESS BUILD-UP LAYER (BBUL) PACKAGES (18244689)
Main Inventor
Pramod MALATKAR
PACKAGE ARCHITECTURE WITH VERTICAL STACKING OF INTEGRATED CIRCUIT DIES HAVING PLANARIZED EDGES (17846086)
Main Inventor
Sagar Suthram
PACKAGE ARCHITECTURE WITH VERTICALLY STACKED BRIDGE DIES HAVING PLANARIZED EDGES (17846129)
Main Inventor
Sagar Suthram
PACKAGE ARCHITECTURE OF THREE-DIMENSIONAL INTERCONNECT CUBE WITH INTEGRATED CIRCUIT DIES HAVING PLANARIZED EDGES (17846153)
Main Inventor
Sagar Suthram
PACKAGING ARCHITECTURE WITH COAXIAL PILLARS FOR HIGH-SPEED INTERCONNECTS (17847434)
Main Inventor
Hiroki Tanaka
MICROELECTRONIC ASSEMBLIES INCLUDING SOLDER AND NON-SOLDER INTERCONNECTS (17848246)
Main Inventor
Alois Nitsch
PACKAGE ARCHITECTURE OF PHOTONIC SYSTEM WITH VERTICALLY STACKED DIES HAVING PLANARIZED EDGES (17846173)
Main Inventor
Sagar Suthram
PACKAGE ARCHITECTURE WITH VERTICAL STACKING OF INTEGRATED CIRCUIT DIES HAVING PLANARIZED EDGES AND MULTI-SIDE ROUTING (17846109)
Main Inventor
Sagar Suthram
SIGE:GAB SOURCE OR DRAIN STRUCTURES WITH LOW RESISTIVITY (17850782)
Main Inventor
Debaleena NANDI
LOWER DEVICE ACCESS IN STACKED TRANSISTOR DEVICES (17847628)
Main Inventor
Cheng-Ying Huang
SINGLE GATED 3D NANOWIRE INVERTER FOR HIGH DENSITY THICK GATE SOC APPLICATIONS (18244741)
Main Inventor
Rahul RAMASWAMY
GATE ALL AROUND TRANSISTORS ON ALTERNATE SUBSTRATE ORIENTATION (17847559)
Main Inventor
Ashish Agrawal
SELF-ASSEMBLED MONOLAYER ON A DIELECTRIC FOR TRANSITION METAL DICHALCOGENIDE GROWTH FOR STACKED 2D CHANNELS (17850078)
Main Inventor
Carl H. NAYLOR
STACKED SINGLE CRYSTAL TRANSITION-METAL DICHALCOGENIDE USING SEEDED GROWTH (17850623)
Main Inventor
Carl H. NAYLOR
INTEGRATED CIRCUIT STRUCTURE WITH BACKSIDE POWER STAPLE (17850778)
Main Inventor
Sukru YEMENICIOGLU
2D LAYERED GATE OXIDE (17852016)
Main Inventor
Chelsey DOROW
SELF-ALIGNED EMBEDDED SOURCE AND DRAIN CONTACTS (17851658)
Main Inventor
Nitesh Kumar
FABRICATION OF GATE-ALL-AROUND INTEGRATED CIRCUIT STRUCTURES HAVING COMMON METAL GATES AND HAVING GATE DIELECTRICS WITH AN OPPOSITE POLARITY DIPOLE LAYER (17850769)
Main Inventor
Dan S. LAVRIC
INTEGRATED CIRCUIT STRUCTURES HAVING AOI GATES WITH ROUTING ACROSS NANOWIRES (17851960)
Main Inventor
Abhishek Anil SHARMA
GATE CUT AND FIN TRIM ISOLATION FOR ADVANCED INTEGRATED CIRCUIT STRUCTURE FABRICATION (18367292)
Main Inventor
Tahir GHANI
DIFFUSION CUT STRESSORS FOR STACKED TRANSISTORS (17809329)
Main Inventor
Cheng-Ying Huang
MOBILITY IMPROVEMENT IN GATE ALL AROUND TRANSISTORS BASED ON SUBSTRATE ORIENTATION (17847555)
Main Inventor
Seung Hoon Sung
VARACTOR DEVICE WITH BACKSIDE ELECTRICAL CONTACT (17848660)
Main Inventor
Ayan Kar
DEVICE, SYSTEM AND METHOD TO DELIVER POWER WITH PHASE CIRCUITS OF AN INTEGRATED CIRCUIT DIE (17851997)
Main Inventor
Tamir Salus
AUTO PHASE SCALING FOR DYNAMIC VOLTAGE ID (17982318)
Main Inventor
Patrick Kam-shing Leung
SYSTEMS, APPARATUS, ARTICLES OF MANUFACTURE, AND METHODS FOR PRIVATE NETWORK MOBILITY MANAGEMENT (18343586)
Main Inventor
Stephen Palermo
TECHNOLOGIES FOR ALLOCATING RESOURCES ACROSS DATA CENTERS (18238096)
Main Inventor
Anjaneya Reddy CHAGAM REDDY
CONCEPT FOR A TELEMETRY HUB FOR MICROSERVICES (17809297)
Main Inventor
Rajesh POORNACHANDRAN
TECHNOLOGIES FOR PROTOCOL EXECUTION WITH AGGREGATION AND CACHING (18356587)
Main Inventor
Matthias Schunter
PACKET PROCESSING WITH REDUCED LATENCY (18243896)
Main Inventor
Eliezer Tamir
SECURE STREAM PROTOCOL FOR SERIAL INTERCONNECT (18345278)
Main Inventor
Vedvyas Shanbhogue
TECHNOLOGIES FOR ACCELERATED HTTP PROCESSING WITH HARDWARE ACCELERATION (18202408)
Main Inventor
Parthasarathy Sarangam
METHODS AND ARRANGEMENTS FOR SHORT BEACON FRAMES IN WIRELESS NETWORKS (18242998)
Main Inventor
MINYOUNG PARK
ADAPTIVE RESOLUTION OF POINT CLOUD AND VIEWPOINT PREDICTION FOR VIDEO STREAMING IN COMPUTING ENVIRONMENTS (18347278)
Main Inventor
MAYURESH VARERKAR
ADAPTIVE FOVEATED ENCODER AND GLOBAL MOTION PREDICTOR (18345880)
Main Inventor
Yunbiao Lin
CYBER ATTACK DETECTION FUNCTION (18465766)
Main Inventor
Abhijeet Kolekar
TECHNIQUES FOR INTEGRATED ACCESS AND BACKHAUL (IAB) NODES (18450318)
Main Inventor
Wei Mao
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