Intel Corporation patent applications on September 5th, 2024
Patent Applications by Intel Corporation on September 5th, 2024
Intel Corporation: 25 patent applications
Intel Corporation has applied for patents in the areas of G06V10/82 (3), H04L5/00 (3), H04W64/00 (2), H04W24/02 (2), G06F11/36 (2) B25J9/161 (1), H01L23/53209 (1), H04W36/0072 (1), H04W24/02 (1), H04N19/146 (1)
With keywords such as: device, network, circuitry, data, output, based, layer, signal, reference, and phase in patent application abstracts.
Patent Applications by Intel Corporation
Inventor(s): Javier Turek of Beaverton OR (US) for intel corporation, Leobardo Campos Macias of Guadalajara (MX) for intel corporation, Rafael De La Guardia Gonzalez of Teuchitlan (MX) for intel corporation, Javier Felip Leon of Hillsboro OR (US) for intel corporation, David Gonzalez Aguirre of Portland OR (US) for intel corporation
IPC Code(s): B25J9/16
CPC Code(s): B25J9/161
Abstract: a system for human-cobot (collaborative robot) ergonomic interaction, including: a communication interface operable to receive sensor data related to human motion; ergonomic assessment processor circuitry operable to evaluate the sensor data to generate a strain score for at least one human joint, wherein the strain score represents a strain level of the at least one human joint based on an integration of motion of the at least one human joint over a period of time; human intent prediction processor circuitry operable to interpret the sensor data to predict an object the human intends to grasp, and to select a destination container for the predicted object; and cobot motion processor circuitry operable to determine a position or orientation for the cobot to place the selected destination container based on the predicted object and the strain score.
Inventor(s): Jason W. Brandt of Austin TX (US) for intel corporation, Deepak K. Gupta of Portland OR (US) for intel corporation, Rodrigo Branco of Hillsboro OR (US) for intel corporation, Joseph Nuzman of Haifa (IL) for intel corporation, Robert S. Chappell of Portland OR (US) for intel corporation, Sergiu Ghetie of Hillsboro OR (US) for intel corporation, Wojciech Powiertowski of Beaverton OR (US) for intel corporation, Jared W. Stark, IV of Portland OR (US) for intel corporation, Ariel Sabba of Lavon (IL) for intel corporation, Scott J. Cape of Portland OR (US) for intel corporation, Hisham Shafi of San Jose CA (US) for intel corporation, Lihu Rappoport of Haifa (IL) for intel corporation, Yair Berger of Pardes-Hanna Karkur (IL) for intel corporation, Scott P. Bobholz of Bolton MA (US) for intel corporation, Gilad Holzstein of Haifa (IL) for intel corporation, Sagar V. Dalvi of Hillsboro OR (US) for intel corporation, Yogesh Bijlani of Portland OR (US) for intel corporation
IPC Code(s): G06F9/38, G06F9/30
CPC Code(s): G06F9/3844
Abstract: methods and apparatuses relating to mitigations for speculative execution side channels are described. speculative execution hardware and environments that utilize the mitigations are also described. for example, three indirect branch control mechanisms and their associated hardware are discussed herein: (i) indirect branch restricted speculation (ibrs) to restrict speculation of indirect branches, (ii) single thread indirect branch predictors (stibp) to prevent indirect branch predictions from being controlled by a sibling thread, and (iii) indirect branch predictor barrier (ibpb) to prevent indirect branch predictions after the barrier from being controlled by software executed before the barrier.
Inventor(s): Katalin Klara Bartfai-Walcott of El Dorado Hills CA (US) for intel corporation, Arkadiusz Berent of Tuchom (PL) for intel corporation, Vasuki Chilukuri of Hillsboro OR (US) for intel corporation, Mark Baldwin of Hillsboro OR (US) for intel corporation, Vasudevan Srinivasan of Portland OR (US) for intel corporation, Bartosz Gotowalski of Gdansk (PL) for intel corporation
IPC Code(s): G06F9/445, G06F11/30, G06F21/10, G06Q10/087, G06Q30/04, H04L9/32
CPC Code(s): G06F9/44505
Abstract: methods, apparatus, systems and articles of manufacture (e.g., physical storage media) to provide device enhancements for software defined silicon implementations are disclosed. example non-transitory computer readable medium comprising instructions cause one or more processors to at least cause transmission of a message to a semiconductor device, the message to cause the semiconductor device to unlock a first feature of the semiconductor device and associate a soft stock keeping unit with the semiconductor device having at least the first feature unlocked.
Inventor(s): Ziye YANG of Shanghai (CN) for intel corporation, Paul LUSE of Chandler AZ (US) for intel corporation, James HARRIS of Chandler AZ (US) for intel corporation, Benjamin WALKER of Chandler AZ (US) for intel corporation
IPC Code(s): G06F9/54
CPC Code(s): G06F9/545
Abstract: examples relate to an apparatus, device, method, and computer program for providing access to offloading circuitry of a computer system, to a method and computer program for setting up access to offloading circuitry of a computer system, and to corresponding computer systems. the apparatus comprises circuitry configured to provide a common interface for accessing offloading circuitry of the computer system from one or more software applications. the circuitry is configured to select one of a kernel-space driver and a user-space driver for accessing the offloading circuitry. the circuitry is configured to provide the access to the offloading circuitry for the one or more software applications via the selected driver at runtime.
Inventor(s): Qian OUYANG of Shanghai (CN) for intel corporation, Junjie MAO of Shanghai (CN) for intel corporation, Yi QIAN of Shanghai (CN) for intel corporation, Minggui CAO of Shanghai (CN) for intel corporation, Jian Jun CHEN of Shanghai (CN) for intel corporation, Junjun SHAN of Shanghai (CN) for intel corporation, Xiangyang WU of Shanghai CA (US) for intel corporation
IPC Code(s): G06F11/36
CPC Code(s): G06F11/3684
Abstract: it relates to an apparatus, a device, a method, and a computer program for generating test cases for a verification of hardware instructions of a hardware device in a hypervisor. the apparatus comprises circuitry configured to generate a transition table based on a specification of the hardware device. the transition table comprises a plurality of entries. each entry represents a change of a state of the hardware device in response to an event. the circuitry is configured to determine entries of the transition table that are equivalent. the circuitry is configured to generate a plurality of test cases based on the entries of the transition table. at least one entry of the transition table is omitted in the generation of the test cases due to being equivalent to another entry of the transition table.
Inventor(s): Tao ZHAO of Shanghai (CN) for intel corporation, Yun LIU of Shanghai (CN) for intel corporation, Edwin Lei WANG of Shanghai (CN) for intel corporation
IPC Code(s): G06F11/36
CPC Code(s): G06F11/3688
Abstract: examples relate to an apparatus, device, method, and computer program for performing unit tests on firmware code, and to an apparatus, device, method, and computer program for preparing data for performing unit tests on firmware code. the firmware code is suitable for interacting with a hardware device. the apparatus comprises circuitry configured to obtain a timeline of changes of transaction data encountered at one or more interfaces of the hardware device during simulation of the hardware device, the simulation being based on one or more simulation parameters defined by one or more unit tests to be performed on the firmware code. the circuitry is configured to perform the one or more unit tests of the firmware code using the timeline of changes of transaction data of the simulated hardware device, the one or more unit tests being based on the one or more simulation parameters.
Inventor(s): Junyuan WANG of Shanghai (CN) for intel corporation, Maksim LUKOSHKOV of Clarecastle (IE) for intel corporation, Weigang LI of Shanghai (CN) for intel corporation, Xin ZENG of Shanghai (CN) for intel corporation
IPC Code(s): G06F13/42
CPC Code(s): G06F13/4221
Abstract: techniques to improve device scalability using a peer-to-peer protocol over a communication link. the techniques can include use of an input/output (io) device access instruction set architecture (isa) command to place an io job request through an agent device from a host processor to a device, the host processor, agent device and device coupled to a communication link switch. the io job request can be communicated through the communication link switch.
Inventor(s): Chee Hak Teh of Bayan Lepas (MY) for intel corporation, Yu Ying Ong of Bayan Lepas (MY) for intel corporation, George Chong Hean Ooi of Bayan Lepas (MY) for intel corporation
IPC Code(s): G06F15/78, G06F13/16, G06F13/40
CPC Code(s): G06F15/7825
Abstract: described herein are memory controllers for integrated circuits that implement network-on-chip (noc) to provide access to memory to couple processing cores of the integrated circuit to a memory device. the noc may be dedicated to service the memory controller and may include one or more routers to facilitate management of the access to the memory controller.
20240296530. TEMPORAL NOISE REDUCTION ARCHITECTURE_simplified_abstract_(intel corporation)
Inventor(s): Rony Zatzarinni of Tel Aviv (IL) for intel corporation, Hava Matichin of Petah Tikva (IL) for intel corporation, Dor Barber of Herzliya (IL) for intel corporation
IPC Code(s): G06T5/70, G06T3/40, G06T7/20, G06V10/56, G06V10/60
CPC Code(s): G06T5/70
Abstract: systems and methods for improving a temporal noise reducer (tnr) architecture that improves tnr performance and iq. temporal noise reduction is a core feature of a video processing pipeline, where tnr can be used to decrease noise in video streams. tnrs generally includes two main steps: motion analysis and blending. motion analysis includes identifying moving elements, and can include generating a motion map indicating regions of the input image that are static versus regions with movement. blending includes blending the current input image frame with the previous temporally-denoised frame. an architecture is provided that separates the motion analysis from the blending step. in particular, the architecture includes a motion analysis block that operates on the raw image at the start of the pipeline, while the blending operation is completed on the processed image at the end of the image processing pipeline.
Inventor(s): Dmitry Kozlov of Nizhny Novgorod (RU) for intel corporation, Aleksei Chernigin of Nizhny Novgorod (RU) for intel corporation, Dmitry Tarakanov of Nizhny Novgorod (RU) for intel corporation
IPC Code(s): G06T11/40, G06T3/4046
CPC Code(s): G06T11/40
Abstract: one embodiment provides a graphics processor comprising a set of processing resources configured to perform a supersampling anti-aliasing operation via a mixed precision convolutional neural network. the set of processing resources include circuitry configured to receive, at an input block of a neural network model, a set of data including previous frame data, current frame data, jitter offset data, and velocity data, pre-process the set of data to generate pre-processed data, provide pre-processed data to a feature extraction network of the neural network model and an output block of the neural network model, process the first pre-processed data at the feature extraction network via one or more encoder stages and one or more decoder stages, output tensor data from the feature extraction network to the output block, and generate an anti-aliased output frame via the output block based on the current frame data and the tensor data output from the feature extraction network.
Inventor(s): Dongqi Cai of Beijing (CN) for intel corporation, Anbang Yao of Beijing (CN) for intel corporation, Yurong Chen of Beijing (CN) for intel corporation
IPC Code(s): G06V10/44, G06V10/771, G06V10/82
CPC Code(s): G06V10/44
Abstract: technology to conduct image sequence/video analysis can include a processor, and a memory coupled to the processor, the memory storing a neural network, the neural network comprising a plurality of convolution layers, a network depth relay structure comprising a plurality of network depth calibration layers, where each network depth calibration layer is coupled to an output of a respective one of the plurality of convolution layers, and a feature dimension relay structure comprising a plurality of feature dimension calibration slices, where the feature dimension relay structure is coupled to an output of another layer of the plurality of convolution layers. each network depth calibration layer is coupled to a preceding network depth calibration layer via first hidden state and cell state signals, and each feature dimension calibration slice is coupled to a preceding feature dimension calibration slice via second hidden state and cell state signals.
Inventor(s): Ido Nissenboim of Zichron Yaakov (IL) for intel corporation, Noam Levy of Karmiel (IL) for intel corporation, Alexander Itskovich of Kiryat Bialik (IL) for intel corporation
IPC Code(s): G06V10/776, G06V10/764, G06V10/82, G06V20/40
CPC Code(s): G06V10/776
Abstract: video segmentation predictions can be temporally unstable. some techniques can be implemented to mitigate temporal instability, but the techniques can be computationally complex. some techniques only account for changes in the output and do not account for changes in the input. to address some of these shortcomings, a lightweight technique can be implemented to compute a temporal consistency loss. the temporal consistency loss can be higher when a pixel-wise intensity change is small, and a pixel-wise prediction change is large. the temporal consistency loss can be lower otherwise. the temporal consistency loss can be used with one or more other losses as a part of a loss function for training a segmentation network to improve temporal stability in output segmentation maps.
Inventor(s): Dongqi Cai of Beijing (CN) for intel corporation, Yurong Chen of Beijing (CN) for intel corporation, Anbang Yao of Beijing (CN) for intel corporation
IPC Code(s): G06V10/82, G06V10/94
CPC Code(s): G06V10/82
Abstract: technology to conduct image sequence/video analysis can include a processor, and a memory coupled to the processor, the memory storing a neural network, the neural network comprising a plurality of convolution layers, and a plurality of normalization layers arranged as a relay structure, wherein each normalization layer is coupled to and following a respective one of the plurality of convolution layers. the plurality of normalization layers can be arranged as a relay structure where a normalization layer for a layer (k) is coupled to and following a normalization layer for a preceding layer (k−1). the normalization layer for the layer (k) is coupled to the normalization layer for the preceding layer (k−1) via a hidden state signal and a cell state signal, each signal generated by the normalization layer for the preceding layer (k−1). each normalization layer (k) can include a meta-gating unit (mgu) structure.
20240297119. LIQUID METAL CONNECTION DEVICE AND METHOD_simplified_abstract_(intel corporation)
Inventor(s): Srikant Nekkanty of Chandler AZ (US) for intel corporation, Karumbu Meyyappan of Portland OR (US) for intel corporation, Andres Ramirez Macias of Zapopan (MX) for intel corporation, Zhe Chen of Shanghai (CN) for intel corporation, Jeffory L. Smalley of East Olympia WA (US) for intel corporation, Zhichao Zhang of Chandler AZ (US) for intel corporation, Steven A. Klein of Chandler AZ (US) for intel corporation, Eric Erike of Mesa AZ (US) for intel corporation
IPC Code(s): H01L23/532, H01L23/32, H01L23/40, H01L23/498, H01L23/528
CPC Code(s): H01L23/53209
Abstract: an electronic device () and associated methods are disclosed. in one example, the electronic device () includes an interconnect socket () that includes a liquid metal. in selected examples, the interconnect socket () includes a resilient material spacer () located between pins () in an array of pins (). in selected examples, the electronic device () includes configurations to aid in de-socketing.
Inventor(s): Keng Chen of Acton MA (US) for intel corporation, Shunjiang Xu of Milpitas CA (US) for intel corporation, Christopher Schaef of Hillsboro OR (US) for intel corporation, Tamir Salus of Zichron Yaakov (IL) for intel corporation, Kishan Joshi of Mountain House CA (US) for intel corporation, Arvind Raghavan of San Jose CA (US) for intel corporation, Huanhuan Zhang of Ashland MA (US) for intel corporation
IPC Code(s): H02M3/158, G06F1/26
CPC Code(s): H02M3/1584
Abstract: embodiments described herein may include apparatus, systems, techniques, and/or processes that are directed to multiphase power converters and how current level outputs of each phase circuit are calibrated. the multiple phase circuits are grouped into multiple subsets, wherein one phase circuit of each subset is designated as a reference phase circuit. the reference phase circuits of each subset are calibrated together, using, for example, a closed loop daisy chain technique where each reference phase circuit calibrates their current output to the current output of the previous phase circuit, or alternatively, a current averaging technique where each reference phase circuit balances their current output to the average output of the reference phase circuits. the other phase circuits in each subset calibrate their current level outputs to the reference phase circuits in their subset using, for example, an open loop daisy chain technique, a reference/follower technique or by calibrating their output to the average output of the reference phase circuits.
Inventor(s): Nic Chautru of Santa Clara CA (US) for intel corporation
IPC Code(s): H03M13/11, H03M13/09
CPC Code(s): H03M13/1125
Abstract: a low-density parity check (ldpc) decoder architecture is provided for a self-adapting an ldpc control input that is used to successfully decode corresponding received code blocks. the architecture enables a machine-learning based process that facilitates learning of optimal ldpc control inputs, such as log-likelihood (llr) terms scaling, that is required for a given channel condition and deployment scenario. this is achieved by gathering, as a background process, a posteriori decoding metrics via unused ldpc decoder accelerators, which function to process the labelled llr data sets for different ldpc control input values. then, such optimal ldpc control input estimates may be applied to the real-time ldpc decoding based on previous learning across ue/channel conditions.
Inventor(s): Oner Orhan of San Jose CA (US) for intel corporation, Hosein Nikopour of San Jose CA (US) for intel corporation, Shilpa Talwa of Cupertino CA (US) for intel corporation, Dor Shaviv of Fremont CA (US) for intel corporation, Roya Doostnejad of Los Altos CA (US) for intel corporation, Adesoji J. Sajuyigbe of Mountain View CA (US) for intel corporation
IPC Code(s): H04B17/21, H04B7/06
CPC Code(s): H04B17/21
Abstract: millimeter-wave (mmwave) and sub-mmwave technology, apparatuses, and methods that relate to transceivers and receivers for wireless communications are described. the various aspects include an apparatus of a communication device including an antenna array and processing circuitry coupled to the antenna array. the processing circuitry is configured to initialize a beam tracking algorithm based on received signals received at the antenna array, wherein antenna phases used in the beam tracking are bound by an upper phase limit and a lower phase limit, to generate a beam tracking result. the processing circuitry is further configured to generate a calibration vector based on the beam tracking result and receive subsequent transmissions using a codebook adapted based on the calibration vector.
Inventor(s): Hua LI of Beijing (CN) for intel corporation, Andrey CHERVYAKOV of Maynooth (IE) for intel corporation, Ilya BOLOTIN of Nizhny Novgorod (RU) for intel corporation, Rui HUANG of Beijing (CN) for intel corporation, Meng ZHANG of Beijing (CN) for intel corporation
IPC Code(s): H04L5/00, H04B17/318, H04L1/1812
CPC Code(s): H04L5/0096
Abstract: this disclosure describes systems, methods, and devices for medium access control element-based transmission configuration indicator (tci) state switching with a pathloss reference signal. a user equipment (ue) may decode a pathloss reference signal; generate a first time between a downlink transmission received from a network device and a hybrid automatic repeat request (harq) acknowledgement sent by the ue to the network device: generate a second time to a first pathloss reference signal transmission after a layer-1 reference signal received power (l1-rsrp) measurement: identify a periodicity of the pathloss reference signal: generate, based on the first time, the second time, and the periodicity, a tci state switch delay time by which the ue device is to transmit an uplink signal to the network device after switching tci states; and encode the uplink signal to transmit to the network device by the tci state switch delay time.
Inventor(s): Rui HUANG of Beijing (CN) for intel corporation, Candy YIU of Portland OR (US) for intel corporation, Meng ZHANG of Beijing (CN) for intel corporation, Andrey CHERVYAKOV of Maynooth (IE) for intel corporation, Hua LI of Beijing (CN) for intel corporation
IPC Code(s): H04L5/00, H04W24/10
CPC Code(s): H04L5/0098
Abstract: this disclosure describes systems, methods, and devices for activating and deactivating pre-configured measurement gaps in carrier aggregation. a user equipment (ue) device may detect a pre-configured measurement gap configured by a network; detect that the pre-configured measurement gap has been activated or deactivated; and activate or deactivate the measurement gap based on the detection that the pre-configured measurement gap has been activated or deactivated.
20240297811. PILOT TONES OF DISTRIBUTED RESOURCE UNIT (DRU)_simplified_abstract_(intel corporation)
Inventor(s): Xiaogang CHEN of Portland OR (US) for intel corporation, Thomas KENNEY of Portland OR (US) for intel corporation, Qinghua LI of San Ramon CA (US) for intel corporation, Hao SONG of Santa Clara CA (US) for intel corporation
IPC Code(s): H04L27/26, H04L5/00
CPC Code(s): H04L27/2613
Abstract: this disclosure describes systems, methods, and devices related to distributed resource unit (dru) pilot tones. a device may determine a plurality of pilot tones across a first frequency resource. the device may adjust the plurality of pilot tones with a first pilot offset adjustment parameter. the device may cause to send a frame to a first station device using the adjusted plurality of pilot tones.
Inventor(s): Gang Shen of Hillsboro OR (US) for intel corporation, Hassnaa Moustafa of San Jose CA (US) for intel corporation, Jianhui Dai of Shanghai (CN) for intel corporation, Qiujiao Wu of Shanghai (CN) for intel corporation, Jianlin Qiu of Shanghai (CN) for intel corporation
IPC Code(s): H04L65/65, H04L65/1069, H04N21/6437, H04N21/845
CPC Code(s): H04L65/65
Abstract: systems and techniques for selective transport of spatially partitioned immersive media content are described herein. in an example, the system may negotiate an attribute for media content between a media producer and a media consumer. a content structure for the media content may be determined based on the negotiation of the attribute, and a network packet may be created with information corresponding to the determined content structure encoded into a transport protocol header of the network packet. the network packet may be filtered to produce filtered media content. the filtered media content may be transmitted to the media consumer.
20240298004. LOW- DELAY VIDEO ENCODING_simplified_abstract_(intel corporation)
Inventor(s): Vasily Aristarkhov of Magdebury (DE) for intel corporation
IPC Code(s): H04N19/146, H04N19/114
CPC Code(s): H04N19/146
Abstract: technology for low-delay encoding of live video streams in multi-adapter systems can include a host processor and memory comprising instructions which, when executed, cause a computing system to encode, via a first graphics adapter, an i-frame of a live video signal and a first subset of p-frames of the live video signal, encode, via a second graphics adapter, a second subset of p-frames of the live video signal, and combine the encoded video frames from the first adapter and the encoded video frames from the second adapter into an output video bitstream. frames of the live video signal are divided into the first and second subsets of p-frames on an alternating frame basis, and the i-frame copied from the first graphics adapter to the second graphics adapter prior to encoding the second subset of p-frames, such that encoding the first and second subsets of p-frames occurs essentially in parallel.
Inventor(s): Markus Dominik MUECK of Unterhaching (DE) for intel corporation, Miltiadis FILIPPOU of Muenchen (DE) for intel corporation, Thomas LUETZENKIRCHEN of Taufkirchen (DE) for intel corporation, Leonardo GOMES BALTAR of Muenchen (DE) for intel corporation
IPC Code(s): H04W24/02, H04W48/18, H04W64/00
CPC Code(s): H04W24/02
Abstract: this disclosure describes systems, methods, and devices related to facilitating machine learning-based operations at a user equipment (ue) connected to a radio access network (ran). a network ai/ml (artificial intelligence/machine learning) service or function may identify a first request, received from a user equipment (ue) device, for a machine learning model configuration; determine a location of the ue device; select, based on the first request and the location, an available machine learning agent; format a second request to the available machine learning agent for the machine learning configuration; identify the machine learning configuration received from the available machine learning agent based on the second request; and format a response to the first request, the response comprising the machine learning configuration for the ue device.
Inventor(s): Maruti Gupta HYDE of Portland OR (US) for intel corporation, Yi ZHANG of San Jose CA (US) for intel corporation, Vaibhav SINGH of New Delhi (IN) for intel corporation, Ziyi LI of Beijing (CN) for intel corporation, Christian Maciocco of Portland OR (US) for intel corporation
IPC Code(s): H04W36/00, H04W24/02, H04W52/02
CPC Code(s): H04W36/0072
Abstract: an apparatus for an access node, includes a memory interface to send or receive, to or from a data storage device, measurement information for measurement signaling between a first next generation radio access network (ng-ran) node and a second ng-ran node. the apparatus also includes processor circuitry communicatively coupled to the memory interface, the processor circuitry to initiate execution of a machine learning (ml) model by the first ng-ran node to select an energy saving state for the first ng-ran node, the second ng-ran node or a user equipment (ue), and generate one or more messages with an information element (ie) with one or more parameters to request measurement information according to the one or more parameters, the measurement information to comprise feedback information to train the ml model. other embodiments are described and claimed.
Inventor(s): Rui HUANG of Beijing (CN) for intel corporation, Meng ZHANG of Beijing (CN) for intel corporation, Andrey CHERVYAKOV of Maynooth (IE) for intel corporation, Hua LI of Beijing (CN) for intel corporation, Yi GUO of Shanghai (CN) for intel corporation
IPC Code(s): H04W64/00, H04W76/27, H04W76/28
CPC Code(s): H04W64/003
Abstract: the disclosure is directed to systems and methods for wireless network for calculating a position measurement in a wireless network. a user equipment (ue) in wireless network may identify a positioning reference signal (prs) received from a base station (gnb) every a discontinuous reception (drx) cycle of the ue and when the ue is in a radio resource control (rrc) inactive state; and perform a positioning measurement based on the prs received every drx cycle.
Intel Corporation patent applications on September 5th, 2024
- Intel Corporation
- B25J9/16
- CPC B25J9/161
- Intel corporation
- G06F9/38
- G06F9/30
- CPC G06F9/3844
- G06F9/445
- G06F11/30
- G06F21/10
- G06Q10/087
- G06Q30/04
- H04L9/32
- CPC G06F9/44505
- G06F9/54
- CPC G06F9/545
- G06F11/36
- CPC G06F11/3684
- CPC G06F11/3688
- G06F13/42
- CPC G06F13/4221
- G06F15/78
- G06F13/16
- G06F13/40
- CPC G06F15/7825
- G06T5/70
- G06T3/40
- G06T7/20
- G06V10/56
- G06V10/60
- CPC G06T5/70
- G06T11/40
- G06T3/4046
- CPC G06T11/40
- G06V10/44
- G06V10/771
- G06V10/82
- CPC G06V10/44
- G06V10/776
- G06V10/764
- G06V20/40
- CPC G06V10/776
- G06V10/94
- CPC G06V10/82
- H01L23/532
- H01L23/32
- H01L23/40
- H01L23/498
- H01L23/528
- CPC H01L23/53209
- H02M3/158
- G06F1/26
- CPC H02M3/1584
- H03M13/11
- H03M13/09
- CPC H03M13/1125
- H04B17/21
- H04B7/06
- CPC H04B17/21
- H04L5/00
- H04B17/318
- H04L1/1812
- CPC H04L5/0096
- H04W24/10
- CPC H04L5/0098
- H04L27/26
- CPC H04L27/2613
- H04L65/65
- H04L65/1069
- H04N21/6437
- H04N21/845
- CPC H04L65/65
- H04N19/146
- H04N19/114
- CPC H04N19/146
- H04W24/02
- H04W48/18
- H04W64/00
- CPC H04W24/02
- H04W36/00
- H04W52/02
- CPC H04W36/0072
- H04W76/27
- H04W76/28
- CPC H04W64/003
