Intel Corporation patent applications on September 26th, 2024
Patent Applications by Intel Corporation on September 26th, 2024
Intel Corporation: 56 patent applications
Intel Corporation has applied for patents in the areas of G06F9/30 (6), H01L29/06 (6), H01L29/423 (5), H01L29/66 (4), H01L23/498 (4) H01L23/15 (2), G06F9/30036 (2), G06F21/53 (2), H01L23/5283 (2), H04W72/1273 (1)
With keywords such as: source, device, semiconductor, gate, drain, include, region, between, data, and example in patent application abstracts.
Patent Applications by Intel Corporation
Inventor(s): Peter NOEST of Munich (DE) for intel corporation, Klaus UHL of Karlsruhe (DE) for intel corporation, Mirela Ecaterina STOICA of Ottobrunn (DE) for intel corporation
IPC Code(s): G01C21/34, B25J5/00, B25J9/16
CPC Code(s): G01C21/3407
Abstract: disclosed herein are devices, methods, and systems for navigating and positioning an autonomous robot within a map of an environment. the system may obtain an occupancy grid associated with the environment around the robot, wherein the occupancy grid includes grid points of potential destinations for the robot. the system may determine, for each grid point of the grid points of potential destinations, a weight for the grid point based on a distance to the grid point from a predefined reference point and based on a directional deviation to the grid point, where the directional deviation comprises an angular difference between a current heading of the robot and an angular direction from the reference point toward the grid point. the system may select, based on the weight, a target point from among the grid points and generate a movement instruction associated with moving the robot toward the target point.
20240319269. MEMORY TIMING CHARACTERIZATION CIRCUITRY_simplified_abstract_(intel corporation)
Inventor(s): Amit Agarwal of Hillsboro OR (US) for intel corporation, Steven K. Hsu of Lake Oswego OR (US) for intel corporation, Mark A. Anders of Hillsboro OR (US) for intel corporation, Ram Kumar Krishnamurthy of Portland OR (US) for intel corporation
IPC Code(s): G01R31/317, G01R31/3185
CPC Code(s): G01R31/31725
Abstract: an apparatus includes a plurality of delay generators, a first plurality of flip-flop circuits, a second plurality of flip-flop circuits, and a third plurality of flip-flop circuits. the plurality of delay generators includes a data delay generator, an enable delay generator, and a reference delay generator. the first plurality of flip-flop circuits is coupled to the data delay generator to receive a delayed data input signal, and provide the delayed data input signal to a plurality of data input terminals of a memory circuit. the second plurality of flip-flop circuits is coupled to the enable delay generator to receive a delayed enable signal and provide the delayed enable signal to a plurality of enable terminals of the memory circuit. the third plurality of flip-flop circuits is coupled to an output terminal of the memory circuit. the reference delay generator provides a synchronized clock signal to the flip-flop circuits.
20240319323. RADAR APPARATUS, SYSTEM, AND METHOD_simplified_abstract_(intel corporation)
Inventor(s): Oren Shalita of Tel-Aviv (IL) for intel corporation, Ophir Shabtay of Tsofit (IL) for intel corporation, Yaniv Avital of Mevasseret Zion (IL) for intel corporation
IPC Code(s): G01S7/02, G01S13/89, G01S13/931
CPC Code(s): G01S7/023
Abstract: some demonstrative aspects include radar apparatuses, devices, systems and methods. in one example, a radar system may include one or more radar devices. for example, a radar device may include one or more transmit (tx) antennas to transmit radar tx signals, one or more receive (rx) antennas to receive radar rx signals, and a processor to generate radar information based on the radar rx signals. in one example, the radar system may be implemented as part of a vehicle. in other aspects, the radar system may include any other additional or alternative elements and/or may be implemented as part of any other device or system.
20240319326. RADAR APPARATUS, SYSTEM, AND METHOD_simplified_abstract_(intel corporation)
Inventor(s): Oren Shalita of Tel-Aviv (IL) for intel corporation, Yossi Tsfati of Rishon Le Zion (IL) for intel corporation, Ofer Markish of Ra'anana (IL) for intel corporation
IPC Code(s): G01S7/02, G01S7/03, G01S7/295, G01S13/931
CPC Code(s): G01S7/025
Abstract: some demonstrative aspects include radar apparatuses, devices, systems and methods. in one example, a radar system may include a plurality of radar devices. for example, a radar device may include one or more transmit (tx) antennas to transmit radar tx signals, one or more receive (rx) antennas to receive radar rx signals, and a processor to generate radar information based on the radar rx signals. in one example, the radar system may be implemented as part of a vehicle. in other aspects, the radar system may include any other additional or alternative elements and/or may be implemented as part of any other device or system.
Inventor(s): Oren Shalita of Tel-Aviv (IL) for intel corporation, Moshe Teplitsky of Tel-Aviv (IL) for intel corporation, Sharon Heruti of Tel-Aviv (IL) for intel corporation, Alon Cohen of Modi’in-Maccabim-Reut (IL) for intel corporation, Ophir Shabtay of Tsofit (IL) for intel corporation, Ilia Yoffe of Ashdod (IL) for intel corporation, Roy Sofer of Binyamina (IL) for intel corporation, Merav Sicron of Kfar-Saba (IL) for intel corporation
IPC Code(s): G01S7/40, G01S7/35, G01S13/58, G01S13/931
CPC Code(s): G01S7/4008
Abstract: for example, an apparatus may include a scheduler configured to determine scheduling information to schedule radar transmissions of a radar device during a sequence of radar frames. for example, the scheduler may be configured to determine a burst-based frame setting to schedule a sequence of radar burst transmissions during a radar frame of the sequence of radar frames. in one example, the burst-based frame setting may include a setting of a burst gap duration. in one example, the burst gap duration may include a duration of a burst gap between first and second consecutive radar burst transmissions of the sequence of radar burst transmissions.
Inventor(s): Xiaoqian Li of Chandler AZ (US) for intel corporation, Omkar G. Karhade of Chandler AZ (US) for intel corporation, Nitin A. Deshpande of Chandler AZ (US) for intel corporation, Julia Chiu of Portland OR (US) for intel corporation, Chia-Pin Chiu of Tempe AZ (US) for intel corporation, Kaveh Hosseini of Livermore CA (US) for intel corporation, Madhubanti Chatterjee of Portland OR (US) for intel corporation
IPC Code(s): G02B6/12, G02B6/136
CPC Code(s): G02B6/12002
Abstract: a photonic integrated circuit (pic), a semiconductor assembly including the pic, a multi-chip package including the pic, and a method of forming the pic. the pic includes a pic substrate, and a semiconductor layer on a top surface of the pic substrate and including a semiconductor material and an optical component. the pic substrate defines an air cavity therein extending in a direction from a bottom surface of the pic substrate toward and in registration with the optical component. the semiconductor layer is free of any opening therethrough in communication with the air cavity.
Inventor(s): Chia-Pin Chiu of Tempe AZ (US) for intel corporation, Kaveh Hosseini of Livermore CA (US) for intel corporation
IPC Code(s): G02B6/42
CPC Code(s): G02B6/4273
Abstract: in one embodiment, a photonic integrated circuit (pic) device includes conductive pads on a surface of the pic and a micro ring resonator (mrr) with a heater element centrally located between the conductive pads. the pic also includes a cavity defined within a substrate of the pic below the mrr, and a plurality of holes defined between the mrr and the conductive pads. the holes extend from a top surface of the pic into the cavity, and each hole is between a respective conductive pad and the mrr.
20240319772. CAMERA COVER WITH MULTIPLE INTEGRATED LENSES_simplified_abstract_(intel corporation)
Inventor(s): Surya Pratap Mishra of Portland OR (US) for intel corporation, Mark Edmund Sprenger of Tigard OR (US) for intel corporation, James M. Yoder of Beaverton OR (US) for intel corporation, Prosenjit Ghosh of Portland OR (US) for intel corporation, Jordan E. Maslov of Portland OR (US) for intel corporation
IPC Code(s): G06F1/16, G03B17/12, H04N23/51, H04N23/55
CPC Code(s): G06F1/1686
Abstract: in one embodiment, an apparatus includes a camera sensor within a housing and a camera cover comprising a plurality of lenses coupled to the housing. the camera cover is moveably coupled to the housing to allow each respective lens of the plurality of lenses to be optically aligned with the camera sensor.
Inventor(s): Ned M. Smith of Beaverton OR (US) for intel corporation, Kshitij Arun Doshi of Tempe AZ (US) for intel corporation, John Joseph Browne of Limerick (IE) for intel corporation, Vincent J. Zimmer of Tacoma WA (US) for intel corporation, Francesc Guim Bernat of Barcelona (ES) for intel corporation, Kapil Sood of Portland OR (US) for intel corporation
IPC Code(s): G06F8/65, G06F21/44, G06F21/64, H04L9/08, H04L9/12, H04L9/14, H04L9/32, H04L9/40
CPC Code(s): G06F8/65
Abstract: various systems and methods for enabling derivation and distribution of an attestation manifest for a software update image are described. in an example, these systems and methods include orchestration functions and communications, providing functionality and components for a software update process which also provides verification and attestation among multiple devices and operators.
Inventor(s): Subramaniam Maiyuran of Gold River CA (US) for intel corporation, Jorge Parra of El Dorado Hills CA (US) for intel corporation, Ashutosh Garg of Folsom CA (US) for intel corporation, Chandra Gurram of Folsom CA (US) for intel corporation, Chunhui Mei of San Diego CA (US) for intel corporation, Durgesh Borkar of Folsom CA (US) for intel corporation, Shubra Marwaha of Folsom CA (US) for intel corporation, Supratim Pal of Folsom CA (US) for intel corporation, Varghese George of Folsom CA (US) for intel corporation, Wei Xiong of Fremont CA (US) for intel corporation, Yan Li of San Diego CA (US) for intel corporation, Yongsheng Liu of San Diego CA (US) for intel corporation, Dipankar Das of Pune (IN) for intel corporation, Sasikanth Avancha of Bangalore (IN) for intel corporation, Dharma Teja Vooturi of Jagtial (IN) for intel corporation, Naveen K. Mellempudi of Bangalore (IN) for intel corporation
IPC Code(s): G06F9/30, G06F9/38, G06F15/80
CPC Code(s): G06F9/30036
Abstract: an apparatus to facilitate utilizing structured sparsity in systolic arrays is disclosed. the apparatus includes a processor comprising a systolic array to receive data from a plurality of source registers, the data comprising unpacked source data, structured source data that is packed based on sparsity, and metadata corresponding to the structured source data; identify portions of the unpacked source data to multiply with the structured source data, the portions of the unpacked source data identified based on the metadata; and output, to a destination register, a result of multiplication of the portions of the unpacked source data and the structured source data.
Inventor(s): Robert VALENTINE of Kiryat Tivon (IL) for intel corporation, Zeev SPERBER of Zikhron Yaakov (IL) for intel corporation, Mark J. CHARNEY of Lexington MA (US) for intel corporation, Bret L. TOLL of Hillsboro OR (US) for intel corporation, Jesus CORBAL of King City OR (US) for intel corporation, Dan BAUM of Haifa (IL) for intel corporation, Alexander HEINECKE of San Jose CA (US) for intel corporation, Elmoustapha OULD-AHMED-VALL of Chandler AZ (US) for intel corporation
IPC Code(s): G06F9/30, G06F7/485, G06F7/487, G06F7/76, G06F9/38, G06F17/16
CPC Code(s): G06F9/30036
Abstract: detailed herein are embodiment systems, processors, and methods for matrix move. for example, a processor comprising decode circuitry to decode an instruction having fields for an opcode, a source matrix operand identifier, and a destination matrix operand identifier; and execution circuitry to execute the decoded instruction to move each data element of the identified source matrix operand to corresponding data element position of the identified destination matrix operand is described.
Inventor(s): Jay LAWLOR of Hillsboro OR (US) for intel corporation, David SHEFFIELD of Portland OR (US) for intel corporation, Xiang ZOU of Portland OR (US) for intel corporation, Michael KINNEY of Woodinville WA (US) for intel corporation, Charles HOLTHAUS of Round Rock TX (US) for intel corporation, Thomas TOLL of Portland OR (US) for intel corporation, Salessawi Ferede YITBAREK of Hillsboro OR (US) for intel corporation, Andreas KLEEN of Portland OR (US) for intel corporation, Keshavan TIRUVALLUR of Tigard OR (US) for intel corporation, Sarathy JAYAKUMAR of Portland OR (US) for intel corporation, Ruiyu NI of Shanghai (CN) for intel corporation
IPC Code(s): G06F9/30, G06F9/48, G06F12/02, G06F12/1009
CPC Code(s): G06F9/30043
Abstract: an apparatus and method for a more efficient system management mode. for example, one embodiment of a processor comprises: a plurality of cores, at least a first core of the plurality of cores to perform operations to cause the plurality of cores to enter into a system management mode (smm), the operations comprising: allocating a memory region for a system management ram (smram); writing an smram state save location to a first register; and generating a page table in the smram, including mapping a virtual address space a physical address space.
Inventor(s): Junyong DING of Shanghai (CN) for intel corporation, Qi ZHANG of Shanghai (CN) for intel corporation, Shiyu ZHANG of Shanghai (CN) for intel corporation, Yuan CHEN of Shanghai (CN) for intel corporation, Hao XU of Shanghai (CN) for intel corporation, Tao PAN of Shanghai (CN) for intel corporation
IPC Code(s): G06F9/455
CPC Code(s): G06F9/45516
Abstract: various examples relate to an apparatus, a device, a method, and a computer program for executing code written in a dynamic script language and to an apparatus, a device, a method, and a computer program for providing code of a dynamic scripting language. the apparatus for executing code written in a dynamic script language comprises processing circuitry con-figured to obtain code written in the dynamic script language, obtain one or more profiles for accelerating an execution of the code, with the one or more profiles being bundled with the code, and execute the code based on the one or more profiles.
20240320043. VIRTUAL EXECUTION ENVIRONMENT POWER USAGE_simplified_abstract_(intel corporation)
Inventor(s): John J. BROWNE of Limerick (IE) for intel corporation, Chris MACNAMARA of Limerick (IE) for intel corporation
IPC Code(s): G06F9/48, G06F9/455
CPC Code(s): G06F9/4893
Abstract: examples described herein relate to determination of per-virtualized execution environment power usage based on an identifier of a processor that executes at least two virtualized execution environments, power usage of the processor, and number of virtualized execution environments executed by the processor.
Inventor(s): Jianhui Li of San Jose CA (US) for intel corporation, Zhennan Qin of Shanghai (CN) for intel corporation, Jiong Gong of Shanghai (CN) for intel corporation, Jingze Cui of Shanghai (CN) for intel corporation, Yijie Mei of Shanghai (CN) for intel corporation, Yunfei Song of Shanghai (CN) for intel corporation
IPC Code(s): G06F9/50
CPC Code(s): G06F9/5027
Abstract: systems, apparatuses and methods may provide for technology that identifies a data layout associated with input tensors and output tensors, generates a micro-kernel based at least in part on the data layout, and generates a nested outer loop for a kernel, wherein the micro-kernel performs one or more subtasks associated with a task represented by the kernel. the technology also includes micro-kernel code caches, fused kernel generators and cyclic dependence free graph partitioning for deep learning workloads.
Inventor(s): Xiaopeng TONG of Beijing (CN) for intel corporation, Qian LI of Portland OR (US) for intel corporation, Zongrui DING of Portland OR (US) for intel corporation, Alexandre Saso STOJANOVSKI of Paris (FR) for intel corporation, Thomas LUETZENKIRCHEN of () for intel corporation, Abhijeet KOLEKAR of Portland OR (US) for intel corporation, Youn Hyoung HEO of Seoul (KR) for intel corporation, Sangeetha L. BANGOLAE of Portland OR (US) for intel corporation, RongZhen YANG of Shanghai (CN) for intel corporation
IPC Code(s): G06F9/54, G06F16/242, G06F16/953, H04L67/60
CPC Code(s): G06F9/547
Abstract: this disclosure describes systems, methods, and devices for providing data query and manipulation services. a wireless communications network service-based architecture for providing data query and manipulation services may detect a request from a service consumer, received at a graphql interface of a network function, to query or manipulate data; and provide, using the graphql interface, a response to the request.
20240320100. WARM RESTART IN A NETWORK PROCESSOR DEVICE_simplified_abstract_(intel corporation)
Inventor(s): Robert Valiquette of Carignan (CA) for intel corporation, Alexandre Hamel of Brossard (CA) for intel corporation, Benoit Roy of Pierrefonds (CA) for intel corporation, Michel Noiseux of Brossard (CA) for intel corporation, Simon Perron Caissy of Saint-Constant (CA) for intel corporation, Benjamin H. Shelton of Eugene OR (US) for intel corporation
IPC Code(s): G06F11/14, H04L67/00, H04L69/28
CPC Code(s): G06F11/1438
Abstract: a warm restart is initiated at a network processor device, which includes a switch, one or more hardware components, and physical layer circuitry to implement one or more communication links. the switch is to be reset during the warm restart while the one or more communication links remain in an up state. a notification of the warm restart is sent to a set of drivers for the one or more hardware components and notifications are received from the set of drivers, where the notifications identify that reinitializations of the hardware components in association with the warm restart are complete. an indication is sent that the reinitializations of the hardware components are complete, where completion of the warm restart based on the indication.
Inventor(s): Kaijie Guo of Shanghai (CN) for intel corporation, Qianjun Xie of Shanghai (CN) for intel corporation, Weigang Li of Shanghai (CN) for intel corporation, Junyuan Wang of Shanghai (CN) for intel corporation, Ashok Raj of Portland OR (US) for intel corporation, Zijuan Fan of Shanghai (CN) for intel corporation
IPC Code(s): G06F12/1045, G06F9/30
CPC Code(s): G06F12/1045
Abstract: systems, methods, and apparatuses to support a device translation lookaside buffer pre-translation instruction are described. a hardware system includes an input/output device, an input/output memory controller to perform a direct memory access of a memory for the input/output device, and a processor core separate from the input/output device and comprising a decoder circuit to decode a single instruction into a decoded single instruction, the single instruction including one or more fields to identify a virtual address to physical address mapping for the input/output device in the memory, and an opcode to indicate an execution circuit is to store the virtual address to physical address mapping into a translation lookaside buffer within the input/output device, and the execution circuit to execute the decoded single instruction according to the opcode.
Inventor(s): Sean J. W. Lawrence of Bangalore (IN) for intel corporation, Peter Mark Ewert of Hillsboro OR (US) for intel corporation, Sajal Kumar Das of Bangalore (IN) for intel corporation, Sathyanarayana Nujella of Fremont CA (US) for intel corporation, Srikanth Potluri of Folsom CA (US) for intel corporation
IPC Code(s): G06F13/10, G06F9/455
CPC Code(s): G06F13/102
Abstract: methods, apparatus, systems, and articles of manufacture to automatically provisional peripheral data are disclosed. an example apparatus includes at least one programmable circuit to use a machine learning model to select a first application or a second application based on context information associated with at least one of the first application, the second application, or an input signal from a peripheral device; and forward the input signal to the selected one of the first application or the second application.
20240320179. SYSTEM DECODER FOR TRAINING ACCELERATORS_simplified_abstract_(intel corporation)
Inventor(s): Francesc Guim Bernat of Barcelona (ES) for intel corporation, Da-Ming Chiang of San Jose CA (US) for intel corporation, Kshitij A. Doshi of Tempe AZ (US) for intel corporation, Suraj Prabhakaran of Aachen (DE) for intel corporation, Mark A. Schmisseur of Phoenix AZ (US) for intel corporation
IPC Code(s): G06F13/40, G06F9/455, G06F9/50, G06F9/54, G06F13/362, G06F13/42, G06N3/02, G06N3/04, G06N3/045, G06N3/08
CPC Code(s): G06F13/4068
Abstract: there is disclosed an example of an artificial intelligence (ai) system, including: a first hardware platform; a fabric interface configured to communicatively couple the first hardware platform to a second hardware platform; a processor hosted on the first hardware platform and programmed to operate on an ai problem; and a first training accelerator, including: an accelerator hardware; a platform inter-chip link (icl) configured to communicatively couple the first training accelerator to a second training accelerator on the first hardware platform without aid of the processor; a fabric icl to communicatively couple the first training accelerator to a third training accelerator on a second hardware platform without aid of the processor; and a system decoder configured to operate the fabric icl and platform icl to share data of the accelerator hardware between the first training accelerator and second and third training accelerators without aid of the processor.
20240320184. MULTI-TILE ARCHITECTURE FOR GRAPHICS OPERATIONS_simplified_abstract_(intel corporation)
Inventor(s): Altug Koker of El Dorado Hills CA (US) for intel corporation, Ben Ashbaugh of Folsom CA (US) for intel corporation, Scott Janus of Loomis CA (US) for intel corporation, Aravindh Anantaraman of Folsom CA (US) for intel corporation, Abhishek R. Appu of El Dorado Hills CA (US) for intel corporation, Niranjan Cooray of Folsom CA (US) for intel corporation, Varghese George of Folsom CA (US) for intel corporation, Arthur Hunter of Cameron Park CA (US) for intel corporation, Brent E. Insko of Portland OR (US) for intel corporation, Elmoustapha Ould-Ahmed-Vall of Chandler AZ (US) for intel corporation, Selvakumar Panneer of Portland OR (US) for intel corporation, Vasanth Ranganathan of El Dorado Hills CA (US) for intel corporation, Joydeep Ray of Folsom CA (US) for intel corporation, Kamal Sinha of Rancho Cordova CA (US) for intel corporation, Lakshminarayanan Striramassarma of Folsom CA (US) for intel corporation, Prasoonkumar Surti of Folsom CA (US) for intel corporation, Saurabh Tangri of Folsom CA (US) for intel corporation
IPC Code(s): G06F15/78, G06F7/544, G06F7/575, G06F7/58, G06F9/30, G06F9/38, G06F9/50, G06F12/02, G06F12/06, G06F12/0802, G06F12/0804, G06F12/0811, G06F12/0862, G06F12/0866, G06F12/0871, G06F12/0875, G06F12/0882, G06F12/0888, G06F12/0891, G06F12/0893, G06F12/0895, G06F12/0897, G06F12/1009, G06F12/128, G06F15/80, G06F17/16, G06F17/18, G06N3/08, G06T1/20, G06T1/60, G06T15/06, H03M7/46
CPC Code(s): G06F15/7839
Abstract: embodiments are generally directed to a multi-tile architecture for graphics operations. an embodiment of an apparatus includes a multi-tile architecture for graphics operations including a multi-tile graphics processor, the multi-tile processor includes one or more dies; multiple processor tiles installed on the one or more dies; and a structure to interconnect the processor tiles on the one or more dies, wherein the structure to enable communications between processor tiles the processor tiles.
Inventor(s): Jiewen Yao of Shanghai (CN) for intel corporation, Vedvyas Shanbhogue of Austin TX (US) for intel corporation, Ravi Sahita of Portland OR (US) for intel corporation
IPC Code(s): G06F21/53, G06F21/64
CPC Code(s): G06F21/53
Abstract: systems, methods, and apparatuses for implementing a trusted execution environment security manager are described. in one example, hardware processor includes a hardware processor core comprising a trust domain manager to manage one or more hardware isolated virtual machines as a respective trust domain, a coupling between the hardware processor core and an input/output device, and a secure startup service circuit separate from the trust domain manager to, in response to a request from the trust domain manager, generate a secure communication session between the trust domain manager and the input/output device.
Inventor(s): Ziye YANG of Shanghai (CN) for intel corporation
IPC Code(s): G06F21/53, G06F21/54
CPC Code(s): G06F21/53
Abstract: a method, system, and apparatus for deploying application units within a computing cluster is disclosed. the apparatus includes memory circuitry, machine-readable instructions, and processor circuitry configured to identify a plurality of worker nodes, each with a hardware-based security resource. the apparatus receives deployment requests specifying security requirements, selects compatible worker nodes based on these requirements, and schedules the application units for execution on the selected nodes.
Inventor(s): Andreas KLEEN of Portland OR (US) for intel corporation, David SHEFFIELD of Portland OR (US) for intel corporation, Xiang ZOU of Portland OR (US) for intel corporation, Jason BRANDT of Austin TX (US) for intel corporation
IPC Code(s): G06F21/57, G06F9/30
CPC Code(s): G06F21/575
Abstract: an apparatus and method for booting a processor directly into a paged 64-bit execution environment. for example, one embodiment of an a processor comprises: a register to store a first value and a second value related to a secure boot process; a plurality of cores, at least one of which performs operations comprising: receiving a first initialization message, the core to clear a plurality of registers responsively; receiving a second initialization message and reading the first and second values responsively, the first value indicating whether a first initialization mode is supported, and the second value comprising an address pointer identifying a data structure comprising a plurality of state values; and initializing a paged 64-bit execution environment using the state values from the data structure responsive to the first value indicating the first initialization mode is supported and the data structure indicating enabling the paged 64-bit execution environment.
Inventor(s): Saravanan SETHURAMAN of Portland OR (US) for intel corporation, George VERGIS of Portland OR (US) for intel corporation
IPC Code(s): G06F21/60
CPC Code(s): G06F21/602
Abstract: a memory subsystem allows the memory controller and the memory to create a trusted communication channel based on a certificate exchange. the memory and memory controller have a key storage to store the certificates. the memory controller can be restricted to only be enabled to access a system data storage array after the trusted communication channel is established.
Inventor(s): Jainaveen Sundaram Priya of Hillsboro OR (US) for intel corporation, Prerna Budhkar of Hillsboro OR (US) for intel corporation, Vui Seng Chua of Hillsboro OR (US) for intel corporation, Srivatsa Rangachar Srinivasa of Hillsboro OR (US) for intel corporation, Tanay Karnik of Portland OR (US) for intel corporation
IPC Code(s): G06N3/08, G06N3/048
CPC Code(s): G06N3/08
Abstract: a modified 2-pass version of the softmax operation can be implemented to address reduce computational cost without loss of accuracy, in particular for deep learning neural networks such as transformer-based neural networks and large language models (llms). the first pass is modified to include two scalar operations at the end. at the end of the first pass, a first scalar operation is performed to calculate a logarithm of the denominator, and a second scalar operation is performed to calculate an operand value based on a sum of the logarithm of the denominator and the maximum value. the second pass is modified to perform addition and exponentiation. in the second pass, an element of an input tensor is subtracted by the operand value to obtain an exponent, and a base is raised to the exponent. the second pass avoids divisions.
Inventor(s): Lorenzo TESSARI of Baden Wuerttemberg (DE) for intel corporation
IPC Code(s): G06T1/60, G06T1/20
CPC Code(s): G06T1/60
Abstract: apparatus and method for density-aware stochastic subsets for improved importance sampling. for example, one embodiment of an apparatus comprises: a sampling weight generator to determine a plurality of sampling weights associated with a corresponding plurality of input primitives, the sampling weight generator to determine each sampling weight based on a surface area or diagonal of a bounding box of the corresponding input primitive and a plurality of distance values corresponding to distances between the input primitive and a corresponding plurality of neighboring input primitives; a sampler to identify a representative subset of the input primitives based, at least in part, on the plurality of sampling weights; bounding volume hierarchy (bvh) builder hardware logic to construct an approximate bvh based on the representative subset of input primitives; hardware logic to insert input primitives not in the representative subset into leaves of the approximate bvh; and the bvh builder or a different bvh builder to construct a final bvh based on the primitives inserted into the leaves of the approximate bvh.
Inventor(s): Anthony Rhodes of Portland OR (US) for intel corporation, Ilke Demir of Hermosa Beach CA (US) for intel corporation, Yali Bian of Fremont CA (US) for intel corporation
IPC Code(s): G06V10/74, G06V10/46
CPC Code(s): G06V10/761
Abstract: an example apparatus includes interface circuitry, machine-readable instructions, and at least one processor circuit to be programmed by the machine-readable instructions to access a first saliency map and a second saliency map associated with an image dataset, encode pixel-level intensity of the first saliency map, encode pixel-level intensity of the second saliency map, generate a saliency comparison metric based on the pixel-level intensity of the first saliency map and the pixel-level intensity of the second saliency map, and compare spatial properties of the first saliency map and the second saliency map using the saliency comparison metric.
20240321656. GLASS CORE SUBSTRATE WITH LGA NOTCH_simplified_abstract_(intel corporation)
Inventor(s): Gang DUAN of Chandler AZ (US) for intel corporation, Aaron GARELICK of Chandler AZ (US) for intel corporation, Brandon C. MARIN of Gilbert AZ (US) for intel corporation, Srinivas V. PIETAMBARAM of Chandler AZ (US) for intel corporation
IPC Code(s): H01L23/15, H01L23/498
CPC Code(s): H01L23/15
Abstract: embodiments disclosed herein include package substrates. in an embodiment, the package substrate comprises a core, where the core comprises glass, and an insert in the core. in an embodiment, the insert is a different material than the core. in an embodiment, a first layer is over the core and a second layer is under the core. in an embodiment, a notch is provided through the first layer, the core, and the second layer. in an embodiment, the notch passes through the insert in the core.
Inventor(s): Darko Grujicic of Chandler AZ (US) for intel corporation, Suddhasattwa Nad of Chandler AZ (US) for intel corporation, Srinivas Pietambaram of Chandler AZ (US) for intel corporation, Rengarajan Shanmugam of Tempe AZ (US) for intel corporation, Marcel Wall of Phoenix AZ (US) for intel corporation, Sashi Kandanur of Chandler AZ (US) for intel corporation, Rahul Manepalli of Chandler AZ (US) for intel corporation, Robert May of Chandler AZ (US) for intel corporation
IPC Code(s): H01L23/15, H01L23/498
CPC Code(s): H01L23/15
Abstract: photonic integrated circuit packages and methods of manufacturing are disclosed. an example integrated circuit package includes: a semiconductor die; a package substrate supporting the semiconductor die, the package substrate including a glass core, the glass core including a through glass via extending between opposing first and second surfaces of the glass core, the glass core including a recess spaced apart from the through glass via, the recess defined by a third surface of the glass core, the recess having a different shape than the through glass via; and a reflective metal disposed on the third surface to define a mirror, the reflective metal also disposed between a wall of the through glass via and a conductive material disposed in the through glass via.
Inventor(s): Shakul Tandon of Portland OR (US) for intel corporation
IPC Code(s): H01L23/31, H01L21/56, H01L23/00, H01L23/498, H01L23/532, H01L25/065, H01L25/10
CPC Code(s): H01L23/3107
Abstract: embodiments of semiconductor devices with stitched guard rings, along with methods and lithographic reticles for forming the same, are disclosed herein. in one example, a semiconductor die includes a substrate with integrated circuitry, and a guard ring surrounding the integrated circuitry. the guard ring includes traces arranged in a pattern of lines and rungs, where the lines extend around the integrated circuitry and the rungs extend crosswise between at least some of the lines.
Inventor(s): Leonard P. Guler of Hillsboro OR (US) for intel corporation, Shengsi Liu of Portland OR (US) for intel corporation, Saurabh Acharya of Hillsboro OR (US) for intel corporation, Baofu Zhu of Portland OR (US) for intel corporation, Charles H. Wallace of Portland OR (US) for intel corporation
IPC Code(s): H01L23/48, H01L21/768, H01L21/8234, H01L27/088
CPC Code(s): H01L23/481
Abstract: techniques are provided herein to form semiconductor devices arranged between a gate cut on one side and a deep backside via on the other side. a row of semiconductor devices each include a semiconductor region extending in a first direction between corresponding source or drain regions, and a gate structure extending in a second direction over the semiconductor regions. each semiconductor device may be separated from an adjacent semiconductor device along the second direction by either a gate cut or a deep backside via. the gate cut may be a dielectric wall that extends through an entire thickness of the gate structure and the deep backside via may include a conductive layer and a dielectric barrier that also extend through at least an entire thickness of the gate structure. each semiconductor device may include a gate cut on one side and a deep backside via on the other side.
Inventor(s): Leonard P. Guler of Hillsboro OR (US) for intel corporation, Charles H. Wallace of Portland OR (US) for intel corporation, Shengsi Liu of Portland OR (US) for intel corporation, Saurabh Acharya of Hillsboro OR (US) for intel corporation
IPC Code(s): H01L23/528, H01L27/092, H01L29/06, H01L29/423, H01L29/66, H01L29/778
CPC Code(s): H01L23/5283
Abstract: techniques are provided herein to form semiconductor devices having one or more source or drain regions with backside contacts that are separated using dielectric walls. in an example, a first semiconductor device includes a first semiconductor region, such as one or more first nanoribbons, extending from a first source or drain region, and a second semiconductor device including a second semiconductor region, such as one or more second nanoribbons, extending from a second source or drain region adjacent to the first source or drain region. a first conductive contact abuts the underside of the first source or drain region and a second conductive contact abuts the underside of the second source or drain region. a dielectric wall extends between the first and second contacts, thus separating them from contacting each other. the dielectric wall also extends between the first source or drain region and the second source or drain region.
20240321738. BRIDGING CONTACT STRUCTURES_simplified_abstract_(intel corporation)
Inventor(s): Leonard P. Guler of Hillsboro OR (US) for intel corporation, Prabhjot Kaur Luthra of Portland OR (US) for intel corporation, Nidhi Khandelwal of Portland OR (US) for intel corporation, Marie T. Conte of Hillsboro OR (US) for intel corporation, Saurabh Acharya of Hillsboro OR (US) for intel corporation, Shengsi Liu of Portland OR (US) for intel corporation, Gary Allen of Portland OR (US) for intel corporation, Clifford J. Engel of Hillsboro OR (US) for intel corporation, Charles H. Wallace of Portland OR (US) for intel corporation
IPC Code(s): H01L23/528, H01L27/092, H01L29/06, H01L29/423, H01L29/66, H01L29/778
CPC Code(s): H01L23/5283
Abstract: techniques to form an integrated circuit having a bridging contact structure. a bridging contact structure may, for example, bridge between source/drain contacts and to an adjacent gate electrode within the same device layer. in an example, a gate cut structure extends in a first direction to separate the source or drain regions and gate structures of neighboring semiconductor devices. contacts may be formed over the source or drain regions of the neighboring devices on opposite sides of the gate cut along a second direction orthogonal to the first direction. a portion of the gate cut is replaced with a first conductive bridge between the source or drain contacts. a portion of one or more dielectric barriers between one of the source or drain contacts and an adjacent gate electrode is replaced with a second conductive bridge in the first direction between the source or drain contact and the gate structure.
Inventor(s): Kristof Kuwawi Darmawikarta of Chandler AZ (US) for intel corporation, Srinivas V. Pietambaram of Chandler AZ (US) for intel corporation
IPC Code(s): H01L23/538, H01L23/15
CPC Code(s): H01L23/5384
Abstract: disclosed herein are microelectronic assemblies including strengthened glass layers, as well as related devices and methods. in some embodiments, a microelectronic assembly may include a glass layer having a first surface, an opposing second surface, and side surfaces extending between the first and second surfaces; a material on the first, second, and side surfaces of the glass layer, the material including an epoxy material, a mold material, or a dielectric material; a via extending through the glass layer and through the material on the first and second surfaces, the via including a conductive material; and a dielectric layer on the material at the first surface of the glass layer, the dielectric layer including a conductive pathway electrically coupled to the via.
20240321762. HIGH DENSITY ORGANIC BRIDGE DEVICE AND METHOD_simplified_abstract_(intel corporation)
Inventor(s): Mihir K. Roy of Chandler AZ (US) for intel corporation, Stefanie M. Lotz of Phoenix AZ (US) for intel corporation, Wei-Lun Kane Jen of Phoenix AZ (US) for intel corporation
IPC Code(s): H01L23/538, H01L21/48, H01L23/00, H01L23/13, H01L23/14, H01L23/498, H01L25/065, H05K1/03, H05K1/14, H05K1/18, H05K3/34, H05K3/46
CPC Code(s): H01L23/5386
Abstract: embodiments that allow multi-chip interconnect using organic bridges are described. in some embodiments an organic package substrate has an embedded organic bridge. the organic bridge can have interconnect structures that allow attachment of die to be interconnected by the organic bridge. in some embodiments, the organic bridge comprises a metal routing layer, a metal pad layer and interleaved organic polymer dielectric layers but without a substrate layer. embodiments having only a few layers may be embedded into the top layer or top few layers of the organic package substrate. methods of manufacture are also described.
Inventor(s): Andrew COLLINS of Chandler AZ (US) for intel corporation, Sujit SHARAN of Chandler AZ (US) for intel corporation, Jianyong XIE of Chandler AZ (US) for intel corporation
IPC Code(s): H01L23/66, H01L21/48, H01L23/48, H01L23/522, H01L23/528, H01L23/538, H01L25/00, H01L25/16
CPC Code(s): H01L23/66
Abstract: a package substrate is disclosed. the package substrate includes a die package in the package substrate located at least partially underneath a location of a power delivery interface in a die that is coupled to the surface of the package substrate. connection terminals are accessible on a surface of the die package to provide connection to the die that is coupled to the surface of the package substrate. metal-insulator-metal layers inside the die package are coupled to the connection terminals.
Inventor(s): Jonas CROISSANT of Hillsboro OR (US) for intel corporation, Xavier F. BRUN of Chandler AZ (US) for intel corporation, Gustavo BELTRAN of Chandler AZ (US) for intel corporation, Roberto SERNA of Chandler AZ (US) for intel corporation, Ye Seul NAM of Chandler AZ (US) for intel corporation, Timothy GOSSELIN of Phoenix AZ (US) for intel corporation, Jesus S. NIETO PESCADOR of Chandler AZ (US) for intel corporation, Dingying David XU of Chandler AZ (US) for intel corporation, John C. DECKER of Tempe AZ (US) for intel corporation, Ifeanyi OKAFOR of Gilbert AZ (US) for intel corporation, Yiqun BAI of Chandler AZ (US) for intel corporation
IPC Code(s): H01L23/00, H01L25/16
CPC Code(s): H01L24/32
Abstract: embodiments disclosed herein include multi-die modules. in an embodiment, the multi-die module comprises a first die and a second die coupled to the first die. in an embodiment, the second die comprises a keep out zone that at least partially overlaps the first die. the multi-die module may further comprise an underfill between the first die and the second die. in an embodiment, the underfill is entirely outside the keep out zone, and an edge of the underfill facing the keep out zone is non-vertical.
Inventor(s): Tao Chu of Portland OR (US) for intel corporation, Minwoo Jang of Portland OR (US) for intel corporation, Yanbin Luo of Portland OR (US) for intel corporation, Paul Packan of Hillsboro OR (US) for intel corporation, Guowei Xu of Portland OR (US) for intel corporation, Chiao-Ti Huang of Portland OR (US) for intel corporation, Robin Chao of Portland OR (US) for intel corporation, Feng Zhang of Hillsboro OR (US) for intel corporation, Anand S. Murthy of Portland OR (US) for intel corporation, Tahir Ghani of Portland OR (US) for intel corporation
IPC Code(s): H01L27/02, H01L27/088
CPC Code(s): H01L27/0207
Abstract: an ic device may include an array of transistors. the transistors may have separate gate electrodes. a gate electrode may include polysilicon. the gate electrodes may be separated from each other by one or more electrical insulators. the separated gate electrodes have shorter lengths, compared with connected gate electrodes, which can optimize the performance of the ic device due to local layout effect. also, the ic device may include conductive structures crossing the support structures of multiple transistors. such conductive structures may cause strain in the ic device, which can boost the local layout effect. the conductive structures may be insulated from a power plane. alternatively or additionally, the ic device may include dielectric structures, which may be formed by removing gate electrodes in some of the transistors and providing a dielectric material into the openings. the presence of the dielectric structures can further boost the local layout effect.
Inventor(s): Leonard P. Guler of Hillsboro OR (US) for intel corporation, Shengsi Liu of Portland OR (US) for intel corporation, Saurabh Acharya of Hillsboro OR (US) for intel corporation, Thomas Obrien of Portland OR (US) for intel corporation, Krishna Ganesan of Portland OR (US) for intel corporation, Ankit Kirit Lakhani of Hillsboro OR (US) for intel corporation, Prabhjot Kaur Luthra of Portland OR (US) for intel corporation, Nidhi Khandelwal of Portland OR (US) for intel corporation, Clifford J. Engel of Hillsboro OR (US) for intel corporation, Baofu Zhu of Portland OR (US) for intel corporation, Meenakshisundaram Ramanathan of Hillsboro OR (US) for intel corporation
IPC Code(s): H01L27/088, H01L21/8234, H01L29/06, H01L29/423, H01L29/778, H01L29/786
CPC Code(s): H01L27/088
Abstract: techniques to form an integrated circuit having a gate cut between adjacent pairs of semiconductor devices. at least one of those adjacent pairs of semiconductor devices includes a conductive link (e.g., a bridge) through the gate cut to connect the adjacent gates together. in an example, neighboring semiconductor devices each include a semiconductor region extending between a source region and a drain region, and a gate structure extending over the semiconductor regions of the neighboring semiconductor devices. a gate cut is present between each pair of neighboring semiconductor devices thus interrupting the gate structure and isolating the gate of one semiconductor device from the gate of the other semiconductor device. a conductive link extends over a given gate cut to electrically connect the adjacent gate electrodes together. a dielectric layer extends over the bridged gate electrodes and the conductive link, and may have different thicknesses over those respective features.
Inventor(s): Tao Chu of Portland OR (US) for intel corporation, Yanbin Luo of Portland OR (US) for intel corporation, Yusung Kim of Portland OR (US) for intel corporation, Minwoo Jang of Portland OR (US) for intel corporation, Paul Packan of Hillsboro OR (US) for intel corporation, Guowei Xu of Portland OR (US) for intel corporation, Chiao-Ti Huang of Portland OR (US) for intel corporation, Robin Chao of Portland OR (US) for intel corporation, Feng Zhang of Hillsboro OR (US) for intel corporation, Yang Zhang of Rio Rancho NM (US) for intel corporation, Zheng Guo of Hillsboro OR (US) for intel corporation
IPC Code(s): H01L27/092, H01L29/49
CPC Code(s): H01L27/0922
Abstract: an ic device may have layout with reduced n-p boundary effect. the ic device may include two rows of transistors. the first row may include one or more p-type transistors. the second row may include n-type transistors. the gate electrode of a p-type transistor may include different conductive materials from the gate electrode of a n-type transistor. each p-type transistor in the first row may be over a n-type transistor in the second row and contact the n-type transistor in the second row. for instance, the gate of the p-type transistor may contact the gate of the n-type transistor. vacancy diffusion may occur at the boundary of the p-type transistor and the n-type transistor, causing n-p boundary effect. at least one or more other n-type transistors in the second row do not contact any p-type transistor, which can mitigate the n-p boundary effect in the ic device.
Inventor(s): Leonard P. Guler of Hillsboro OR (US) for intel corporation, Glenn Glass of Portland OR (US) for intel corporation, Jessica Panella of Banks OR (US) for intel corporation, Dan S. Lavric of Portland OR (US) for intel corporation, Charles H. Wallace of Portland OR (US) for intel corporation
IPC Code(s): H01L27/12, H01L21/84
CPC Code(s): H01L27/1203
Abstract: techniques to form semiconductor devices having one or more epitaxial source or drain regions formed between dielectric walls that separate each adjacent pair of source or drain regions. in an example, a semiconductor device includes a semiconductor region extending in a first direction from a source or drain region. dielectric walls extend in the first direction adjacent to opposite sides of the source or drain region. the first and second dielectric walls also extend in the first direction through a gate structure present over the semiconductor region. a dielectric liner exists between at least a portion of the first side of the source or drain region and the first dielectric wall and/or at least a portion of the second side of the source or drain region and the second dielectric wall. the dielectric walls may separate the source or drain region from other adjacent source or drain regions.
20240321962. ROUNDED NANORIBBONS WITH REGROWN CAPS_simplified_abstract_(intel corporation)
Inventor(s): Tao Chu of Portland OR (US) for intel corporation, Robin Chao of Portland OR (US) for intel corporation, Guowei Xu of Portland OR (US) for intel corporation, Feng Zhang of Hillsboro OR (US) for intel corporation, Minwoo Jang of Portland OR (US) for intel corporation
IPC Code(s): H01L29/06, H01L21/8238, H01L27/092, H01L29/775
CPC Code(s): H01L29/068
Abstract: described herein are nanoribbon-based transistor devices in which the nanoribbons have rounded cross-sections. the nanoribbons may include caps or outer layers of semiconductor channel material grown over an inner layer of semiconductor channel material. different materials may be used for the outer layers of nmos and pmos transistors. in one example, an integrated circuit device includes nmos transistors formed from or more nanoribbons with rounded cross-sections and an outer layer of silicon, and a pmos transistors formed from or more nanoribbons with rounded cross-sections and an outer layer of silicon germanium.
Inventor(s): Leonard P. Guler of Hillsboro OR (US) for intel corporation, Shengsi Liu of Portland OR (US) for intel corporation, Baofu Zhu of Portland OR (US) for intel corporation, Charles H. Wallace of Portland OR (US) for intel corporation, Clifford J. Engel of Hillsboro OR (US) for intel corporation, Gary Allen of Portland OR (US) for intel corporation, Saurabh Acharya of Hillsboro OR (US) for intel corporation, Thomas Obrien of Portland OR (US) for intel corporation
IPC Code(s): H01L29/417, H01L29/06, H01L29/40, H01L29/423, H01L29/66, H01L29/775
CPC Code(s): H01L29/41733
Abstract: techniques are provided herein to form semiconductor devices that include a contact over a given source or drain region that extends over the top of an adjacent source or drain region without contacting it. in an example, a semiconductor device includes a gate structure around a fin of semiconductor material that extends from a source or drain region, or one or more nanowires or nanoribbons or nanosheets of semiconductor material that extend from the source or drain region. a conductive contact is formed over the source or drain region that extends laterally across the source/drain trench above an adjacent source or drain region without contacting the adjacent source or drain region. the contact may extend along the source/drain trench through a dielectric wall (e.g., a gate cut) that extends orthogonally through the source/drain trench.
Inventor(s): Tao Chu of Portland OR (US) for intel corporation, Guowei Xu of Portland OR (US) for intel corporation, Robin Chao of Portland OR (US) for intel corporation, Chiao-Ti Huang of Portland OR (US) for intel corporation, Feng Zhang of Hillsboro OR (US) for intel corporation, Minwoo Jang of Portland OR (US) for intel corporation, Chia-Ching Lin of Portland OR (US) for intel corporation, Biswajeet Guha of Hillsboro OR (US) for intel corporation, Yue Zhong of Portland OR (US) for intel corporation, Anand S. Murthy of Portland OR (US) for intel corporation
IPC Code(s): H01L29/423, H01L27/088, H01L29/06, H01L29/66, H01L29/775, H01L29/78, H01L29/786
CPC Code(s): H01L29/42392
Abstract: described herein are integrated circuit devices that include both nanoribbon-based transistors and fin-shaped transistors. the nanoribbon transistors may have shorter channel lengths than the fin transistors. in addition, the nanoribbon transistors may have thinner gate dielectrics than the fin transistors.
20240322775. THREE-DIMENSIONAL POWER COMBINERS_simplified_abstract_(intel corporation)
Inventor(s): Telesphor Kamgaing of Chandler AZ (US) for intel corporation, Peter Baumgartner of Munich (DE) for intel corporation, Steven Callender of Denver CO (US) for intel corporation, Richard Geiger of Munich (DE) for intel corporation, Harald Gossner of Riemerling (DE) for intel corporation, Jonathan Jensen of Portland OR (US) for intel corporation
IPC Code(s): H03F3/60, H01L23/66, H03F3/195, H03F3/24
CPC Code(s): H03F3/602
Abstract: disclosed herein are electronic assemblies, integrated circuit (ic) packages, and communication devices implementing three-dimensional power combiners. an electronic assembly may include a first die, comprising a first transmission line, and a second die, comprising a second transmission line. each die includes a first face and an opposing second face, and the second die is stacked above the first die so that the first face of the second die is coupled to the second face of the first die. the electronic assembly further includes a first conductive pathway between one end of the first transmission line and a first connection point at the first face of the first die, a second conductive pathway between one end of the second transmission line and a second connection point at the first face of the first die, and a third conductive pathway between the other ends of the first and second transmission lines.
Inventor(s): Gang XIONG of Portland OR (US) for intel corporation, Yingyang LI of Beijing (CN) for intel corporation, Debdeep CHATTERJEE of San Jose CA (US) for intel corporation, Sergey SOSNIN of Zavolzhie (RU) for intel corporation, Gregory ERMOLAEV of Nizhny Novgorod (RU) for intel corporation
IPC Code(s): H04L1/08, H04L5/14
CPC Code(s): H04L1/08
Abstract: this disclosure describes systems, methods, and devices for physical uplink shared channel (pusch) repetition for half duplex frequency division duplex (hd-fdd) wireless operations. a user equipment (ue) device may detect a use of hd-fdd operations; identify an available time slot during which to transmit a pusch repetition for the hd-fdd operations; and encode the pusch repetition to be transmitted during the available time slot.
Inventor(s): Laurent CARIOU of Milizac (FR) for intel corporation, Thomas J. KENNEY of Portland OR (US) for intel corporation
IPC Code(s): H04L1/1607
CPC Code(s): H04L1/1635
Abstract: this disclosure describes systems, methods, and devices related to enhanced acknowledgment. a device may identify a physical layer (phy) convergence protocol data unit (ppdu) received from an access point (ap), wherein the ppdu comprises a header and a payload. the device may generate a failure of decoding the payload. the device may generate an acknowledgment indicating the failure and indicating additional information to assist the ap in determining a failure reason. the device may cause to send the acknowledgment to the ap.
Inventor(s): Oliver GRAU of Hannover (DE) for intel corporation, Deepak VEMBAR of Portland OR (US) for intel corporation
IPC Code(s): H04N13/344, H04N13/156, H04N13/383
CPC Code(s): H04N13/344
Abstract: a system and method for foveated stereo rendering. for example, one embodiment of an apparatus comprises: a graphics processor comprising graphics processing circuitry to render images of a graphics scene to be displayed in a head mounted display (hmd); and an interface to couple the graphics processing circuitry to the hmd, wherein to render the images, the graphics processing circuitry is to perform operations comprising: rendering a peripheral image having a first resolution based on a first viewpoint of the graphics scene, rendering first and second foveal regions of the graphics scene at a second resolution higher than the first resolution, wherein the first foveal region is based on a second viewpoint of the graphics scene corresponding to the first hmd display, and the second foveal region is based on a third viewpoint of the graphics scene corresponding to the second hmd display, and blending the first foveal region with the peripheral image to render a first final image to be displayed on the first hmd display, and blending the second foveal region with the peripheral image to render a second final image to be displayed on the second hmd display.
Inventor(s): Jill Boyce of Portland OR (US) for intel corporation, Lidong Xu of Beijing (CN) for intel corporation
IPC Code(s): H04N19/46, H04N19/136, H04N19/146, H04N19/167, H04N19/172, H04N19/42
CPC Code(s): H04N19/46
Abstract: disclosed examples populate a supplemental enhancement information (sei) message with a value corresponding to a number of subpictures of a video sequence; populate a level indicator in the sei message; populate a subpicture identifier; populate the subpicture identifier in a slice header, and cause the sei message and the slice header to be included in a video bitstream.
Inventor(s): Liuyang YANG of Vancouver WA (US) for intel corporation, Ignacio J. ALVAREZ of Portland OR (US) for intel corporation, Xiruo LIU of Portland OR (US) for intel corporation, Kathiravetpillai SIVANESAN of Portland OR (US) for intel corporation, Leonardo GOMES BALTAR of Munich (DE) for intel corporation
IPC Code(s): H04W4/38, G06Q50/40, H04W4/40
CPC Code(s): H04W4/38
Abstract: the present disclosure is related to vehicle-to-everything (v2x) and intelligent transport system (its) communications technologies, and in particular, to misbehavior detection and misbehavior reporting services for collective perception messages (cpms). the misbehavior detection mechanisms include one or more data consistency checks, including a multi-step systematic data consistency check within individual cpms, across multiple cpms from the same transmitter, and across multiple cpms from different transmitters. potential misbehaviors are reported to a misbehavior authority in one or more misbehavior reports.
20240323711. GOOD CELL QUALITY CRITERIA_simplified_abstract_(intel corporation)
Inventor(s): Hua LI of Beijing (CN) for intel corporation, Andrey CHERVYAKOV of Maynooth (IE) for intel corporation, Ilya BOLOTIN of Nizhny Novgorod (RU) for intel corporation, Dmitry BELOV of Nizhny Novgorod (RU) for intel corporation, Rui HUANG of Beijing (CN) for intel corporation, Meng ZHANG of Beijing (CN) for intel corporation
IPC Code(s): H04W24/02, H04W24/08
CPC Code(s): H04W24/02
Abstract: this disclosure describes systems, methods, and devices related to good cell criteria. a device may establish a relaxation criteria for radio link monitoring (rlm) and beam failure detection (bfd). the device may utilize the relaxation criteria to assist a user equipment (ue) to enter or exit a relaxed condition. the device may apply a relaxation threshold to both rlm and bfd, wherein the relaxation threshold is based on a signal to noise ratio (snr) of at least one reference signal (rs).
Inventor(s): Avik SENGUPTA of San Jose CA (US) for intel corporation, Debdeep CHATTERJEE of San Jose CA (US) for intel corporation
IPC Code(s): H04W72/1273, H04L1/00, H04W72/231, H04W76/20, H04W76/40
CPC Code(s): H04W72/1273
Abstract: the disclosure is directed to systems and methods for multicast and broadcast services (mbs) for a wireless network including transmitting to a user equipment (ue) a signaling configuration for reception by the ue of multicast and broadcast services (mbs) in a low quality of service (qos) multicast or broadcast delivery using an multicast control channel (mcch) carried over a physical downlink shared channel (pdsch) scheduled by a downlink control information (dci) holding a cyclic redundancy check (crc) scrambled with a dedicated radio network temporary identifier (rnti) identifying the low qos or broadcast reception capability of the ue. the method includes monitoring by the ue a physical downlink control channel (pdcch) cell specific search space (css) configured for mbs for the dci scheduling, the pdsch carrying the mcch in the dci. the pdcch css is configured for a coreset #0 for the ue in rrc_connected/idle mode, the monitoring in type0 pdcch css or type0a pdcch css configured as part of a pdcch-configcommon configuration.
Inventor(s): Juha T. Paavola of Hillsboro OR (US) for intel corporation
IPC Code(s): H05K3/30, H05K1/02, H05K1/16, H05K1/18
CPC Code(s): H05K3/301
Abstract: architectures and methods for a reworkable heat management component. a “debonding film” is deposited in cooperation with an adhesive to provide reworkable (“peelable”) heat management solutions for a variety of heat management components and ic components.
Inventor(s): Juha Tapani Paavola of Hillsboro OR (US) for intel corporation, Christopher Moore of Warren OR (US) for intel corporation, Jeff Ku of Taipei (TW) for intel corporation, Prakash Kurma Raju of Bangalore (IN) for intel corporation
IPC Code(s): H05K7/20, G06F1/20
CPC Code(s): H05K7/20336
Abstract: cooling systems with heat pipes for electronic devices are disclosed herein. an example cooling system includes a heat pipe having a top wall and a bottom wall. the heat pipe contains a fluid. the cooling system includes a wick disposed in the heat pipe and a stiffener coupled to the wick. the stiffener contacts the top wall and the bottom wall of the heat pipe.
Inventor(s): Sudipto Naskar of Portland OR (US) for intel corporation, Abhishek Anil Sharma of Portland OR (US) for intel corporation, Sukru Yemenicioglu of Portland OR (US) for intel corporation, Weimin Han of Portland OR (US) for intel corporation, Van Le of Beaverton OR (US) for intel corporation
IPC Code(s): H10B12/00
CPC Code(s): H10B12/00
Abstract: a high performance (hp) thin film transistor (tft) architecture to enable fabricating backside memory after metallization starts, or as part of back end of line (beol) processes. the hp tft material is suitable for fabricating the memory stack at the lower beol temperatures while still delivering the switching speed requirements of a 3d memory stack in the cim component. a through silicon via (tsv) architecture connects the logic and the memory in the die.
Intel Corporation patent applications on September 26th, 2024
- Intel Corporation
- G01C21/34
- B25J5/00
- B25J9/16
- CPC G01C21/3407
- Intel corporation
- G01R31/317
- G01R31/3185
- CPC G01R31/31725
- G01S7/02
- G01S13/89
- G01S13/931
- CPC G01S7/023
- G01S7/03
- G01S7/295
- CPC G01S7/025
- G01S7/40
- G01S7/35
- G01S13/58
- CPC G01S7/4008
- G02B6/12
- G02B6/136
- CPC G02B6/12002
- G02B6/42
- CPC G02B6/4273
- G06F1/16
- G03B17/12
- H04N23/51
- H04N23/55
- CPC G06F1/1686
- G06F8/65
- G06F21/44
- G06F21/64
- H04L9/08
- H04L9/12
- H04L9/14
- H04L9/32
- H04L9/40
- CPC G06F8/65
- G06F9/30
- G06F9/38
- G06F15/80
- CPC G06F9/30036
- G06F7/485
- G06F7/487
- G06F7/76
- G06F17/16
- G06F9/48
- G06F12/02
- G06F12/1009
- CPC G06F9/30043
- G06F9/455
- CPC G06F9/45516
- CPC G06F9/4893
- G06F9/50
- CPC G06F9/5027
- G06F9/54
- G06F16/242
- G06F16/953
- H04L67/60
- CPC G06F9/547
- G06F11/14
- H04L67/00
- H04L69/28
- CPC G06F11/1438
- G06F12/1045
- CPC G06F12/1045
- G06F13/10
- CPC G06F13/102
- G06F13/40
- G06F13/362
- G06F13/42
- G06N3/02
- G06N3/04
- G06N3/045
- G06N3/08
- CPC G06F13/4068
- G06F15/78
- G06F7/544
- G06F7/575
- G06F7/58
- G06F12/06
- G06F12/0802
- G06F12/0804
- G06F12/0811
- G06F12/0862
- G06F12/0866
- G06F12/0871
- G06F12/0875
- G06F12/0882
- G06F12/0888
- G06F12/0891
- G06F12/0893
- G06F12/0895
- G06F12/0897
- G06F12/128
- G06F17/18
- G06T1/20
- G06T1/60
- G06T15/06
- H03M7/46
- CPC G06F15/7839
- G06F21/53
- CPC G06F21/53
- G06F21/54
- G06F21/57
- CPC G06F21/575
- G06F21/60
- CPC G06F21/602
- G06N3/048
- CPC G06N3/08
- CPC G06T1/60
- G06V10/74
- G06V10/46
- CPC G06V10/761
- H01L23/15
- H01L23/498
- CPC H01L23/15
- H01L23/31
- H01L21/56
- H01L23/00
- H01L23/532
- H01L25/065
- H01L25/10
- CPC H01L23/3107
- H01L23/48
- H01L21/768
- H01L21/8234
- H01L27/088
- CPC H01L23/481
- H01L23/528
- H01L27/092
- H01L29/06
- H01L29/423
- H01L29/66
- H01L29/778
- CPC H01L23/5283
- H01L23/538
- CPC H01L23/5384
- H01L21/48
- H01L23/13
- H01L23/14
- H05K1/03
- H05K1/14
- H05K1/18
- H05K3/34
- H05K3/46
- CPC H01L23/5386
- H01L23/66
- H01L23/522
- H01L25/00
- H01L25/16
- CPC H01L23/66
- CPC H01L24/32
- H01L27/02
- CPC H01L27/0207
- H01L29/786
- CPC H01L27/088
- H01L29/49
- CPC H01L27/0922
- H01L27/12
- H01L21/84
- CPC H01L27/1203
- H01L21/8238
- H01L29/775
- CPC H01L29/068
- H01L29/417
- H01L29/40
- CPC H01L29/41733
- H01L29/78
- CPC H01L29/42392
- H03F3/60
- H03F3/195
- H03F3/24
- CPC H03F3/602
- H04L1/08
- H04L5/14
- CPC H04L1/08
- H04L1/1607
- CPC H04L1/1635
- H04N13/344
- H04N13/156
- H04N13/383
- CPC H04N13/344
- H04N19/46
- H04N19/136
- H04N19/146
- H04N19/167
- H04N19/172
- H04N19/42
- CPC H04N19/46
- H04W4/38
- G06Q50/40
- H04W4/40
- CPC H04W4/38
- H04W24/02
- H04W24/08
- CPC H04W24/02
- H04W72/1273
- H04L1/00
- H04W72/231
- H04W76/20
- H04W76/40
- CPC H04W72/1273
- H05K3/30
- H05K1/02
- H05K1/16
- CPC H05K3/301
- H05K7/20
- G06F1/20
- CPC H05K7/20336
- H10B12/00
- CPC H10B12/00
