Intel Corporation patent applications on September 19th, 2024
Patent Applications by Intel Corporation on September 19th, 2024
Intel Corporation: 51 patent applications
Intel Corporation has applied for patents in the areas of H01L23/498 (5), G06T1/20 (5), G06T15/04 (3), H01L29/775 (3), H05K1/02 (3) G06T15/04 (3), G06T1/20 (2), A63F13/52 (1), H04L43/50 (1), H01L23/528 (1)
With keywords such as: memory, data, device, based, frame, described, apparatus, address, herein, and embodiment in patent application abstracts.
Patent Applications by Intel Corporation
Inventor(s): Selvakumar Panneer of Portland OR (US) for intel corporation, John Feit of Folsom CA (US) for intel corporation, Sarthak Rajesh Shah of Portland OR (US) for intel corporation, SungYe Kim of Folsom CA (US) for intel corporation, Nilesh Jain of Portland OR (US) for intel corporation
IPC Code(s): A63F13/52
CPC Code(s): A63F13/52
Abstract: described herein is a technique to enhance the responsiveness of gameplay for a 3d gaming application while maintaining the ability to enqueue multiple frames for processing on the gpu. each frame or a set of workloads within a frame is submitted to the gpu with predication, such that the indicated rendering and resource manipulation commands are not actually performed if the predication condition is enabled. a low latency command can be submitted to the gpu via a copy engine command queue. the command will cause the copy engine to enable or disable predication for command buffers in the command queue. when predication for queued command buffers is enabled, command buffers for workloads that are not related to the workload that is generated in response to the user input are bypassed. high priority command buffers that include workloads generated in response to user input can then be executed immediately.
20240310881. HINGES FOR ELECTRONIC DEVICES_simplified_abstract_(intel corporation)
Inventor(s): Jeffrey Ho of Folsom CA (US) for intel corporation, Shawn Mceuen of Portland OR (US) for intel corporation, Min Suet Lim of Pulau Pinang (MY) for intel corporation, Yew San Lim of Gelugor (MY) for intel corporation, Bruce Cheng of Taipei City (TW) for intel corporation
IPC Code(s): G06F1/16, F16C11/04
CPC Code(s): G06F1/1681
Abstract: hinges for electronic devices are disclosed herein. an example hinge includes a bracket capable of being coupled to a first portion of the electrical device. the bracket has a barrel defining a first opening. the hinge also includes a shaft in the first opening. the shaft is rotatable in the first opening. the hinge further includes a sleeve capable of being inserted into a bore in a second portion of the electronic device. the sleeve defines a second opening to receive a portion of the shaft.
20240310889. CONTROLLING A POWER CONSUMPTION OF CIRCUITRY_simplified_abstract_(intel corporation)
Inventor(s): Nikos KABURLASOS of Folsom CA (US) for intel corporation
IPC Code(s): G06F1/26, G06F1/3212, G06F1/3215, G06F1/3234
CPC Code(s): G06F1/263
Abstract: an apparatus for managing a power consumption of processor or memory circuitry comprising a plurality of processing or memory functional units may be provided. the processor or memory circuitry is arranged to receive electrical power from an alternating current, ac, power source or a battery. the apparatus comprises processing circuitry to: based on an indication that the processor or memory circuitry is receiving electrical power from the ac power source, selectively cause operational electrical power to be provided to a first number of the functional units of the processor or memory circuitry. the processing circuitry is further to: based on an indication that the circuitry is receiving electrical power from the battery, selectively cause operational electrical power to be provided to a second number of the functional units of the processor or memory circuitry, the second number being less than the first number.
20240311083. COMMUTATIVE 1ULP HARDWARE MULTIPLIER_simplified_abstract_(intel corporation)
Inventor(s): Theo Alan Drane of El Dorado Hills CA (US) for intel corporation
IPC Code(s): G06F7/533
CPC Code(s): G06F7/5336
Abstract: described herein is a truncated modified booth multiplier that is commutative and accurate to 1 unit in the last place. in various embodiments, the truncated booth multiplier is a radix-4 booth multiplier or a radix-8 booth multiplier. the truncated booth multiplier can be included within integer, floating-point, or fixed-point units within a graphics processor or compute accelerator, including matrix accelerator units or tensor processors.
Inventor(s): Gilles Pokam of Livermore CA (US) for intel corporation, Andre Seznec of Acigne (FR) for intel corporation, Jared Warner Stark, IV of Portland OR (US) for intel corporation, Bhargav Reddy Godala of Princeton NJ (US) for intel corporation
IPC Code(s): G06F9/30, G06F9/38, G06F9/48
CPC Code(s): G06F9/30047
Abstract: techniques and mechanisms for prioritizing entries of a processor resource which is accessed to facilitate the fetching of an instruction for execution. in an embodiment, a first entry of the resource includes, or otherwise corresponds to, a version of the instruction. the first entry is prioritized based on an event wherein the instruction is retired from execution after a front end stall which is due to the instruction. while the first entry is prioritized, the entry is protected from a selection to be evicted from the resource. in another embodiment, second entries of a cache are variously prioritized, based on respective retirement events, to be available for instruction prefetching.
Inventor(s): David M. Durham of Beaverton OR (US) for intel corporation, Sergej Deutsch of Hillsboro OR (US) for intel corporation, Karanvir Grewal of Hillsboro OR (US) for intel corporation
IPC Code(s): G06F11/10, H04L9/08
CPC Code(s): G06F11/1044
Abstract: the technology disclosed herein includes a memory to store a plurality of pages, a page of the plurality of pages configured as one of a trusted execution environment (tee) configuration and a non-tee configuration, and a memory controller to attempt to access the page using a memory address and the tee configuration and generate a first error correcting code (ecc); and when data for the first ecc is at least one of correct and correctable by ecc for the attempt to access the page using the tee configuration, attempt to access the page using the memory address and the non-tee configuration and generate a second ecc, and when data the second ecc is at least one of correct and correctable by ecc for the attempt to access the page using the non-tee configuration, store the memory address as an unknown cacheline address.
Inventor(s): Guadalupe J. Garcia of Chandler AZ (US) for intel corporation
IPC Code(s): G06F12/02, G06T1/20
CPC Code(s): G06F12/0292
Abstract: hashing to provide memory addressing with arbitrary enablement or disablement of memory resources is described. an example of an apparatus includes one or more processors and a memory including multiple memory portions. the one or more processors are to perform memory address hashing for memory portions to generate memory address mapping. performance of the memory address hashing includes receiving memory address information including identification of one or more memory portions of the memory portions to be inactive, generating one or more individual memory address hashes, wherein each memory address hash includes a mapping of a number of active memory portions of the plurality of memory portions to a range of memory addresses, and outputting a memory address hash including a final memory address based at least in part on the memory address mapping for the one or more individual memory address hashes.
Inventor(s): Guadalupe J. Garcia of Chandler AZ (US) for intel corporation, Jayakrishna P. S of Bangalore (IN) for intel corporation
IPC Code(s): G06F12/0802, G06T1/20, G06T1/60
CPC Code(s): G06F12/0802
Abstract: a configuration independent surface layout for graphics is described. an example of an apparatus includes one or more processors and memory including one or more memory devices. the one or more processors are to establish a memory surface within the memory according to a configuration. the memory surface is to provide for storage of data in multiple memory portions and for storage of a set of metadata, wherein the set of metadata includes respective metadata that is associated with the data stored in each of the multiple memory portions. establishment of the memory surface the storage for the set of metadata to be accessible for fetching by a data consuming device without use of the configuration by the data consuming device.
Inventor(s): Jason BRANDT of Austin TX (US) for intel corporation, Ido OUZIEL of Portland OR (US) for intel corporation, Michael CHYNOWETH of Placitas NM (US) for intel corporation, Raoul RIVAS TOLEDANO of Hillsboro OR (US) for intel corporation, Gilbert NEIGER of Portland OR (US) for intel corporation, Andreas KLEEN of Portland OR (US) for intel corporation, Jacob DOWECK of Haifa (IL) for intel corporation, Andrew NELSON of Happy Valley OR (US) for intel corporation
IPC Code(s): G06F12/1045
CPC Code(s): G06F12/1045
Abstract: an apparatus and method are described for reduced power tlb management. for example, one embodiment of a processor comprises: a plurality of cores; a first core of the plurality of cores comprising: a first translation lookaside buffer (tlb) to store address translations associated with page table walk operations, and power management logic to cause the first core to enter into a first low power state in which the address translations in the first tlb are no longer valid, wherein prior to entering into the low power state, the first core is to write an indication in a memory location that the first tlb no longer contains valid address translations; a second core of the plurality of cores to perform an operation requiring invalidation of one or more of the address translations previously stored in the first tlb, the second core to determine whether to transmit a request to the first core to invalidate the one or more address translations based on the indication.
Inventor(s): Debendra Das Sharma of Saratoga CA (US) for intel corporation, Narasimha Lanka of Dublin CA (US) for intel corporation, Peter Onufryk of Flanders NJ (US) for intel corporation, Swadesh Choudhary of Mountain View CA (US) for intel corporation, Gerald Pasdast of San Jose CA (US) for intel corporation, Zuoguo Wu of San Jose CA (US) for intel corporation, Dimitrios Ziakas of Portland OR (US) for intel corporation, Sridhar Muthrasanallur of Bangalore (IN) for intel corporation
IPC Code(s): G06F13/42, G06F13/16
CPC Code(s): G06F13/4295
Abstract: embodiments described herein may include apparatus, systems, techniques, or processes that are directed to on-package die-to-die (d2d) interconnects. specifically, embodiments herein may relate to on-package d2d interconnects for memory that use or relate to the universal chiplet interconnect express (ucie) adapter or physical layer (phy). other embodiments are described and claimed.
Inventor(s): David Kehlet of Los Altos Hills CA (US) for intel corporation, Nij Dorairaj of Campbell CA (US) for intel corporation, Shuanghong Sun of Sunnyvale CA (US) for intel corporation
IPC Code(s): G06F30/31
CPC Code(s): G06F30/31
Abstract: a computer system is provided for protecting an original circuit design for an integrated circuit. the computer system includes a logic circuit replacement tool that generates a redacted circuit design for the integrated circuit by replacing logic circuits in the original circuit design with first and second configurable circuits that perform logic functions of the logic circuits when a bitstream stored in storage circuits configures the first and the second configurable circuits. the logic circuit replacement tool couples one of the storage circuits that stores a bit in the bitstream to an input in each of the first and the second configurable circuits in the redacted circuit design.
Inventor(s): Selvakumar Panneer of Portland OR (US) for intel corporation, Nilesh Jain of Portland OR (US) for intel corporation, SungYe Kim of Folsom CA (US) for intel corporation
IPC Code(s): G06T1/20, G06T3/00
CPC Code(s): G06T1/20
Abstract: described herein is a graphics processor configured to perform time based frame generation via a temporally aware machine learning model that enables the generation of a frame at a target timestamp relative to the render times of input frames. for example, for an extrapolated frame generated by the temporally aware machine learning model, a low relative timestamp would indicate that the extrapolated frame will appear close in time after the final frame in a sequence of frames and should be relatively close in appearance to the final frame. a higher relative timestamp would indicate that the extrapolated frame should depict a greater degree of evolution based on the optical flow.
Inventor(s): Selvakumar Panneer of Portland OR (US) for intel corporation, Sarthak Rajesh Shah of Portland OR (US) for intel corporation, Nilesh Jain of Portland OR (US) for intel corporation, John Feit of Folsom CA (US) for intel corporation
IPC Code(s): G06T1/20, G06F9/50
CPC Code(s): G06T1/20
Abstract: described herein is a graphics processor configured to perform time based frame predication to bypass execution of a command buffer based on a comparison with time stamps stored in a time stamp buffer that tracks execution time for command buffers. the graphics processors can bypass a frame that will not complete in time for a target display update and trigger neural frame generation to generate the frame data for the bypassed command buffer. dynamic render scaling is also described.
Inventor(s): Darshan R. Iyer of Santa Clara CA (US) for intel corporation, Deepak Vembar of Portland OR (US) for intel corporation, Changliang Wang of Bellevue WA (US) for intel corporation, Sumit Bhatia of Folsom CA (US) for intel corporation
IPC Code(s): G06T3/40, G06T3/00, G06T5/00, G06T7/20
CPC Code(s): G06T3/4046
Abstract: described herein are techniques to enhance the user experience for 3d rendered applications via neural frame generation using upsampled optical flow data. in one embodiment, a neural network is trained using both sparse optical flow data and dense optical flow data to enable neural frame generation to be performed by a deployed neural network using only sparse optical flow data. the sparse optical flow data can be upsampled to dense optical flow data by the trained neural network. the neural network can then use the upsampled dense optical flow data to perform frame generation.
Inventor(s): Selvakumar Panneer of Portland OR (US) for intel corporation, Mrutunjayya Mrutunjayya of Hillsboro OR (US) for intel corporation, Lorenzo Tessari of Karlsruhe (DE) for intel corporation
IPC Code(s): G06T7/246, G06T3/00, G06T15/80
CPC Code(s): G06T7/251
Abstract: described herein, in one embodiment, is computer-implemented method of estimating dense optical flow using primitive id data comprising generating a primitive id buffer (e.g., triangle id buffer) for a frame during rendering, rendering the frame with a unique color for each primitive id, providing a rendered primitive id buffer for the current and previous frame along with a confidence buffer and sparse optical flow between frames to a machine learning model, and generating an estimated dense optical flow via the machine learning model based on the input.
Inventor(s): William ZORN of Woodinville WA (US) for intel corporation, Theo DRANE of El Dorado Hills CA (US) for intel corporation, Brett SAIKI of Seattle WA (US) for intel corporation
IPC Code(s): G06T7/40, G06T1/20, G06T3/40
CPC Code(s): G06T7/40
Abstract: an apparatus to facilitate level-of-detail (lod) determination using major squared and efficient clamping in a graphics environment is disclosed. the apparatus includes a processing core comprising a rasterizer hardware unit to: identify components of partial derivative vectors corresponding to two adjacent lines of a quadrilateral in texture space of an image, the quadrilateral corresponding to a pixel sampling area in screen space; combine the partial derivative vectors into a transformation matrix representing a transformation of coordinates from the screen space to the texture space; determine a value of a square of a major axis length (major squared) of the ellipse based on a sum of squares (sos) of the components of the transformation matrix and a determinant of the transformation matrix; and compute a lod value and an anisotropic ratio (iratio) value using the determinant of the transformation matrix and the value of the major squared.
Inventor(s): David Gonzalez Aguirre of Portland OR (US) for intel corporation
IPC Code(s): G06T7/73, G06F3/01, G06F3/16, G06V10/70, G06V10/94, G06V20/50, G06V20/70, G10L15/18, G10L15/22
CPC Code(s): G06T7/73
Abstract: various aspects of techniques, systems, and use cases may be used for human-robot collaboration for three-dimensional (3d) functional mapping. an example technique may include receiving identification of a direction or location based on a user gaze identified via an extended reality device, causing environmental data of an environment to be captured using a sensor of a robotic device corresponding to the direction or location based on receiving the identification, and detecting, within the environmental data, at least one physical feature of the environment. the example technique may include determining, from a user input, an annotation to apply to the at least one physical feature, and labeling the at least one physical feature with the annotation.
Inventor(s): Shandong WANG of Beijing (CN) for intel corporation, Yurong CHEN of Beijing (CN) for intel corporation, Ming LU of Beijing (CN) for intel corporation, Li XU of Shanghai (CN) for intel corporation, Anbang YAO of Beijing (CN) for intel corporation
IPC Code(s): G06T7/73, G06T7/80
CPC Code(s): G06T7/74
Abstract: this disclosure describes systems, methods, and devices related to real-time multi-person three-dimensional pose tracking using a single camera. a method may include receiving, by a device, two-dimensional image data from a camera, the two-dimensional image data representing a first person and a second person; generating, based on the two-dimensional image data, two-dimensional positions of body parts represented by the first person; generating, using a deep neural network, based on the two-dimensional positions, a three-dimensional pose regression of the body parts represented by the first person; identifying, based on the two-dimensional positions and the three-dimensional pose regression, contact between a ground plane and a foot of the first person; generating an absolute three-dimensional position of the contact between the ground plane and the foot of the first person; generating, based on the absolute three-dimensional position, a three-dimensional pose of the body parts represented by the first person.
20240312107. PRESERVING G-BUFFER & OPTICAL FLOW IN UV SPACE_simplified_abstract_(intel corporation)
Inventor(s): Selvakumar Panneer of Portland OR (US) for intel corporation, Mrutunjayya Mrutunjayya of Hillsboro OR (US) for intel corporation, SungYe Kim of Folsom CA (US) for intel corporation
IPC Code(s): G06T15/00
CPC Code(s): G06T15/005
Abstract: described herein are techniques to preserve g-buffer and optical flow data in uv coordinate space. the g-buffer and optical flow data can be used to correct disocclusion artifacts in frames generated via a neural network.
Inventor(s): William ZORN of Woodinville WA (US) for intel corporation, Theo DRANE of El Dorado Hills CA (US) for intel corporation, Brett SAIKI of Seattle WA (US) for intel corporation
IPC Code(s): G06T15/04
CPC Code(s): G06T15/04
Abstract: an apparatus to facilitate level-of-detail (lod) eigenvector determination in a graphics environment is disclosed. the apparatus includes a processing core comprising a rasterizer hardware unit to: identify components of partial derivative vectors corresponding to two adjacent lines of a quadrilateral in texture space of an image, the quadrilateral corresponding to a pixel sampling area in screen space; combine the partial derivative vectors into a transformation matrix representing a transformation of coordinates from the screen space to the texture space; determine a value of a square of a major axis length (major squared) of the ellipse based on a sum of squares (sos) of the components of the transformation matrix and a determinant of the transformation matrix; and compute eigenvector values for the ellipse using the components of the partial derivative vectors, the determinant of the transformation matrix, and the value of the major squared.
Inventor(s): Selvakumar Panneer of Portland OR (US) for intel corporation, Changliang Wang of Bellevue WA (US) for intel corporation
IPC Code(s): G06T15/04, G06T7/20
CPC Code(s): G06T15/04
Abstract: described herein are techniques to perform optical flow mipmap level of detail adjustment for rendering and performing cloud gaming encoding adjustment based on mipmap level of detail. one embodiment provides a graphics processor comprising first circuitry to process input data via a processing resource, the first circuitry to render a first frame of a scene of a three dimensional environment, determine motion data between the first frame and a second frame, determine speeds for pixels and objects in the scene based on the determined motion data, adjust a mipmap level of detail (lod) associated with the objects based on their motion relative to a motion threshold, and render the objects in a third frame of the scene with an adjusted mipmap lod.
20240312113. UV SPACE RENDERING AND AI PROCESSING_simplified_abstract_(intel corporation)
Inventor(s): Selvakumar Panneer of Portland OR (US) for intel corporation, Mrutunjayya Mrutunjayya of Hillsboro OR (US) for intel corporation, John H. Feit of Folsom CA (US) for intel corporation
IPC Code(s): G06T15/04, G06T3/4053, G06T7/20, G06T15/50
CPC Code(s): G06T15/04
Abstract: described herein are techniques to render frame data in uv space and process the uv space data via a machine learning model. one embodiment provides an apparatus including a parallel processor having first circuitry configured to execute operations associated with a three-dimensional (3d) application programming interface (api) to render scene data for a frame in a uv coordinate space, second circuitry configured to execute instructions to perform a matrix multiply accumulate operation associated with a machine learning model that is trained to process the scene data in the uv coordinate space to generate processed scene data in the uv coordinate space, and third circuitry to rasterize the processed scene data in the uv coordinate space into a screen space representation of the scene data.
Inventor(s): Stephen PALERMO of Chandler AZ (US) for intel corporation, Bhupesh AGRAWAL of Hillsboro OR (US) for intel corporation, Valerie PARKER of Portland OR (US) for intel corporation
IPC Code(s): G06T17/00, H04N21/2187
CPC Code(s): G06T17/00
Abstract: methods, apparatus, systems, and articles of manufacture are disclosed for location-aware virtual reality (vr). an example apparatus disclosed herein is to determine a first location of a first vr device and a second location of a second vr device. the disclosed example apparatus is to identify a preset guardian boundary corresponding to a vr live stream based on at least one of first credentials associated with the first vr device or second credentials associated with the second vr device. additionally, the disclosed example apparatus is to, after a determination that the first location and the second location satisfy the preset guardian boundary, at least one of execute or instantiate an instance of a vr live stream application associated with the vr live steam based on the first location and the second location, the first vr device and the second vr device to be associated with the vr live stream application.
Inventor(s): Dongqi CAI of Beijing (CN) for intel corporation, Anbang YAO of Beijing (CN) for intel corporation, Yurong CHEN of Beijing (CN) for intel corporation, Chao LI of Beijing (CN) for intel corporation
IPC Code(s): G06V10/82, G06N3/0464, G06V20/40
CPC Code(s): G06V10/82
Abstract: an apparatus, method, device and medium for dynamic quadruple convolution in a 3-dimensional (3d) convolutional neural network (cnn) are provided. the method includes: a multi-dimensional attention block configured to: receive an input feature map of a video data sample; and dynamically generate convolutional kernel scalars along four dimensions of a 3-dimensional convolution kernel space based on the input feature map, the four dimensions comprising an output channel number, an input channel number, a temporal size and a spatial size; and a convolution block configured to sequentially multiply the generated convolutional kernel scalars with a static 3d convolution kernel in a matrix-vector product way to obtain a dynamic kernel of dynamic quadruple convolution.
Inventor(s): Ashish SHARMA of Bangalore (IN) for intel corporation, Arvind SUNDARAM of Bangalore (IN) for intel corporation, Vikas MISHRA of Chandler AZ (US) for intel corporation, Vimal John CYRIL of Bangalore (IN) for intel corporation
IPC Code(s): H01F27/28, H01F27/26, H05K1/16, H05K3/00
CPC Code(s): H01F27/2804
Abstract: embodiments disclosed herein include a motherboard. in an embodiment, the motherboard comprises a first layer with a first trace with a shape. in an embodiment, an insulating layer is provided over the first layer. in an embodiment, a second layer with a second trace with the shape is over the insulating layer. in an embodiment, the second trace is provided directly over the first trace.
Inventor(s): Abhishek Srivastav of Bangalore (IN) for intel corporation, Smit Kapila of Bangalore (IN) for intel corporation, Prakash Kurma Raju of Bangalore (IN) for intel corporation, Sumod Cherukkate of Bangalore (IN) for intel corporation, Vijith Halestoph R of Bangalore (IN) for intel corporation, Srikanth Potluri of Folsom CA (US) for intel corporation
IPC Code(s): H01H13/14, G06F3/02, H01H13/70, H04R1/02, H04R7/04
CPC Code(s): H01H13/14
Abstract: keyboards for electronic devices with keys having integrated speakers are disclosed herein. an example keyboard includes a key having a key cap and a speaker coupled to the key cap. the speaker is disposed in or at least partially covered by the key cap.
Inventor(s): Hong Seung YEON of Chandler AZ (US) for intel corporation, Mariano PHIELIPP of Mesa AZ (US) for intel corporation, Yi LI of Chandler AZ (US) for intel corporation, Minglu LIU of Chandler AZ (US) for intel corporation, Robin McREE of Chandler AZ (US) for intel corporation, Yosuke KANAOKA of Chandler AZ (US) for intel corporation, Gang DUAN of Chandler AZ (US) for intel corporation
IPC Code(s): H01L21/68, H01L21/67
CPC Code(s): H01L21/68
Abstract: a method for real-time offset adjustment of a semiconductor die placement comprising: obtaining or receiving operational parameters of a die mounting tool in real-time, wherein the die mounting tool is configured for placing the semiconductor die on a panel; predicting an offset adjustment of the semiconductor die placement based on the operational parameters; and determining semiconductor die placement coordinates based on an original die placement and the offset adjustment.
20240312853. VIA STRUCTURES IN BONDED GLASS SUBSTRATES_simplified_abstract_(intel corporation)
Inventor(s): Sashi S. KANDANUR of Phoenix AZ (US) for intel corporation, Srinivas V. PIETAMBARAM of Chandler AZ (US) for intel corporation, Darko GRUJICIC of Chandler AZ (US) for intel corporation, Brandon C. MARIN of Gilbert AZ (US) for intel corporation, Suddhasattwa NAD of Chandler AZ (US) for intel corporation, Benjamin DUONG of Phoenix AZ (US) for intel corporation, Gang DUAN of Chandler AZ (US) for intel corporation, Mohammad Mamunur RAHMAN of Gilbert AZ (US) for intel corporation, Numair AHMED of Chandler AZ (US) for intel corporation
IPC Code(s): H01L23/15, H01L23/498
CPC Code(s): H01L23/15
Abstract: embodiments herein relate to systems, apparatuses, techniques and/or processes for creating a substrate out of a plurality of layers of glass, where the substrate includes one or more vias that extend through each of the plurality of layers of glass. in embodiments, a high aspect ratio via may be constructed through the substrate by electrically coupling the individual vias. other embodiments may be described and/or claimed.
Inventor(s): Kyle Arrington of Gilbert AZ (US) for intel corporation, Bohan Shan of Chandler AZ (US) for intel corporation, Haobo Chen of Chandler AZ (US) for intel corporation, Bai Nie of Chandler AZ (US) for intel corporation, Srinivas Pietambaram of Chandler AZ (US) for intel corporation, Gang Duan of Chandler AZ (US) for intel corporation, Ziyin Lin of Chandler AZ (US) for intel corporation, Hongxia Feng of Chandler AZ (US) for intel corporation, Yiqun Bai of Chandler AZ (US) for intel corporation, Xiaoying Guo of Chandler AZ (US) for intel corporation, Dingying Xu of Chandler AZ (US) for intel corporation
IPC Code(s): H01L23/373, H01L21/48, H01L23/498
CPC Code(s): H01L23/3733
Abstract: methods, systems, apparatus, and articles of manufacture to improve reliability of vias in a glass substrate of an integrated circuit package are disclosed. an example integrated circuit (ic) package substrate includes a glass substrate, a via extending between first and second surfaces of the glass substrate, and a conductive material provided in the via, the conductive material including gallium and silver.
Inventor(s): Tongyan Zhai of Portland OR (US) for intel corporation, Telesphor Kamgaing of Chandler AZ (US) for intel corporation, Min Suet Lim of Gelugor (MY) for intel corporation
IPC Code(s): H01L23/473, H01L23/00, H01L23/528
CPC Code(s): H01L23/473
Abstract: described herein are integrated circuit devices that include semiconductor devices near the center of the device, rather than towards the top or bottom of the device. in this arrangement, heat can become trapped inside the device. a microfluidic cooling layer is formed near a top or front the device, e.g., over the semiconductor devices and any front side interconnect structures, to transfer heat away from the semiconductor devices.
20240312888. VIA STRUCTURES IN BONDED GLASS SUBSTRATES_simplified_abstract_(intel corporation)
Inventor(s): Sashi S. KANDANUR of Phoenix AZ (US) for intel corporation, Srinivas V. PIETAMBARAM of Chandler AZ (US) for intel corporation, Darko GRUJICIC of Chandler AZ (US) for intel corporation, Brandon C. MARIN of Gilbert AZ (US) for intel corporation, Suddhasattwa NAD of Chandler AZ (US) for intel corporation, Benjamin DUONG of Phoenix AZ (US) for intel corporation, Gang DUAN of Chandler AZ (US) for intel corporation, Mohammad Mamunur RAHMAN of Gilbert AZ (US) for intel corporation, Numair AHMED of Chandler AZ (US) for intel corporation
IPC Code(s): H01L23/498, H01L21/48, H01L23/15
CPC Code(s): H01L23/49827
Abstract: embodiments herein relate to systems, apparatuses, techniques and/or processes for creating a substrate out of a plurality of layers of glass, where the substrate includes one or more vias that extend through each of the plurality of layers of glass. in embodiments, a high aspect ratio via may be constructed through the substrate by electrically coupling the individual vias. other embodiments may be described and/or claimed.
Inventor(s): Chee Hak Teh of Bayan Lepas (MY) for intel corporation, Chee Seng Leong of Gelugor (MY) for intel corporation, Lai Guan Tang of Tanjung Bungah (MY) for intel corporation, Han Wooi Lim of Bayan Lepas (MY) for intel corporation, Hee Kong Phoon of Bayan Lepas (MY) for intel corporation
IPC Code(s): H01L23/528, H01L23/498, H03K19/17704
CPC Code(s): H01L23/528
Abstract: the presently disclosed programmable fabric die includes a direct fabric die-to-fabric die interconnect interface column disposed in a sector of programmable logic fabric. each row of the interconnect interface column includes at least one interconnect interface that is electrically coupled to a microbump. the microbump is configured to be electrically coupled to another microbump of another interconnect interface of another fabric die through an interposer. the fabric die may include multiple interconnect interface columns that each extend deep into the sector, enabling low latency connections between the fabric dies and reducing routing congestion. in some embodiments, the fabric die may include interconnect interfaces that are instead distributed throughout logic blocks of the sector.
Inventor(s): Pezhman MONADGEMI of Santa Clara CA (US) for intel corporation
IPC Code(s): H01L23/538, H01L25/00, H01L25/065
CPC Code(s): H01L23/5386
Abstract: embodiments disclosed herein include a multi-die module. in an embodiment, the multi-die module comprises an interposer, where the interposer comprises a first region and a second region. in an embodiment, the first region is spaced apart from the second region by a saw street. in an embodiment, a first die is over the interposer, where the first die is positioned over the saw street. in an embodiment, a second die is adjacent to a first end of the first die, and a third die is adjacent to a second end of the first die opposite from the first end.
Inventor(s): Shishir Deshpande of Chandler AZ (US) for intel corporation, Jung Kyu Han of Chandler AZ (US) for intel corporation, Gang Duan of Chandler AZ (US) for intel corporation, Srinivas Pietambaram of Chandler AZ (US) for intel corporation
IPC Code(s): H01L23/544
CPC Code(s): H01L23/544
Abstract: microelectronic devices, systems, and techniques are disclosed having package substrate land side fiducial structures that are readily distinguishable from adjacent interconnect structures during registration of the land side of the package substrate. the fiducial structure includes a ring shape, a double ring shape, a donut shape, a triangular shape, an h-shape, or an i-shape in contrast to the circular, square, or rectangular shape of the adjacent interconnect structure. the fiducial structure shape may also have a different size relative to the interconnect structure shape.
Inventor(s): Vidya JAYARAM of Chandler AZ (US) for intel corporation, Karan BHANGAONKAR of Chandler AZ (US) for intel corporation, Chandrasekharan NAIR of Mesa AZ (US) for intel corporation
IPC Code(s): H01L23/00, H01L21/311, H01L23/498, H01L23/522
CPC Code(s): H01L24/19
Abstract: embodiments disclosed herein include package substrates. in an embodiment, the package substrate comprises a layer with a film over the layer. in an embodiment, the film is an inorganic material. in an embodiment, the package substrate may further comprise a plurality of electrically conductive traces over the film, and a seed layer between the plurality of electrically conductive traces and the film. in an embodiment, edges of the seed layer are substantially aligned with edges of the plurality of electrically conductive traces.
Inventor(s): Dan S. LAVRIC of Beaverton OR (US) for intel corporation, Shao Ming KOH of Tigard OR (US) for intel corporation, Sudipto NASKAR of Portland OR (US) for intel corporation, Anand S. MURTHY of Portland OR (US) for intel corporation, Nikhil MEHTA of Portland OR (US) for intel corporation, Leonard P. GULER of Hillsboro OR (US) for intel corporation
IPC Code(s): H01L27/088, H01L21/8238, H01L27/092
CPC Code(s): H01L27/088
Abstract: integrated circuit structures having uniform grid metal gate and trench contact cut are described. for example, an integrated circuit structure includes a gate electrode over a vertical stack of horizontal nanowires. a conductive trench contact is adjacent to the gate electrode. a dielectric sidewall spacer is between the gate electrode and the conductive trench contact. first and second dielectric cut plug structures extend through the gate electrode, through the dielectric sidewall spacer, and through the conductive trench contact, the second dielectric cut plug structure laterally spaced apart from and parallel with the first dielectric cut plug structure. the gate electrode has a zero edge placement error between the first dielectric cut plug structure and the second dielectric cut plug structure. an epitaxial source or drain structure is at an end of the vertical stack of horizontal nanowires and beneath the conductive trench contact.
Inventor(s): Dan S. LAVRIC of Beaverton OR (US) for intel corporation, Shao Ming KOH of Tigard OR (US) for intel corporation, David J. TOWNER of Portland OR (US) for intel corporation
IPC Code(s): H01L27/092, H01L29/06, H01L29/423, H01L29/51, H01L29/775
CPC Code(s): H01L27/092
Abstract: gate-all-around integrated circuit structures having tuned upper nanowires are described. for example, an integrated circuit structure includes a first vertical arrangement of horizontal nanowires, and a second vertical arrangement of horizontal nanowires over the first vertical arrangement of horizontal nanowires. a p-type gate stack is over the first vertical arrangement of horizontal nanowires, the p-type gate stack having a p-type conductive layer over a first gate dielectric including a first dipole material. an n-type gate stack is over the second vertical arrangement of horizontal nanowires, the n-type gate stack having an n-type conductive layer over a second gate dielectric including a second dipole material, wherein the second dipole material has a greater number of layers than the first dipole material or wherein the second dipole material does not include the first dipole material.
Inventor(s): Dan S. LAVRIC of Beaverton OR (US) for intel corporation, Shao Ming KOH of Tigard OR (US) for intel corporation, Anand S. MURTHY of Portland OR (US) for intel corporation, Mauro J. KOBRINSKY of Portland OR (US) for intel corporation
IPC Code(s): H01L27/092, H01L29/06, H01L29/423, H01L29/66, H01L29/775, H01L29/786
CPC Code(s): H01L27/0922
Abstract: integrated circuit structures having uniform grid metal gate and trench contact cut with pyramidal channel structures are described. for example, an integrated circuit structure includes a vertical stack of horizontal nanowires having a pyramidal profile with a pyramid angle. a gate electrode is over the vertical stack of horizontal nanowires. a conductive trench contact is adjacent to the gate electrode. a dielectric sidewall spacer is between the gate electrode and the conductive trench contact. a dielectric cut plug structure extends through the gate electrode, through the dielectric sidewall spacer, and through the conductive trench contact. the dielectric cut plug structure has a re-entrant profile with a cut angle laterally spaced apart from the pyramid angle of the pyramidal profile of the vertical stack of horizontal nanowires.
Inventor(s): Ehren MANNEBACH of Tigard OR (US) for intel corporation, Shaun MILLS of Hillsboro OR (US) for intel corporation, Joseph D’SILVA of Hillsboro OR (US) for intel corporation, Mauro J. KOBRINSKY of Portland OR (US) for intel corporation
IPC Code(s): H01L29/775, H01L27/088, H01L29/06, H01L29/417, H01L29/423
CPC Code(s): H01L29/775
Abstract: integrated circuit structures having back-side contact selectivity are described. in an example, an integrated circuit structure includes a plurality of horizontally stacked nanowires. a gate stack is over the plurality of horizontally stacked nanowires. an epitaxial source or drain structure is at an end of the plurality of horizontally stacked nanowires. a hardmask material is below a bottom of the epitaxial source or drain structure. a conductive gate contact is vertically beneath and in contact with a bottom of the gate stack, the conductive gate contact extending under and in contact with a portion of the hardmask material.
Inventor(s): Markus Dominik MUECK of Unterhaching (DE) for intel corporation, Amit ELAZARI BAR ON of Pacifica CA (US) for intel corporation, Stephane DU BOISPEAN of Schaerbeek, Brussels (BE) for intel corporation
IPC Code(s): H04L43/50, H04L41/40, H04W12/03, H04W12/12
CPC Code(s): H04L43/50
Abstract: the present disclosure discusses various implementation solutions to meet the requirements of the european union's radio equipment directive (red). various testing architectures and test services are provided for each of the red requirements that allow for reproducible validation and/or verification of radio equipment. other aspects may be described and/or claimed.
Inventor(s): Pratik M. MAROLIA of Hillsboro OR (US) for intel corporation, Rajesh M. SANKARAN of Portland OR (US) for intel corporation, Ashok RAJ of Portland OR (US) for intel corporation, Nrupal JANI of Hillsboro OR (US) for intel corporation, Parthasarathy SARANGAM of Portland OR (US) for intel corporation, Robert O. SHARP of Austin TX (US) for intel corporation
IPC Code(s): H04L45/74, G06F12/1081, G06F13/28, H04L45/60, H04L49/90
CPC Code(s): H04L45/742
Abstract: a network interface controller can be programmed to direct write received data to a memory buffer via either a host-to-device fabric or an accelerator fabric. for packets received that are to be written to a memory buffer associated with an accelerator device, the network interface controller can determine an address translation of a destination memory address of the received packet and determine whether to use a secondary head. if a translated address is available and a secondary head is to be used, a direct memory access (dma) engine is used to copy a portion of the received packet via the accelerator fabric to a destination memory buffer associated with the address translation. accordingly, copying a portion of the received packet through the host-to-device fabric and to a destination memory can be avoided and utilization of the host-to-device fabric can be reduced for accelerator bound traffic.
Inventor(s): Wenjie WANG of Shanghai (CN) for intel corporation, Yi ZHANG of Shanghai (CN) for intel corporation, Junjie LI of Shanghai (CN) for intel corporation, Yi QIAN of Shanghai (CN) for intel corporation, Wanglei SHEN of Shanghai (CN) for intel corporation, Lingyun ZHU of Shanghai (CN) for intel corporation
IPC Code(s): H04L47/2441, H04L47/38
CPC Code(s): H04L47/2441
Abstract: systems, apparatuses and methods include technology that identifies data that is to be transferred from a first device to a second device. the technology classifies the data into a category from a plurality of categories, selects a compression scheme from a plurality of compression schemes based on the category and compresses the data based on the compression scheme.
Inventor(s): Steffen Schulz of Darmstadt (DE) for intel corporation, Patrick Koeberl of Portland OR (US) for intel corporation, Alpa Narendra Trivedi of Hillsboro OR (US) for intel corporation, Scott Weber of Piedmont CA (US) for intel corporation
IPC Code(s): H04L67/51, H04L9/40, H04L67/00
CPC Code(s): H04L67/51
Abstract: a multitenancy system that includes a host provider, a programmable device, and multiple tenants is provided. the host provider may publish a multitenancy mode sharing and allocation policy that includes a list of terms to which the programmable device and tenants can adhere. the programmable device may include a secure device manager configured to operate in a multitenancy mode to load a tenant persona into a given partial reconfiguration (pr) sandbox region on the programmable device. the secure device manager may be used to enforce spatial isolation between different pr sandbox regions and temporal isolation between successive tenants in one pr sandbox region.
20240314277. AUTOMATIC PROJECTION CORRECTION_simplified_abstract_(intel corporation)
Inventor(s): Bo PENG of Beijing (CN) for intel corporation, Bin WANG of Beijing (CN) for intel corporation
IPC Code(s): H04N9/31
CPC Code(s): H04N9/3185
Abstract: this disclosure describes systems, methods, and devices related to automatic projection correction. a device may generate a first image having a first resolution. the device may project the first image onto a surface resulting in a first projected image on a first projection area. the device may receive input data from a depth camera device, wherein the input data is associated with the first projected image on the first projected area. the device may perform automatic projection correction based on the input data. the device may generate a second image to be projected based on the automatic projection correction. the device may project the second image onto a second projection area.
Inventor(s): David Israel Gonzalez Aguirre of Portland OR (US) for intel corporation, Javier Perez-Ramirez of North Plains OR (US) for intel corporation, Javier Felip Leon of Hillsboro OR (US) for intel corporation, Edgar Macias Garcia of Zapopan (MX) for intel corporation, Julio Cesar Zamora Esquivel of West Sacramento CA (US) for intel corporation
IPC Code(s): H04N13/388, G06T17/00, H04N23/69, H04N23/695
CPC Code(s): H04N13/388
Abstract: example systems, apparatus, articles of manufacture, and methods to model volumetric representations of objects in scenes are disclosed. example apparatus disclosed herein are to form a set of polycells from image data of a scene, a first one of the polycells based on an intersection of (a) a first polytope representative of at least a portion of a first view frustrum corresponding to a first camera, and (b) a second polytope representative of at least a portion of a second view frustrum corresponding to a second camera. disclosed example apparatus is also to determine a probability that the first one of the polycells is at least partially within an object in the scene, and based on comparison of the probability to a threshold, remove the first one of the polycells from the set of polycells to determine an updated set of polycells that model the object.
Inventor(s): Dibakar Das of Hillsboro OR (US) for intel corporation, Necati Canpolat of Beaverton OR (US) for intel corporation, Dave Cavalcanti of Beaverton OR (US) for intel corporation, Ganesh Venkatesan of Hillsboro OR (US) for intel corporation, Roya Doostnejad of Los Altos CA (US) for intel corporation, Laurent Cariou of Milizac (FR) for intel corporation
IPC Code(s): H04W28/02, H04W28/12
CPC Code(s): H04W28/0268
Abstract: for example, an apparatus may be configured to cause wireless communication station (sta) to set a cellular quality of service (qos) index value in a cellular qos index field to indicate a predefined setting of a set of a plurality qos parameters for a cellular qos traffic flow to be communicated by the sta over a wireless local area network (wlan). for example, the apparatus may be configured to cause the sta to transmit a stream classification service (scs) request to an access point (ap) of the wlan, the scs request including an scs descriptor element, the scs descriptor element including the cellular qos index field.
Inventor(s): Necati CANPOLAT of Beaverton OR (US) for intel corporation, Binita GUPTA of San Diego CA (US) for intel corporation, Vivek GUPTA of San Jose CA (US) for intel corporation
IPC Code(s): H04W28/24, H04W12/108, H04W28/02, H04W76/10, H04W84/12
CPC Code(s): H04W28/24
Abstract: this disclosure describes systems, methods, and devices related to quality-of-service (qos) for fifth generation (5g) wireless communications. a device may identify a frame received from a second device, the frame indicative of fifth-generation (5g) quality-of-service (qos) characteristics; determine an internet protocol security (ipsec) security parameter index (spi) field, the ipsec spi field; generate, using a wireless local area network station (wlan sta) of the device, a request frame, the request frame including a requested 802.11 user priority, and comprising an ipsec information element, the ipsec information element including an ipsec security protocol field indicative of an encapsulated security protocol, the ipsec information element further including the ipsec spi field and a destination internet protocol (ip) address; send the request frame to an access point; and identify a response frame received, from the access point device, the response frame indicative of an admission or rejection of the requested 802.11 user priority.
Inventor(s): Sudeep K. Palat of Cheltenham (GB) for intel corporation, Yi Guo of Shanghai (CN) for intel corporation, Marta Martinez Tarradell of Hillsboro OR (US) for intel corporation, Sangeetha L. Bangolae of Portland OR (US) for intel corporation, Ansab Ali of Hillsboro OR (US) for intel corporation, Seau S. Lim of Swindon (GB) for intel corporation, Youn Hyoung Heo of Sunnyvale CA (US) for intel corporation
IPC Code(s): H04W76/19, H04W12/041, H04W12/0431, H04W28/06, H04W76/30
CPC Code(s): H04W76/19
Abstract: a computer-readable storage medium stores instructions for execution by one or more processors of a ue. the instructions configure the ue for small data transmission (sdt) in a 5g nr network and cause the ue to perform operations comprising detecting while in an rrc_inactive state, a radio link failure during a first sdt of ul data to a base station. a secure key for a second sdt is generated based on the radio link failure. a configuration message including an indication of the second sdt is transmitted to the base station. a response message including a ul grant is received from the base station. the ul data is encoded for the second sdt using the secure key. the second sdt is performed using the ul grant while the ue is in the rrc_inactive state.
Inventor(s): Jeff Ku of Taipei City (TW) for intel corporation, Baomin Liu of Hillsboro OR (US) for intel corporation, Cora Nien of Taipei City (TW) for intel corporation, Min Suet Lim of Gelugor (MY) for intel corporation, Tongyan Zhai of Portland OR (US) for intel corporation
IPC Code(s): H05K1/02, F16K31/50, H05K7/20
CPC Code(s): H05K1/0209
Abstract: methods, apparatus, systems, and articles of manufacture are disclosed to cool electronic devices. an example thermal solution to cool an electronic device includes a first cooling plate at a first side of a printed circuit board and a second cooling plate at a second side of the printed circuit board, the second side opposite the first side. the second cooling plate is fluidically coupled with the first cooling plate.
Inventor(s): Arumanayagam RAJASEKAR of Nagercoil (IN) for intel corporation, Hariharan KALIYAVARATHAN of Villupuram (IN) for intel corporation, Srinivas REDDY B.M. of Bangalore (IN) for intel corporation, Yagnesh Vinodrai WAGHELA of Bengaluru (IN) for intel corporation, Piyush BHATT of Bangalore (IN) for intel corporation
IPC Code(s): H05K1/02
CPC Code(s): H05K1/0224
Abstract: embodiments disclosed herein include a printed circuit board (pcb). in an embodiment, the pcb comprises a core and routing layers over and under the core. in an embodiment, a multi-layer shield is over at least one of the routing layers. in an embodiment, the multi-layer shield comprises a metallic layer with a first surface and a second surface opposite from the first surface, and a conductive adhesive over the first surface of the metallic layer. in an embodiment, a base layer is over the second surface of the metallic layer, where the base layer is electrically insulating.
Inventor(s): Chen ZHANG of Shanghai (CN) for intel corporation, Xiang QUE of Suzhou (CN) for intel corporation, Yang YAO of Shanghai (CN) for intel corporation, Yuehong FAN of Shanghai (CN) for intel corporation, Guangying ZHANG of Shanghai (CN) for intel corporation, Liguang DU of Shanghai (CN) for intel corporation, Shaorong ZHOU of Shanghai (CN) for intel corporation, Chuanlou WANG of Shanghai (CN) for intel corporation, Yingqiong BU of Shanghai (CN) for intel corporation, Yue YANG of Shanghai (CN) for intel corporation
IPC Code(s): H05K7/20, H05K1/02
CPC Code(s): H05K7/20236
Abstract: an apparatus is described that includes an immersion bath chamber and a cover that is to seal the immersion bath chamber. an apparatus is described that includes an immersion bath chamber and an installable/removable transfer member. the installable/removable transfer member has fluidic connectors designed to couple to respective warmed fluid flow output ports of pluggable units to be cooled in the immersion bath chamber and having respective backplane interface designs. an apparatus is described that includes an immersion bath chamber and an overflow chamber. the overflow chamber is to receive an overflow of liquid coolant from the immersion bath chamber, wherein a first exit flow channel from the overflow chamber is coupled to a second exit fluid flow channel from the immersion bath chamber through a valve, wherein, an opening of the valve is controllable to vary a gravitational fluid flow within the immersion bath chamber.
Intel Corporation patent applications on September 19th, 2024
- Intel Corporation
- A63F13/52
- CPC A63F13/52
- Intel corporation
- G06F1/16
- F16C11/04
- CPC G06F1/1681
- G06F1/26
- G06F1/3212
- G06F1/3215
- G06F1/3234
- CPC G06F1/263
- G06F7/533
- CPC G06F7/5336
- G06F9/30
- G06F9/38
- G06F9/48
- CPC G06F9/30047
- G06F11/10
- H04L9/08
- CPC G06F11/1044
- G06F12/02
- G06T1/20
- CPC G06F12/0292
- G06F12/0802
- G06T1/60
- CPC G06F12/0802
- G06F12/1045
- CPC G06F12/1045
- G06F13/42
- G06F13/16
- CPC G06F13/4295
- G06F30/31
- CPC G06F30/31
- G06T3/00
- CPC G06T1/20
- G06F9/50
- G06T3/40
- G06T5/00
- G06T7/20
- CPC G06T3/4046
- G06T7/246
- G06T15/80
- CPC G06T7/251
- G06T7/40
- CPC G06T7/40
- G06T7/73
- G06F3/01
- G06F3/16
- G06V10/70
- G06V10/94
- G06V20/50
- G06V20/70
- G10L15/18
- G10L15/22
- CPC G06T7/73
- G06T7/80
- CPC G06T7/74
- G06T15/00
- CPC G06T15/005
- G06T15/04
- CPC G06T15/04
- G06T3/4053
- G06T15/50
- G06T17/00
- H04N21/2187
- CPC G06T17/00
- G06V10/82
- G06N3/0464
- G06V20/40
- CPC G06V10/82
- H01F27/28
- H01F27/26
- H05K1/16
- H05K3/00
- CPC H01F27/2804
- H01H13/14
- G06F3/02
- H01H13/70
- H04R1/02
- H04R7/04
- CPC H01H13/14
- H01L21/68
- H01L21/67
- CPC H01L21/68
- H01L23/15
- H01L23/498
- CPC H01L23/15
- H01L23/373
- H01L21/48
- CPC H01L23/3733
- H01L23/473
- H01L23/00
- H01L23/528
- CPC H01L23/473
- CPC H01L23/49827
- H03K19/17704
- CPC H01L23/528
- H01L23/538
- H01L25/00
- H01L25/065
- CPC H01L23/5386
- H01L23/544
- CPC H01L23/544
- H01L21/311
- H01L23/522
- CPC H01L24/19
- H01L27/088
- H01L21/8238
- H01L27/092
- CPC H01L27/088
- H01L29/06
- H01L29/423
- H01L29/51
- H01L29/775
- CPC H01L27/092
- H01L29/66
- H01L29/786
- CPC H01L27/0922
- H01L29/417
- CPC H01L29/775
- H04L43/50
- H04L41/40
- H04W12/03
- H04W12/12
- CPC H04L43/50
- H04L45/74
- G06F12/1081
- G06F13/28
- H04L45/60
- H04L49/90
- CPC H04L45/742
- H04L47/2441
- H04L47/38
- CPC H04L47/2441
- H04L67/51
- H04L9/40
- H04L67/00
- CPC H04L67/51
- H04N9/31
- CPC H04N9/3185
- H04N13/388
- H04N23/69
- H04N23/695
- CPC H04N13/388
- H04W28/02
- H04W28/12
- CPC H04W28/0268
- H04W28/24
- H04W12/108
- H04W76/10
- H04W84/12
- CPC H04W28/24
- H04W76/19
- H04W12/041
- H04W12/0431
- H04W28/06
- H04W76/30
- CPC H04W76/19
- H05K1/02
- F16K31/50
- H05K7/20
- CPC H05K1/0209
- CPC H05K1/0224
- CPC H05K7/20236
