Intel Corporation patent applications on September 12th, 2024
Patent Applications by Intel Corporation on September 12th, 2024
Intel Corporation: 26 patent applications
Intel Corporation has applied for patents in the areas of H01L23/532 (3), H01L23/522 (2), G06F30/327 (2), H01L21/768 (2), H01L23/498 (2) G03H1/02 (1), H01L23/49838 (1), H04W12/06 (1), H04W8/02 (1), H04N19/103 (1)
With keywords such as: circuitry, network, device, apparatus, layer, frame, circuit, data, processor, and based in patent application abstracts.
Patent Applications by Intel Corporation
Inventor(s): Alexey Supikov of Santa Clara CA (US) for intel corporation, Michael Mefenza Nentedem of Santa Clara CA (US) for intel corporation
IPC Code(s): G03H1/02, G03H1/08
CPC Code(s): G03H1/02
Abstract: a method and system calibrates spatial light modulators.
Inventor(s): Keqiang Wu of Palatine IL (US) for intel corporation, Lingxiang Xiang of San Jose CA (US) for intel corporation, Heidi Pan of Burlingame CA (US) for intel corporation, Christopher J. Hughes of Santa Clara CA (US) for intel corporation, Zhe Wang of San Jose CA (US) for intel corporation
IPC Code(s): G06F12/0831, G06F12/084, G06F12/0891
CPC Code(s): G06F12/0835
Abstract: in one embodiment, a processor includes interconnect circuitry, processing circuitry, a first cache, and cache controller circuitry. the interconnect circuitry communicates over a processor interconnect with a second processor that includes a second cache. the processing circuitry generates a memory read request for a corresponding memory address of a memory. based on the memory read request, the cache controller circuitry detects a cache miss in the first cache, which indicates that the first cache does not contain a valid copy of data for the corresponding memory address. based on the cache miss, the cache controller circuitry requests the data from the second cache or the memory based on a current bandwidth utilization of the processor interconnect.
Inventor(s): Udaya NATARAJAN of El Dorado Hills CA (US) for intel corporation, Kannappan RAJARAMAN of Bangalore (IN) for intel corporation
IPC Code(s): G06F13/38, G06F11/14, G06F13/42
CPC Code(s): G06F13/387
Abstract: some aspects of the present disclosure relate to an apparatus for bringing up a multi-purpose communication port, the apparatus comprising interface circuitry, machine-readable instructions, and processor circuitry to execute the machine-readable instructions to determine, during a boot phase, a link type of a link to be established via the multi-purpose communication port, and perform, during the boot phase, link training on the multi-purpose communication port according to the link type, wherein, in case the link supports a first higher link rate or a first higher number of lanes, a second lower link rate or second lower number of lanes is used for link training on the multi-purpose communication port.
20240303343. PARTITIONING OF PROCESSOR SOCKETS_simplified_abstract_(intel corporation)
Inventor(s): Yi ZENG of Shanghai (CN) for intel corporation, Russell J. WUNDERLICH of Livermore CO (US) for intel corporation, Janusz JURSKI of Beaverton OR (US) for intel corporation, Lumin ZHANG of Shanghai (CN) for intel corporation, Kasper WSZOLEK of Gdansk (PL) for intel corporation, Jeanne GUILLORY of Reseda CA (US) for intel corporation, Ching Yu LO of Taipei (TW) for intel corporation, Teresa C. HERRICK of Folsom CA (US) for intel corporation, Richard Marian THOMAIYAR of Trichy (IN) for intel corporation
IPC Code(s): G06F21/57, G06F1/06
CPC Code(s): G06F21/575
Abstract: examples described herein relate to multiple processor sockets comprising processors connected thereto and first circuitry. the first circuitry is to: based on a first mode of operation: configure the multiple processor sockets to operate with a single memory address space and share interfaces and based on a second mode of operation: configure the interfaces accessible to the multiple processor sockets to provide isolated communications to processor sockets in different partitions and configure the multiple processor sockets to operate in independent memory address spaces.
Inventor(s): Sourav Saha of Bangalore (IN) for intel corporation, Rakshit Bazaz of Bangalore (IN) for intel corporation, Anmol Khatri of Bangalore (IN) for intel corporation, Raj Chetan Yadav of Bangalore (IN) for intel corporation
IPC Code(s): G06F30/31, G06F30/327, G06F30/392
CPC Code(s): G06F30/31
Abstract: methods, apparatus, systems, and articles of manufacture to predict outputs of electronic design automation (eda) tools using machine learning are disclosed. an example apparatus includes memory; machine readable instructions; and programmable circuitry to at least one of instantiate or execute the machine readable instructions to: access circuit design data to be optimized by an eda tool as part of a circuit design process for an integrated circuit; extract features from the circuit design data; apply a machine learning model to the features to estimate an output of the eda tool, the estimated output determined without execution of the eda tool; and provide results of the estimated output.
Inventor(s): Yi Peng of Newark CA (US) for intel corporation, Brandon Lewis Gordon of Campell CA (US) for intel corporation
IPC Code(s): G06F30/343, G06F30/327, G06F30/3308, G06F30/367, G06F30/398
CPC Code(s): G06F30/343
Abstract: a system includes an integrated circuit device configured to implement a circuit design. the integrated circuit device includes a communication interface configured to receive the circuit design in a configuration bitstream and instrumentation logic in the configuration bitstream and signal collector block configured to collect signal data based on the instrumentation logic during implementation of the circuit design.
Inventor(s): Raizy Kellerman of Jerusalem (IL) for intel corporation, Alex Nayshtut of Gan Yavne (IL) for intel corporation, Omer Ben-Shalom of Rishon Le-Tzion (IL) for intel corporation
IPC Code(s): G06N3/047
CPC Code(s): G06N3/047
Abstract: implementations herein disclose an activation function for homomorphically-encrypted neural networks. a data-agnostic activation technique is provided that collects information about the distribution of the most-dominant activated locations in the feature maps of the trained model and maintains a map of those locations. this map, along with a defined percent of random locations, decides which neurons in the model are activated using an activation function. advantages of implementations herein include allowing for efficient activation function computations in encrypted computations of neural networks, yet no data-dependent computation is done during inference time (e.g., data-agnostic). implementations utilize negligible overhead in model storage, while preserving the same accuracy as with general activation functions and runs in orders of magnitude faster than approximation-based activation functions. furthermore, implementations herein can be applied post-hoc to already-trained models and, as such, do not utilize fine-tuning.
Inventor(s): Wenjing KANG of Beijing (CN) for intel corporation, Xiaochuan LUO of Beijing (CN) for intel corporation, Xianchao XU of Beijing (CN) for intel corporation
IPC Code(s): G06N3/08
CPC Code(s): G06N3/08
Abstract: the disclosure provides an apparatus, method, device, and medium for loss balancing in mtl. the apparatus includes interface circuitry and processor circuitry. the processor circuitry is configured to initialize parameters of shared layers of a deep neural network for mtl using a pre-trained neural network; determine a custom interval consisting of a designated number of mini-batch training steps and a designated window of n custom intervals (n>2); for each task, calculate a loss change rate between each pair of n−1 pairs of neighboring custom intervals within a designated window prior to a present custom interval and a gradient magnitude with respect to selected shared weights within the designated window prior to the present custom interval, and adjust, a weight of the task, based on the calculated loss change rate and gradient magnitude with respect to selected shared weights.
Inventor(s): Dmitry Grilikhes of Rehovot (IL) for intel corporation
IPC Code(s): G06T5/92, G06T5/40, G06V10/60
CPC Code(s): G06T5/92
Abstract: techniques for improving image quality of a hdr image by increasing the contrast in the dark portion of the image while preserving the bright parts of the image. the methods preserve the input dynamic range. an image with a luminance histogram gap between a main portion with low brightness and a small portion with high brightness. a first tone mapping curve is determined for the low brightness portion of the image. a second tone mapping curve is determined from a selected point on the first tone mapping curve to a maximum brightness level of the input image. a final tone mapping curve is generated including the first tone mapping curve from a minimum brightness input to the selected point and the second tone mapping curve from the selected point to a maximum brightness level. the method can increase overall image quality and contrast.
Inventor(s): Darshan R. Iyer of Santa Clara CA (US) for intel corporation, Deepak Vembar of Portland OR (US) for intel corporation
IPC Code(s): G06T15/00, G06T3/00, G06T3/40, G06T7/20, G06T9/00
CPC Code(s): G06T15/005
Abstract: described herein are techniques to enhance the user experience for 3d rendered applications via neural frame generation and neural supersampling. one embodiment provides a latency aware unified neural network for frame interpolation and extrapolation. this unified neural network merges interpolation and extrapolation networks into one generalized network that can be applied to both interpolation and extrapolation, depending on the acceptable latency of performance. a further embodiment provides hardware-efficient and latency-aware spatiotemporal neural frame prediction. hardware-efficient and latency-aware spatiotemporal neural frame prediction enables both frame generation and machine learning supersampling using a single network, rather than using separate networks for frame generation and supersampling.
20240303915. INFERRED SHADING MECHANISM_simplified_abstract_(intel corporation)
Inventor(s): Selvakumar Panneer of Portland OR (US) for intel corporation, Mrutunjayya Mrutunjayya of Hillsboro OR (US) for intel corporation, Carl S. Marshall of Portland OR (US) for intel corporation, Ravishankar Iyer of Portland OR (US) for intel corporation, Zack Waters of Portland OR (US) for intel corporation
IPC Code(s): G06T15/80, G06N3/08, G06T15/00, G06T15/10
CPC Code(s): G06T15/80
Abstract: an apparatus to facilitate inferred object shading is disclosed. the apparatus comprises one or more processors to receive rasterized pixel data and hierarchical data associated with one or more objects and perform an inferred shading operation on the rasterized pixel data, including using one or more trained neural networks to perform texture and lighting on the rasterized pixel data to generate a pixel output, wherein the one or more trained neural networks uses the hierarchical data to learn a three-dimensional (3d) geometry, latent space and representation of the one or more objects.
Inventor(s): Yaoxin SHI of Shanghai (CN) for intel corporation, Bo ZHAO of Shanghai (CN) for intel corporation, Fuguang ZHENG of Shanghai (CN) for intel corporation
IPC Code(s): G06V30/14, G06V30/146
CPC Code(s): G06V30/1444
Abstract: a system that includes a system to analyze a frame of a video and to identify one or more bounding regions in the frame that correspond to regions of interest; select a location of a text bounding region in the frame that does not overlap with the one or more bounding regions, wherein the text bounding region in the frame is associated with text; and cause the text to be displayed in the text bounding region corresponding to the selected location.
Inventor(s): Zewei Wang of Chandler AZ (US) for intel corporation, George Frank Robinson, JR. of Chandler AZ (US) for intel corporation, Tingting Gao of Chandler AZ (US) for intel corporation, Viet Chau of Vancouver WA (US) for intel corporation
IPC Code(s): H01L21/67, H01L21/48
CPC Code(s): H01L21/67121
Abstract: methods, apparatus, systems, and articles of manufacture to place balls for second level interconnects of integrated circuit packages are disclosed. an example apparatus includes a ball head including a first surface having an array of holes. the array of holes hold a corresponding array of solder balls to be placed on a package substrate of an integrated circuit package. the apparatus also includes a protrusion extending away from the surface of the ball head. the protrusion is positioned relative to the holes to contact a second surface of the package substrate when the solder balls are to be placed on the package substrate.
Inventor(s): Sangeon LEE of Chandler AZ (US) for intel corporation, Tingting GAO of Chandler AZ (US) for intel corporation, Xiao LU of Chandler AZ (US) for intel corporation, Matthew MAGNAVITA of Chandler AZ (US) for intel corporation, Khalid ABDELAZIZ of Chandler AZ (US) for intel corporation
IPC Code(s): H01L23/29, H01L23/31, H01L23/498
CPC Code(s): H01L23/296
Abstract: embodiments disclosed herein include socket interconnects with liquid metal. in an embodiment, a board comprises a substrate. a pad may be provided over the substrate. in an embodiment, a confinement layer is over the substrate, where the confinement layer defines a cavity over the pad. in an embodiment, a liquid metal is on the pad within the cavity. in an embodiment, a protective layer is provided over the liquid metal.
Inventor(s): Sanjay THARMARAJAH of Queen Creek AZ (US) for intel corporation, Kristof DARMAWIKARTA of Chandler AZ (US) for intel corporation
IPC Code(s): H01L23/498, H01L23/532
CPC Code(s): H01L23/49838
Abstract: embodiments disclosed herein include package substrates. in an embodiment, the package substrate comprises a substrate layer, and a plurality of traces on the substrate layer. in an embodiment, each of the plurality of traces are covered on sidewalls and an entire top surface by a first layer. in an embodiment, a pad is on the substrate layer, where the pad is covered on sidewalls and an entire top surface by a second layer.
Inventor(s): Kevin Lin of Beaverton OR (US) for intel corporation, Noriyuki Sato of Hillsboro OR (US) for intel corporation, Tristan Tronic of Aloha OR (US) for intel corporation, Michael Christenson of Beaverton OR (US) for intel corporation, Christopher Jezewski of Portland OR (US) for intel corporation, Jiun-Ruey Chen of Hillsboro OR (US) for intel corporation, James M. Blackwell of Portland OR (US) for intel corporation, Matthew Metz of Portland OR (US) for intel corporation, Miriam Reshotko of Portland OR (US) for intel corporation, Nafees Kabir of Hillsboro OR (US) for intel corporation, Jeffery Bielefeld of Forest Grove OR (US) for intel corporation, Manish Chandhok of Beaverton OR (US) for intel corporation, Hui Jae Yoo of Hillsboro OR (US) for intel corporation, Elijah Karpov of Portland OR (US) for intel corporation, Carl Naylor of Portland OR (US) for intel corporation, Ramanan Chebiam of Hillsboro OR (US) for intel corporation
IPC Code(s): H01L23/522, H01L21/3213, H01L21/768, H01L23/528, H01L23/532
CPC Code(s): H01L23/5226
Abstract: ic interconnect structures including subtractively patterned features. feature ends may be defined through multiple patterning of multiple cap materials for reduced misregistration. subtractively patterned features may be lines integrated with damascene vias or with subtractively patterned vias, or may be vias integrated with damascene lines or with subtractively patterned lines. subtractively patterned vias may be deposited as part of a planar metal layer and defined currently with interconnect lines. subtractively patterned features may be integrated with air gap isolation structures. subtractively patterned features may be include a barrier material on the bottom, top, or sidewall. a bottom barrier of a subtractively patterned features may be deposited with an area selective technique to be absent from an underlying interconnect feature. a barrier of a subtractively patterned feature may comprise graphene or a chalcogenide of a metal in the feature or in a seed layer.
Inventor(s): Hui Jae Yoo of Hillsboro OR (US) for intel corporation, Kevin L. Lin of Beaverton OR (US) for intel corporation
IPC Code(s): H01L23/528, H01L21/311, H01L21/32, H01L21/768, H01L23/522, H01L23/532
CPC Code(s): H01L23/5283
Abstract: integrated circuit metallization lines having a planar top surface but different vertical heights, for example to control intra-layer resistance/capacitance of integrated circuit interconnect. a hardmask material layer may be inserted between two thicknesses of dielectric material that are over a via metallization. following deposition of the hardmask material layer, trench openings may be patterned through the hardmask layer to define where line metallization will have a greater height. following the deposition of a thickness of dielectric material over the hardmask material layer, a trench pattern may be etched through the uppermost thickness of dielectric material, exposing the hardmask material layer wherever the trench does not coincide with an opening in the hardmask material layer. the trench etch may be retarded where the hardmask material layer is exposed, resulting to trenches of differing depth. trenches of differing depth may be filled with metallization and then planarized.
Inventor(s): Chiao-Ti Huang of Portland OR (US) for intel corporation, Tao Chu of Portland OR (US) for intel corporation, Robin Chao of Portland OR (US) for intel corporation, Guowei Xu of Portland OR (US) for intel corporation, Feng Zhang of Hillsboro OR (US) for intel corporation, Biswajeet Guha of Hillsboro OR (US) for intel corporation, Stephen M. Cea of Hillsboro OR (US) for intel corporation
IPC Code(s): H01L27/092, H01L21/8238, H01L29/06, H01L29/423, H01L29/66, H01L29/775
CPC Code(s): H01L27/092
Abstract: fabrication method for nanoribbon-based transistors and associated transistor arrangements, ic structures, and devices are disclosed. an example fabrication method is based on patterning a foundation over which a superlattice is provided so that a single superlattice may be used to form both pmos and nmos stacks of nanoribbons. an example ic structure includes a support, an nmos stack of nanoribbons stacked vertically above one another over the support, and a pmos stack of nanoribbons stacked vertically above one another over the support, wherein at least one of the nanoribbons of the nmos stack is vertically offset with respect to at least one of the nanoribbons of the pmos stack.
Inventor(s): Anjo Lucas Vahldiek-Oberwagner of Berlin (DE) for intel corporation, Marcin Andrzej Chrapek of Zurich (CH) for intel corporation, Scott Constable of Portland OR (US) for intel corporation
IPC Code(s): H04L9/32
CPC Code(s): H04L9/3236
Abstract: systems, apparatus, methods, and articles of manufacture to validate the accuracy of artificial intelligence models are disclosed. an example apparatus includes machine-readable instructions; and at least one processor circuit to be programmed by the machine-readable instructions to: compute accuracy statistics of an artificial intelligence model using software applied by a trusted third party and an input data set; determine a signed artifact based on (1) the accuracy statistics indicative of the accuracy of the artificial intelligence model, (2) the software applied by the trusted third party, and (3) the input data set; and communicate the signed artifact to a user of the artificial intelligence model.
Inventor(s): Jingwen BAI of San Jose CA (US) for intel corporation, Shu-ping YEH of Campbell CA (US) for intel corporation, Shilpa TALWAR of Cupertino CA (US) for intel corporation
IPC Code(s): H04L41/0895, H04L41/5009, H04W24/08, H04W72/11, H04W72/115
CPC Code(s): H04L41/0895
Abstract: the present disclosure provides a resilient (radio) access network ((r)an) slicing framework encompassing a resource planning engine and distributed dynamic slice-aware scheduling modules at one or more network access nodes, edge compute nodes, or cloud computing service. the resilient (r)an slicing framework includes resource planning and slice-aware scheduling, as well as signaling exchanges for provisioning resilient (r)an slicing. the intelligent (r)an slicing framework can realize resource isolation in a more efficient and agile manner than existing network slicing technologies.
Inventor(s): Kapil Sood of Portland OR (US) for intel corporation, Seosamh O'Riordain of Ennis (IE) for intel corporation, Ned M. Smith of Beaverton OR (US) for intel corporation, Tarun Viswanathan of El Dorado Hills CA (US) for intel corporation
IPC Code(s): H04L9/40, G06F9/4401, G06F9/455, G06F9/46, G06F9/50, G06F21/53, G06F21/57, G06F21/62
CPC Code(s): H04L63/06
Abstract: technologies for providing secure utilization of tenant keys include a compute device. the compute device includes circuitry configured to obtain a tenant key. the circuitry is also configured to receive encrypted data associated with a tenant. the encrypted data defines an encrypted image that is executable by the compute device to perform a workload on behalf of the tenant in a virtualized environment. further, the circuitry is configured to utilize the tenant key to decrypt the encrypted data and execute the workload without exposing the tenant key to a memory that is accessible to another workload associated with another tenant.
Inventor(s): Ned M. Smith of Beaverton OR (US) for intel corporation
IPC Code(s): H04L9/40
CPC Code(s): H04L63/1433
Abstract: systems, apparatus, articles of manufacture, and methods are disclosed to optimize attestation verification. an example method includes determining a first network of nodes from attestation evidence, a node of the first network of nodes associated with an appraisal context of an device, obtaining an endorsement for the device, determining a second network of nodes from the endorsements, identifying a node that is in the first network of nodes and the second network of nodes, combining the first network of nodes and the second network of nodes to form a third network of nodes, and generating an attestation result for the device from the third network of nodes.
Inventor(s): Jason Daniel Tanner of Folsom CA (US) for intel corporation, James Holland of Folsom CA (US) for intel corporation, Stanley Jacob Baran of Chandler AZ (US) for intel corporation, Satya Yedidi of Roseville CA (US) for intel corporation, Penne Yat-Pei Lee of Bellevue WA (US) for intel corporation, Sumit Bhatia of Folsom CA (US) for intel corporation
IPC Code(s): H04N19/103, H04N19/136, H04N19/172, H04N19/177
CPC Code(s): H04N19/103
Abstract: systems, apparatus, articles of manufacture, and methods are disclosed of adaptive configurations of video encoder preset modes. an example apparatus comprising interface circuitry to obtain a video to be encoded, instructions, and at least one processor circuit to be programmed by the instructions to configure a video encoder to encode a first frame of the video based on a first preset mode of a plurality of preset modes associated respectively with a plurality of different relative encoder performance targets, select a second preset mode of the plurality of preset modes based on one or more characteristics associated with a second frame of the video, the second preset mode different from the first preset mode, and configure the video encoder to encode the second frame based on the second preset mode.
Inventor(s): Laurent CARIOU of Milizac (FR) for intel corporation, Thomas J. KENNEY of Portland OR (US) for intel corporation
IPC Code(s): H04W8/02, H04W36/08
CPC Code(s): H04W8/02
Abstract: this disclosure describes systems, methods, and devices related to enhanced bss roaming. a device may generate a basic service set transition management (btm) query frame comprising one or more fields. the device may include an indication of an intent to receive information from an associated ap, wherein the information is related to preserving one or more agreements with a target neighbor ap recommended by the associated ap. the device may cause to send the frame to the ap. the device may identify a btm request frame received from the associated ap.
Inventor(s): Abhijeet Ashok Kolekar of Hillsboro OR (US) for intel corporation
IPC Code(s): H04W12/06, H04W12/106, H04W12/72, H04W60/04
CPC Code(s): H04W12/06
Abstract: an apparatus and system are described for secure authentication and identification in trusted non-3gpp access networks. a temporary identifier is generated by a trusted non-3gpp gateway function (tngf) and sent to a user equipment (ue) over an encrypted channel. the temporary identifier is unique and not associated with personally identifiable information of a user of the ue. the ue uses the temporary identifier to establish a secure connection with the tngf.
Inventor(s): Hassan YAGHOOBI of San Jose CA (US) for intel corporation, Emily H. QI of Gig Harbor WA (US) for intel corporation, Jonathan SEGEV of Sunnyvale CA (US) for intel corporation, Carlos CORDEIRO of Camas WA (US) for intel corporation
IPC Code(s): H04W74/0816, H04W52/36, H04W76/14
CPC Code(s): H04W74/0816
Abstract: this disclosure describes systems, methods, and devices related to spectrumaware-p2p. a device may identify a frame received an access point (ap) comprising one or more fields carrying information associated channel access during a peer-to-peer (p2p) communication with a first p2p device. the device may extract a channel and maximum power information element (ie). the device may initiate the p2p communication with the first p2p device based on the channel and maximum power ie.
Intel Corporation patent applications on September 12th, 2024
- Intel Corporation
- G03H1/02
- G03H1/08
- CPC G03H1/02
- Intel corporation
- G06F12/0831
- G06F12/084
- G06F12/0891
- CPC G06F12/0835
- G06F13/38
- G06F11/14
- G06F13/42
- CPC G06F13/387
- G06F21/57
- G06F1/06
- CPC G06F21/575
- G06F30/31
- G06F30/327
- G06F30/392
- CPC G06F30/31
- G06F30/343
- G06F30/3308
- G06F30/367
- G06F30/398
- CPC G06F30/343
- G06N3/047
- CPC G06N3/047
- G06N3/08
- CPC G06N3/08
- G06T5/92
- G06T5/40
- G06V10/60
- CPC G06T5/92
- G06T15/00
- G06T3/00
- G06T3/40
- G06T7/20
- G06T9/00
- CPC G06T15/005
- G06T15/80
- G06T15/10
- CPC G06T15/80
- G06V30/14
- G06V30/146
- CPC G06V30/1444
- H01L21/67
- H01L21/48
- CPC H01L21/67121
- H01L23/29
- H01L23/31
- H01L23/498
- CPC H01L23/296
- H01L23/532
- CPC H01L23/49838
- H01L23/522
- H01L21/3213
- H01L21/768
- H01L23/528
- CPC H01L23/5226
- H01L21/311
- H01L21/32
- CPC H01L23/5283
- H01L27/092
- H01L21/8238
- H01L29/06
- H01L29/423
- H01L29/66
- H01L29/775
- CPC H01L27/092
- H04L9/32
- CPC H04L9/3236
- H04L41/0895
- H04L41/5009
- H04W24/08
- H04W72/11
- H04W72/115
- CPC H04L41/0895
- H04L9/40
- G06F9/4401
- G06F9/455
- G06F9/46
- G06F9/50
- G06F21/53
- G06F21/62
- CPC H04L63/06
- CPC H04L63/1433
- H04N19/103
- H04N19/136
- H04N19/172
- H04N19/177
- CPC H04N19/103
- H04W8/02
- H04W36/08
- CPC H04W8/02
- H04W12/06
- H04W12/106
- H04W12/72
- H04W60/04
- CPC H04W12/06
- H04W74/0816
- H04W52/36
- H04W76/14
- CPC H04W74/0816
