Intel Corporation patent applications on October 3rd, 2024
Patent Applications by Intel Corporation on October 3rd, 2024
Intel Corporation: 109 patent applications
Intel Corporation has applied for patents in the areas of H01L29/66 (13), H01L29/06 (13), H01L29/423 (12), H01L23/00 (10), H01L21/768 (8) G06F9/4893 (3), H01L23/3737 (2), H01L27/0924 (2), H01L23/49838 (2), H04L9/0631 (2)
With keywords such as: circuit, layer, based, device, data, source, circuitry, integrated, gate, and disclosed in patent application abstracts.
Patent Applications by Intel Corporation
20240325885. NETWORK AND RENDER AWARE SPLIT RENDERING_simplified_abstract_(intel corporation)
Inventor(s): Selvakumar Panneer of Portland OR (US) for intel corporation, Yunbiao Lin of Shanghai (CN) for intel corporation, Fan He of Shanghai (CN) for intel corporation, Chao Hu of Chandler AZ (US) for intel corporation, Sarthak Rajesh Shah of Hillsboro OR (US) for intel corporation, Changliang Wang of Bellevue WA (US) for intel corporation
IPC Code(s): A63F13/355, G06T1/20
CPC Code(s): A63F13/355
Abstract: described herein is a network and renderer aware split rendering technique that enables a cloud gaming service to split execution of cloud gaming workloads between a graphics processor of a cloud gaming server and a graphics processor of a client of the cloud gaming service. the split rendering technique enables portions of a frame that most vulnerable to quality degradation at low bitrates to be rendered on the client, which results in an improvement of the quality of the final frame that is presented at the client device.
20240326242. SELF-RECONFIGURABLE ROBOT CONTROLLER_simplified_abstract_(intel corporation)
Inventor(s): Alejandro Ibarra Von Borstel of Manchaca TX (US) for intel corporation, Fernando Ambriz Meza of Manchaca TX (US) for intel corporation, Cornelius Buerkle of Karlsruhe (DE) for intel corporation, Jose Rodrigo Camacho Perez of Guadalajara (MX) for intel corporation, Hector Cordourier Maruri of Guadalajara (MX) for intel corporation, Paulo Lopez Meyer of Zapopan (MX) for intel corporation, Fabian Oboril of Karlsruhe (DE) for intel corporation, Julio Zamora Esquivel of West Sacramento CA (US) for intel corporation, Jose Miguel Hernandez Miramontes of Austin TX (US) for intel corporation
IPC Code(s): B25J9/16
CPC Code(s): B25J9/163
Abstract: a self-reconfigurable controller for a robot, including: input/output (i/o) interfaces to enable communication with i/o peripheral devices coupled to the robot; and processing circuitry that is operable to: register the i/o peripheral devices and associated functionalities; receive a command for the robot to perform a task; conduct a self-awareness check to correlate functionalities to perform the task with functionalities of the i/o peripheral devices; and generate, based on a net of deep learning (dl) models and a result of the correlation, a target deep learning controller (tdlc) model to control the robot to perform the task.
Inventor(s): Javier Felip Leon of Hillsboro OR (US) for intel corporation, Leobardo Campos Macias of Guadalajara (MX) for intel corporation, David Gomez Gutierrez of Tlaquepaque (MX) for intel corporation, Javier Turek of Beaverton OR (US) for intel corporation, David Gonzalez Aguirre of Portland OR (US) for intel corporation
IPC Code(s): B25J9/16, G06V10/26, H04N23/695
CPC Code(s): B25J9/1697
Abstract: various aspects of techniques, systems, and use cases may be used for camera and end-effector planning for visual servoing for example in redundant manipulators. a technique may include generating a set of paths of an end effector of a robotic arm, and ranking the set of paths using an objective function that results in an improvement to a distance between the end effector and a target while maintaining a collision mitigation path for the end effector and minimizing occlusion of a camera affixed to a joint of the robotic arm. the technique may include converting a path of the set of paths into a trajectory based on the ranking, and outputting the trajectory for controlling the robotic arm to move the end effector.
20240327201. MEMS DIES EMBEDDED IN GLASS CORES_simplified_abstract_(intel corporation)
Inventor(s): Numair Ahmed of Chandler AZ (US) for intel corporation, Mohammad Mamunur Rahman of Gilbert AZ (US) for intel corporation, Suddhasattwa Nad of Chandler AZ (US) for intel corporation, Sashi Kandanur of Chandler AZ (US) for intel corporation, Darko Grujicic of Chandler AZ (US) for intel corporation, Benjamin Duong of Phoenix AZ (US) for intel corporation, Srinivas Pietambaram of Chandler AZ (US) for intel corporation, Tarek Ibrahim of Mesa AZ (US) for intel corporation, Whitney Bryks of Tempe AZ (US) for intel corporation
IPC Code(s): B81B7/00, B81C1/00, G02B6/12
CPC Code(s): B81B7/0048
Abstract: mems dies embedded in glass cores of integrated circuit (ic) package substrates are disclosed. an example integrated circuit (ic) package includes a package substrate including a glass core, the example integrated circuit (ic) package also includes a micro electromechanical system (mems) die positioned in a cavity of the glass core.
20240327679. MEDIA TRAY WITH SWITCHABLE ADHESION_simplified_abstract_(intel corporation)
Inventor(s): Yuan MENG of Chandler AZ (US) for intel corporation, Elizabeth NOFEN of Phoenix AZ (US) for intel corporation, Zhixin XIE of Chandler AZ (US) for intel corporation, Dingying XU of Chandler AZ (US) for intel corporation, Seyed Hadi ZANDAVI of Phoenix AZ (US) for intel corporation
IPC Code(s): C09J7/38, C09J11/04, H05K13/00
CPC Code(s): C09J7/38
Abstract: this disclosure describes systems, methods, and devices related to switchable adhesion. a switchable adhesion system may comprise a shape memory polymer having a shaped surface to enhance adhesion using a trigger and a force applied to the shape memory polymer, wherein the trigger is applied to alter characteristics of the shape memory polymer, and wherein the force is applied to deform the shape memory polymer while the trigger is applied. the system may further comprise a media tray connected to the shape memory polymer.
Inventor(s): Craig Yost of Gilbert AZ (US) for intel corporation, Paul Jonathan Diglio of Gaston OR (US) for intel corporation, Ruben Eduardo Nunez Blanco of Gilbert AZ (US) for intel corporation
IPC Code(s): F16J15/06, H05K7/20
CPC Code(s): F16J15/06
Abstract: methods, apparatus, systems, and articles of manufacture are disclosed that reduce leakage of a cooling fluid used to cool an electronic component. an example disclosed herein includes a seal assembly comprising a socket to receive an electronic component, the electronic component including a semiconductor die and a substrate to support the die, a first seal to be forced against the electronic component, the first seal to surround the die, and a second seal to be forced against the electronic component, the second seal to surround the first seal.
Inventor(s): Sairam Subramanian of Portland OR (US) for intel corporation, Amit Paliwal of Hillsboro OR (US) for intel corporation, Xiao Wen of Beaverton OR (US) for intel corporation, Dipto Thakurta of Portland OR (US) for intel corporation, Manish Sharma of Portland OR (US) for intel corporation, Daniel Murray of Portland OR (US) for intel corporation
IPC Code(s): G01R31/28
CPC Code(s): G01R31/2851
Abstract: an integrated circuit on a production die comprises a device under test (dut) cell array formed in a fill region on the production die, the dut cell array comprising a plurality of dut transistor structures configured for voltage contrast (vc) detection of electrical opens on the production die. the dut transistor structures comprise one or more vias that are not located on power lines or signal lines, such that the dut transistor structures are not connected to each other or to the electrically functioning transistors. a guard ring buffer is formed at a transition between the active transistor region and the dut cell array.
Inventor(s): Sairam SUBRAMANIAN of Portland OR (US) for intel corporation, Amit PALIWAL of Hillsboro OR (US) for intel corporation, Xiao WEN of Beaverton OR (US) for intel corporation, Dipto THAKURTA of Portland OR (US) for intel corporation
IPC Code(s): G01R31/28
CPC Code(s): G01R31/2884
Abstract: a device under test (dut) structure for voltage contrast (vc) detection of contact opens comprises a fin formed along a first direction over a substrate, the fin having a diffusion region, the fin doped to form i) a p-type fin and a p-type diffusion region or ii) an n-type fin and an n-type diffusion region. a trench contact (tcn) segment is along a second direction generally orthogonal to the first direction over the fin and in contact with the diffusion region. a floating gate is generally parallel to the tcn segment over the fin, wherein the floating gate and the tcn segment are not in contact, and the floating gate does not have a via formed thereon.
Inventor(s): Sridhar Muthrasanallur of Bengaluru (IN) for intel corporation, Debendra Das Sharma of Saratoga CA (US) for intel corporation, Swadesh Choudhary of Mountain View CA (US) for intel corporation, Gerald Pasdast of San Jose CA (US) for intel corporation, Peter Onufryk of Flanders NJ (US) for intel corporation
IPC Code(s): G01R31/317, G06F11/27, G06F13/42
CPC Code(s): G01R31/31705
Abstract: technologies for a unified debug and test architecture in chiplets is disclosed. in an illustrative embodiment, several chiplets are integrated on an integrated circuit package. the chiplets are connected by a package interconnect, such as a universal chiplet interconnect express (ucie) interconnect. each chiplet includes several debug nodes, which are connected by an on-chiplet network. one of the chiplets, referred to as a package debug endpoint, acts as a link endpoint for an off-package link, such as a peripheral component interconnect express (pcie) link. in use, debug messages can be sent to the package debug endpoint over a pcie link. the debug messages can be routed within the chiplets and between chiplets, allowing for the debug functionality at each debug node to be probed using a common protocol. in this manner, chiplets from different vendors can be integrated into the same package and tested using common software.
20240329301. EMBEDDED PHOTONIC INTEGRATED CIRCUITS_simplified_abstract_(intel corporation)
Inventor(s): Kaveh Hosseini of Livermore CA (US) for intel corporation, Ravindranath V. Mahajan of Chandler AZ (US) for intel corporation, Chia-Pin Chiu of Tempe AZ (US) for intel corporation
IPC Code(s): G02B6/12
CPC Code(s): G02B6/12004
Abstract: a substrate for a multi-chip package includes at least one photonic integrated circuit (pic) interposer mounted in a cavity in a first major surface. each pic interposer is configured to electrically connect with, or optically couple to, a plurality of integrated circuit devices. the substrate further includes at least one optical coupler that is optically coupled to the pic interposer.
Inventor(s): Chia-Pin Chiu of Tempe AZ (US) for intel corporation, Kaveh Hosseini of Livermore CA (US) for intel corporation, Xiaoqian Li of Chandler AZ (US) for intel corporation
IPC Code(s): G02B6/26
CPC Code(s): G02B6/26
Abstract: technologies for optical coupling to photonic integrated circuit (pic) dies are disclosed. in one illustrative embodiment, a pic die has one or more waveguides. a lens array is positioned adjacent the pic die. light from waveguides of the pic die reflects off of a reflective surface of the lens array. the reflective surface directs the light from the pic die towards lenses in the lens array. the lenses collimate the light, facilitating coupling of light to and from other components. the reflective surface on the lens array may be oriented at any suitable angle, resulting in a collimated beam of light that is oriented at any suitable angle.
Inventor(s): Nicholas D. Psaila of Lanark (GB) for intel corporation, Richard Laming of Santa Clara CA (US) for intel corporation
IPC Code(s): G02B6/30, G02B6/32, G02B6/38
CPC Code(s): G02B6/305
Abstract: an optical interconnect component for use in transmitting light between a photonic integrated circuit and one or more optical fibres attached to an optical fibre connector ferrule is disclosed. the optical interconnect component comprises a step formed at an edge of the optical interconnect component, the step including a ledge and a facet, one or more optical beam management elements formed in a surface of the optical interconnect component, and a plurality of integrated optical waveguides. each of two or more of the integrated optical waveguides extends from the facet so as to define a plurality of optical ports at the facet, and each of the one or more optical beam management elements is aligned with, but separated from, an end of a corresponding one of the plurality of integrated optical waveguides. also disclosed are an optical fibre connector ferrule, an optical interconnect assembly comprising the optical interconnect component and the optical fibre connector ferrule, and an optical system comprising the optical interconnect assembly, a photonic integrated circuit, and one or more optical fibres.
Inventor(s): Robert May of Chandler AZ (US) for intel corporation, Bai Nie of Chandler AZ (US) for intel corporation, Changhua Liu of Chandler AZ (US) for intel corporation, Hiroki Tanaka of Gilbert AZ (US) for intel corporation, Kristof Darmawikarta of Chandler AZ (US) for intel corporation, Lilia May of Chandler AZ (US) for intel corporation, Shriya Seshadri of Chandler AZ (US) for intel corporation, Srinivas Pietambaram of Chandler AZ (US) for intel corporation, Tarek Ibrahim of Mesa AZ (US) for intel corporation
IPC Code(s): G02B6/42, G02B6/13, H01L25/065, H01L25/16
CPC Code(s): G02B6/4202
Abstract: multi-die packages including both photonic and electric integrated circuit (ic) die interconnected to each other through a routing structure built-up on a glass substrate. a glass preform comprising an optical waveguide may also be attached to the routing structure. a plurality of electrical ic (eic) die may be arrayed over the routing structure along with a plurality of photonic ic (pic). each pic may be coupled to an optical waveguide within the glass preform. conductive vias may extend through the glass substrate and be further coupled with a host substrate. the host substrate may comprise glass and an optical waveguide embedded within the glass. a vertical coupler may be attached to the host substrate to optically couple the host substrate to the optical waveguide within the glass preform of the multi-die package. many of the multi-die packages may be arrayed over a routing structure on the host substrate.
Inventor(s): Jeremy Ecton of Gilbert AZ (US) for intel corporation, Changhua Liu of Chandler AZ (US) for intel corporation, Hiroki Tanaka of Gilbert AZ (US) for intel corporation, Brandon C. Marin of Gilbert AZ (US) for intel corporation, Srinivas V. Pietambaram of Chandler AZ (US) for intel corporation
IPC Code(s): G02B6/42, G02B6/38
CPC Code(s): G02B6/4228
Abstract: microelectronic assemblies, related devices and methods, are disclosed herein. in some embodiments, a microelectronic assembly may include a photonic integrated circuit (pic) having a first surface having a channel and a first magnetic material; a fiber connector including a second surface with a second magnetic material; and a fiber physically coupled to the second surface of the fiber connector by an adhesive material; wherein the first surface of the pic is coupled to the second surface of the fiber connector by the first and second magnetic materials with the fiber positioned in the channel.
Inventor(s): Kosta Luria of Pardesiya (IL) for intel corporation, Michael Zelikson of Haifa (IL) for intel corporation, Lior Gil of Haifa (IL) for intel corporation
IPC Code(s): G05F1/575, G05F1/565, G05F1/59
CPC Code(s): G05F1/575
Abstract: embodiments herein relate to a digital linear voltage regulator (dlvr). the dlvr includes a set of power links which each includes many columns of power transistors. the columns can be turned on or off individually based on digital data from a main control circuit. additionally, individual power links can be turned on or off based on monitoring of a dropout voltage of the set of power links and a drain-to-source resistance, rds_on, of replica columns. an input voltage may be monitored as an alternative. the monitoring compensates for changes in rds_on due to changes in an input voltage, vin, which could otherwise result in unstable behavior. the dlvr can avoid the complexity and power losses of dynamic biasing of the control gate voltages of the transistors.
Inventor(s): Naoki Matsumura of San Jose CA (US) for intel corporation, Kirk Jardin of Sacramento CA (US) for intel corporation, Shirley Arnold Jayachandran of Folsom CA (US) for intel corporation, David Woods of El Dorado Hills CA (US) for intel corporation, Mark Sprenger of Tigard OR (US) for intel corporation, Tod Schiff of Portland OR (US) for intel corporation, Jagadish Singh of Bangalore (IN) for intel corporation
IPC Code(s): G06F1/20, G06F1/3212, G06F1/3234
CPC Code(s): G06F1/206
Abstract: techniques for system power control based on a battery's thermal limit and impedance are described. in certain examples, a system includes: a hardware processor that includes a continuous boost power mode; and a power management circuit to couple to a battery, wherein the power management circuit is to: determine heat dissipation for the battery over time when the hardware processor is in the continuous boost power mode, and control power provided to the hardware processor in the continuous boost power mode without exceeding a limit of the heat dissipation over time.
Inventor(s): Rizwana BEGUM of Wylie TX (US) for intel corporation, Vasudev BIBIKAR of Austin TX (US) for intel corporation, Efraim ROTEM of Haifa (IS) for intel corporation
IPC Code(s): G06F1/3206
CPC Code(s): G06F1/3206
Abstract: an apparatus and method for workload, power, and performance-aware dynamic core frequency ramp rate. for example, one embodiment of a processor comprises: a processor comprising: a plurality of cores, a first core of the plurality of cores to execute an application comprising one or more workloads; and dynamic ramp rate selection circuitry to determine a core frequency ramp rate to be used to increase a frequency of the first core based, at least in part, on a workload type of a first workload of the one or more workloads.
Inventor(s): Amit K. Jain of Portland OR (US) for intel corporation, Howard L. Heck of Hillsboro OR (US) for intel corporation, Marva Mason Ortiz of San Jose (CR) for intel corporation, Stephen Harvey Hall of Forest Grove OR (US) for intel corporation, Eskinder Hailu of Cary NC (US) for intel corporation, Chin Lee Kuan of Bayan Lepas (MY) for intel corporation, Sameer Shekhar of Portland OR (US) for intel corporation
IPC Code(s): G06F1/3215, G06F1/324
CPC Code(s): G06F1/3215
Abstract: an apparatus, system, and method for improved power consumption and/or noise reduction in a differential input/output (i/o) buffer are provided. a circuit can include a differential signal buffer and encoding scheme quantifying and selection circuitry. the encoding scheme quantifying and selection circuitry can be configured to generate a selection code indicating a selected encoding scheme of the encoding schemes based on respective signals indicating whether each respective encoding scheme of encoding schemes has a net positive power consumption reduction in differential signals. the encoding scheme quantifying and selection circuitry can be configured to provide the selection code to an encoder.
Inventor(s): Somvir DAHIYA of Hillsboro OR (US) for intel corporation, Scot KELLAR of Bend OR (US) for intel corporation, Stephen H. GUNTHER of Beaverton OR (US) for intel corporation, Mark GALLINA of Hillsboro OR (US) for intel corporation, Efraim ROTEM of Santa Clara CA (US) for intel corporation, Prasanna JOTHI of Bengaluru (IN) for intel corporation
IPC Code(s): G06F1/3296, G06F9/48, G06F9/50
CPC Code(s): G06F1/3296
Abstract: an apparatus and method to control temperature ramp rates including temperature spike detection and control. for example, one embodiment of a processor comprises: a plurality of cores to execute instructions; a power management unit to control power consumption of each core of the plurality of cores, the power management unit comprising: a frequency ramp governor or power step governor to determine a frequency ramp rate limit or power step limit for a core of the plurality of cores based, at least in part, on a present frequency or present power metrics of the core; a frequency limiter or voltage limiter to determine a maximum frequency or maximum voltage of the core based, at least in part, on a measured temperature; and limit resolution circuitry to determine a first frequency or a first power level of the core in accordance with the frequency ramp rate limit or the power step limit and the maximum frequency or maximum voltage.
20240329731. USER-TO-AVATAR ACTION MAPPING AND ADJUSTMENT_simplified_abstract_(intel corporation)
Inventor(s): Aleksander Magi of Portland OR (US) for intel corporation, Glen J. Anderson of Beaverton OR (US) for intel corporation, Sangeeta Ghangam Manepalli of Chandler AZ (US) for intel corporation, David Warren Browning of Portland OR (US) for intel corporation, Michael Daniel Rosenzweig of Queen Creek AZ (US) for intel corporation, Stanley Jacob Baran of Chandler AZ (US) for intel corporation, Chia-Hung Sophia Kuo of Folsom CA (US) for intel corporation, Passant Vatsalya Karunaratne of Chandler AZ (US) for intel corporation, Atsuo Kuwahara of Camas WA (US) for intel corporation, Siew Wen Chin of Penang (MY) for intel corporation, Haichuan Tan of Santa Clara CA (US) for intel corporation
IPC Code(s): G06F3/01, G06T13/40
CPC Code(s): G06F3/013
Abstract: methods, apparatus, systems, and articles of manufacture for user-to-avatar mapping and adjustment are disclosed. an example apparatus includes processor circuitry to at least one of instantiate or execute the machine readable instructions to: determine a dissonance between a first orientation of a user in a real-world environment and a second orientation of an avatar in a virtual environment, the avatar corresponding to the user; determine an avatar adjustment value based on the dissonance; and apply the avatar adjustment value to the avatar model to change the second orientation.
Inventor(s): Aleksander Magi of Portland OR (US) for intel corporation, Glen J. Anderson of Beaverton OR (US) for intel corporation, Arvind Kumar of Beaverton OR (US) for intel corporation, Meng Shi of Hillsboro OR (US) for intel corporation
IPC Code(s): G06F3/04815, G06V10/94
CPC Code(s): G06F3/04815
Abstract: technologies for device management in metaverse interactions are disclosed. in an illustrative embodiment, a compute device is connected to remote compute devices in a metaverse. the compute device may detect local devices, such as by seeing a device in images captured by a camera of the compute device. the local device may be, e.g., a cell phone or smartwatch. the local devices may be registered by the compute device and reproduced in the metaverse. the local user of the compute device may interface with the local devices in the metaverse. the local user may allow remote users to interface or control the local device as well.
Inventor(s): Yonghae Kim of Atlanta GA (US) for intel corporation, David M. Durham of Beaverton OR (US) for intel corporation, Michael LeMay of Hillsboro OR (US) for intel corporation
IPC Code(s): G06F3/06
CPC Code(s): G06F3/0631
Abstract: an apparatus includes circuitry to receive a memory access request based on a memory address in a memory allocation of a program. the memory allocation is assigned to a slot of memory apportioned into a plurality of slots. the circuitry is to calculate an index based, at least in part, on whether a size of the slot exceeds a slot threshold size, and determine whether a buffer communicatively coupled to the circuitry includes a buffer entry corresponding to the index and containing a set of metadata associated with the memory allocation. based on the slot size, the circuitry is to calculate the index by either determining a metadata virtual address or by determining a virtual address of a midpoint of the slot. the indexed data may include bounds and tag information for the circuitry to determine if a memory access is within the bounds and matches the tag value.
20240329873. MANAGEMENT OF BUFFER UTILIZATION_simplified_abstract_(intel corporation)
Inventor(s): Ho-Ming LEUNG of Cupertino CA (US) for intel corporation, Salma Mirza JOHNSON of Littleton MA (US) for intel corporation, Jackson ELLIS of Fort Collins CO (US) for intel corporation, Daniel Christian BIEDERMAN of Saratoga CA (US) for intel corporation
IPC Code(s): G06F3/06
CPC Code(s): G06F3/0656
Abstract: examples described herein relate to a device that includes: a host interface; and circuitry to: based on allocation of a region in a buffer, wherein the buffer is associated with non-volatile memory express over fabrics (nvme-of) transactions: based on a first size of compressed data to be stored in the buffer, deallocate a portion of the region in the buffer and store the compressed data of the first size into a second portion of the region in the buffer and based on a second size of the compressed data to be stored in the buffer, utilize the allocated region in the buffer to store the compressed data of the second size.
20240329938. MATRIX TRANSPOSE AND MULTIPLY_simplified_abstract_(intel corporation)
Inventor(s): Menachem Adelman of Modi'in (IL) for intel corporation, Robert Valentine of Kiryat Tivon (IL) for intel corporation, Barukh Ziv of Haifa (IL) for intel corporation, Amit Gradstein of Binyamina (IL) for intel corporation, Simon Rubanovich of Haifa (IL) for intel corporation, Zeev Sperber of Zichron Yackov (IL) for intel corporation, Mark J. Charney of Lexington MA (US) for intel corporation, Christopher J. Hughes of Santa Clara CA (US) for intel corporation, Alexander F. Heinecke of San Jose CA (US) for intel corporation, Evangelos Georganas of San Jose CA (US) for intel corporation, Binh Pham of Burlingame CA (US) for intel corporation
IPC Code(s): G06F7/78, G06F9/30, G06F17/16
CPC Code(s): G06F7/78
Abstract: embodiments for a matrix transpose and multiply operation are disclosed. in an embodiment, a processor includes a decoder and execution circuitry. the decoder is to decode an instruction having a format including an opcode field to specify an opcode, a first destination operand field to specify a destination matrix location, a first source operand field to specify a first source matrix location, and a second source operand field to specify a second source matrix location. the execution circuitry is to, in response to the decoded instruction, transpose the first source matrix to generate a transposed first source matrix, perform a matrix multiplication using the transposed first source matrix and the second source matrix to generate a result, and store the result in a destination matrix location.
Inventor(s): Maurizio Iacaruso of Lucca (IT) for intel corporation, Stefano Dell'Osa of Napoli (IT) for intel corporation, Srikanth Kaniyanoor Srinivasan of Bangalore (IN) for intel corporation, Kevin Smith of High Wycombe (GB) for intel corporation
IPC Code(s): G06F8/41
CPC Code(s): G06F8/41
Abstract: various systems and methods for implementing functional safety verification of a software compiler and a compiled software product are disclosed. in an example, verification of functional safety testing requirements includes: generating first code coverage data for a compiler (e.g., a toolchain testsuite code coverage report), the first code coverage data based on a plurality of validation tests of the compiler; performing compilation of a software product (e.g., application, library, operating system) with the compiler; generating second code coverage data (e.g., a toolchain safety application code coverage report) for the compilation of the software product, based on lines of source code invoked in the compiler with the compilation of the software product; and outputting data for verification of functional safety testing requirements based on a comparison of the first code coverage data for the compiler with the second code coverage data for the compilation of the software product.
Inventor(s): Martin LANGHAMMER of Alderbury (GB) for intel corporation, Alexander F. HEINECKE of San Jose CA (US) for intel corporation
IPC Code(s): G06F9/30
CPC Code(s): G06F9/30145
Abstract: an apparatus of an aspect includes decoder circuitry to decode an instruction. the instruction to indicate at least one source floating-point vector, a destination storage location, and at least one value. the source floating-point vector is to have floating-point data elements. the at least one value is to indicate at least one of: (a) a number of significand bits of the floating-point data elements; (b) a number of exponent bits of the floating-point data elements; (c) exponent bias information for the floating-point data elements; or (d) any combination thereof. execution circuitry coupled with decoder circuitry is to perform operations according to the instruction. the operations include to interpret the floating-point data elements consistent with the at least one value, perform an operation specified by the instruction on the at least one source floating-point vector to generate a result vector, and store the result vector in the destination storage location.
Inventor(s): Scott D. Constable of Portland OR (US) for intel corporation
IPC Code(s): G06F9/30, G06F11/10, G06F12/14
CPC Code(s): G06F9/3016
Abstract: circuitry and methods for implementing one or more predicated capability instructions are described. in certain examples, a hardware processor (e.g., core) includes a capability management circuit to check a capability for a memory access request for a memory, the capability comprising an address field for an address to be accessed by the memory access request and a bounds field that is to indicate a lower bound and an upper bound of an address space to which the capability authorizes access; a decoder circuit to decode a single instruction into a decoded single instruction, the single instruction comprising a field to indicate the capability, and an opcode to indicate: an operation to be performed for the address, that an execution circuit is to perform a first check that a condition code, that indicates a status from a previous execution of the execution circuit, is a certain value, that the capability management circuit is to perform a second check that the capability authorizes access to the address, and in response to the first check and the second check both passing, cause the execution circuit to perform the operation for the address; and the execution circuit to execute the decoded single instruction according to the opcode.
Inventor(s): Adam Herr of Forest Grove OR (US) for intel corporation, Derek Gerstmann of Del Mar CA (US) for intel corporation, Justin Gottschlich of Santa Clara CA (US) for intel corporation, Mikael Bourges-Sevenier of Santa Clara CA (US) for intel corporation, Sridhar Sharma of Palo Alto CA (US) for intel corporation
IPC Code(s): G06F9/30, G06F8/30, G06F8/52, G06F8/75, G06F8/76, G06F9/38, G06N3/04
CPC Code(s): G06F9/30174
Abstract: methods, apparatus, systems and articles of manufacture are disclosed for intentional programming for heterogeneous systems. an example apparatus includes a code lifter to identify annotated code corresponding to an algorithm to be executed on the heterogeneous system based on an identifier being associated with the annotated code, and convert the annotated code in the first representation to intermediate code in a second representation by identifying the intermediate code as having a first algorithmic intent that corresponds to a second algorithmic intent of the annotated code, a domain specific language (dsl) generator to translate the intermediate code in the second representation to dsl code in a third representation when the first algorithmic intent matches the second algorithmic intent, the third representation corresponding to a dsl representation, and a code replacer to invoke a compiler to generate an executable including variant binaries based on the dsl code.
Inventor(s): Scott D. Constable of Portland OR (US) for intel corporation, Michael LeMay of Hillsboro OR (US) for intel corporation
IPC Code(s): G06F9/38, G06F9/30
CPC Code(s): G06F9/3861
Abstract: techniques for implementing forward-edge control-flow integrity (fecfi) using capability instructions in a hardware processor are described. in certain examples, a hardware processor (e.g., core) includes a capability management circuit to check a capability for a memory access request for a memory, the capability comprising an address field and a bounds field that is to indicate a lower bound and an upper bound of an address space to which the capability authorizes access; a decoder circuit to decode a single instruction into a decoded single instruction, the single instruction comprising: a first capability to indicate a first call table comprising a respective entry for each of a plurality of functions of a first type, a field to indicate a first offset of a first entry for a first function requested for execution, and an opcode to indicate the capability management circuit is to perform a first check that the first offset is within a lower bound and an upper bound of the first capability and a second check that the first offset is a permitted offset for the entries in the first call table, and in response to the first check and the second check both passing, cause an execution circuit to execute the first function; and the execution circuit to execute the decoded single instruction according to the opcode.
Inventor(s): John Wiegert of Aloha OR (US) for intel corporation, Joydeep Ray of Folsom CA (US) for intel corporation, Timothy Bauer of Hillsboro OR (US) for intel corporation, James Valerio of North Plains OR (US) for intel corporation
IPC Code(s): G06F9/38, G06F9/30, G06F9/355, G06F15/78
CPC Code(s): G06F9/3887
Abstract: embodiments described herein provide a technique to decompose 64-bit per-lane virtual addresses to access a plurality of data elements on behalf of a multi-lane parallel processing execution resource of a graphics or compute accelerator. the 64-bit per-lane addresses are decomposed into a base address and a plurality of per-lane offsets for transmission to memory access circuitry. the memory access circuitry then combines the base address and the per-lane offsets to reconstruct the per-lane addresses.
Inventor(s): Efraim ROTEM of Santa Clara CA (US) for intel corporation, Stephen H. GUNTHER of Beaverton OR (US) for intel corporation, Rajshree CHABUKSWAR of Sunnyvale CA (US) for intel corporation, Vishwesh MAGODE RUDRAMUNI of Bangalore (IN) for intel corporation, Bharath Kumar VEERA of Portland OR (US) for intel corporation, Joseph ALBERTS of Aloha OR (US) for intel corporation, Madhusudan CHIDAMBARAM of Bangalore (IN) for intel corporation, Zhongsheng WANG of Camas WA (US) for intel corporation, Preeti AGARWAL of Portland OR (US) for intel corporation, Praveen Kumar GUPTA of Santa Clara CA (US) for intel corporation
IPC Code(s): G06F9/48
CPC Code(s): G06F9/4893
Abstract: an apparatus and method are described for intelligently scheduling threads across a plurality of logical processors. for example, one embodiment of a processor comprises: a plurality of cores and power management circuitry to associate a plurality of performance values and a plurality of efficiency values with the plurality of cores. in some implementations, each core is associated with at least one performance value and at least one efficiency value. the performance values and efficiency values are used by a scheduler for scheduling threads on the plurality of cores. some implementations include dynamic core configuration hardware logic coupled to or integral to the power management circuitry to resolve a plurality of configuration requests into a consolidated request for updating one or more performance values of the plurality of performance values and/or one or more efficiency values of the plurality of efficiency values.
Inventor(s): Stephen H. Gunther of Beaverton OR (US) for intel corporation, Praveen Kumar Gupta of Santa Clara CA (US) for intel corporation
IPC Code(s): G06F9/48
CPC Code(s): G06F9/4893
Abstract: embodiments described herein may include apparatus, systems, techniques, and/or processes that are directed to computing systems with heterogenous processing engines. the heterogenous processing engines may have differing capabilities that change dynamically during system operation due, for example, to changing power budgets, frequencies, voltages, and the like of each processing engine. by dynamically exposing and updating the run-time capability of each processing engine based on current operational conditions, the operating system or system software may select the optimal processing engine for a given task, thereby providing more performance, power efficiencies, and better experience to the user.
Inventor(s): Madhusudan Chidambaram of Bangalore (IN) for intel corporation, Efraim Rotem of Haifa (IL) for intel corporation, Stephen H. Gunther of Beaverton OR (US) for intel corporation, Rajshree Chabukswar of Sunnyvale CA (US) for intel corporation, Zhongsheng Wang of Camas WA (US) for intel corporation
IPC Code(s): G06F9/48, G06F9/50
CPC Code(s): G06F9/4893
Abstract: embodiments herein relate to selecting cores in a processor using a core mask. in one aspect, a computing device includes different types of cores arranged in one or more processors. the core types are different in terms of performance and power consumption. a core mask is provided which indicates the number of cores which are selected to be active for each core type. a driver can receive a gear setting, which represents a first preference for higher performance or reduced power consumption. a slider value, which represents a second preference for higher performance or reduced power consumption, is provided based on the gear setting and a core utilization percentage and/or foreground activity percentage. a core mask is selected based on the slider value and the current workload type. the first preference can guide, without dictating, a decision of which cores are selected.
Inventor(s): Andrew J. Herdrich of Hillsboro OR (US) for intel corporation, Philip Abraham of Beaverton OR (US) for intel corporation, Priya Autee of Chandler AZ (US) for intel corporation, Stephen Van Doren of Portland OR (US) for intel corporation, Yen-Cheng Liu of Portland OR (US) for intel corporation, Rajesh Sankaran of Portland OR (US) for intel corporation, Kameswar Subramaniam of Austin TX (US) for intel corporation, Ritesh Parikh of San Jose CA (US) for intel corporation
IPC Code(s): G06F9/50, G06F9/30
CPC Code(s): G06F9/5016
Abstract: techniques for region-aware memory bandwidth allocation control are described. in an embodiment, an apparatus includes a processing core and control circuitry. the processing core is to execute a plurality of threads. the control circuitry is to control use of memory bandwidth per memory region and per thread.
Inventor(s): Mario Flajslik of Hudson MA (US) for intel corporation, James Dinan of Hopkinton MA (US) for intel corporation
IPC Code(s): G06F9/54, G06F9/52
CPC Code(s): G06F9/544
Abstract: systems, apparatuses and methods may provide for detecting an outbound communication and identifying a context of the outbound communication. additionally, a completion status of the outbound communication may be tracked relative to the context. in one example, tracking the completion status includes incrementing a sent messages counter associated with the context in response to the outbound communication, detecting an acknowledgement of the outbound communication based on a network response to the outbound communication, incrementing a received acknowledgements counter associated with the context in response to the acknowledgement, comparing the sent messages counter to the received acknowledgements counter, and triggering a per-context memory ordering operation if the sent messages counter and the received acknowledgements counter have matching values.
20240330092. REPORTING OF ERRORS IN PACKET PROCESSING_simplified_abstract_(intel corporation)
Inventor(s): Jonathan KENNY of Ballina (IE) for intel corporation, Andrew CUNNINGHAM of Ennis (IE) for intel corporation, Peter WALDRON of Shannon (IE) for intel corporation, Jacqueline KEARNEY of Shannon (IE) for intel corporation, Hugh McCARTHY of Shannon (IE) for intel corporation
IPC Code(s): G06F11/07
CPC Code(s): G06F11/0772
Abstract: examples described herein relate to a network interface device that includes: a host interface; a direct memory access (dma) circuitry; a network interface; and circuitry that is configured to: based on a configuration, detect an error in an accelerator from processing data associated with a packet received by the network interface; based on detection of the error from processing associated with the data, provide, in-band, a notification via a second packet for delivery to a computing system coupled to the network interface device, wherein the notification is indicative of telemetry associated with the error and a time stamp associated with the error; and based on non-detection of the error from processing the packet, update state associated with a flow of the packet.
20240330146. SNAPSHOTTING OF PERFORMANCE MONITORING_simplified_abstract_(intel corporation)
Inventor(s): Moshe Cohen of Zichron Yaakov (IL) for intel corporation, Ahmad Yasin of Haifa (IL) for intel corporation
IPC Code(s): G06F11/34
CPC Code(s): G06F11/3495
Abstract: techniques for snapshotting of performance monitoring are described. in an embodiment, an apparatus includes a plurality of performance monitoring hardware resources, hardware to capture a record of state data related to state of the apparatus in connection with an occurrence of an event, and storage to store a first indicator corresponding to at least a first performance monitoring hardware resource of the plurality of performance monitoring hardware resources and to enable the hardware to include, in the record, performance data from the first performance monitoring hardware resource.
Inventor(s): Ravishankar Subramanian of Bangalore (IN) for intel corporation, Venkataramani Gopalakrishnan of Folsom CA (US) for intel corporation, Yaniv Hayat of Herzliya (IL) for intel corporation, Reuven Rozic of Binyamina (IL) for intel corporation
IPC Code(s): G06F13/12, G06F13/38, G06F13/42
CPC Code(s): G06F13/12
Abstract: embodiments herein relate to reducing the power consumption of a serial link such as peripheral component interconnect express (pcie) link. the link may extend between a system-on-a-chip (soc) or other circuit and a universal serial bus (usb4) host in a computing device. the usb4 host includes a pcie switch which connects lanes of the link to adapters in a usb4 router, such as a usb3 adapter, a pcie adapter, a host interface adapter and a displayport adapter. the available bandwidth of the link can be adjusted based on a measured data rate. for example, the data rate can be compared to one or more thresholds. in one approach, the data rate is based on downstream transmissions, from the soc to the usb4 host. a transmitter clock rate can be adjusted to adjust the bandwidth and reduce power consumption.
Inventor(s): Akhilesh S. THYAGATURU of Ruskin FL (US) for intel corporation, Stanley MO of Portland OR (US) for intel corporation, Jason M. HOWARD of Portland OR (US) for intel corporation, Sanjaya TAYAL of Portland OR (US) for intel corporation, Nicholas ROSS of Lake Forest CA (US) for intel corporation
IPC Code(s): G06F13/28
CPC Code(s): G06F13/28
Abstract: examples described herein relate to a network interface device that includes a direct memory access (dma) circuitry; a network interface; at least two host interfaces to simultaneously connect to multiple platforms; an interface to a memory device; and circuitry. in some examples, at least two of the multiple platforms include a processor and a memory coupled to a circuit board. in some examples, the circuitry is to: based on a level of security classification of a second platform of the multiple platforms, perform secure transfer of data from a first platform of the multiple platforms to the second platform of the multiple platforms and enforce rules for data access and data transfer by the multiple platforms.
Inventor(s): Rajaram Regupathy of Bangalore (IN) for intel corporation, Reuven Rozic of Binyamina (IL) for intel corporation, Dmitriy Berchanskiy of Rocklin CA (US) for intel corporation, Nirmala Bailur of Bangalore (IN) for intel corporation, Vrukesh V. Panse of Bangalore (IN) for intel corporation, Saranya Gopal of Bangalore (IN) for intel corporation
IPC Code(s): G06F13/42, G06F13/38
CPC Code(s): G06F13/4282
Abstract: a data scaling module for usb4 that embodies display driver (dd) and connection manager (cm) operations. periodic and aperiodic transfer requests are monitored. the periodic bw activity on periodic peripherals, such as display panels (dps) is monitored, and determinations as to reduced periodic activity on a dp are made. responsive to receiving a high aperiodic bandwidth request, the original refresh rate for the dp is reduced. the newly freed usb4 bw is provided for the aperiodic task. at completion of the aperiodic task, the dd increases the refresh rate to its original value.
Inventor(s): Jianwei DAI of Portland OR (US) for intel corporation,, Somvir Singh DAHIYA of Hillsboro OR (US) for intel corporation,, Mahesh KUMAR P of Bangalore (IN) for intel corporation,, Stephen H. GUNTHER of Beaverton OR (US) for intel corporation,, Sapumal WIJERATNE of Portland OR (US) for intel corporation,, Mark GALLINA of Hillsboro OR (US) for intel corporation,
IPC Code(s): G06F15/78
CPC Code(s): G06F15/7814
Abstract: an apparatus and method for temperature-constrained frequency control and scheduling. for example, one embodiment of a processor comprises: a plurality of cores; power management circuitry to control a frequency of each core of the plurality of cores based, at least in part, on a temperature associated with one or more cores of the plurality of cores, the power management circuitry comprising: a temperature limit-driven frequency controller to determine a first frequency limit value based on a temperature of a corresponding core reaching a first threshold; frequency prediction hardware logic to predict a temperature-constrained frequency of the corresponding core based on the first frequency limit value and an initial frequency limit value; and performance determination hardware logic to determine a new performance value for the corresponding core based on the temperature-constrained frequency, the new performance value to be provided to a task scheduler.
Inventor(s): Omid Azizi of Redwood City CA (US) for intel corporation
IPC Code(s): G06F17/16, G06F9/30, G06F9/38, G06N20/00
CPC Code(s): G06F17/16
Abstract: this disclosure relates matrix operation acceleration for different matrix sparsity patterns. a matrix operation accelerator may be designed to perform matrix operations more efficiently for a first matrix sparsity pattern rather than for a second matrix sparsity pattern. a matrix with the second sparsity pattern may be converted to a matrix with the first sparsity pattern and provided to the matrix operation accelerator. by rearranging the rows and/or columns of the matrix, the sparsity pattern of the matrix may be converted to a sparsity pattern that is suitable for computation with the matrix operation accelerator.
Inventor(s): Scott Douglas Constable of Portland OR (US) for intel corporation, Marcin Andrzej Chrapek of Zurich (CH) for intel corporation, Marcin Spoczynski of Hillsboro OR (US) for intel corporation, Cory Cornelius of Portland OR (US) for intel corporation, Mona Vij of Hillsboro OR (US) for intel corporation, Anjo Lucas Vahldiek-Oberwagner of Berlin (DE) for intel corporation
IPC Code(s): G06F21/57
CPC Code(s): G06F21/57
Abstract: methods, apparatus, systems, and articles of manufacture to verify integrity of a model are disclosed. an example apparatus includes programmable circuitry to initialize an instance of a trusted execution environment; upload a security manifest of the trusted execution environment and a machine learning model; determine whether to store the machine learning model into a memory based on checking of the security manifest; determine whether the machine learning model is valid; and output a validation result.
Inventor(s): Benjamin Gras of Naarden (NL) for intel corporation, Daniël Trujillo of Zurich (CH) for intel corporation
IPC Code(s): G06F30/3308, G06F30/327
CPC Code(s): G06F30/3308
Abstract: embodiments described herein are generally directed to detecting security issues in a hardware design using ift. in an example, dataflows are tracked within a hardware design represented in an hdl without instrumenting the hdl. dataflow primitives are received specifying taint sources from which the dataflows are to be tracked. a baseline simulation trace log is obtained for a baseline rtl simulation of the hardware design by causing a simulator to perform the baseline rtl simulation during which none of the taint sources are altered. injection simulation trace logs are obtained for injection rtl simulations by causing the simulator to perform an injection rtl simulation, for each taint source, during which the taint source is altered. the dataflows are then identified based on comparisons between the baseline and the injection simulation trace logs. a potential security issue is detected within the hardware design by applying a policy to the dataflows.
Inventor(s): Raghavendra Vasappanavara of Folsom CA (US) for intel corporation, Srinivasa R Stg of Bangalore (IN) for intel corporation, Narendra Nimmagadda of Bangalore (IN) for intel corporation, Fadi Aboud of Nazareth (IL) for intel corporation
IPC Code(s): G06F30/392
CPC Code(s): G06F30/392
Abstract: methods, apparatus, systems, and articles of manufacture are disclosed to group design stages in design space optimization of semiconductor design for tool agnostic design flows. an example apparatus is to parse a file to identify a first design stage and a second design stage of a design flow, the first design stage and the second design stage corresponding to a class of design stages. additionally, the example apparatus is to generate, based on a dictionary file, a group of operations to perform the first design stage and the second design stage, the dictionary file associated with the first design stage and the second design stage. the example apparatus is also to generate adjusted parameters for experimenting on the class of design stages, the adjusted parameters based on the group of operations. additionally, the example apparatus is to generate instructions based on the group of operations and the adjusted parameters.
Inventor(s): Florian Luethi of Portland OR (US) for intel corporation, Hubert C. George of Portland OR (US) for intel corporation, Felix Frederic Leonhard Borjans of Portland OR (US) for intel corporation, Simon Schaal of Hillsboro OR (US) for intel corporation, Lester Lampert of Portland OR (US) for intel corporation, Thomas Francis Watson of Portland OR (US) for intel corporation, Jeanette M. Roberts of North Plains OR (US) for intel corporation, Jong Seok Park of Hillsboro OR (US) for intel corporation, Sushil Subramanian of Hillsboro OR (US) for intel corporation, Stefano Pellerano of Beaverton OR (US) for intel corporation
IPC Code(s): G06N10/00, H01L29/12
CPC Code(s): G06N10/00
Abstract: an array of quantum dot qubits (e.g., an array of spin qubits) relies on a gradient magnetic field to ensure that the qubits are separated in frequency in order to be individually addressable. furthermore, a strong magnetic field gradient is required to electrically drive the electric dipole spin resonance (edsr) of the qubits. quantum dot devices disclosed herein use microcoil arrangements for providing a gradient magnetic field, the microcoil arrangements integrated on the same chip (e.g., on the same die or wafer) as quantum dot qubits themselves. unlike previous approaches to quantum dot formation and manipulation, various embodiments of the quantum dot devices disclosed herein may enable improved control over magnetic fields and their gradients to realize better frequency targeting of individual qubits, help minimize adverse effects of charge noise on qubit decoherence and provide good scalability in the number of quantum dots included in the device.
Inventor(s): Ronald Tadao Azuma of San Jose CA (US) for intel corporation, Horst Werner Haussecker of Palo Alto CA (US) for intel corporation
IPC Code(s): G06T3/00, G06F3/01, G06F3/0346, G06T19/00, H04L65/1089, H04L65/80
CPC Code(s): G06T3/16
Abstract: methods, systems, apparatus, and articles of manufacture to produce immersive videos are disclosed. an example apparatus includes programmable circuitry to access a first video stream corresponding to a scene, the first video stream including a first video frame, the first video frame including a first tile representative of the scene from a first viewpoint and a second tile representative of the scene from a second viewpoint different from the first viewpoint, access a second video stream corresponding to the scene, the first video stream including a second video frame, the second video frame including a third tile representative of the scene from a third viewpoint and a fourth tile representative of the scene from a fourth viewpoint different from the third viewpoint, and select at least one of the first tile, the second tile, the third tile, or the fourth tile for presentation by a device.
Inventor(s): James Holland of Folsom CA (US) for intel corporation, Muhammad Hamdan of Palo Alto CA (US) for intel corporation, Timothy Chong of Palo Alto CA (US) for intel corporation, Lidong Xu of Beijing (CN) for intel corporation, Yang Zhou of Beijing (CN) for intel corporation
IPC Code(s): G06T7/246
CPC Code(s): G06T7/248
Abstract: systems, apparatus, articles of manufacture, and methods are disclosed to determine confidence of motion vectors. examples disclosed herein are to generate feature data associated with a motion vector, the motion vector generated based on a first block of pixel data in a first video frame and a second block of pixel data in a second video frame, determine a confidence score for the motion vector based on a model and the feature data, and concatenate the motion vector and the confidence score to output an estimated likelihood that the motion vector is accurate.
Inventor(s): Lidan Zhang of Beijing (CN) for intel corporation, Qianying Zhu of Beijing (CN) for intel corporation, Xiangbin Wu of Beijing (CN) for intel corporation, Xinxin Zhang of Beijing (CN) for intel corporation, Fei Li of Beijing (CN) for intel corporation
IPC Code(s): G06T7/80, G06T7/50, G06V10/26, G06V10/82, G06V20/56, G06V20/58
CPC Code(s): G06T7/80
Abstract: methods, apparatus, systems and articles of manufacture are disclosed for scale recovery from monocular video. an example non-transitory computer readable medium comprises instructions that, when executed, cause a machine to at least segment an input image from a monocular video to detect an object in the camera field, estimate camera parameters from the segmented input image, iteratively refine the estimated camera parameters using known object heights, calculate a scale for the video, iteratively refine the scale based on a user input, and report the scaling results for visualization.
Inventor(s): Yurong Chen of Beijing (CN) for intel corporation, Anbang Yao of Beijing (CN) for intel corporation, Ming Lu of Beijing (CN) for intel corporation, Dongqi Cai of Beijing (CN) for intel corporation, Xiaolong Liu of Beijing (CN) for intel corporation
IPC Code(s): G06V10/82
CPC Code(s): G06V10/82
Abstract: methods and apparatus to perform parallel double-batched self-distillation in resource-constrained image recognition environments are disclosed herein. example apparatus disclosed herein are to identify a source data batch and an augmented data batch, the augmented data generated based on at least one data augmentation technique. disclosed example apparatus is also to share one or more parameters between a student neural network corresponding to the source data batch and a teacher neural network corresponding to the augmented data batch, the one or more parameters including one or more convolution layers to be shared between the teacher neural network and the student neural network. disclosed example apparatus is further to align knowledge corresponding to the teacher neural network and the student neural network, the knowledge corresponding to the one or more parameters shared between the student neural network and the teacher neural network.
20240331705. METHODS AND APPARATUS TO MODEL SPEAKER AUDIO_simplified_abstract_(intel corporation)
Inventor(s): Michal Karzynski of Gdynia (PL) for intel corporation, Adam Kupryjanow of Gdansk (PL) for intel corporation, Srikanth Potluri of Folsom CA (US) for intel corporation
IPC Code(s): G10L17/04
CPC Code(s): G10L17/04
Abstract: methods, apparatus, systems, and articles of manufacture are disclosed. an example apparatus includes: interface circuitry; instructions; and programmable circuitry to at least one of execute or instantiate the instructions to: calculate a sample embedding vector that characterizes a speaker based on a first audio signal; perform a first update of a personal embedding vector based on the sample embedding vector, the updated personal embedding vector to characterize the speaker based on a second audio signal and the first audio signal, and perform a second update of the personal embedding vector based on the first update and a universal embedding vector.
Inventor(s): Charles Augustine of Portland OR (US) for intel corporation, Amlan Ghosh of Mebane NC (US) for intel corporation, Seenivasan Subramaniam of Hillsboro OR (US) for intel corporation, Patrick Morrow of Portland OR (US) for intel corporation, Muhammad M. Khellah of Tigard OR (US) for intel corporation, Feroze Merchant of Austin TX (US) for intel corporation
IPC Code(s): G11C11/4096, G11C11/4093, G11C11/4094
CPC Code(s): G11C11/4096
Abstract: an apparatus includes a first write bit line (wbl), a first p-channel metal oxide semiconductor (pmos) transistor including a source coupled to the wbl, a first inverter including an input coupled to a drain of the first pmos transistor, and a second pmos transistor including a source coupled to an output of the first inverter. the first pmos transistor and the second pmos transistor are disposed in at least one pmos layer configured between a first metal layer and a second metal layer. the register file circuit further includes a first via connecting a gate of the first pmos transistor and a gate of the second pmos transistor in the at least one pmos layer to the first metal layer.
20240331921. ELECTRONIC SUBSTRATES HAVING EMBEDDED INDUCTORS_simplified_abstract_(intel corporation)
Inventor(s): Benjamin Duong of Phoenix AZ (US) for intel corporation, Michael Garelick of Chandler AZ (US) for intel corporation, Darko Grujicic of Chandler AZ (US) for intel corporation, Tarek Ibrahim of Mesa AZ (US) for intel corporation, Brandon C. Marin of Chandler AZ (US) for intel corporation, Sai Vadlamani of Chandler AZ (US) for intel corporation, Marcel Wall of Phoenix AZ (US) for intel corporation
IPC Code(s): H01F27/28, H01F41/32, H01L23/498, H01L23/64
CPC Code(s): H01F27/2804
Abstract: an electronic substrate may be fabricated by forming a base substrate and forming an inductor extending through the base substrate, wherein the inductor includes a magnetic material layer and a barrier layer, such that the barrier layer prevents the magnetic material layer from leaching into plating solutions during the fabrication of the electronic substrate. in one embodiment, the barrier material may comprise titanium. in another embodiment, the barrier layer may comprise a polymeric material. in still another embodiment, the barrier layer may comprise a nitride material layer. the inductor may further include a plating seed layer on the barrier layer and a conductive fill material abutting the plating seed layer.
Inventor(s): Ehren MANNEBACH of Tigard OR (US) for intel corporation, Shaun MILLS of Hillsboro OR (US) for intel corporation, Joseph D’SILVA of Hillsboro OR (US) for intel corporation, Mauro J. KOBRINSKY of Portland OR (US) for intel corporation
IPC Code(s): H01L21/768, H01L21/8234, H01L23/528
CPC Code(s): H01L21/76808
Abstract: embodiments described herein may be related to apparatuses, processes, systems, and/or techniques for forming a package that has a transistor layer with a front side metal interconnect layer and a back side metal contact and interconnect layer. in particular, back side metal contact and interconnect layers may be patterned before a transistor layer, or other device layer, is formed on the patterned layers and before front side metal interconnect layers are formed on the transistor layer. other embodiments may be described and/or claimed.
Inventor(s): Alireza Narimannezhad of Hillsboro OR (US) for intel corporation, Vladislav Kamysbayev of Hillsboro OR (US) for intel corporation, Xiaoye Qin of Portland OR (US) for intel corporation, Sunzida Ferdous of Portland OR (US) for intel corporation, Reken Patel of Portland OR (US) for intel corporation
IPC Code(s): H01L21/768, C23C16/40, C23C16/455, C23C16/50, H01L21/02, H01L23/532
CPC Code(s): H01L21/76834
Abstract: a low-leakage oxide dielectric material with high elastic modulus is deposited directly upon an oxidizable feature with a polycyclic pe-ald process that limits the formation of an oxide on the feature. a precursor of one or more constituents, such as silicon, may be deposited upon a workpiece during a deposition phase, and the absorbed precursor(s) may be oxidized during a first oxidation phase under more conservative conditions until a first film thickness is achieved. subsequently, absorbed precursor(s) may be oxidized during a second oxidation phase under more aggressive conditions to arrive at a total film thickness. transistor contact metal, which may provide local interconnection between source or drain terminals of multiple transistors, may maintain high electrical conductivity after being electrically insulated with such a low-leakage film.
Inventor(s): Shaun MILLS of Hillsboro OR (US) for intel corporation, Ehren MANNEBACH of Tigard OR (US) for intel corporation, Mauro J. KOBRINSKY of Portland OR (US) for intel corporation
IPC Code(s): H01L21/768, H01L23/48
CPC Code(s): H01L21/76898
Abstract: integrated circuit structures having backside gate connection are described. in an example, an integrated circuit structure includes a plurality of horizontally stacked nanowires or a fin. a gate stack is over the plurality of horizontally stacked nanowires or the fin. an epitaxial source or drain structure is at an end of the plurality of horizontally stacked nanowires or the fin. a conductive gate-to-contact connection is vertically beneath the epitaxial source or drain structure and vertically beneath and in electrical contact with the gate stack.
Inventor(s): Reza Bayati of Portland OR (US) for intel corporation, Swapnadip Ghosh of Hillsboro OR (US) for intel corporation, Chiao-Ti Huang of Portland OR (US) for intel corporation, Matthew Prince of Portland OR (US) for intel corporation, Jeffrey Miles Tan of Hillsboro OR (US) for intel corporation, Ramy Ghostine of Portland OR (US) for intel corporation, Anupama Bowonder of Portland OR (US) for intel corporation
IPC Code(s): H01L21/8234, H01L21/3213, H01L27/088, H01L29/06, H01L29/423, H01L29/66, H01L29/775
CPC Code(s): H01L21/823456
Abstract: one or more transistors may have gate structures with differing sidewall slopes. the gate structures may be over stacks of channel regions in nanosheets (or nanoribbons or nanowires), and the differing gate profiles may correspond to differing electrical characteristics. transistors with metal gate structures may be tuned by strategically etching the gate structures, for example, using lower etch powers, higher etch temperatures, and/or longer etch durations, to achieve substantially vertical gate profiles.
Inventor(s): Pratyush Mishra of Tempe AZ (US) for intel corporation, Marcel Wall of Phoenix AZ (US) for intel corporation, Sashi Kandanur of Chandler AZ (US) for intel corporation, Pooya Tadayon of Portland OR (US) for intel corporation, Srinivas Pietambaram of Chandler AZ (US) for intel corporation, Benjamin Duong of Phoenix AZ (US) for intel corporation, Suddhasattwa Nad of Chandler AZ (US) for intel corporation
IPC Code(s): H01L23/15, H01F27/24, H01L23/48, H01L23/498, H01L23/522
CPC Code(s): H01L23/15
Abstract: glass-integrated inductors in integrated circuit (ic) packages are disclosed. a disclosed ic package includes a glass layer having an aperture extending therethrough, and an inductor in the aperture, the inductor including a metal core extending through the aperture, the metal core electrically coupled to interconnects on opposite sides of the glass layer, and at least one of a ferrite or a magnetic alloy in the aperture and laterally surrounding the metal core.
Inventor(s): Susmriti Das Mahapatra of Tempe AZ (US) for intel corporation, Malavarayan Sankarasubramanian of Chandler AZ (US) for intel corporation, Shenavia Howell of Chandler AZ (US) for intel corporation, John Harper of Chandler AZ (US) for intel corporation, Mitul Modi of Phoenix AZ (US) for intel corporation
IPC Code(s): H01L23/36, H01L21/48, H01L21/50, H01L21/60, H01L21/768, H01L23/00, H01L23/367, H01L23/373, H01L23/42, H01L23/488
CPC Code(s): H01L23/36
Abstract: an integrated circuit (ic) package comprising a die having a front side and a back side. a solder thermal interface material (stim) comprising a first metal is over the backside. the tim has a thermal conductivity of not less than 40 w/mk; and a die backside material (dbm) comprising a second metal over the stim, wherein the dbm has a cte of not less than 18�10m/mk, wherein an interface between the stim and the dbm comprises at least one intermetallic compound (imc) of the first metal and the second metal.
Inventor(s): Chun Keang Ooi of Lunes (MY) for intel corporation
IPC Code(s): H01L23/367, H01L23/00
CPC Code(s): H01L23/3675
Abstract: an electronic device and associated methods are disclosed. in one example, the electronic device includes a thermal interface material between a heat spreader and a semiconductor die. in selected examples, the thermal interface material includes a liquid metal, and the heat spreader includes a top opening that is used to introduce the thermal interface material to a space between the die and the heat spreader.
20240332125. 2D FILLERS FOR REDUCED CTE FOR PID_simplified_abstract_(intel corporation)
Inventor(s): Kyle ARRINGTON of Gilbert AZ (US) for intel corporation, Clay ARRINGTON of Queen Creek AZ (US) for intel corporation, Bohan SHAN of Chandler AZ (US) for intel corporation, Haobo CHEN of Gilbert AZ (US) for intel corporation, Srinivas V. PIETAMBARAM of Chandler AZ (US) for intel corporation, Gang DUAN of Chandler AZ (US) for intel corporation, Ziyin LIN of Chandler AZ (US) for intel corporation, Hongxia FENG of Chandler AZ (US) for intel corporation, Yiqun BAI of Chandler AZ (US) for intel corporation, Xiaoying GUO of Chandler AZ (US) for intel corporation, Dingying XU of Chandler AZ (US) for intel corporation, Bai NIE of Chandler AZ (US) for intel corporation
IPC Code(s): H01L23/373, H01L21/48, H01L23/24, H01L23/498
CPC Code(s): H01L23/3737
Abstract: embodiments disclosed herein include a package substrate. in an embodiment, the package substrate comprises a first layer and a second layer over the first layer. in an embodiment, the second layer comprises a dielectric material including sulfur. in an embodiment, fillers are within the second layer. in an embodiment, the fillers have a volume fraction that is less than approximately 0.2.
Inventor(s): Andy Wei of Yamhill OR (US) for intel corporation, Po-Yao Ke of Kaohsiung City (TW) for intel corporation, Kai-Chiang Wu of Hsinchu City (TW) for intel corporation, Han-wen Lin of Zhubei City (TW) for intel corporation, Klaus Max Schruefer of Baldham (DE) for intel corporation, Dean Huang of Hsinchu City (TW) for intel corporation, Hsin-Hua Wang of San Jose CA (US) for intel corporation
IPC Code(s): H01L23/373, H01L23/367
CPC Code(s): H01L23/3737
Abstract: thermal dissipation and grounding of integrated circuit (ic) devices with backside power delivery networks are discussed. an ic device layer between frontside and backside interconnect sections, composed mostly of an insulating material, is coupled to a crystalline heat spreader or a metal thermal ground layer by an array of thermal pillars extending through the insulating material. the crystalline heat spreader layer may include one or more thermal sensors, such as thermal sensing diodes, also coupled to the ic device layer by one or more thermal pillars. the ic device layer and crystalline layers are coupled by a hybrid bond, which forms the thermal pillars through a continuous section of the insulating material.
20240332127. ON-PACKAGE EMBEDDED COOLING DEVICE_simplified_abstract_(intel corporation)
Inventor(s): Eng Kwong Lee of Bayan Lepas (MY) for intel corporation, Tin Poay Chuah of Bayan Baru (MY) for intel corporation, Chew Ching Lim of Bayan Lepas (MY) for intel corporation
IPC Code(s): H01L23/38
CPC Code(s): H01L23/38
Abstract: in one embodiment, an integrated circuit package includes an integrated heat spreader (ihs) that incorporates a peltier element. the ihs may include one or more peltier elements, which may be in a top portion of the ihs. the peltier element(s) may be electrically connected to the package substrate through a trace on a sidewall of the ihs.
Inventor(s): Liang He of Chandler AZ (US) for intel corporation, Jung Kyu Han of Chandler AZ (US) for intel corporation, Gang Duan of Chandler AZ (US) for intel corporation
IPC Code(s): H01L23/495, H01L21/768, H01L23/00, H01L23/15, H01L23/528, H01L23/532
CPC Code(s): H01L23/49513
Abstract: methods and apparatus to mitigate electromigration are disclosed. a disclosed example integrated circuit (ic) package includes a dielectric substrate, a contact pad at least partially extending though or positioned on the dielectric substrate, the contact pad including copper, and a metal interconnect coupled to the contact pad, the interconnect including indium.
Inventor(s): Tchefor NDUKUM of Chandler AZ (US) for intel corporation, Yonggang LI of Chandler AZ (US) for intel corporation, Rengarajan SHANMUGAM of Tempe AZ (US) for intel corporation, Darko GRUJICIC of Chandler AZ (US) for intel corporation, Deniz TURAN of Chandler AZ (US) for intel corporation
IPC Code(s): H01L23/498, H01L21/48, H01L23/15
CPC Code(s): H01L23/49838
Abstract: embodiments disclosed herein include electronic packages. in an embodiment, the electronic package comprises a substrate and a seed layer over the substrate. in an embodiment, sidewalls of the seed layer are sloped. in an embodiment, the electronic package further comprises a feature over the seed layer, where the feature is electrically conductive.
Inventor(s): Jianyong Mo of Chandler AZ (US) for intel corporation, Jason Michael Gamba of Gilbert AZ (US) for intel corporation, Liang Zhang of Chandler AZ (US) for intel corporation
IPC Code(s): H01L23/498, H01L21/48, H01L23/00, H01L23/48, H01L23/538, H01L25/065
CPC Code(s): H01L23/49838
Abstract: substrates with a glass core and glass buildup layers, and methods of forming the same, are described herein. in one example, a substrate includes a glass core, glass layers above and below the glass core, conductive traces in the glass core and at least some of the glass layers, and conductive contacts on a surface of the substrate.
20240332166. INTEGRATED CIRCUIT STRUCTURES HAVING AIR GAPS_simplified_abstract_(intel corporation)
Inventor(s): Seda CEKLI of Portland OR (US) for intel corporation, Sudipto NASKAR of Portland OR (US) for intel corporation, Ananya DUTTA of Portland OR (US) for intel corporation, Supanee SUKRITTANON of North Plains OR (US) for intel corporation, Akshit PEER of Hillsboro OR (US) for intel corporation, Navneethakrishnan SALIVATI of Hillsboro OR (US) for intel corporation, Jeffery BIELEFELD of Forest Grove OR (US) for intel corporation, Makram ABD EL QADER of Hillsboro OR (US) for intel corporation, Mauro J. KOBRINSKY of Portland OR (US) for intel corporation, Sachin VAIDYA of Portland OR (US) for intel corporation
IPC Code(s): H01L23/522, H01L21/768, H01L23/532
CPC Code(s): H01L23/5226
Abstract: integrated circuit structures having air gaps are described. in an example, an integrated circuit structure includes alternating conductive lines and air gaps above a first dielectric layer. a dielectric structure is between adjacent ones of the conductive lines and over the air gaps. a first etch stop layer is on the dielectric structure but not on the conductive lines. a second etch stop layer is on the first etch stop layer and on the conductive lines. a second dielectric layer is above the second etch stop layer. a conductive via structure is in the second dielectric layer, in the second etch stop layer, and on one of the conductive lines.
Inventor(s): Ehren MANNEBACH of Tigard OR (US) for intel corporation, Shaun MILLS of Hillsboro OR (US) for intel corporation, Joseph D’SILVA of Hillsboro OR (US) for intel corporation, Mauro J. KOBRINSKY of Portland OR (US) for intel corporation, Makram ABD El QADER of Hillsboro OR (US) for intel corporation
IPC Code(s): H01L23/528, H01L29/423
CPC Code(s): H01L23/528
Abstract: integrated circuit structures having backside contact widening are described. in an example, an integrated circuit structure includes a plurality of horizontally stacked nanowires. a gate stack is over the plurality of horizontally stacked nanowires. an epitaxial source or drain structure is at an end of the plurality of horizontally stacked nanowires. a conductive gate contact is vertically beneath and in contact with a bottom of the gate stack. the conductive gate contact is in a cavity in an isolation layer, the cavity extending beyond the gate stack in a direction parallel with the epitaxial source or drain structure, and the cavity confined to the gate stack in a direction toward the epitaxial source or drain structure.
20240332175. BACKSIDE TRANSISTOR CONTACT SURROUNDED BY OXIDE_simplified_abstract_(intel corporation)
Inventor(s): Joseph D’SILVA of Hillsboro OR (US) for intel corporation, Ehren MANNEBACH of Tigard OR (US) for intel corporation, Mauro J. KOBRINSKY of Portland OR (US) for intel corporation
IPC Code(s): H01L23/528, H01L21/8238, H01L27/092, H01L29/06, H01L29/423, H01L29/66, H01L29/775, H01L29/78, H01L29/786
CPC Code(s): H01L23/5283
Abstract: embodiments described herein may be related to apparatuses, processes, systems, and/or techniques for forming backside contacts on a transistor structure by forming, during front-side processing, trenches through the transistor structure into a silicon wafer, and then, using a catalytic oxidant material that is subsequently removed, forming an oxide structure in the silicon wafer around the trenches to isolate the backside gate contact from the source/drain trenches. other embodiments may be described and/or claimed.
Inventor(s): Lijiang Wang of Chandler AZ (US) for intel corporation, Sujit Sharan of Chandler AZ (US) for intel corporation
IPC Code(s): H01L23/538
CPC Code(s): H01L23/5381
Abstract: in one embodiment, an interconnect bridge circuitry includes a first set of bridge-to-die electrical connectors in a first region of the circuitry, a second set of bridge-to-die electrical connectors in a second region of the circuitry, and an interconnection between a bridge-to-die connector of the first set and a bridge-to-die connector of the second set. the interconnection is in a third region of the circuitry between the first region and the second region, and includes a first trace connected to the bridge-to-die electrical connector of the first set, a second trace connected to the bridge-to-die electrical connector of the second set, the second trace parallel with the first trace, and a third trace connected between the first trace and the second trace.
Inventor(s): Naiya SOETAN-DODD of Mesa AZ (US) for intel corporation, Srinivas V. PIETAMBARAM of Chandler AZ (US) for intel corporation, Suddhasattwa NAD of Chandler AZ (US) for intel corporation, Brandon C. MARIN of Gilbert AZ (US) for intel corporation, Sheng C. LI of Gilbert AZ (US) for intel corporation, Liwei CHENG of Chandler AZ (US) for intel corporation
IPC Code(s): H01L23/538
CPC Code(s): H01L23/5384
Abstract: embodiments disclosed herein include an electronic package. in an embodiment, the electronic package comprises a core, where the core comprises glass. in an embodiment, a cavity is in the core, and a bridge is in the cavity. in an embodiment, the bridge comprises through substrate vias (tsvs). in an embodiment, pads are at a bottom of the cavity, where the tsvs are electrically coupled to the pads.
Inventor(s): Robert Alan MAY of Chandler AZ (US) for intel corporation, Islam A. SALAMA of Chandler AZ (US) for intel corporation, Sri Ranga Sai BOYAPATI of Chandler AZ (US) for intel corporation, Sheng LI of Gilbert AZ (US) for intel corporation, Kristof DARMAWIKARTA of Chandler AZ (US) for intel corporation, Robert L. SANKMAN of Phoenix AZ (US) for intel corporation, Amruthavalli Pallavi ALUR of Tempe AZ (US) for intel corporation
IPC Code(s): H01L23/538, H01L21/56, H01L21/683, H01L23/00, H01L23/31, H01L25/065, H01L25/07, H01L25/11
CPC Code(s): H01L23/5389
Abstract: a microelectronic device is formed to include an embedded die substrate on an interposer; where the embedded die substrate is formed with no more than a single layer of transverse routing traces. in the device, all additional routing may be allocated to the interposer to which the embedded die substrate is attached. the embedded die substrate may be formed with a planarized dielectric formed over an initial metallization layer supporting the embedded die.
Inventor(s): Archanna Srinivasan of San Jose CA (US) for intel corporation, Guang Chen of Fremont CA (US) for intel corporation
IPC Code(s): H01L23/64, H01L23/498, H01L25/16
CPC Code(s): H01L23/642
Abstract: an electronic device and associated methods are disclosed. in one example, the electronic device includes plurality of metal-insulator-metal capacitor units and a control circuit to dynamically select different amounts of the plurality of metal-insulator-metal capacitor units in correlation to a type of operation in a semiconductor die.
Inventor(s): Vivek Chidambaram of Singapore (SG) for intel corporation, Jonathan Burk of Portland OR (US) for intel corporation, Zhihua Zou of Chandler AZ (US) for intel corporation
IPC Code(s): H01L23/00, H01L23/538, H01L25/065
CPC Code(s): H01L24/16
Abstract: disclosed herein are microelectronic assemblies with direct bonding using nanotwinned copper (ntc). an example microelectronic assembly may include a first microelectronic component and a second microelectronic component coupled to the first microelectronic component by a direct bonding (db) region, wherein the db region includes a db contact comprising a first portion and a second portion having different microstructures. the first portion is between the first microelectronic component and the second portion. the second portion is between the first portion and the second microelectronic component. in some implementations, the first portion has non-columnar microstructure, and the second portion has columnar microstructure. in some implementations, less than about 40% of grains of the first portion have ac <111> orientation, and at least about 50% of grains of the second portion have the <111> orientation. in some embodiments, the first portion includes pcc or fgc, and the second portion includes ntc.
Inventor(s): Min Suet LIM of Gelugor (MY) for intel corporation, Kavitha NAGARAJAN of Bangalore (IN) for intel corporation, Stephan STOECKL of Schwandorf (DE) for intel corporation, Eng Huat GOH of Ayer Itam (MY) for intel corporation
IPC Code(s): H01L25/065, H01L23/00, H01L23/498
CPC Code(s): H01L25/0652
Abstract: embodiments disclosed herein include electronic packages. in an embodiment, the electronic package comprises a substrate with a first surface and a second surface opposite from the first surface. in an embodiment, a plurality of first dies are coupled to the first surface of the substrate, and a bump field is on the second surface of the substrate. in an embodiment, the bump field comprises a voided region towards a center of the substrate. in an embodiment, a second die is coupled to the second surface of the substrate, where the second die is provided in the voided region.
Inventor(s): Sukru Yemenicioglu of Portland OR (US) for intel corporation, Abhishek Anil Sharma of Portland OR (US) for intel corporation, Sudipto Naskar of Portland OR (US) for intel corporation, Kalyan C. Kolluru of Portland OR (US) for intel corporation, Chu-Hsin Liang of Santa Cruz CA (US) for intel corporation, Bashir Uddin Mahmud of Portland OR (US) for intel corporation, Van Le of Beaverton OR (US) for intel corporation
IPC Code(s): H01L27/02, H01L21/84, H01L29/66, H01L29/786, H01L29/872, H02H9/04
CPC Code(s): H01L27/0266
Abstract: an integrated circuit device comprising a resistor formed on a non-crystalline substrate, the resistor comprising a gate electrode; a gate dielectric in contact with the gate electrode; a source electrode and a drain electrode; and a thin film transistor tft channel material coupled between the source electrode and the drain electrode.
20240332290. TRANSISTOR WITH CHANNEL-SYMMETRIC GATE_simplified_abstract_(intel corporation)
Inventor(s): Shao-Ming Koh of Tigard OR (US) for intel corporation, Patrick Morrow of Portland OR (US) for intel corporation, Nikhil Mehta of Portland OR (US) for intel corporation, Leonard Guler of Hillsboro OR (US) for intel corporation, Sudipto Naskar of Portland OR (US) for intel corporation, Alison Davis of Portland OR (US) for intel corporation, Dan Lavric of Portland OR (US) for intel corporation, Matthew Prince of Portland OR (US) for intel corporation, Jeanne Luce of Hillsboro OR (US) for intel corporation, Charles Wallace of Portland OR (US) for intel corporation, Cortnie Vogelsberg of Beaverton OR (US) for intel corporation, Rajaram Pai of Lake Oswego OR (US) for intel corporation, Caitlin Kilroy of Hillsboro OR (US) for intel corporation, Jojo Amonoo of Portland OR (US) for intel corporation, Sean Pursel of Tigard OR (US) for intel corporation, Yulia Gotlib of Portland OR (US) for intel corporation
IPC Code(s): H01L27/088, H01L21/033, H01L21/3213, H01L29/06, H01L29/423, H01L29/775
CPC Code(s): H01L27/088
Abstract: transistor structures comprising a gate electrode, or “gate,” that is self-aligned to underlying channel material. a mask material employed for patterning the channel material is further employed to define a cap of mask material having a larger width that protects a portion of gate material during a gate etch. the cap is therefore self-aligned to the channel material so that an amount by which a gate material extends laterally beyond the channel material is ensured to be symmetrical about a centerline of the channel material.
Inventor(s): Abhishek Anil Sharma of Portland OR (US) for intel corporation, Van Le of Beaverton OR (US) for intel corporation, Sudipto Naskar of Portland OR (US) for intel corporation, Sukru Yemenicioglu of Portland OR (US) for intel corporation
IPC Code(s): H01L27/092
CPC Code(s): H01L27/0922
Abstract: an integrated circuit device comprising a plurality of first field effect transistors (fets) formed on a substrate, wherein a first fet comprises a first channel material comprising a portion of the substrate; and a plurality of second fets formed on the substrate, wherein a second fet comprises a second channel material that is different from the first channel material, wherein the second channel material comprises a thin film transistor (tft) channel material.
Inventor(s): Willy RACHMADY of Beaverton OR (US) for intel corporation, Caleb BARRETT of Ridgefield WA (US) for intel corporation, Prashant WADHWA of Portland OR (US) for intel corporation, Chun-Kuo HUANG of Portland OR (US) for intel corporation, Conor P. PULS of Portland OR (US) for intel corporation, Daniel James HARRIS of Beaverton OR (US) for intel corporation, Giorgio MARIOTTINI of Hillsboro OR (US) for intel corporation, Patrick MORROW of Portland OR (US) for intel corporation
IPC Code(s): H01L27/092, H01L21/8238, H01L29/06, H01L29/423, H01L29/66, H01L29/775, H01L29/78, H01L29/786
CPC Code(s): H01L27/0924
Abstract: integrated circuit structures having sub-fin isolation, and methods of fabricating integrated circuit structures having sub-fin isolation, are described. for example, an integrated circuit structure includes a channel structure, and an oxide sub-fin structure over the channel structure, the oxide sub-fin structure including silicon and oxygen and aluminum.
Inventor(s): Joseph D’SILVA of Hillsboro OR (US) for intel corporation, Mauro J. KOBRINSKY of Portland OR (US) for intel corporation, Debaleena NANDI of Hillsboro OR (US) for intel corporation, Ehren MANNEBACH of Tigard OR (US) for intel corporation, Shaun MILLS of Hillsboro OR (US) for intel corporation
IPC Code(s): H01L27/092, H01L29/06, H01L29/417, H01L29/423, H01L29/66, H01L29/775, H01L29/78, H01L29/786
CPC Code(s): H01L27/0924
Abstract: integrated circuit structures having backside conductive source or drain contacts having enhanced contact area, and methods of fabricating integrated circuit structures having backside conductive source or drain contacts having enhanced contact area, are described. for example, an integrated circuit structure includes a sub-fin structure over a vertical stack of horizontal nanowires or a fin. an epitaxial source or drain structure is laterally adjacent to and coupled to the vertical stack of horizontal nanowires or the fin. the epitaxial source or drain structure has a recess within a laterally surrounding outer portion. a conductive source or drain contact is laterally adjacent to the sub-fin structure and is over and in contact with the epitaxial source or drain structure. the conductive source or drain contact is within the recess in the epitaxial source or drain structure.
Inventor(s): Srinivasan Raman of Chandler AZ (US) for intel corporation, Brandon C. Marin of Gilbert AZ (US) for intel corporation, Srinivas Venkata Ramanuja Pietambaram of Chandler AZ (US) for intel corporation, Gang Duan of Chandler AZ (US) for intel corporation, Suddhasattwa Nad of Chandler AZ (US) for intel corporation, Kripa Chauhan of Gilbert AZ (US) for intel corporation
IPC Code(s): H01L27/13, H01L21/84, H01L23/482, H01L25/16, H01L25/18, H01L29/66, H01L29/772
CPC Code(s): H01L27/13
Abstract: an electronic device and associated methods are disclosed. in one example, the electronic device includes an electronic package substrate including a glass core layer and a regulator circuit. a first portion of the circuit components of the regulator circuit is embedded in the glass core layer and a second portion of the circuit components of the regulator circuit is formed on a surface of the glass core layer.
Inventor(s): Xavier F. Brun of Hillsboro OR (US) for intel corporation, Rajesh Surapaneni of Portland OR (US) for intel corporation, Brad S. Hamlin of Portland OR (US) for intel corporation
IPC Code(s): H01L29/06, H01L21/78
CPC Code(s): H01L29/0657
Abstract: microelectronic integrated circuit package structures include a die having a dielectric die edge sidewall and a bulk silicon die edge sidewall, where the bulk silicon die edge sidewall is in substantial alignment with the dielectric die edge sidewall. the bulk silicon die edge sidewall has a plurality of scallop structures along a vertical distance of the bulk silicon die edge sidewall.
Inventor(s): Shaun MILLS of Hillsboro OR (US) for intel corporation, Ehren MANNEBACH of Tigard OR (US) for intel corporation, Mauro J. KOBRINSKY of Portland OR (US) for intel corporation
IPC Code(s): H01L29/417, H01L29/06, H01L29/40, H01L29/423, H01L29/45, H01L29/66, H01L29/775
CPC Code(s): H01L29/41733
Abstract: integrated circuit structures having backside source or drain contact selectivity are described. in an example, an integrated circuit structure includes a first epitaxial source or drain structure at an end of a first plurality of horizontally stacked nanowires or fin, with a first conductive source or drain contact vertically beneath and in contact with a bottom of the first epitaxial source or drain structure, and with a first hardmask material beneath and in contact with the first conductive source or drain contact. a second epitaxial source or drain structure is at an end of a second plurality of horizontally stacked nanowires or fin, with a second conductive source or drain contact vertically beneath and in contact with a bottom of the second epitaxial source or drain structure, and a second hardmask material beneath and in contact with the second conductive source or drain contact.
Inventor(s): Shaun Mills of Hillsboro OR (US) for intel corporation, Ehren Mannebach of Beaverton OR (US) for intel corporation, Mauro Kobrinsky of Portland OR (US) for intel corporation, Kai Loon Cheong of Beaverton OR (US) for intel corporation, Makram Abd El Qader of Hillsboro OR (US) for intel corporation
IPC Code(s): H01L29/417, H01L21/8234, H01L27/088, H01L29/06, H01L29/423, H01L29/775
CPC Code(s): H01L29/41766
Abstract: devices, transistor structures, systems, and techniques are described herein related to backside contacts for field effect transistors formed using a backside contact etch prior to cavity spacer formation. a transistor includes semiconductor structures such as nanoribbons extending between a source and a drain. a spacer material is between a gate and the source/drain as cavity spacer fill. the spacer material is also between a portion of a backside contact and a portion of the source/drain, to eliminate a short between the backside contact and the gate.
Inventor(s): Nicole THOMAS of Portland OR (US) for intel corporation, Michael K. HARPER of Hillsboro OR (US) for intel corporation, Leonard P. GULER of Hillsboro OR (US) for intel corporation, Marko RADOSAVLJEVIC of Portland OR (US) for intel corporation, Thoe MICHAELOS of Portland OR (US) for intel corporation
IPC Code(s): H01L29/423, H01L21/02, H01L21/768, H01L21/8234, H01L29/06
CPC Code(s): H01L29/42392
Abstract: embodiments disclosed herein include semiconductor devices and methods of making such devices. in an embodiment, the semiconductor device comprises a plurality of stacked semiconductor channels comprising first semiconductor channels and second semiconductor channels over the first semiconductor channels. in an embodiment a spacing is between the first semiconductor channels and the second semiconductor channels. the semiconductor device further comprises a gate dielectric surrounding individual ones of the semiconductor channels of the plurality of stacked semiconductor channels. in an embodiment, a first workfunction metal surrounds the first semiconductor channels, and a second workfunction metal surrounds the second semiconductor channels.
Inventor(s): Dan S. LAVRIC of Beaverton OR (US) for intel corporation, Glenn A. GLASS of Portland OR (US) for intel corporation, Thomas T. TROEGER of Portland OR (US) for intel corporation, Suresh VISHWANATH of Portland OR (US) for intel corporation, Jitendra Kumar JHA of Hillsboro OR (US) for intel corporation, John F. RICHARDS of Portland OR (US) for intel corporation, Anand S. MURTHY of Portland OR (US) for intel corporation, Srijit MUKHERJEE of Portland OR (US) for intel corporation
IPC Code(s): H01L29/45, H01L21/28, H01L21/285, H01L29/08, H01L29/161, H01L29/49, H01L29/66, H01L29/78
CPC Code(s): H01L29/45
Abstract: approaches for fabricating an integrated circuit structure including a titanium silicide material, and the resulting structures, are described. in an example, an integrated circuit structure includes a semiconductor fin above a substrate, a gate electrode over the top and adjacent to the sidewalls of a portion of the semiconductor fin. a titanium silicide material is in direct contact with each of first and second epitaxial semiconductor source or drain structures at first and second sides of the gate electrode. the titanium silicide material is conformal with and hermetically sealing a non-flat topography of each of the first and second epitaxial semiconductor source or drain structures. the titanium silicide material has a total atomic composition including 95% or greater stoichiometric tisi.
Inventor(s): David N. GOLDSTEIN of Beaverton OR (US) for intel corporation, David J. TOWNER of Portland OR (US) for intel corporation, Dax M. CRUM of Beaverton OR (US) for intel corporation, Omair SAADAT of Beaverton OR (US) for intel corporation, Dan S. LAVRIC of Beaverton OR (US) for intel corporation, Orb ACTON of Portland OR (US) for intel corporation, Tongtawee WACHARASINDHU of Hillsboro OR (US) for intel corporation, Anand S. MURTHY of Portland OR (US) for intel corporation, Tahir GHANI of Portland OR (US) for intel corporation
IPC Code(s): H01L29/49, H01L27/092, H01L29/06, H01L29/40, H01L29/423, H01L29/66, H01L29/775
CPC Code(s): H01L29/4908
Abstract: gate-all-around integrated circuit structures having a multi-layer molybdenum metal gate stack are described. for example, an integrated circuit structure includes a first vertical arrangement of horizontal nanowires, and a second vertical arrangement of horizontal nanowires. a pmos gate stack is over the first vertical arrangement of horizontal nanowires, the pmos gate stack having a multi-layer molybdenum structure on a first gate dielectric. an nmos gate stack is over the second vertical arrangement of horizontal nanowires, the nmos gate stack having the multi-layer molybdenum structure or an n-type conductive layer on a second gate dielectric.
Inventor(s): Tahir GHANI of Portland OR (US) for intel corporation, Byron HO of Hillsboro OR (US) for intel corporation, Michael L. HATTENDORF of Portland OR (US) for intel corporation, Christopher P. AUTH of Portland OR (US) for intel corporation
IPC Code(s): H01L29/66, H01L21/02, H01L21/033, H01L21/28, H01L21/285, H01L21/308, H01L21/311, H01L21/762, H01L21/768, H01L21/8234, H01L21/8238, H01L23/00, H01L23/522, H01L23/528, H01L23/532, H01L27/02, H01L27/088, H01L27/092, H01L29/06, H01L29/08, H01L29/165, H01L29/167, H01L29/417, H01L29/51, H01L29/78, H10B10/00
CPC Code(s): H01L29/66545
Abstract: embodiments of the disclosure are in the field of advanced integrated circuit structure fabrication and, in particular, 10 nanometer node and smaller integrated circuit structure fabrication and the resulting structures. in an example, a method includes forming a plurality of fins and forming a plurality of gate structures over the plurality of fins. a dielectric material structure is formed between adjacent ones of the plurality of gate structures. a portion of a first of the plurality of gate structures is removed to expose a first portion of each of the plurality of fins, and a portion of a second of the plurality of gate structures is removed to expose a second portion of each of the plurality of fins. the exposed first portion of each of the plurality of fins is removed, but the exposed second portion of each of the plurality of fins is not removed.
20240332403. STACKED TRANSISTORS_simplified_abstract_(intel corporation)
Inventor(s): Patrick MORROW of Portland OR (US) for intel corporation, Rishabh MEHANDRU of Portland OR (US) for intel corporation, Aaron D. LILAK of Beaverton OR (US) for intel corporation
IPC Code(s): H01L29/66, H01L21/822, H01L21/8234, H01L21/8238, H01L27/06, H01L27/088, H01L27/092, H01L29/06, H01L29/423, H01L29/786
CPC Code(s): H01L29/66795
Abstract: a first interconnect layer is bonded to a first substrate. the first interconnect layer is deposited on a first device layer on a second device layer on a second substrate. the second device layer is revealed from the second substrate side. a first insulating layer is deposited on the revealed second device layer. a first opening is formed in the first insulating layer to expose a first portion of the second device layer. a contact region is formed on the exposed first portion of the second device layer.
Inventor(s): Sukru Yemenicioglu of Portland OR (US) for intel corporation, Abhishek Anil Sharma of Portland OR (US) for intel corporation, Sudipto Naskar of Portland OR (US) for intel corporation, Kalyan C. Kolluru of Portland OR (US) for intel corporation
IPC Code(s): H01L29/93, H01L29/417, H01L29/66
CPC Code(s): H01L29/93
Abstract: an integrated circuit device comprising a varactor comprising a first conductive contact; a second conductive contact; and a thin film transistor (tft) channel material coupled between the first conductive contact and the second conductive contact.
Inventor(s): Chinmay Pradeep Joshi of Portland OR (US) for intel corporation, Dinesh Somasekhar of Portland (UA) for intel corporation, David Edward Bradley of Fort Collins CO (US) for intel corporation, Radhika Kudva of Beaverton OR (US) for intel corporation
IPC Code(s): H03K3/012, H03K3/037
CPC Code(s): H03K3/012
Abstract: methods and apparatus are disclosed to improve flip-flop toggle efficiency. an example circuit includes an upper flip-flop latch circuit including a first clock input terminal, a first output terminal, and a first data input terminal, a first gating circuit including a first gating transistor, the first gating transistor including a first power input terminal, a first gating output terminal and a gating signal input terminal, the gating signal input terminal coupled to the first input terminal of the first flip-flop latch circuit, a first clock transistor including a clock power input terminal coupled to the first gating output terminal of the first gating transistor, a clock power output terminal, and a clock signal input terminal coupled to the first clock input terminal of the upper flip-flop latch circuit, and a first latch output transistor including a latch power input terminal, a latch power output terminal coupled to the clock power output terminal of the first clock transistor, and a latch input terminal coupled to an output of a second latch output transistor of the upper flip-flop latch circuit.
Inventor(s): Minki Cho of Portland OR (US) for intel corporation, Balkaran Gill of Cornelius OR (US) for intel corporation
IPC Code(s): H03K19/003, H01L27/02
CPC Code(s): H03K19/00315
Abstract: the disclosure is directed to methods, a standard cell, and a system for forming a logic gate with reduced aging including organizing a plurality of transistors to provide a logic function for the logic gate, identifying a least one transistor in the plurality of transistors having a voltage swing to an output above a predetermined threshold, and coupling a voltage dividing transistor to the at least one transistor to reduce a voltage across the at least one transistor such that the voltage dividing transistor lowers a voltage across the at least one transistor.
20240333392. OPTICAL TRANSCEIVERS WITH MULTI-LASER MODULES_simplified_abstract_(intel corporation)
Inventor(s): Saeed Fathololoumi of Los Gatos CA (US) for intel corporation, Ling Liao of Santa Clara CA (US) for intel corporation, Quan Tran of Fremont CA (US) for intel corporation
IPC Code(s): H04B10/50, H04B10/508
CPC Code(s): H04B10/5053
Abstract: disclosed herein are optical transceivers with multi-laser modules, as well as related optoelectronic assemblies and methods. in some embodiments, an optical transceiver may include: a first laser and a second laser, an optical output path, wherein an output of the first laser is coupled to the optical output path; and switching circuitry to decouple the output of the first laser from the optical output path and to couple an output of the second laser to the optical output path.
Inventor(s): Wayne Ballantyne of Chandler AZ (US) for intel corporation, Laurence Bays of Allentown PA (US) for intel corporation, Peter Pawliuk of Tempe AZ (US) for intel corporation
IPC Code(s): H04L1/00
CPC Code(s): H04L1/0007
Abstract: this disclosure describes systems, methods, and devices for placing bits in an isochronous data stream from a first data port to a second data port. a device may inject, using a first port, based on a periodicity less than a defined frame rate of a data stream comprising multiple frames, a status or control bit in place of one or more low-order bits, reserved bits, or unused bits of a frame of the data stream, wherein the frame includes one or more data words; receive, using a second port synchronized to the periodicity, the data stream from the first port; extract, using the second port, based on the periodicity, the status or control bit; and extract, using the second port, a remainder of the frame.
Inventor(s): Raghavan Kumar of Hillsboro OR (US) for intel corporation, Sanu Mathew of Portland OR (US) for intel corporation, Sachin Taneja of Hillsboro OR (US) for intel corporation
IPC Code(s): H04L9/06
CPC Code(s): H04L9/0631
Abstract: in one embodiment, a method comprises: combining, in a first adder circuit of a cryptographic engine, a round key with masked plaintext to generate an additively masked input; converting, in a first converter of the cryptographic engine, the additively masked input to a multiplicatively masked input; and performing, in a substitution box circuit of the cryptographic engine, a non-linear inverse operation on the multiplicatively masked input when the multiplicatively masked input is non-zero, and performing the non-linear inverse operation on a random non-zero value when the multiplicatively masked input is zero. other embodiments are described and claimed.
Inventor(s): Raghavan Kumar of Hillsboro OR (US) for intel corporation, Sanu Mathew of Portland OR (US) for intel corporation, Avinash V. Varna of Chandler AZ (US) for intel corporation, Kirk S. YAP of Westborough MA (US) for intel corporation
IPC Code(s): H04L9/06
CPC Code(s): H04L9/0631
Abstract: an apparatus of an aspect includes a substitution box (s-box) circuitry. the s-box circuitry includes multiplicative inverse circuitry. the multiplicative inverse circuitry is to receive an 8-bit input in galois field and is to generate a corresponding 8-bit output in galois field. the 8-bit output is to be a multiplicative inverse of the 8-bit input as long as there has been no error in the generation of the 8-bit output. the apparatus also includes error detection circuitry to receive the 8-bit input and that is coupled with the s-box circuitry to receive the 8-bit output. the error detection circuitry to detect whether an error has occurred in the generation of the 8-bit output based at least in part on whether the 8-bit output is the multiplicative inverse of the 8-bit input. other apparatus, methods, and systems are also disclosed.
Inventor(s): David M. Durham of Beaverton OR (US) for intel corporation, Michael LeMay of Hillsboro OR (US) for intel corporation, Salmin Sultana of Hillsboro OR (US) for intel corporation, Karanvir S. Grewal of Hillsboro OR (US) for intel corporation, Sergej Deutsch of Hillsboro OR (US) for intel corporation
IPC Code(s): H04L9/14, G06F21/60, G06F21/62, G06F21/78
CPC Code(s): H04L9/14
Abstract: in a technique of hardware thread isolation, a processor comprises a first core including a first hardware thread register. the core is to select a first key identifier stored in the first hardware thread register in response to receiving a first memory access request associated with a first hardware thread of a process. memory controller circuitry coupled to the first core is to obtain a first encryption key associated with the first key identifier. the first key identifier may be selected from the first hardware thread register based, at least in part, on a first portion of a pointer of the first memory access request. the first key identifier selected from the first hardware thread register is to be appended to a physical address translated from a linear address at least partially included in the pointer.
Inventor(s): Hai Tao WANG of Shanghai (CN) for intel corporation, Yong LI of Shanghai (CN) for intel corporation, Kailun QIN of Shanghai (CN) for intel corporation, Chengye LI of Shanghai (CN) for intel corporation
IPC Code(s): H04L41/16, G06N3/091, G16Y20/20, G16Y40/35, G16Y40/40
CPC Code(s): H04L41/16
Abstract: systems, apparatuses and methods include technology that identifies a model update that originates from a plurality of iot devices. the technology determines votes from the plurality of iot devices, where the votes indicate whether the model update will be deployed. the technology deploys the model update to the plurality of iot devices based on the votes.
Inventor(s): Joey CHOU of Scottsdale AZ (US) for intel corporation, Yizhi YAO of Chandler AZ (US) for intel corporation
IPC Code(s): H04L43/091, H04L12/14, H04L41/5009
CPC Code(s): H04L43/091
Abstract: this disclosure describes systems, methods, and devices related to performance measurements. a device may decode a service request received from a management service consumer for the 5g system (5gs), wherein the service request may be associated with a performance measurement collection service to be delivered by the service producer to the service consumer related to a network exposure function (nef). the device may detect performance measurements data received from the nef. the device may decode from the performance measurements data a measurement label associated with the performance measurements data based on the service request. the device may encode a service response based on the performance measurements data received from the nef.
Inventor(s): Niloufar Pourian of Los Gatos CA (US) for intel corporation
IPC Code(s): H04N13/264, H04N13/271
CPC Code(s): H04N13/264
Abstract: methods, apparatus, systems and articles of manufacture (e.g., physical storage media) to generate optical flow maps based on foreground and background image segmentation are disclosed. example apparatus disclosed herein are to generate a reference optical flow map based on a stereo pair of background images corresponding to a first camera field-of-view and a second camera field-of-view, and generate a first optical flow map based on a stereo pair of input images corresponding to the first camera field-of-view and the second camera field-of-view. disclosed example apparatus are also to combine the reference optical flow map and the first optical flow map based on an alpha matte to generate a second optical flow map associated with the stereo pair of input images, the alpha matte representative of segmentation of at least one of the stereo pair of input images into foreground and background regions.
Inventor(s): Phoenix WORTH of Delta (CA) for intel corporation, Faouzi KOSSENTINI of Vancouver (CA) for intel corporation, Foued BEN AMARA of Surrey (CA) for intel corporation
IPC Code(s): H04N19/146
CPC Code(s): H04N19/146
Abstract: a system that includes at least one memory and circuitry coupled to the at least one memory, wherein the circuitry is to access media from the at least one memory, wherein the circuitry is to: select one or more settings to apply to encode the video based on a cost of signaling applicable settings.
Inventor(s): Venkateshan Udhayan of Portland OR (US) for intel corporation, Kristoffer Fleming of Chandler AZ (US) for intel corporation, Chia-Hung S. Kuo of Folsom CA (US) for intel corporation, Sangeeta Manepalli of Chandler AZ (US) for intel corporation, Vishal Sinha of Portland OR (US) for intel corporation, Jason Tanner of Folsom CA (US) for intel corporation
IPC Code(s): H04N19/30, H04N19/14, H04N19/164, H04N19/172
CPC Code(s): H04N19/30
Abstract: a video source device for wireless display sharing, including: an encoder operable to dynamically switch between encoding a video full-frame into a first bitstream at a first resolution, and a video sub-frame into a second bitstream at a second resolution, wherein the second resolution is higher than the first resolution; processing circuitry operable to decide between encoding the video full-frame and encoding the video sub-frame based on an amount of available wireless transmission bandwidth, a number of pixels in a changed region of the video full-frame, spatial complexity of a changed region of the video full-frame, temporal complexity of a changed region of the video full-frame, or a category of region change of the video full-frame; and a transmitter operable to wirelessly transmit the first bitstream and the second bitstream to a video sink device.
Inventor(s): Cheng CHEN of Camas WA (US) for intel corporation, Carlos CORDEIRO of Camas WA (US) for intel corporation, Dibakar DAS of Hillsboro OR (US) for intel corporation
IPC Code(s): H04W24/08, H04W84/12
CPC Code(s): H04W24/08
Abstract: this disclosure describes systems, methods, and devices related to non-trigger based (non-tb) sensing. a device may initiate sensing measurements by sending a sensing null data packet announcement (ndpa) frame to an access point (ap) responder. the device may send one or more first null data packet (ndp) packets to the ap responder. the device may identify one or more second ndp packets received from the ap responder.
20240334245. PROCESSING OF PACKET FRAGMENTS_simplified_abstract_(intel corporation)
Inventor(s): John J. BROWNE of Limerick (IE) for intel corporation, Andrey CHILIKIN of Limerick (IE) for intel corporation, Elazar COHEN of Haifa (IL) for intel corporation, Joseph HASTING of Orefield PA (US) for intel corporation, James CLEE of Orefield PA (US) for intel corporation, Jerry PIROG of Easton PA (US) for intel corporation, Jamison D. WHITESELL of Pennsburg PA (US) for intel corporation, Ambalavanar ARULAMBALAM of Center Valley PA (US) for intel corporation, Anjali Singhai JAIN of Portland OR (US) for intel corporation, Andrew CUNNINGHAM of Ennis (IE) for intel corporation, Ruben DAHAN of Petah Tikva (IL) for intel corporation
IPC Code(s): H04W28/06, H04W28/02
CPC Code(s): H04W28/06
Abstract: examples described herein relate to a network interface device that performs: offloading processing of fragments of a packet to an accelerator; processing non-fragmented packets; and prioritizing dropping of fragments of the packet over dropping of non-fragmented packets. offloading processing of fragments of the packet to the accelerator can include: the accelerator performing: reassembling the fragments of the packet into a first reassembly packet; and based on congestion associated with at least one of the fragments of the packet of the first reassembly packet: dropping fragments of the first reassembly packet associated with one or more flows; halting reassembly of the first reassembly packet; and forwarding a second packet to a host system, wherein the second packet indicates that congestion occurred, identifies one or more impacted flows, and indicates a number of dropped packet fragments.
Inventor(s): Yizhi YAO of Chandler AZ (US) for intel corporation, Joey CHOU of Scottsdale AZ (US) for intel corporation
IPC Code(s): H04W64/00, H04L43/067, H04W4/02
CPC Code(s): H04W64/003
Abstract: this disclosure describes systems, methods, and devices related to performance measurements. a device may decode a management service (mns) service request received from an mns consumer for the 5g system (5gs), wherein the service request is associated with a performance measurement collection service to be delivered by the service producer to the consumer related to a location management function (lmf). the device may detect performance measurements data received from the lmf. the device may decode from the performance measurements data a measurement label associated with the performance measurements data based on the mns service. the device may encode a service response based on the performance measurements data received from the pcf.
Inventor(s): Alexey Khoryaev of Santa Clara CA (US) for intel corporation, Sergey Sosnin of Santa Clara CA (US) for intel corporation, Mikhail Shilov of Santa Clara CA (US) for intel corporation, Sergey Panteleev of Kildare (IE) for intel corporation, Artyom Putilin of Santa Clara CA (US) for intel corporation, Seunghee Han of Santa Clara CA (US) for intel corporation
IPC Code(s): H04W72/23, H04W64/00, H04W72/51, H04W72/54, H04W74/00
CPC Code(s): H04W72/23
Abstract: methods, systems, and storage media are described for new radio downlink positioning reference signal (nr dl prs) resource allocation and configuration. in particular, some embodiments relate to some embodiments relate to nr dl prs resource configurations such as comb size, number of symbols, dl prs resource time configuration (e.g., initial start time and periodicity), and providing formulas for calculation of seed for dl prs sequence generation. other embodiments may be described and/or claimed.
Inventor(s): Min Suet Lim of Gelugor (MY) for intel corporation, Rijo Kizhakkedathu Avarachan of Bayan Lepas (MY) for intel corporation, Eng Huat Goh of Ayer Itam (MY) for intel corporation
IPC Code(s): H05K1/11, H01L23/00, H05K1/18, H10B80/00
CPC Code(s): H05K1/111
Abstract: printed circuit boards including direct routing from integrated circuit packages are disclosed. an example substrate disclosed herein including a first contact pad array to receive an integrated circuit package, a second contact pad array to receive a memory die, the first contact pad array having a matching arrangement as the second contact pad array, and a layer including a plurality of interconnections extending between the first contact pad array and the second contact pad array.
Inventor(s): Sunita Thulasi of Portland OR (US) for intel corporation, Dorian Alden of Portland OR (US) for intel corporation, Mark Horsch of Missouri City TX (US) for intel corporation, A S M Jonayat of North Plains OR (US) for intel corporation, Cheng-Tsung Lee of Beaverton OR (US) for intel corporation, Silvia Liong of Portland OR (US) for intel corporation, Seth Morton of Beaverton OR (US) for intel corporation, Omar Rahal-Arabi of Tigard OR (US) for intel corporation, Prashanth Kumar Siddhamshetty of Portland OR (US) for intel corporation
IPC Code(s): H05K3/00, G03F7/00
CPC Code(s): H05K3/0005
Abstract: this disclosure describes systems, methods, and devices related to shifting layouts of electronic circuit vias during optical proximity corrections (opc). a method may include identifying a first metal line, of an electronic circuit, drawn at a first position; identifying a second metal line, of the electronic circuit, drawn at a second position; identifying a via drawn at a third position extending between the first metal line and the second metal line; determining a fourth position to which the first metal line is to move from the first position; determining a fifth position to which the second metal line is to move from the second position; determining, based on the fourth position, the fifth position, a sixth position to which the via is to move from third position; and generating a layout for generating a photomask for the via at the sixth position.
Inventor(s): Chiao-Ti Huang of Portland OR (US) for intel corporation, Akitomo Matsubayashi of Beaverton OR (US) for intel corporation, Brian Greene of Portland OR (US) for intel corporation, Chung-Hsun Lin of Portland OR (US) for intel corporation
IPC Code(s): H10B10/00, H01L27/088, H01L29/06, H01L29/423, H01L29/66, H01L29/78
CPC Code(s): H10B10/12
Abstract: an apparatus comprising a source or drain of a field effect transistor (fet), a first dielectric between a portion of the source or drain and a fet gate, the first dielectric comprising silicon nitride, and a second dielectric above at least a portion of the first dielectric, the second dielectric comprising silicon oxide doped with at least one of oxygen or carbon, the second dielectric having a dielectric constant lower than the first dielectric.
20240334715. FOR MEMORY ON PACKAGE WITH REDUCED THICKNESS_simplified_abstract_(intel corporation)
Inventor(s): Navneet Kumar Singh of Bangalore (IN) for intel corporation, Phani Alaparthi of Bangalore (IN) for intel corporation, Samarth Alva of Bangalore (IN) for intel corporation, Ritu Bawa of Bangalore (IN) for intel corporation, Gaurav Hada of Bangalore (IN) for intel corporation, Aiswarya M. Pious of Bangalore (IN) for intel corporation
IPC Code(s): H10B80/00, H01L23/00, H01L23/31, H01L23/48, H01L25/065, H01L25/18
CPC Code(s): H10B80/00
Abstract: technologies for memory on package with reduced package thickness are disclosed. in the illustrative embodiment, a die assembly includes a substrate with a processor die mounted on the top surface and a memory die mounted on the bottom surface. the die assembly is mounted on another substrate, such as a mainboard. a cavity is defined in the mainboard, and the memory die mounted on the bottom surface of the die assembly is positioned in the cavity. positioning the memory die on the bottom surface of the die assembly can reduce the overall thickness of the die assembly and, therefore, can reduce the overall thickness of a device that incorporates the die assembly.
- Intel Corporation
- A63F13/355
- G06T1/20
- CPC A63F13/355
- Intel corporation
- B25J9/16
- CPC B25J9/163
- G06V10/26
- H04N23/695
- CPC B25J9/1697
- B81B7/00
- B81C1/00
- G02B6/12
- CPC B81B7/0048
- C09J7/38
- C09J11/04
- H05K13/00
- CPC C09J7/38
- F16J15/06
- H05K7/20
- CPC F16J15/06
- G01R31/28
- CPC G01R31/2851
- CPC G01R31/2884
- G01R31/317
- G06F11/27
- G06F13/42
- CPC G01R31/31705
- CPC G02B6/12004
- G02B6/26
- CPC G02B6/26
- G02B6/30
- G02B6/32
- G02B6/38
- CPC G02B6/305
- G02B6/42
- G02B6/13
- H01L25/065
- H01L25/16
- CPC G02B6/4202
- CPC G02B6/4228
- G05F1/575
- G05F1/565
- G05F1/59
- CPC G05F1/575
- G06F1/20
- G06F1/3212
- G06F1/3234
- CPC G06F1/206
- G06F1/3206
- CPC G06F1/3206
- G06F1/3215
- G06F1/324
- CPC G06F1/3215
- G06F1/3296
- G06F9/48
- G06F9/50
- CPC G06F1/3296
- G06F3/01
- G06T13/40
- CPC G06F3/013
- G06F3/04815
- G06V10/94
- CPC G06F3/04815
- G06F3/06
- CPC G06F3/0631
- CPC G06F3/0656
- G06F7/78
- G06F9/30
- G06F17/16
- CPC G06F7/78
- G06F8/41
- CPC G06F8/41
- CPC G06F9/30145
- G06F11/10
- G06F12/14
- CPC G06F9/3016
- G06F8/30
- G06F8/52
- G06F8/75
- G06F8/76
- G06F9/38
- G06N3/04
- CPC G06F9/30174
- CPC G06F9/3861
- G06F9/355
- G06F15/78
- CPC G06F9/3887
- CPC G06F9/4893
- CPC G06F9/5016
- G06F9/54
- G06F9/52
- CPC G06F9/544
- G06F11/07
- CPC G06F11/0772
- G06F11/34
- CPC G06F11/3495
- G06F13/12
- G06F13/38
- CPC G06F13/12
- G06F13/28
- CPC G06F13/28
- CPC G06F13/4282
- CPC G06F15/7814
- Intel corporation,
- G06N20/00
- CPC G06F17/16
- G06F21/57
- CPC G06F21/57
- G06F30/3308
- G06F30/327
- CPC G06F30/3308
- G06F30/392
- CPC G06F30/392
- G06N10/00
- H01L29/12
- CPC G06N10/00
- G06T3/00
- G06F3/0346
- G06T19/00
- H04L65/1089
- H04L65/80
- CPC G06T3/16
- G06T7/246
- CPC G06T7/248
- G06T7/80
- G06T7/50
- G06V10/82
- G06V20/56
- G06V20/58
- CPC G06T7/80
- CPC G06V10/82
- G10L17/04
- CPC G10L17/04
- G11C11/4096
- G11C11/4093
- G11C11/4094
- CPC G11C11/4096
- H01F27/28
- H01F41/32
- H01L23/498
- H01L23/64
- CPC H01F27/2804
- H01L21/768
- H01L21/8234
- H01L23/528
- CPC H01L21/76808
- C23C16/40
- C23C16/455
- C23C16/50
- H01L21/02
- H01L23/532
- CPC H01L21/76834
- H01L23/48
- CPC H01L21/76898
- H01L21/3213
- H01L27/088
- H01L29/06
- H01L29/423
- H01L29/66
- H01L29/775
- CPC H01L21/823456
- H01L23/15
- H01F27/24
- H01L23/522
- CPC H01L23/15
- H01L23/36
- H01L21/48
- H01L21/50
- H01L21/60
- H01L23/00
- H01L23/367
- H01L23/373
- H01L23/42
- H01L23/488
- CPC H01L23/36
- CPC H01L23/3675
- H01L23/24
- CPC H01L23/3737
- H01L23/38
- CPC H01L23/38
- H01L23/495
- CPC H01L23/49513
- CPC H01L23/49838
- H01L23/538
- CPC H01L23/5226
- CPC H01L23/528
- H01L21/8238
- H01L27/092
- H01L29/78
- H01L29/786
- CPC H01L23/5283
- CPC H01L23/5381
- CPC H01L23/5384
- H01L21/56
- H01L21/683
- H01L23/31
- H01L25/07
- H01L25/11
- CPC H01L23/5389
- CPC H01L23/642
- CPC H01L24/16
- CPC H01L25/0652
- H01L27/02
- H01L21/84
- H01L29/872
- H02H9/04
- CPC H01L27/0266
- H01L21/033
- CPC H01L27/088
- CPC H01L27/0922
- CPC H01L27/0924
- H01L29/417
- H01L27/13
- H01L23/482
- H01L25/18
- H01L29/772
- CPC H01L27/13
- H01L21/78
- CPC H01L29/0657
- H01L29/40
- H01L29/45
- CPC H01L29/41733
- CPC H01L29/41766
- CPC H01L29/42392
- H01L21/28
- H01L21/285
- H01L29/08
- H01L29/161
- H01L29/49
- CPC H01L29/45
- CPC H01L29/4908
- H01L21/308
- H01L21/311
- H01L21/762
- H01L29/165
- H01L29/167
- H01L29/51
- H10B10/00
- CPC H01L29/66545
- H01L21/822
- H01L27/06
- CPC H01L29/66795
- H01L29/93
- CPC H01L29/93
- H03K3/012
- H03K3/037
- CPC H03K3/012
- H03K19/003
- CPC H03K19/00315
- H04B10/50
- H04B10/508
- CPC H04B10/5053
- H04L1/00
- CPC H04L1/0007
- H04L9/06
- CPC H04L9/0631
- H04L9/14
- G06F21/60
- G06F21/62
- G06F21/78
- CPC H04L9/14
- H04L41/16
- G06N3/091
- G16Y20/20
- G16Y40/35
- G16Y40/40
- CPC H04L41/16
- H04L43/091
- H04L12/14
- H04L41/5009
- CPC H04L43/091
- H04N13/264
- H04N13/271
- CPC H04N13/264
- H04N19/146
- CPC H04N19/146
- H04N19/30
- H04N19/14
- H04N19/164
- H04N19/172
- CPC H04N19/30
- H04W24/08
- H04W84/12
- CPC H04W24/08
- H04W28/06
- H04W28/02
- CPC H04W28/06
- H04W64/00
- H04L43/067
- H04W4/02
- CPC H04W64/003
- H04W72/23
- H04W72/51
- H04W72/54
- H04W74/00
- CPC H04W72/23
- H05K1/11
- H05K1/18
- H10B80/00
- CPC H05K1/111
- H05K3/00
- G03F7/00
- CPC H05K3/0005
- CPC H10B10/12
- CPC H10B80/00
