Intel Corporation patent applications on October 24th, 2024
Patent Applications by Intel Corporation on October 24th, 2024
Intel Corporation: 59 patent applications
Intel Corporation has applied for patents in the areas of H01L23/00 (8), H01L29/06 (7), H01L23/538 (7), H01L21/48 (6), H01L29/423 (6) H01L23/5386 (2), H01L23/5385 (2), H01L29/41733 (2), H01L23/544 (1), H01L23/562 (1)
With keywords such as: example, package, substrate, layer, based, disclosed, include, data, device, and gate in patent application abstracts.
Patent Applications by Intel Corporation
Inventor(s): Edgar Macias Garcia of Jalisco (MX) for intel corporation, Leobardo Campos Macias of Guadalajara (MX) for intel corporation, Hector Cordourier Maruri of Guadalajara (MX) for intel corporation, Rafael De La Guardia Gonzalez of Leioa (MX) for intel corporation, David Gonzalez Aguirre of Portland OR (US) for intel corporation, Alejandro Ibarra Von Borstel of Buda TX (US) for intel corporation, Paulo Lopez Meyer of Zapopan (MX) for intel corporation, Javier Turek of Beaverton OR (US) for intel corporation, Julio Zamora Esquivel of West Sacramento CA (US) for intel corporation
IPC Code(s): B25J9/16
CPC Code(s): B25J9/163
Abstract: an apparatus, including: an interface configured to receive a target end-effector pose of a cobot; processing circuitry configured to: generate in a generic robot model a joint trajectory based on the target end-effector pose; employ a trained neural network model to map the joint trajectory generated in the generic robot model into a cobot model; and generate a movement instruction to control a movement of the cobot based on the joint trajectory mapped to the cobot model, wherein the generic robot model has a number of degrees of freedom that is equal to or greater than that of the cobot model.
20240351207. AUTONOMOUS NAVIGATION SYSTEM FOR MOBILE ROBOTS_simplified_abstract_(intel corporation)
Inventor(s): Leobardo Campos Macias of Guadalajara (MX) for intel corporation
IPC Code(s): B25J9/16, B25J5/00, G05D1/246
CPC Code(s): B25J9/1664
Abstract: an apparatus, including: an interface operable to receive sensor data and generate a map representation of an environment of a robot; processing circuitry operable to: plan a sequence of states to direct the robot to a task goal of the robot based on the map representation and a kinematic state of the robot for a plurality of degrees of freedom; determine a time-dependent trajectory of the robot to the task goal based on the sequence of states by dynamically enabling or disabling one or more of the plurality of degrees of freedom; and generate a movement instruction to control movement of the robot based on the time-dependent trajectory.
Inventor(s): Krishnendu Saha of Bangalore (IN) for intel corporation, Chethan Holla of Bangalore (IN) for intel corporation, Hari Shanker Thakur of Bangalore (IN) for intel corporation
IPC Code(s): C01B33/158, C01B33/159, C09D183/04, G06F1/20, H05K5/02
CPC Code(s): C01B33/1585
Abstract: aerogel including low thermal conductivity gases and related apparatus and methods are disclosed. an example aerogel disclosed herein includes a framework including a plurality of pores and a gas in at least one of the plurality of pores, the gas having a lower thermal conductivity than air.
20240353631. SEMICONDUCTOR PACKAGE WITH EMBEDDED OPTICAL DIE_simplified_abstract_(intel corporation)
Inventor(s): Vivek RAGHUNATHAN of Tempe AZ (US) for intel corporation, Myung Jin YIM of San Jose CA (US) for intel corporation
IPC Code(s): G02B6/42, G02B6/122, G02B6/132, H01L25/16
CPC Code(s): G02B6/4206
Abstract: semiconductor package with one or more optical die(s) embedded therein is disclosed. the optical die(s) may have one or more overlying interconnect layers. electrical contact to the optical die may be via the one or more overlying interconnect layers. an optical waveguide may be disposed next to the optical die and embedded within the semiconductor package. an optical fiber may be optically coupled to the optical waveguide.
Inventor(s): You LI of Hillsboro OR (US) for intel corporation, David DUARTE of Portland OR (US) for intel corporation, Yongping FAN of Portland OR (US) for intel corporation
IPC Code(s): G05F3/30
CPC Code(s): G05F3/30
Abstract: a low power hybrid reverse (lphr) bandgap reference (bgr) and digital temperature sensor (dts) or a digital thermometer, which utilizes subthreshold metal oxide semiconductor (mos) transistors.
Inventor(s): Mohammed Tameem of Bangalore (IN) for intel corporation, Altug Koker of El Dorado Hills CA (US) for intel corporation, Kiran C. Veernapu of Bangalore (IN) for intel corporation, Abhishek R. Appu of El Dorado Hills CA (US) for intel corporation, Ankur N. Shah of Folsom CA (US) for intel corporation, Joydeep Ray of Folsom CA (US) for intel corporation, Travis T. Schluessler of Hillsboro OR (US) for intel corporation, Jonathan Kennedy of Bristol (GB) for intel corporation
IPC Code(s): G06F1/3234, G06F1/3206, G06F1/324, G06F1/3287, G06F1/3296, G06F13/16, G06F13/40
CPC Code(s): G06F1/3253
Abstract: described herein are various embodiments of reducing dynamic power consumption within a processor device. one embodiment provides a technique for dynamic link width adjustment based on throughput demand for client of an interconnect fabric. one embodiment provides for a parallel processor comprising an interconnect fabric including a dynamically configurable bus widths and frequencies.
20240354043. Regional Adjustment of Render Rate_simplified_abstract_(intel corporation)
Inventor(s): Eric J. Asperheim of El Dorado Hills CA (US) for intel corporation, Subramaniam Maiyuran of Gold River CA (US) for intel corporation, Kiran C. Veernapu of Bangalore (IN) for intel corporation, Sanjeev S. Jahagirdar of Folsom CA (US) for intel corporation, Balaji Vembu of Folsom CA (US) for intel corporation, Devan Burke of Portland OR (US) for intel corporation, Philip R. Laws of Santa Clara CA (US) for intel corporation, Kamal Sinha of Rancho Cordova CA (US) for intel corporation, Abhishek R. Appu of El Dorado Hills CA (US) for intel corporation, Elmoustapha Ould-Ahmed-Vall of Chandler AZ (US) for intel corporation, Peter L. Doyle of El Dorado Hills CA (US) for intel corporation, Joydeep Ray of Folsom CA (US) for intel corporation, Travis T. Schluessler of Hillsboro OR (US) for intel corporation, John H. Feit of Folsom CA (US) for intel corporation, Nikos Kaburlasos of Lincoln CA (US) for intel corporation, Jacek Kwiatkowski of Santa Clara CA (US) for intel corporation, Altug Koker of El Dorado Hills CA (US) for intel corporation
IPC Code(s): G06F3/14, G06F3/01, G06F3/0484, G09G5/00, G09G5/391
CPC Code(s): G06F3/1438
Abstract: in accordance with some embodiments, the render rate is varied across and/or up and down the display screen. this may be done based on where the user is looking in order to reduce power consumption and/or increase performance. specifically the screen display is separated into regions, such as quadrants. each of these regions is rendered at a rate determined by at least one of what the user is currently looking at, what the user has looked at in the past and/or what it is predicted that the user will look at next. areas of less focus may be rendered at a lower rate, reducing power consumption in some embodiments.
Inventor(s): Jongwook Sohn of Austin TX (US) for intel corporation, David Dean of Austin TX (US) for intel corporation, Eric Quintana of Austin TX (US) for intel corporation, Wing Shek Wong of Austin TX (US) for intel corporation
IPC Code(s): G06F7/523
CPC Code(s): G06F7/523
Abstract: techniques and mechanisms for circuitry to support the performance of a fused multiply-add (fma) operation with one or more denormal numbers. in some embodiments, a processor is operable to execute a fma instruction comprising or otherwise identifying two multiplicands, and an addend. such execution includes performing one-way alignment of an addend significand based on a difference between respective exponent values of the two multiplicands. the alignment is performed in parallel with operations by a multiplier circuit based on respective significand values of the two multiplicands. subtraction of a j-bit correction value is performed in the multiplier circuit to avoid mitigate execution delay. in another embodiment, first circuitry of a processor executes an fma instruction, wherein components of the first circuitry are shared with second circuitry of the processor, and wherein the second circuitry supports the execution of a floating-point multiplication instruction.
Inventor(s): Frank Hady of Cannon Beach OR (US) for intel corporation, Christopher J. Hughes of Santa Clara CA (US) for intel corporation, Scott Peterson of Beaverton OR (US) for intel corporation
IPC Code(s): G06F9/30, G06F9/32, G06F9/38
CPC Code(s): G06F9/30047
Abstract: in one example, a processor includes: at least one core to execute instructions; and at least one cache memory coupled to the at least one core, the at least one cache memory to store data, at least some of the data a copy of data stored in a memory. the at least one core is to determine whether to conditionally offload a sequence of instructions for execution on a compute circuit associated with the memory, based at least in part on whether one or more first data is present in the at least one cache memory, the one or more first data for use during execution of the sequence of instructions. other embodiments are described and claimed.
Inventor(s): Michael LeMay of Hillsboro OR (US) for intel corporation, David M. Durham of Beaverton OR (US) for intel corporation, Joseph Cihula of Hillsboro OR (US) for intel corporation, Joseph Nuzman of Haifa (IL) for intel corporation, Dan Baum of Haifa (IL) for intel corporation, Jonathan Combs of Austin TX (US) for intel corporation
IPC Code(s): G06F9/30
CPC Code(s): G06F9/3016
Abstract: techniques for implementing instructions and modified instruction encodings for checking tags and for interspersing islands of tags in line with bucketed data for locality by a processor are described. in an example, an apparatus includes decoder circuitry and execution circuitry. the decoder circuitry is to decode an instruction into a decoded instruction. the instruction has an opcode to indicate that the execution circuitry is to use metadata and instruction encodings to selectively perform a memory safety check. the execution circuitry is to execute the decoded instruction according to the opcode.
20240354162. GRAPH ORCHESTRATOR FOR NEURAL NETWORK EXECUTION_simplified_abstract_(intel corporation)
Inventor(s): Srikanth Vasuki of Castleknock (IE) for intel corporation, Niall Hanrahan of Galway (IE) for intel corporation
IPC Code(s): G06F9/50
CPC Code(s): G06F9/5027
Abstract: a barrier may be inserted into a graph representing workloads in an execution of a neural network and placed between a producing workload performed by a producer and a consuming workload performed by a consumer. the consuming workload is to be performed using data generated from the producing workload. a graph orchestrator may modify status information of the barrier in response to receiving a message from the producer. the status information indicates whether one or more producing workloads associated with the barrier are complete. the message indicates that the producing workload is complete. the graph orchestrator may determine whether the one or more producing workloads are complete based on the modified status information. in response to determining that the one or more producing workloads are complete, the graph orchestrator may provide a barrier lift message to the consumer. the barrier lift message causing the consumer to start the consuming workload.
Inventor(s): Junjing SHI of Nanjing (CN) for intel corporation, Wei YANG of Shanghai (CN) for intel corporation, Amir Ali RADJAI of Portland OR (US) for intel corporation, Hongjiu LU of San Jose CA (US) for intel corporation
IPC Code(s): G06F11/10
CPC Code(s): G06F11/1016
Abstract: examples include techniques associated with use of a memory tag with in-line or in-band error correction code (ibecc) memory to provide protection for data to be stored in an address space of a memory device. examples include adding or including the memory tag with a single error correction double error detection (secded) code based on the data to provide ibecc for the data when stored to the first address space in the memory device.
Inventor(s): Naveen Vittal Prabhu of Folsom CA (US) for intel corporation, Aliasgar Madraswala of Folsom CA (US) for intel corporation, Rohit Shenoy of Freemont CA (US) for intel corporation, Shankar Natarajan of Folsom CA (US) for intel corporation, Arun S. Athreya of Folsom CA (US) for intel corporation
IPC Code(s): G06F11/20, G06F1/30, G06F11/16, G11C29/00
CPC Code(s): G06F11/2094
Abstract: an embodiment of an electronic apparatus may include one or more substrates, and logic coupled to the one or more substrates, the logic to control access to a persistent storage media based on a block and sub-block access structure, store a data structure in the persistent storage media to track read fails at a sub-block granularity for a word-line for every block, and update the data structure in response to a read fail on a block to indicate a failed sub-block that corresponds to the read fail for a word-line for the block. other embodiments are disclosed and claimed.
20240354211. APPARATUS, SYSTEM, AND METHOD OF DEBUGGING_simplified_abstract_(intel corporation)
Inventor(s): Aruni Nelson of Folsom CA (US) for intel corporation, Enrico Carrieri of Placerville CA (US) for intel corporation, Ashok Mishra of Portland OR (US) for intel corporation
IPC Code(s): G06F11/22, G06F11/273
CPC Code(s): G06F11/2221
Abstract: for example, a debug target may include an interconnect interface; and a debug manager configured to cause the debug target to process a debug request message received from a debug and test system (dts) via the interconnect interface. for example, the debug request message may include a group identifier (id) value and a debug request. for example, the debug manager may be configured to cause the debug target to execute the debug request, for example, based on a determination that the group id value is to identify a group of debug targets including the debug target. for example, the debug manager may be configured to cause the debug target to send a debug response message via the interconnect interface, the debug response message including the group id value and a debug response for the dts.
Inventor(s): Peng ZHAO of Shanghai (CN) for intel corporation, Xiao Dong LIN of Shanghai (CN) for intel corporation, Zhong CAO of Shanghai (CN) for intel corporation, Wei ZHU of Shanghai (CN) for intel corporation
IPC Code(s): G06F17/16
CPC Code(s): G06F17/16
Abstract: systems, apparatuses and methods include technology that identifies that a computation will be executed based on a plurality of values. the technology determines an order-of-operations associated with the computation and loads the plurality of values in an order determined based on the order-of-operations.
Inventor(s): Rajkishore Barik of Santa Clara CA (US) for intel corporation, Brian T. Lewis of Palo Alto CA (US) for intel corporation, Murali Sundaresan of Sunnyvale CA (US) for intel corporation, Jeffrey Jackson of Newberg OR (US) for intel corporation, Feng Chen of Shanghai (CN) for intel corporation, Xiaoming Chen of Shanghai (CN) for intel corporation, Mike Macpherson of Portland OR (US) for intel corporation
IPC Code(s): G06N3/063, G06F9/46, G06N3/044, G06N3/045, G06N3/084, G06N5/01
CPC Code(s): G06N3/063
Abstract: a mechanism is described for facilitating smart distribution of resources for deep learning autonomous machines. a method of embodiments, as described herein, includes detecting one or more sets of data from one or more sources over one or more networks, and introducing a library to a neural network application to determine optimal point at which to apply frequency scaling without degrading performance of the neural network application at a computing device.
Inventor(s): Dawei Ying of Portland OR (US) for intel corporation, Jaemin Han of Portland OR (US) for intel corporation, Leifeng Ruan of Beijing (CN) for intel corporation, Hui Ma of Kanata (CA) for intel corporation, Qian Li of Beaverton OR (US) for intel corporation
IPC Code(s): G06N20/00, H04L41/16
CPC Code(s): G06N20/00
Abstract: a machine-readable storage medium, an apparatus and a method, each corresponding to either a service consumer or a service producer of a non-real-time (non-rt) radio access network intelligent controller (ric) of a service management and orchestration framework (smo fw). communications from the service consumer to the service producer include: a training request for artificial intelligence/machine learning (ai/ml) training job; a query regarding a training status of the ai/ml training job; a cancel training request to cancel the ai/ml training job; and a notification regarding the training status of the ai/ml training job.
20240354886. UNIFIED MEMORY COMPRESSION MECHANISM_simplified_abstract_(intel corporation)
Inventor(s): Sreenivas Kothandaraman of Sammamish WA (US) for intel corporation, Karthik Vaidyanathan of San Francisco CA (US) for intel corporation, Abhishek R. Appu of El Dorado Hills CA (US) for intel corporation, Karol Szerszen of Hillsboro OR (US) for intel corporation, Prasoonkumar Surti of Folsom CA (US) for intel corporation
IPC Code(s): G06T1/20, G06F9/38, G06F16/907, G06T7/90
CPC Code(s): G06T1/20
Abstract: an apparatus to facilitate compression of memory data is disclosed. the apparatus comprises one or more processors to receive uncompressed data, adapt a format of the uncompressed data to a compression format, perform a color transformation from a first color space to a second color space, perform a residual computation to generate residual data, compress the residual data via entropy encoding to generate compressed data and packing the compressed data.
Inventor(s): Jill Boyce of Portland OR (US) for intel corporation, Maxym Dmytrychenko of Munich BY (DE) for intel corporation
IPC Code(s): G06T3/12, G06T3/16, H04N23/698
CPC Code(s): G06T3/12
Abstract: a mechanism is described for facilitating hemisphere cube map projection format imaging environments, according to one embodiment. a method of embodiments, as described herein, includes capturing, by a camera coupled to one or more processors, an image having image content, wherein the image content being represented by the image is omnidirectional such that the image content is mapped on a sphere while representing less than the sphere; mapping the image to a cubic representation based on six faces of a cube, wherein one or more of the six faces are classified as inactive regions such that they remain unoccupied or partially occupied; and arranging, based on the cubic representation, the six faces in a compact representation by avoiding inclusion of the inactive regions.
20240355032. GRAPHICS SYSTEM WITH ADDITIONAL CONTEXT_simplified_abstract_(intel corporation)
Inventor(s): Atsuo Kuwahara of Hillsboro OR (US) for intel corporation, Deepak S. Vembar of Portland OR (US) for intel corporation, Chandrasekaran Sakthivel of Sunnyvale CA (US) for intel corporation, Radhakrishnan Venkataraman of Folsom CA (US) for intel corporation, Brent E. Insko of Portland OR (US) for intel corporation, Anupreet S. Kalra of Folsom CA (US) for intel corporation, Hugues Labbe of Folsom CA (US) for intel corporation, Abhishek R. Appu of El Dorado Hills CA (US) for intel corporation, Ankur N. Shah of Folsom CA (US) for intel corporation, Joydeep Ray of Folsom CA (US) for intel corporation, Elmoustapha Ould-Ahmed-Vall of Chandler AZ (US) for intel corporation, Prasoonkumar Surti of Folsom CA (US) for intel corporation, Murali Ramadoss of Folsom CA (US) for intel corporation
IPC Code(s): G06T15/00, G06F9/50, G06T15/04, G06T15/80, G06T17/10
CPC Code(s): G06T15/005
Abstract: an embodiment of an electronic processing system may include an application processor, persistent storage media communicatively coupled to the application processor, and a graphics subsystem communicatively coupled to the application processor. the graphics subsystem may include a first graphics engine to process a graphics workload, and a second graphics engine to offload at least a portion of the graphics workload from the first graphics engine. the second graphics engine may include a low precision compute engine. the system may further include a wearable display housing the second graphics engine. other embodiments are disclosed and claimed.
20240355038. OCCUPANCY GRIDS FOR NEURAL RADIANCE FIELDS_simplified_abstract_(intel corporation)
Inventor(s): Alexey M. Supikov of Santa Clara CA (US) for intel corporation, Ronald Tadao Azuma of San Jose CA (US) for intel corporation
IPC Code(s): G06T15/06, G06T7/557, G06T15/50
CPC Code(s): G06T15/06
Abstract: example apparatus disclosed herein query a neural network for an optical density at a sample point along a training ray, the training ray associated with training the neural network to provide a neural representation of a video frame. disclosed example apparatus also generate an occupancy grid for the video frame based on the optical density at the sample point along the training ray, the occupancy grid including voxels to indicate whether respective portions of a three-dimensional (3d) volume associated with the neural representation are occupied with geometry.
Inventor(s): Alexey M. Supikov of Santa Clara CA (US) for intel corporation, Sainan Liu of San Diego CA (US) for intel corporation, Niloufar Pourian of Los Gatos CA (US) for intel corporation
IPC Code(s): G06T17/00, G06T7/90
CPC Code(s): G06T17/00
Abstract: example systems, apparatus, articles of manufacture, and methods are disclosed to implement three dimensional gaussian splatting initialization based on trained neural radiance field representations. example apparatus disclosed herein determine a location for an initial three-dimensional (3d) gaussian splat based on optical densities obtained from a trained neural representation of a scene, the optical densities associated with location sample points along a training ray used to train the neural representation. disclosed example apparatus also set parameters of the initial 3d gaussian splat based on one of the optical densities associated with the location of the initial 3d gaussian splat and a color value obtained from the trained neural representation, the color value associated with the location of the initial 3d gaussian splat, the initial 3d gaussian splat to be used to generate a 3d gaussian splat representation of the scene.
Inventor(s): Alexey M. Supikov of Santa Clara CA (US) for intel corporation, Ronald Tadao Azuma of San Jose CA (US) for intel corporation
IPC Code(s): G06V10/82, G06T7/20, G06T7/90
CPC Code(s): G06V10/82
Abstract: example apparatus disclosed herein are to train a neural network based on initial video frames of an input video to generate neural representations of the initial video frames, the neural network having a first group of layers and a second group of layers, the first group of layers to be retrained for subsequent video frames after the initial video frames, the second group of layers to be selectively frozen for the subsequent video frames. disclosed example apparatus are also to select a layer of the second group of layers to be unfrozen for a first video frame subsequent to the initial video frames, and retrain the first group of layers and the selected layer of the second group of layers to generate a neural representation of the first video frame, unselected ones of the second group of layers to remain frozen in the neural representation of the first video frame.
Inventor(s): Krishna Nidamanuri of Bangalore (IN) for intel corporation, Arvind Tomar of Folsom CA (US) for intel corporation, Bharatkumar Mahajan of Bangalore (IN) for intel corporation, Perazhi Sameer Kalathil of Folsom CA (US) for intel corporation, Nausheen Ansari of Folsom CA (US) for intel corporation, Arthur Runyan of Folsom CA (US) for intel corporation
IPC Code(s): G09G5/00, G06F1/10, G06F3/14
CPC Code(s): G09G5/006
Abstract: systems, apparatus, articles of manufacture, and methods are disclosed to reduce dynamic refresh rate power consumption. an example apparatus includes interface circuitry, machine-readable instructions, and at least one processor circuit to be programmed by the machine-readable instructions to modify a value of a source clock based on a detected application type, generate a pixel clock value change request based on the application type, cause transmission of the pixel clock value change request to a display, and cause transmission of pixels to the display at the modified source clock value.
20240355641. HIGH DENSITY ORGANIC INTERCONNECT STRUCTURES_simplified_abstract_(intel corporation)
Inventor(s): Sri Chaitra Jyotsna Chavali of Chandler AZ (US) for intel corporation, Siddharth K. Alur of Chandler AZ (US) for intel corporation, Lilia May of Chandler AZ (US) for intel corporation, Amanda E. Shuckman of Chandler AZ (US) for intel corporation
IPC Code(s): H01L21/48, H01L23/498
CPC Code(s): H01L21/4857
Abstract: generally discussed herein are systems, devices, and methods that include an organic high-density interconnect structure and techniques for making the same. according to an example a method can include forming one or more low-density buildup layers on a core, conductive interconnect material of the one or more low-density buildup layers electrically and mechanically connected to conductive interconnect material of the core, forming one or more high-density buildup layers on an exposed low-density buildup layer of the one or more low-density buildup layers, conductive interconnect material of the high-density buildup layers electrically and mechanically connected to the conductive interconnect material of the one or more low-density buildup layers, and forming another low-density buildup layer on and around an exposed high-density buildup layer of the one or more high-density buildup layers.
Inventor(s): Varun Mishra of Hillsboro OR (US) for intel corporation, Stephen M. Cea of Hillsboro OR (US) for intel corporation, Cory E. Weber of Hillsboro OR (US) for intel corporation, Jack T. Kavalieros of Portland OR (US) for intel corporation, Tahir Ghani of Portland OR (US) for intel corporation
IPC Code(s): H01L21/84, H01L29/06, H01L29/423, H01L29/78, H10B51/10, H10B51/30
CPC Code(s): H01L21/845
Abstract: embodiments of the present disclosure are based on extending a nanocomb transistor architecture to implement gate all around, meaning that a gate enclosure of at least a gate dielectric material, or both a gate dielectric material and a gate electrode material, is provided on all sides of each nanoribbon of a vertical stack of lateral nanoribbons of a nanocomb transistor arrangement. in particular, extension of a nanocomb transistor architecture to implement gate all around, proposed herein, involves use of two dielectric wall materials which are etch-selective with respect to one another, instead of using only a single dielectric wall material used to implement conventional nanocomb transistor arrangements. nanocomb-based transistor arrangements implementing gate all around as described herein may provide improvements in terms of the short-channel effects of conventional nanocomb transistor arrangements.
Inventor(s): Lizabeth Keser of San Diego CA (US) for intel corporation, Thomas Ort of Veitsbronn (DE) for intel corporation, Thomas Wagner of Regelsbach (DE) for intel corporation, Bernd Waidhas of Pettendorf (DE) for intel corporation
IPC Code(s): H01L23/31, H01L21/48, H01L21/56, H01L21/66, H01L21/78, H01L23/00, H01L23/538
CPC Code(s): H01L23/3192
Abstract: a semiconductor device and method is disclosed. devices shown include a die coupled to an integrated routing layer, wherein the integrated routing layer includes a first width that is wider than the die. devices shown further included a molded routing layer coupled to the integrated routing layer.
20240355725. POWER DELIVERY STRUCTURES_simplified_abstract_(intel corporation)
Inventor(s): Adel Elsherbini of Tempe AZ (US) for intel corporation, Feras Eid of Chandler AZ (US) for intel corporation, Georgios Dogiamis of Chandler AZ (US) for intel corporation, Beomseok Choi of Chandler AZ (US) for intel corporation, Henning Braunisch of Phoenix AZ (US) for intel corporation, William Lambert of Tempe AZ (US) for intel corporation, Krishna Bharath of Chandler AZ (US) for intel corporation, Johanna Swan of Scottsdale AZ (US) for intel corporation
IPC Code(s): H01L23/50, H01L21/48, H01L21/56, H01L23/00, H01L23/31, H01L23/367, H01L23/48, H01L25/00, H01L25/065, H05K1/18
CPC Code(s): H01L23/50
Abstract: an integrated circuit assembly may be fabricated having an electronic substrate, an integrated circuit device having a first surface, an opposing second surface, at least one side extending between the first surface and the second surface, and at least one through-substrate via extending into the integrated circuit device from the second surface, wherein the first surface of the integrated circuit device is electrically attached to the electronic substrate; and at least one power delivery route electrically attached to the second surface of the integrated circuit device and to the electronic substrate, wherein the at least one power delivery route is conformal to the side of the integrated circuit device and the first surface of the electronic substrate.
Inventor(s): Kemal AYGUN of Tempe AZ (US) for intel corporation, Zhiguo QIAN of Chandler AZ (US) for intel corporation, Jianyong XIE of Chandler AZ (US) for intel corporation
IPC Code(s): H01L23/538, H01L21/48, H01L23/00, H01L23/31, H01L23/48, H01L23/498, H01L23/522, H01L23/528, H01L23/532, H01L25/065, H01L25/075, H01L25/16
CPC Code(s): H01L23/5381
Abstract: methods/structures of joining package structures are described. those methods/structures may include a die disposed on a surface of a substrate, an interconnect bridge embedded in the substrate, and at least one vertical interconnect structure disposed through a portion of the interconnect bridge, wherein the at least one vertical interconnect structure is electrically and physically coupled to the die.
Inventor(s): Jeremy Ecton of Gilbert AZ (US) for intel corporation, Gang Duan of Chandler AZ (US) for intel corporation, Jefferson Coker Kaplan of Gilbert AZ (US) for intel corporation, Brandon Christian Marin of Gilbert AZ (US) for intel corporation, Srinivas Venkata Ramanuja Pietambaram of Chandler AZ (US) for intel corporation
IPC Code(s): H01L23/538, H01L23/00, H01L23/15, H01L25/16
CPC Code(s): H01L23/5385
Abstract: disaggregated package substrates with glass cores are disclosed. an example package substrate includes a glass core having a first side and a second side opposite the first side. the example package substrate further includes a first block of redistribution layers on the first side of the glass core. the example package substrate also includes a second block of redistribution layers on the first side of the glass core. the first block is distinct from the second block.
Inventor(s): Adel A. ELSHERBINI of Tempe AZ (US) for intel corporation, Amr ELSHAZLY of Hillsboro OR (US) for intel corporation, Arun CHANDRASEKHAR of Chandler AZ (US) for intel corporation, Shawna M. LIFF of Scottsdale AZ (US) for intel corporation, Johanna M. SWAN of Scottsdale AZ (US) for intel corporation
IPC Code(s): H01L23/538, H01L23/00, H01L25/00
CPC Code(s): H01L23/5385
Abstract: microelectronic assemblies, and related devices and methods, are disclosed herein. for example, in some embodiments, a microelectronic assembly may include a package substrate, a first die coupled to the package substrate with first interconnects, and a second die coupled to the first die with second interconnects, wherein the second die is coupled to the package substrate with third interconnects, a communication network is at least partially included in the first die and at least partially included in the second die, and the communication network includes a communication pathway between the first die and the second die.
Inventor(s): Sanjay THARMARAJAH of Queen Creek AZ (US) for intel corporation, Hiroki TANAKA of Gilbert AZ (US) for intel corporation, Clayton BRENNER of Chandler AZ (US) for intel corporation
IPC Code(s): H01L23/538, H01L21/48
CPC Code(s): H01L23/5386
Abstract: embodiments disclosed herein include an electronic package. in an embodiment, the electronic package comprises a substrate and a pad on the substrate. in an embodiment, a layer is over the pad and the substrate, and an opening through the layer is above the pad. in an embodiment, sidewalls of the layer define the opening. in an embodiment, an undercut at an end of the opening adjacent to the pad is provided, where the undercut is positioned between the pad and the layer. in an embodiment, a bump is in the opening, where the bump at least partially fills the undercut
Inventor(s): Telesphor KAMGAING of Chandler AZ (US) for intel corporation
IPC Code(s): H01L23/538, H01L21/48, H01L23/15
CPC Code(s): H01L23/5386
Abstract: embodiments disclosed herein include a package substrate. in an embodiment, the package substrate comprises a core with a first surface and a second surface, where the core comprises a glass layer. in an embodiment, a first routing layer is over the first surface of the core, where the first routing layer comprises traces with a first width. in an embodiment, a second routing layer is over the second surface of the core, where the second routing layer comprises traces with a second width that is smaller than the first width.
Inventor(s): Steven Adam Klein of Chandler AZ (US) for intel corporation, Jason Gamba of Gilbert AZ (US) for intel corporation, Matthew Thomas Guzy of Phoenix AZ (US) for intel corporation, Nicholas Steven Haehn of Scottsdale AZ (US) for intel corporation, Tarek Adly Ibrahim of Mesa AZ (US) for intel corporation, Brandon Christian Marin of Gilbert AZ (US) for intel corporation, Srinivas Venkata Ramanuja Pietambaram of Chandler AZ (US) for intel corporation, Jacob John Schichtel of Chandler AZ (US) for intel corporation
IPC Code(s): H01L23/544, H01L23/15, H01L23/40
CPC Code(s): H01L23/544
Abstract: systems, apparatus, articles of manufacture, and methods to reduce stress between sockets and associated integrated circuit packages having glass cores are disclosed. an example integrated circuit package includes: a semiconductor die, and a substrate including a glass core. the substrate includes a first surface, a second surface opposite the first surface, and a third surface between the first surface and the second surfaces. the first surface supports the semiconductor die. the second surface includes first contacts to electrical couple with second contacts in a socket. at least a portion of the third surface separated and distinct from the glass core.
Inventor(s): Phil Geng of Washougal WA (US) for intel corporation, Baris Bicen of Chandler AZ (US) for intel corporation, Kai Xiao of Portland OR (US) for intel corporation, Sanjoy Saha of Portland OR (US) for intel corporation, Prasanna Raghavan of Chandler AZ (US) for intel corporation
IPC Code(s): H01L23/00
CPC Code(s): H01L23/562
Abstract: damping structures in integrated circuit (ic) devices, and techniques for forming the structures are discussed. an ic device includes, between an ic package and a socket, both a spring force and a damping structure adjacent an array of pins and corresponding lands. the damping structure may be of a dissipative, viscous, or viscoelastic material. the damping structure may be between the ic package and socket. the damping structure may be within a periphery of the socket. the damping structure may be coupled to the ic package or the socket by an adhesive or a press fit. a heatsink or a heat spreader may be coupled to the ic package over the socket.
Inventor(s): Adel A. Elsherbini of Chandler AZ (US) for intel corporation, Krishna Bharath of Phoenix AZ (US) for intel corporation, Kevin P. O'Brien of Portland OR (US) for intel corporation, Kimin Jun of Portland OR (US) for intel corporation, Han Wui Then of Portland OR (US) for intel corporation, Mohammad Enamul Kabir of Portland OR (US) for intel corporation, Gerald S. Pasdast of San Jose CA (US) for intel corporation, Feras Eid of Chandler AZ (US) for intel corporation, Aleksandar Aleksov of Chandler AZ (US) for intel corporation, Johanna M. Swan of Scottsdale AZ (US) for intel corporation, Shawna M. Liff of Scottsdale AZ (US) for intel corporation
IPC Code(s): H01L23/00, H01L25/065
CPC Code(s): H01L24/08
Abstract: disclosed herein are microelectronic assemblies including microelectronic components that are coupled together by direct bonding, as well as related structures and techniques. for example, in some embodiments, a microelectronic assembly may include a first microelectronic component and a second microelectronic component coupled to the first microelectronic component by a direct bonding region, wherein the direct bonding region includes at least part of an inductor.
Inventor(s): Sameer SHEKHAR of Portland OR (US) for intel corporation, Amit JAIN of Sherwood OR (US) for intel corporation
IPC Code(s): H01L25/065, H01L23/427, H01L23/552, H03H1/00, H03H7/01
CPC Code(s): H01L25/0652
Abstract: embodiments disclosed herein include electronic packages and their components. in an embodiment, an electronic package comprises a package substrate and a base die over the package substrate. in an embodiment, the electronic package further comprises a plurality of chiplets over the base die. in an embodiment, the base die comprises a substrate, a first metal layer and a second metal layer between the substrate and the plurality of chiplets, and a third metal layer and a fourth metal layer between the package substrate and the substrate. in an embodiment, a filter is integrated into one or more layers of the base die.
Inventor(s): Poh Boon KHOO of Perai (MY) for intel corporation, Jiun Hann SIR of Gelugor (MY) for intel corporation, Eng Huat GOH of Air Itam (MY) for intel corporation, Hooi San LAM of Air Itam (MY) for intel corporation, Hazwani JAFFAR of Kepala Batas (MY) for intel corporation
IPC Code(s): H01L25/10, H01L23/00, H01L23/498, H01L23/538, H10B80/00
CPC Code(s): H01L25/105
Abstract: embodiments disclosed herein include electronic packages. in an example, an electronic package includes a package substrate. a die is coupled to the package substrate. the electronic package also includes a memory stack. the memory stack includes a die stack structure coupled to a substrate. the substrate is coupled to and is extending laterally beyond the package substrate. the die stack structure includes a stack of dies and through vias in a mold layer. the die stack structure is laterally spaced apart from the package substrate.
Inventor(s): Quan SHI of Beaverton OR (US) for intel corporation, Sukru YEMENICIOGLU of Portland OR (US) for intel corporation, Marni NABORS of Portland OR (US) for intel corporation, Nikolay RYZHENKO of Beaverton OR (US) for intel corporation, Xinning WANG of Portland OR (US) for intel corporation, Sivakumar VENKATARAMAN of Hillsboro OR (US) for intel corporation
IPC Code(s): H01L27/088, H01L23/50, H01L29/06, H01L29/78
CPC Code(s): H01L27/0886
Abstract: integrated circuit structures having front side signal lines and backside power delivery are described. in an example, an integrated circuit structure includes a plurality of gate lines extending over a plurality of semiconductor nanowire stack or fin channel structures within a cell boundary. a plurality of trench contacts is extending over a plurality of source or drain structures within the cell boundary, individual ones of the plurality of trench contacts alternating with individual ones of the plurality of gate lines. a first signal line, a second signal line, a third signal line, and a fourth signal line are over the plurality of gate lines and the plurality of trench contacts within the cell boundary. a backside power delivery line is coupled to one of the plurality of trench contacts within the cell boundary.
20240355876. NANORIBBON-BASED TRANSISTOR WITH UNIFORM OXIDE_simplified_abstract_(intel corporation)
Inventor(s): Siddharth Gupta of Hillsboro OR (US) for intel corporation, Robin Chao of Portland OR (US) for intel corporation, Jay Prakash Gupta of Hillsboro OR (US) for intel corporation, Aravind Killampalli of Portland OR (US) for intel corporation, Biswajeet Guha of Hillsboro OR (US) for intel corporation
IPC Code(s): H01L29/06, H01L21/8238, H01L27/092, H01L29/423
CPC Code(s): H01L29/0665
Abstract: described herein are nanoribbon-based transistors with a highly uniform oxide layer around semiconductor nanoribbon channels, and a high-pressure steam process for growth the oxide layer. the high-pressure steam process is a self-limiting process that results in a more uniform oxide than standard deposition or implantation methods. the uniformity enables greater control over oxide thickness, with improved breakdown voltages and drive currents.
Inventor(s): Leonard P. Guler of Hillsboro OR (US) for intel corporation, Shengsi Liu of Portland OR (US) for intel corporation, Saurabh Acharya of Hillsboro OR (US) for intel corporation, Baofu Zhu of Portland OR (US) for intel corporation, Meenakshisundaram Ramanathan of Hillsboro OR (US) for intel corporation, Charles H. Wallace of Portland OR (US) for intel corporation, Ankit Kirit Lakhani of Hillsboro OR (US) for intel corporation
IPC Code(s): H01L29/417, H01L27/092, H01L29/06, H01L29/423, H01L29/778, H01L29/786
CPC Code(s): H01L29/41733
Abstract: techniques are provided herein to form semiconductor devices that include a conductive bridge between topside contacts on adjacent source or drain regions. the conductive bridge extends through a dielectric wall that separates the adjacent source or drain regions. in an example, a first semiconductor device includes a first gate structure around or otherwise on a first semiconductor region (or channel region) that extends from a first source or drain region, and a second adjacent semiconductor device includes a second gate structure around or otherwise on a second semiconductor region that extends from a second source or drain region. a conductive bridge connects a first conductive contact on a top surface of the first source or drain region with a second conductive contact on a top surface of the adjacent second source or drain region through a dielectric wall that otherwise separates the conductive contacts.
Inventor(s): Leonard P. Guler of Hillsboro OR (US) for intel corporation, Shengsi Liu of Portland OR (US) for intel corporation, Saurabh Acharya of Hillsboro OR (US) for intel corporation, Baofu Zhu of Portland OR (US) for intel corporation, Meenakshisundaram Ramanathan of Hillsboro OR (US) for intel corporation, Charles H. Wallace of Portland OR (US) for intel corporation, Ankit Kirit Lakhani of Hillsboro OR (US) for intel corporation
IPC Code(s): H01L29/417, H01L27/092, H01L29/06, H01L29/423, H01L29/778, H01L29/786
CPC Code(s): H01L29/41733
Abstract: techniques are provided herein to form semiconductor devices that include a conductive bridge between topside contacts on adjacent source or drain regions. the conductive bridge extends through a dielectric wall that separates the adjacent source or drain regions. in an example, a first semiconductor device includes a first gate structure around or otherwise on a first semiconductor region (or channel region) that extends from a first source or drain region, and a second adjacent semiconductor device includes a second gate structure around or otherwise on a second semiconductor region that extends from a second source or drain region. a conductive bridge connects a first conductive contact on a top surface of the first source or drain region with a second conductive contact on a top surface of the adjacent second source or drain region through a dielectric wall that otherwise separates the conductive contacts.
Inventor(s): Biswajeet GUHA of Hillsboro OR (US) for intel corporation, Dax M. CRUM of Beaverton OR (US) for intel corporation, Stephen M. CEA of Hillsboro OR (US) for intel corporation, Leonard P. GULER of Hillsboro OR (US) for intel corporation, Tahir GHANI of Portland OR (US) for intel corporation
IPC Code(s): H01L29/66, H01L21/28, H01L21/762, H01L21/8234, H01L21/84, H01L27/12, H01L29/06, H01L29/423, H01L29/78, H01L29/786
CPC Code(s): H01L29/6653
Abstract: self-aligned gate endcap (sage) architectures with gate-all-around devices above insulator substrates, and methods of fabricating self-aligned gate endcap (sage) architectures with gate-all-around devices above insulator substrates, are described. in an example, an integrated circuit structure includes includes a semiconductor nanowire above an insulator substrate and having a length in a first direction. a gate structure is around the semiconductor nanowire, the gate structure having a first end opposite a second end in a second direction, orthogonal to the first direction. a pair of gate endcap isolation structures is included. the first of the pair of gate endcap isolation structures is directly adjacent to the first end of the gate structure, and the second of the pair of gate endcap isolation structures is directly adjacent to the second end of the gate structure.
Inventor(s): Leonard P. Guler of Hillsboro OR (US) for intel corporation, Clifford J. Engel of Hillsboro OR (US) for intel corporation, Debaleena Nandi of Hillsboro OR (US) for intel corporation, Gary Allen of Portland OR (US) for intel corporation, Nicholas A. Thomson of Hillsboro OR (US) for intel corporation, Saurabh Acharya of Hillsboro OR (US) for intel corporation, Umang Desai of Portland OR (US) for intel corporation, Vivek Vishwakarma of Hillsboro OR (US) for intel corporation, Charles H. Wallace of Portland OR (US) for intel corporation
IPC Code(s): H01L29/775, H01L27/088, H01L29/06, H01L29/423
CPC Code(s): H01L29/775
Abstract: techniques are provided herein to form an integrated circuit that includes one or more backside conductive structures that extend through the device layer to contact one or more frontside contacts, such as frontside source or drain contacts. in an example, a given semiconductor device along a row of such devices may be separated from an adjacent semiconductor device along the row by a gate cut. the gate cut may be a dielectric wall that extends through an entire thickness of the gate structure around the semiconductor regions of the devices and also extends between source or drain regions of the devices. a backside conductive structure may extend through portions of the source or drain regions and also through a portion of one of the dielectric walls within the gate trench to contact one or more frontside contacts on the source or drain regions.
Inventor(s): Mahmut Sami Kavrik of Eugene OR (US) for intel corporation, Tristan A. Tronic of Aloha OR (US) for intel corporation, Jennifer Lux of Hillsboro OR (US) for intel corporation, Uygar E. Avci of Portland OR (US) for intel corporation, Kevin P. O'Brien of Portland OR (US) for intel corporation
IPC Code(s): H01L29/786, H01L29/66
CPC Code(s): H01L29/78696
Abstract: described herein are transistors with monolayer transition metal dichalcogenides (tmd) semiconductor material. tmd materials include combination of a transition metal (e.g., molybdenum or tungsten) and a chalcogen (e.g., sulfur or selenium) in a monolayer having a hexagonal crystal structure. a transistor has a single layer of tmd forming a channel region, and multiple layers of the tmd material at the source and drain regions. upper portions of the multilayer tmd source and drain regions are doped, and conductive contacts are formed over the doped portions.
Inventor(s): Daniel Klowden of Portland OR (US) for intel corporation, Joshua Fryman of Corvallis OR (US) for intel corporation
IPC Code(s): H01L33/62, H01L33/58
CPC Code(s): H01L33/62
Abstract: an ic package may include a stack of microelectronic units capable of horizontal and vertical optical communications. a microelectronic unit includes one or more power delivery pillars, two light source layers, an optical interconnect layer between the light source layers, and one or more ic devices arranged on the optical interconnect layer. a light source layer includes micro-leds that emit light used for generating optical signals. the optical interconnect layer includes one or more optical interconnects that enable horizontal optical communication, e.g., transmission of optical signals between the ic devices. a light source layer in the microelectronic unit can facilitate optical communications with another microelectronic unit that is below or above the microelectronic unit. a channel may exist above or below the light source layer to promote dissipation of heat generated by the ic devices. light from the light source layer may pass through the channel for vertical optical communication.
Inventor(s): Sidharth Dalmia of Portland OR (US) for intel corporation, Trang Thai of Hillsboro OR (US) for intel corporation
IPC Code(s): H01Q1/22, H01L23/66, H01Q9/04, H01Q21/06
CPC Code(s): H01Q1/2283
Abstract: disclosed herein are antenna boards, integrated circuit (ic) packages, antenna modules, and communication devices. for example, in some embodiments, an antenna module may include: an ic package having a die and a package substrate, and the package substrate has a recess therein; and an antenna patch, coupled to the package substrate, such that the antenna patch is over or at least partially in the recess.
20240356552. LOW CONTENTION CURRENT CIRCUITS_simplified_abstract_(intel corporation)
Inventor(s): Steven Hsu of Lake Oswego OR (US) for intel corporation, Amit Agarwal of Hillsboro OR (US) for intel corporation, Ram Krishnamurthy of Portland OR (US) for intel corporation
IPC Code(s): H03K19/0185, G06F3/06, G11C11/418, G11C11/419, H03K19/21
CPC Code(s): H03K19/018521
Abstract: a disclosed example includes a read local bitline; and a plurality of pulldown transistor circuits coupled to the read local bitline, a first one of the pulldown transistor circuits including: a first low threshold voltage transistor, the first low threshold voltage transistor including a first drain terminal coupled to the read local bitline; and a second low threshold voltage transistor, the second low threshold voltage transistor including a second drain terminal coupled to a first source terminal of the first low threshold voltage transistor, the second low threshold voltage transistor to persist a voltage level detectable at a gate terminal of the second low threshold voltage transistor, the voltage level representative of a bit of information.
20240356739. RANGE CONSTRAINED DEVICE CONFIGURATION_simplified_abstract_(intel corporation)
Inventor(s): Mats Agerstam of Portland OR (US) for intel corporation, Venkata R. Vallabhu of Portland OR (US) for intel corporation
IPC Code(s): H04L9/08, H04L9/40, H04L41/0803, H04L41/28, H04L67/00, H04L67/12, H04L67/141, H04L67/51, H04L69/14, H04W4/70, H04W4/80, H04W8/00, H04W12/02, H04W12/037, H04W12/04, H04W12/0471, H04W52/38, H04W76/11, H04W76/14, H04W88/06, H04W88/12
CPC Code(s): H04L9/0841
Abstract: disclosed in some examples are methods, systems, and machine readable mediums for secure, low end-user effort computing device configuration. in some examples the iot device is configured via a user's computing device over a short range wireless link of a first type. this short range wireless communication may use a connection establishment that does not require end-user input. for example, the end user will not have to enter, or confirm a pin number or other authentication information such as usernames and/or passwords. this allows configuration to involve less user input. in some examples, to prevent man-in-the-middle attacks, the power of a transmitter in the iot device that transmits the short range wireless link is reduced during a configuration procedure so that the range of the transmissions to and from the user's computing device are reduced to a short distance.
Inventor(s): Patrick L. Connor of Beaverton OR (US) for intel corporation, Marcos Emanuel Carranza of Portland OR (US) for intel corporation, Cesar Ignacio Martinez-Spessot of Hillsboro OR (US) for intel corporation, Mateo Guzman of Beaverton OR (US) for intel corporation, Mariano Ortega de Mues of Hillsboro OR (US) for intel corporation
IPC Code(s): H04L41/0803, H04L41/085
CPC Code(s): H04L41/0803
Abstract: methods, apparatus, systems, and articles of manufacture to manage configuration assets for network devices are disclosed. example instructions cause at least one programmable circuit to generate network infrastructure instructions using a model, the network infrastructure instructions based on a configuration request and on a network infrastructure; and deploy a program corresponding to the network infrastructure instructions to at least one device in the network infrastructure.
Inventor(s): Abhishek Chakraborty of Hillsboro OR (US) for intel corporation, Chen Liu of Portland OR (US) for intel corporation, Jason Mou Lap Fung of Portland OR (US) for intel corporation
IPC Code(s): H04L41/5009, H04L43/08
CPC Code(s): H04L41/5009
Abstract: systems, apparatus, articles of manufacture, and methods are disclosed to verify integrity of model execution on computing resources using telemetry information. an example apparatus includes machine-readable instructions, and at least one processor circuit to be programmed by the machine-readable instructions to instruct one or more first computing resources of a service provider to process a first model, compare first telemetry performance metrics received from the service provider with second telemetry performance metrics associated with baseline computing resources, and verify an integrity score of the service provider based on a similarity metric associated with the first telemetry performance metrics and the second telemetry performance metrics.
Inventor(s): Kevin Safford of Fort Collins CO (US) for intel corporation, Victor Ruybalid of Beaverton OR (US) for intel corporation
IPC Code(s): H04L49/109, G06F13/42, H04L12/44, H04L45/02, H04L45/16, H04L45/48
CPC Code(s): H04L49/109
Abstract: embodiments include apparatuses, methods, and systems of routing network containing a set of sources, a primary destination, a set of secondary destinations, and one or more routing elements. a routing element includes an input port, a set of output ports including a primary output port and a set of secondary output ports, and a control unit. the control unit is arranged to select a secondary output port to deliver a received message when the intended destination of the message is a secondary destination and the secondary output port is in a functional state. otherwise, the control unit is arranged to select the primary output port to deliver the received message to the primary destination when the intended destination is the secondary destination and the secondary output port that reaches the secondary destination is in a nonfunctional state. other embodiments may also be described and claimed.
20240357138. HUMAN VISUAL SYSTEM ADAPTIVE VIDEO CODING_simplified_abstract_(intel corporation)
Inventor(s): Ximin Zhang of San Jose CA (US) for intel corporation, Sang-Hee Lee of San Jose CA (US) for intel corporation, Keith Rowe of Shingle Springs CA (US) for intel corporation
IPC Code(s): H04N19/196, H04N19/124, H04N19/14, H04N19/176, H04N19/177
CPC Code(s): H04N19/196
Abstract: an example apparatus for encoding video frames includes a mask selector to select a subset of visual masks according to an actual target compression ratio and gop configuration and a complexity estimator to estimate a picture level spatial/temporal complexity for a current frame. the example apparatus further includes a gop adaptive visual mask selector to specify a visual mask from the subset of the visual masks corresponding to the estimated spatial and temporal complexity value a good enough picture qp deriver to derive a good enough picture qp value using the visual mask. the example apparatus also includes an adjustor to adjust the good enough picture qp value based on block level human visual system sensitivity and statistics of already encoded frames to obtain a final human visual system qp map.
Inventor(s): Yunbiao Lin of shanghai (CN) for intel corporation, Changliang Wang of Bellevue WA (US) for intel corporation, Ce Wang of Bellevue WA (US) for intel corporation, Yongfa Zhou of Beijing (CN) for intel corporation, Bo Zhao of Shanghai 31 (CN) for intel corporation, Ping Liu of Sunnyvale CA (US) for intel corporation, Jianwei Yang of Beijing (CN) for intel corporation, Zhan Lou of Shanghai (CN) for intel corporation, Yu Yang of Beijing (CN) for intel corporation, Yating Wang of Beijing (CN) for intel corporation, Wenyi Tang of Beijing 11 (CN) for intel corporation, Bo Qiu of Hillsboro OR (US) for intel corporation
IPC Code(s): H04N19/527, H04N19/154, H04N19/167, H04N19/176, H04N19/189, H04N19/52, H04N21/6587, H04N13/161
CPC Code(s): H04N19/527
Abstract: an embodiment of an adaptive video encoder may determine headset-related information including at least one of focus-related information and motion-related information and determine one or more video encode parameters based on the headset-related information. the adaptive video encoder may also encode a macroblock of a video image based on the one or more determined video encode parameters. other embodiments are disclosed and claimed.
Inventor(s): Adam Kupryjanow of Gdansk (PL) for intel corporation, Jan Banas of Gdansk (PL) for intel corporation, Pawel Trella of Gdansk (PL) for intel corporation
IPC Code(s): H04R3/00, H04M3/56, H04R29/00
CPC Code(s): H04R3/005
Abstract: techniques are provided herein for auto-muting procedures that result in efficient high-quality audio capture in a multi-device environment. in particular, when there are multiple computing devices in a shared meeting room, the microphone with the highest rated audio input is selected for the teleconference audio input from the shared environment. each computing device connected to the teleconference from the meeting room determines a score for its microphone signal. the score is shared with the other devices in the room, and the microphone signal with the highest score is transmitted to the conference. host-based systems include a host device receiving and reviewing the scores and determining which microphones to auto-mute. other distributed systems include each computing device transmitting its score to the other devices and receiving the scores from the other devices, and each device determining whether to auto-mute.
20240357413. DELAY MEASUREMENTS BETWEEN GNB-CU AND GNB-DU_simplified_abstract_(intel corporation)
Inventor(s): Jaemin Han of Portland OR (US) for intel corporation, Ziyi Li of Beijing (CN) for intel corporation
IPC Code(s): H04W28/02, H04L43/0852
CPC Code(s): H04W28/0236
Abstract: a computer-readable storage medium stores instructions for execution by one or more processors of a base station. the instructions configure the base station for 5g-nr qos monitoring and reporting and cause the base station to encode a downlink user data frame for transmission from a cu-up to a du of the base station. the downlink user data frame includes an indicator requesting a delivery status for a downlink data transmission. a downlink data delivery status frame is encoded for transmission from the du to the cu-up using an f1-u interface. the downlink data delivery status frame includes a feedback delay measured at the du based on the indicator. the feedback delay indicates a time between reception of the downlink user data frame and transmission of the downlink data delivery status frame. a downlink or uplink delay associated with the f1-u interface is determined based on the feedback delay.
Inventor(s): Cheng Chen of Camas WA (US) for intel corporation, Laurent Cariou of Milizac (FR) for intel corporation, Carlos Cordeiro of Camas WA (US) for intel corporation
IPC Code(s): H04W74/0816, H04W74/04, H04W74/08
CPC Code(s): H04W74/0816
Abstract: for example, an apparatus may include logic and circuitry configured to cause a sensing initiator station (sta) to transmit one or more timeslot-scheduling frames over a sub 10 gigahertz (ghz) (sub-10 ghz) wireless communication frequency band to schedule one or more timeslots of a coordinated monostatic millimeterwave (mmwave) sensing measurement exchange for a plurality of sensing responder stas; to transmit a trigger frame over an mmwave wireless communication frequency band during a timeslot of the one or more timeslots; and to process a frame from a sensing responder sta to participate in a monostatic sounding during the timeslot, the frame from the sensing responder sta received over the mmwave wireless communication frequency band during the timeslot.
Inventor(s): Rick Canham of West Richland WA (US) for intel corporation, Jeffory L. Smalley of Olympia WA (US) for intel corporation, Steven Adam Klein of Chandler AZ (US) for intel corporation, Shelby Ann Ferguson of El Dorado Hills CA (US) for intel corporation
IPC Code(s): H05K1/11, H05K1/02, H05K5/00
CPC Code(s): H05K1/117
Abstract: integrated circuit packages including carriers with incorporated substrates and interfaces are disclosed herein. an integrated circuit package carrier disclosed herein includes a frame including an opening to receive an integrated circuit package and at least one of (1) a circuitry component on a substrate on a surface of the frame or (2) a cable interface directly coupled to the frame.
Inventor(s): Berhanu Wondimu of Beaverton OR (US) for intel corporation, David Shia of Portland OR (US) for intel corporation, Xudong Tang of Sammamish WA (US) for intel corporation
IPC Code(s): H05K7/20, B23P15/26, G05B19/042, G06F1/20
CPC Code(s): H05K7/20781
Abstract: methods, systems, and apparatus described herein relate to a conformable cold plate for fluid cooling applications. an example method includes re-shaping a tube to contour non-uniform surfaces; and assembling a fluid cooling assembly using the re-shaped tube, the re-shaped tube capable to transfer fluid for cooling of one or more devices.
- Intel Corporation
- B25J9/16
- CPC B25J9/163
- Intel corporation
- B25J5/00
- G05D1/246
- CPC B25J9/1664
- C01B33/158
- C01B33/159
- C09D183/04
- G06F1/20
- H05K5/02
- CPC C01B33/1585
- G02B6/42
- G02B6/122
- G02B6/132
- H01L25/16
- CPC G02B6/4206
- G05F3/30
- CPC G05F3/30
- G06F1/3234
- G06F1/3206
- G06F1/324
- G06F1/3287
- G06F1/3296
- G06F13/16
- G06F13/40
- CPC G06F1/3253
- G06F3/14
- G06F3/01
- G06F3/0484
- G09G5/00
- G09G5/391
- CPC G06F3/1438
- G06F7/523
- CPC G06F7/523
- G06F9/30
- G06F9/32
- G06F9/38
- CPC G06F9/30047
- CPC G06F9/3016
- G06F9/50
- CPC G06F9/5027
- G06F11/10
- CPC G06F11/1016
- G06F11/20
- G06F1/30
- G06F11/16
- G11C29/00
- CPC G06F11/2094
- G06F11/22
- G06F11/273
- CPC G06F11/2221
- G06F17/16
- CPC G06F17/16
- G06N3/063
- G06F9/46
- G06N3/044
- G06N3/045
- G06N3/084
- G06N5/01
- CPC G06N3/063
- G06N20/00
- H04L41/16
- CPC G06N20/00
- G06T1/20
- G06F16/907
- G06T7/90
- CPC G06T1/20
- G06T3/12
- G06T3/16
- H04N23/698
- CPC G06T3/12
- G06T15/00
- G06T15/04
- G06T15/80
- G06T17/10
- CPC G06T15/005
- G06T15/06
- G06T7/557
- G06T15/50
- CPC G06T15/06
- G06T17/00
- CPC G06T17/00
- G06V10/82
- G06T7/20
- CPC G06V10/82
- G06F1/10
- CPC G09G5/006
- H01L21/48
- H01L23/498
- CPC H01L21/4857
- H01L21/84
- H01L29/06
- H01L29/423
- H01L29/78
- H10B51/10
- H10B51/30
- CPC H01L21/845
- H01L23/31
- H01L21/56
- H01L21/66
- H01L21/78
- H01L23/00
- H01L23/538
- CPC H01L23/3192
- H01L23/50
- H01L23/367
- H01L23/48
- H01L25/00
- H01L25/065
- H05K1/18
- CPC H01L23/50
- H01L23/522
- H01L23/528
- H01L23/532
- H01L25/075
- CPC H01L23/5381
- H01L23/15
- CPC H01L23/5385
- CPC H01L23/5386
- H01L23/544
- H01L23/40
- CPC H01L23/544
- CPC H01L23/562
- CPC H01L24/08
- H01L23/427
- H01L23/552
- H03H1/00
- H03H7/01
- CPC H01L25/0652
- H01L25/10
- H10B80/00
- CPC H01L25/105
- H01L27/088
- CPC H01L27/0886
- H01L21/8238
- H01L27/092
- CPC H01L29/0665
- H01L29/417
- H01L29/778
- H01L29/786
- CPC H01L29/41733
- H01L29/66
- H01L21/28
- H01L21/762
- H01L21/8234
- H01L27/12
- CPC H01L29/6653
- H01L29/775
- CPC H01L29/775
- CPC H01L29/78696
- H01L33/62
- H01L33/58
- CPC H01L33/62
- H01Q1/22
- H01L23/66
- H01Q9/04
- H01Q21/06
- CPC H01Q1/2283
- H03K19/0185
- G06F3/06
- G11C11/418
- G11C11/419
- H03K19/21
- CPC H03K19/018521
- H04L9/08
- H04L9/40
- H04L41/0803
- H04L41/28
- H04L67/00
- H04L67/12
- H04L67/141
- H04L67/51
- H04L69/14
- H04W4/70
- H04W4/80
- H04W8/00
- H04W12/02
- H04W12/037
- H04W12/04
- H04W12/0471
- H04W52/38
- H04W76/11
- H04W76/14
- H04W88/06
- H04W88/12
- CPC H04L9/0841
- H04L41/085
- CPC H04L41/0803
- H04L41/5009
- H04L43/08
- CPC H04L41/5009
- H04L49/109
- G06F13/42
- H04L12/44
- H04L45/02
- H04L45/16
- H04L45/48
- CPC H04L49/109
- H04N19/196
- H04N19/124
- H04N19/14
- H04N19/176
- H04N19/177
- CPC H04N19/196
- H04N19/527
- H04N19/154
- H04N19/167
- H04N19/189
- H04N19/52
- H04N21/6587
- H04N13/161
- CPC H04N19/527
- H04R3/00
- H04M3/56
- H04R29/00
- CPC H04R3/005
- H04W28/02
- H04L43/0852
- CPC H04W28/0236
- H04W74/0816
- H04W74/04
- H04W74/08
- CPC H04W74/0816
- H05K1/11
- H05K1/02
- H05K5/00
- CPC H05K1/117
- H05K7/20
- B23P15/26
- G05B19/042
- CPC H05K7/20781
