Intel Corporation patent applications on October 10th, 2024
Patent Applications by Intel Corporation on October 10th, 2024
Intel Corporation: 16 patent applications
Intel Corporation has applied for patents in the areas of H01L23/538 (3), G06N3/08 (2), H01L25/065 (2), G06F9/455 (2), H01L23/31 (1) G06N3/08 (2), B25J9/1671 (1), G01R31/318541 (1), G06F3/1415 (1), G06F8/65 (1)
With keywords such as: data, based, input, signal, apparatus, instructions, version, substrate, size, and include in patent application abstracts.
Patent Applications by Intel Corporation
Inventor(s): Norbert STOEFFLER of Graefelfing (DE) for intel corporation, Florian GEISSLER of Munich (DE) for intel corporation, Michael PAULITSCH of Ottobrunn (DE) for intel corporation
IPC Code(s): B25J9/16, B25J19/02
CPC Code(s): B25J9/1671
Abstract: the apparatus for the autonomously acting machine comprises an interface for communicating with a computer system, wherein the computer system is separate from the autonomously acting machine. the apparatus includes a processor for executing machine-readable instructions for providing information about an internal state of the autonomously acting machine to the computer system, obtaining a feedback signal from the computer system, the feedback signal indicating whether sensor data for observing the autonomously acting machine is consistent with the internal state of the autonomously acting machine, and wherein the feedback signal is based on a comparison between a digital twin of the autonomously acting machine and the sensor data, wherein an internal state of the digital twin is based on the internal state of the autonomously acting machine, and operating the autonomously acting machine based on the feedback signal.
20240337692. Configurable Storage Circuits And Methods_simplified_abstract_(intel corporation)
Inventor(s): Rajiv Kumar of Tanjung Tokong (MY) for intel corporation, Amit Agarwal of Hillsboro OR (US) for intel corporation, Steven Hsu of Lake Oswego OR (US) for intel corporation, Scott Weber of Piedmont CA (US) for intel corporation
IPC Code(s): G01R31/3185
CPC Code(s): G01R31/318541
Abstract: a flip-flop circuit includes first and second storage circuits. the flip-flop circuit is configurable to store first values of a data signal in the first storage circuit in response to rising edges of a clock signal and to store second values of the data signal in the second storage circuit in response to falling edges of the clock signal during a double edge triggered mode. the flip-flop circuit is configurable to store third values of the data signal in the first storage circuit and to output the third values from the first storage circuit in response to the clock signal during a single edge triggered mode.
20240338161. AUTOMATIC DETECTION OF DISPLAY LAYOUT_simplified_abstract_(intel corporation)
Inventor(s): Jose Rodrigo CAMACHO PEREZ of Guadalajara (MX) for intel corporation, Julio Cesar ZAMORA ESQUIVEL of West Sacramento CA (US) for intel corporation, Mario Ivan LOPEZ VALDOVINOS of Zapopan (MX) for intel corporation, Héctor Alfonso CORDOURIER MARURI of Guadalajara (MX) for intel corporation, Paulo LOPEZ MEYER of Zapopan (MX) for intel corporation, Alejandro IBARRA VON BORSTEL of Manchaca TX (US) for intel corporation
IPC Code(s): G06F3/14, H04W4/80
CPC Code(s): G06F3/1415
Abstract: a system that includes at least one memory and at least one processor, communicatively coupled to the at least one memory. in some examples, the at least one processor is to execute instructions stored on the at least one memory that cause the at least one processor to: determine a location of at least one display based on radiation and/or emitted image.
Inventor(s): Dan HOROVITZ of Rishon Lezion (IL) for intel corporation, Igor METRIK of MEVASERET ZION (IL) for intel corporation, Omer BEN-SHALOM of Rishon Le-Tzion (IL) for intel corporation, Ilil BLUM SHEM-TOV of Kiryat Tivon (IL) for intel corporation, Ofer RIVLIN of Tel-Aviv (IL) for intel corporation
IPC Code(s): G06F8/65, G06F8/61
CPC Code(s): G06F8/65
Abstract: a method and apparatus for anti-rollback protection for a non-persistent software in a system. a software install package includes a main version of software and a fallback version of the software. the fallback version of the software includes a vulnerable versions list that includes a list of vulnerable versions of the software determined up to a release date of the fallback version of the software. the fallback version of the software is stored in the system. the main version of the software is installed if the main version of the software is not listed in the vulnerable versions list. the fallback version may be updated automatically if the new fallback version higher than the existing fallback version is received. the fallback version is stored in a fallback versions' repository by an operating system or installer. the fallback version may include an allowed versions list.
20240338238. HOST TO GUEST NOTIFICATION_simplified_abstract_(intel corporation)
Inventor(s): Wei Wang of Shanghai (CN) for intel corporation, Kun Tian of Shanghai (CN) for intel corporation, Guang Zeng of Shanghai (CN) for intel corporation, Gilbert Neiger of Portland OR (US) for intel corporation, Rajesh Sankaran of Portland OR (US) for intel corporation, Asit Mallick of Saratoga CA (US) for intel corporation, Jr-Shian Tsai of Portland OR (US) for intel corporation, Jacob Jun Pan of Portland OR (US) for intel corporation, Mesut Ergin of Portland OR (US) for intel corporation
IPC Code(s): G06F9/455, G06F9/30
CPC Code(s): G06F9/45558
Abstract: a method and system of host to guest (h2g) notification are disclosed. h2g is provided via an instruction. the instruction is a send user inter-processor interrupt instruction. an exemplary processor includes decoder circuitry to decode a single instruction and execute the decoded single instruction according to the at least the opcode to cause a host to guest notification from a virtual device running in a host machine on the first physical processor to a virtual device driver running on a virtual processor in a guest machine on a second physical processor.
Inventor(s): Utkarsh Y. Kakaiya of El Dorado Hills CA (US) for intel corporation, Sanjay Kumar of Hillsboro OR (US) for intel corporation, Rajesh M. Sankaran of Portland OR (US) for intel corporation, Philip R. Lantz of Cornelius OR (US) for intel corporation, Ashok Raj of Portland OR (US) for intel corporation, Kun Tian of Shanghai (CN) for intel corporation
IPC Code(s): G06F12/1009, G06F9/455, G06F12/06, G06F12/1081
CPC Code(s): G06F12/1009
Abstract: embodiments of apparatuses, methods, and systems for unified address translation for virtualization of input/output devices are described. in an embodiment, an apparatus includes first circuitry to use at least an identifier of a device to locate a context entry and second circuitry to use at least a process address space identifier (pasid) to locate a pasid-entry. the context entry is to include at least one of a page-table pointer to a page-table translation structure and a pasid. the pasid-entry is to include at least one of a first-level page-table pointer to a first-level translation structure and a second-level page-table pointer to a second-level translation structure. the pasid is to be supplied by the device. at least one of the apparatus, the context entry, and the pasid entry is to include one or more control fields to indicate whether the first-level page-table pointer or the second-level page-table pointer is to be used.
Inventor(s): Jean Xu Yu of Austin TX (US) for intel corporation, Haim Shmuel Barad of Zichron Yaakov (IL) for intel corporation, Harsha Gupta of Sunnyvale CA (US) for intel corporation
IPC Code(s): G06F16/33, G06F40/279, G06T11/00
CPC Code(s): G06F16/3344
Abstract: methods, apparatus, systems, and articles of manufacture to determine a number of denoising iterations of model output generation are disclosed. an example apparatus includes at least one programmable circuit to execute a model to generate a plurality of outputs based on a text-based prompt, each of the plurality of outputs generated using different numbers of denoising iterations; generate an ordered set of the plurality of outputs based on the number of denoising iterations; determine a plurality of similarities between neighboring outputs in the ordered set of the plurality of outputs; and select a number of denoising iterations based on the plurality of similarities.
Inventor(s): Liyang LING of Shanghai (CN) for intel corporation
IPC Code(s): G06N3/08
CPC Code(s): G06N3/08
Abstract: the disclosure relates to adaptive buffer management to support a dynamic tensor shape in a dnn. an apparatus for the dnn may include processor circuitry configured to: determine whether a tensor shape of an input tensor of an object in the dnn is dynamic and exists in a shape buffer pool; run the object by use of a compilation result for the object stored in the shape buffer pool when the tensor shape of the input tensor is dynamic and exists in the shape buffer pool; and invoke the compilation procedure to perform jit compilation for the object so as to get the compilation result for the object when the tensor shape of the input tensor is dynamic and does not exist in the shape buffer pool.
Inventor(s): Amanda Sofie Rios of Los Angeles CA (US) for intel corporation, Nilesh Ahuja of Cupertino CA (US) for intel corporation, Ibrahima Jacques Ndiour of Chandler AZ (US) for intel corporation, Ergin Utku Genc of Portland OR (US) for intel corporation, Omesh Tickoo of Portland OR (US) for intel corporation
IPC Code(s): G06N3/08
CPC Code(s): G06N3/08
Abstract: an example apparatus includes interface circuitry, machine-readable instructions, and at least one processor circuit to be programmed by the machine-readable instructions to extract neural network model features from deployment data, identify out-of-distribution data based on the neural network model features, identify samples with the out-of-distribution data to generate one or more scores associated with post-deployment data drift, and classify post-deployment data based on the one or more scores.
Inventor(s): Songki Choi of Seoul (KR) for intel corporation, Eunwoo Shin of Seoul (KR) for intel corporation
IPC Code(s): G06T3/40, G06T7/62
CPC Code(s): G06T3/40
Abstract: example apparatus disclosed herein determine an initial spatial input size for training a computer vision model, the initial spatial input size based on sizes of input training images, apply an adjustment to the initial spatial input size to determine an adjusted spatial input size, the adjustment based on sizes of objects in the input training images, and map the adjusted spatial input size to one of a set of available spatial input sizes to determine a final spatial input size for training the computer vision model. some disclosed apparatus evaluates a linear model to determine a final batch size for training the computer vision model, the linear model based on first and second simulations of training the computer vision model, the first simulation based on the final spatial input size and a first batch size, the second simulation based on the final spatial input size and a second batch size.
Inventor(s): Hiroki TANAKA of Gilbert AZ (US) for intel corporation, Veronica STRONG of Hillsboro OR (US) for intel corporation, Henning BRAUNISCH of Phoenix AZ (US) for intel corporation, Haobo CHEN of Gilbert AZ (US) for intel corporation, Jeremy D. ECTON of Gilbert AZ (US) for intel corporation, Kristof DARMAWIKARTA of Chandler AZ (US) for intel corporation, Brandon C. MARIN of Gilbert AZ (US) for intel corporation
IPC Code(s): H01L23/482, H01L21/768, H01L23/498
CPC Code(s): H01L23/4821
Abstract: embodiments disclosed herein include an interposer. in an embodiment, the interposer comprises a substrate, where the substrate comprises a glass layer. in an embodiment, a trace is on the substrate, where the trace has a bottom surface, sidewall surfaces, and a top surface. in an embodiment, the sidewall surfaces and the top surface are exposed to air. in an embodiment, a trench into the substrate is adjacent to at least one sidewall surface of the trace.
20240339410. DIRECT BONDING IN MICROELECTRONIC ASSEMBLIES_simplified_abstract_(intel corporation)
Inventor(s): Aleksandar Aleksov of Chandler AZ (US) for intel corporation, Adel A. Elsherbini of Chandler AZ (US) for intel corporation, Shawna M. Liff of Scottsdale AZ (US) for intel corporation, Johanna M. Swan of Scottsdale AZ (US) for intel corporation, Feras Eid of Chandler AZ (US) for intel corporation, Randy B. Osborne of Beaverton OR (US) for intel corporation, Van H. Le of Beaverton OR (US) for intel corporation
IPC Code(s): H01L23/538, H01L23/49, H01L25/065
CPC Code(s): H01L23/5384
Abstract: disclosed herein are microelectronic assemblies including microelectronic components that are coupled together by direct bonding, as well as related structures and techniques. for example, in some embodiments, a microelectronic assembly may include a first microelectronic component, including an organic dielectric material; a second microelectronic component coupled to the first microelectronic component by a direct bonding region, wherein the direct bonding region includes metal contacts and a dielectric material between adjacent ones of the metal contacts, and wherein the dielectric material includes an inorganic dielectric material; and a third microelectronic component coupled to the first microelectronic component by wire bonding or solder.
Inventor(s): Cary KULIASHA of Mesa AZ (US) for intel corporation, Brandon C. MARIN of Gilbert AZ (US) for intel corporation, Kristof DARMAWIKARTA of Chandler AZ (US) for intel corporation, Srinivas V. PIETAMBARAM of Chandler AZ (US) for intel corporation
IPC Code(s): H01L23/538, H01L23/64, H01L25/065
CPC Code(s): H01L23/5386
Abstract: embodiments disclosed herein include an interconnect bridge. in an embodiment, the interconnect bridge comprises a substrate, and a first trace on the substrate. in an embodiment, a first layer is on the first trace, where the first layer comprises a magnetic material. in an embodiment, a second layer is over the substrate, where the second layer comprises an insulating material. in an embodiment, a second trace is embedded in the second layer.
20240339428. HIGH DENSITY SUBSTRATE ROUTING IN PACKAGE_simplified_abstract_(intel corporation)
Inventor(s): Weng Hong TEH of Cambridge MA (US) for intel corporation, Chia-Pin CHIU of Tempe AZ (US) for intel corporation
IPC Code(s): H01L23/00, H01L21/56, H01L23/31, H01L23/50, H01L23/538, H01L25/16, H01L25/18
CPC Code(s): H01L24/25
Abstract: discussed generally herein are devices that include high density interconnects between dice and techniques for making and using those devices. in one or more embodiments a device can include a bumpless buildup layer (bbul) substrate including a first die at least partially embedded in the bbul substrate, the first die including a first plurality of high density interconnect pads. a second die can be at least partially embedded in the bbul substrate, the second die including a second plurality of high density interconnect pads. a high density interconnect element can be embedded in the bbul substrate, the high density interconnect element including a third plurality of high density interconnect pads electrically coupled to the first and second plurality of high density interconnect pads.
20240340161. APPARATUS, METHOD, AND SYSTEM_simplified_abstract_(intel corporation)
Inventor(s): Ofer RIVLIN of Tel-Aviv (IL) for intel corporation, Dan HOROVITZ of Rishon Lezion (IL) for intel corporation
IPC Code(s): H04L9/08, H04L9/00, H04L9/32
CPC Code(s): H04L9/0825
Abstract: it is provided an apparatus comprising interface circuitry, machine-readable instructions, and processing circuitry to execute the machine-readable instructions. the machine-readable instructions comprise instructions to encrypt data of a first agent with a homomorphic public key. the first agent is connected to a network. the machine-readable instructions further comprise instructions to transmit the encrypted data of the first agent and the homomorphic public key to a server and to request data from the server, the requested data comprising a reference value for the data of the first agent. the reference value is based on the data of the first agent and on the data of one or more second agents, the one or more second agents are connected to the network. the machine-readable instructions further comprise instructions to receive the requested data from the server. the requested data is encrypted with the homomorphic public key.
Inventor(s): Prerana Rane of Newark CA (US) for intel corporation, Daewon Lee of Porland OR (US) for intel corporation, Aida Vera Lopez of Hillsboro OR (US) for intel corporation, Jiwoo Kim of San Jose CA (US) for intel corporation
IPC Code(s): H04W48/16, H04W74/0833
CPC Code(s): H04W48/16
Abstract: a user equipment (ue) configured for operating in a fifth-generation (5g) new radio (nr) system may search for a 5g nr cell at synchronization signal (ss) block frequency positions associated with synchronization signal (ss) raster values. the ue may detect a synchronization signal block (ssb) at one of the ss block frequency positions and may derive a cell reference frequency corresponding to a nr absolute radio frequency channel number (nr arfcn) value for the 5g nr cell from system information including a channel bandwidth. the frequency positions associated with the ss raster values are based on one or more global synchronization channel number (gscn) values selected for the fr2 operating band n263. the cell reference frequency corresponds to one of a plurality of nr arfcn values selected for the fr2 operating band n263.
- Intel Corporation
- B25J9/16
- B25J19/02
- CPC B25J9/1671
- Intel corporation
- G01R31/3185
- CPC G01R31/318541
- G06F3/14
- H04W4/80
- CPC G06F3/1415
- G06F8/65
- G06F8/61
- CPC G06F8/65
- G06F9/455
- G06F9/30
- CPC G06F9/45558
- G06F12/1009
- G06F12/06
- G06F12/1081
- CPC G06F12/1009
- G06F16/33
- G06F40/279
- G06T11/00
- CPC G06F16/3344
- G06N3/08
- CPC G06N3/08
- G06T3/40
- G06T7/62
- CPC G06T3/40
- H01L23/482
- H01L21/768
- H01L23/498
- CPC H01L23/4821
- H01L23/538
- H01L23/49
- H01L25/065
- CPC H01L23/5384
- H01L23/64
- CPC H01L23/5386
- H01L23/00
- H01L21/56
- H01L23/31
- H01L23/50
- H01L25/16
- H01L25/18
- CPC H01L24/25
- H04L9/08
- H04L9/00
- H04L9/32
- CPC H04L9/0825
- H04W48/16
- H04W74/0833
- CPC H04W48/16
