Intel Corporation patent applications on May 30th, 2024
Patent Applications by Intel Corporation on May 30th, 2024
Intel Corporation: 49 patent applications
Intel Corporation has applied for patents in the areas of H01L23/15 (14), H01L23/00 (7), H01L23/498 (7), H04W72/0446 (6), H01L23/538 (5)
With keywords such as: core, surface, circuit, device, memory, portion, having, optical, integrated, and substrate in patent application abstracts.
Patent Applications by Intel Corporation
Inventor(s): Joshua STACEY of Chandler AZ (US) for intel corporation, Thomas HEATON of Gilbert AZ (US) for intel corporation, Dilan SENEVIRATNE of Phoenix AZ (US) for intel corporation
IPC Code(s): B32B37/00, B32B37/02, B32B37/06, B32B37/20, B32B37/30
Abstract: the present disclosure is directed to an apparatus including a first laminating component configured to laminate a dry film onto a substrate using heat, and a focused cure module configured to selectively cure a first portion of the dry film without curing a second portion of the dry film. the first portion forms a perimeter that surrounds the second portion.
20240175640.VARIABLE DIMENSION HEAT PIPE_simplified_abstract_(intel corporation)
Inventor(s): Santosh Gangal of Bengaluru (IN) for intel corporation, Akarsha Kadadevaramath of Santa Clara CA (US) for intel corporation, Raghavendra S. Kanivihalli of Bangalore (IN) for intel corporation, Prakash Kurma Raju of Bangalore (IN) for intel corporation, Navneet Singh of Bangalore (IN) for intel corporation, Sarma Vmk Vedhanabhatla of Bengaluru (IN) for intel corporation
IPC Code(s): F28D15/04
Abstract: a heat pipe, including: a variable dimension heat pipe exoskeleton formed of a heat-conductive material by blow molding or additive manufacturing, wherein the variable dimension heat pipe exoskeleton including: a first heat pipe exoskeleton portion with a dimension having a first value; and a second heat pipe exoskeleton portion with the dimension having a second value different from the first value. further, a method of manufacturing a heat pipe, including: providing a heat-conductive material; and performing blow molding or additive manufacturing to form a variable dimension heat pipe exoskeleton of the heat-conductive material, wherein the heat pipe exoskeleton has a first heat pipe exoskeleton portion with a dimension having a first value, and a second heat pipe exoskeleton portion with the dimension having a second value different from the first value.
Inventor(s): Ruben NUNEZ BLANCO of Gilbert AZ (US) for intel corporation, Christopher ACKERMAN of Phoenix AZ (US) for intel corporation, Paul DIGLIO of Gaston OR (US) for intel corporation, Varun NARAYAN of Tempe AZ (US) for intel corporation, Craig YOST of Gilbert AZ (US) for intel corporation, Jensen STENBERG of Phoenix AZ (US) for intel corporation, Kelly LOFGREEN of Phoenix AZ (US) for intel corporation, Joseph PETRINI of Gilbert AZ (US) for intel corporation, Sami ALELYANI of Phoenix AZ (US) for intel corporation
IPC Code(s): G01R31/28, H01L23/467
Abstract: this disclosure describes systems, methods, and devices related to preventing water leakage from jet impingement applied to an integrated circuit under test. an integrated circuit testing apparatus for applying jet impingement to an integrated circuit may include an impingement chamber in contact with an integrated circuit being tested, the impingement chamber comprising water associated with cooling the integrated circuit; and an actuator-driven thermal management block including an air inlet configured to direct a flow of air into an immediate test environment for the integrated circuit to generate a positive pressure differential with respect to the water in the impingement chamber to prevent leakage of the water from the impingement chamber.
Inventor(s): Xiaoqian Li of Chandler AZ (US) for intel corporation
IPC Code(s): G02B6/12, G02B6/124
Abstract: microelectronic assemblies, related devices and methods, are disclosed herein. in some embodiments, a microelectronic assembly may include a substrate having a glass core with a surface and a dielectric material on a portion of the surface of the core, the dielectric material including conductive pathways; a photonic integrated circuit (pic) having an active surface, wherein the pic is coupled to the surface of the core with the active surface facing away from the core; a processor integrated circuit (xpu) electrically coupled to the conductive pathways in the dielectric material and to the active surface of the pic; a first optical component optically coupled to a lateral surface of the pic and to the surface of the core; and a second optical component coupled to the core, wherein the second optical component is optically coupled to the pic by an optical pathway through the first optical component and the core.
Inventor(s): Xiaoqian Li of Chandler AZ (US) for intel corporation
IPC Code(s): G02B6/12, H01L25/16
Abstract: microelectronic assemblies, related devices and methods, are disclosed herein. in some embodiments, a microelectronic assembly may include a substrate having a glass core with a surface and a dielectric material on a portion of the surface of the core, the dielectric material including conductive pathways and an interconnect die; a processor integrated circuit (xpu) and a photonic integrated circuit (pic), having an active surface facing towards the core, electrically coupled to the interconnect die and to the conductive pathways; a first optical component optically coupled to the active surface of the pic and to the surface of the core; and a second optical component coupled to the core, wherein the second optical component is optically coupled to the pic by an optical pathway through the first optical component and the core.
Inventor(s): Jeremy Ecton of Gilbert AZ (US) for intel corporation, Brandon C. Marin of Gilbert AZ (US) for intel corporation, Changhua Liu of Chandler AZ (US) for intel corporation, Srinivas V. Pietambaram of Chandler AZ (US) for intel corporation, Hiroki Tanaka of Gilbert AZ (US) for intel corporation
IPC Code(s): G02B6/12, H01L25/16
Abstract: microelectronic assemblies, related devices and methods, are disclosed herein. in some embodiments, a photonic assembly may include a substrate having a core with a surface, wherein a material of the core includes glass; and a dielectric material on a portion of the surface of the core, the dielectric material including conductive pathways; a photonic integrated circuit (pic) electrically coupled to the conductive pathways in the dielectric material; a first optical component between the pic and the surface of the core, wherein the first optical component is coupled to the surface of the core by optical glue or by fusion bonding; and a second optical component coupled to the core, wherein the second optical component is optically coupled to the pic by an optical pathway through the core and the first optical component.
Inventor(s): Jeremy D. Ecton of Gilbert AZ (US) for intel corporation, Srinivas V. Pietambaram of Chandler AZ (US) for intel corporation, Brandon Christian Marin of Gilbert AZ (US) for intel corporation, Gang Duan of Chandler AZ (US) for intel corporation, Bai Nie of Chandler AZ (US) for intel corporation
IPC Code(s): G02B6/42
Abstract: a pic first patch architecture includes a solderless electrical connection at a die interconnect surface. redistribution layers (rdls) are patterned onto a face of an integrated circuit (ic) die and photonic integrated circuit (pic) die prior to placement of the rdls into a cavity in a glass layer. optical interconnections for the pic die are protected during rdl patterning and optical waveguides may be patterned into the glass layer fore or after assembling the pic first patch including the rdl and glass layer.
Inventor(s): Jeremy Ecton of Gilbert AZ (US) for intel corporation, Brandon C. Marin of Gilbert AZ (US) for intel corporation, Srinivas V. Pietambaram of Chandler AZ (US) for intel corporation, Gang Duan of Chandler AZ (US) for intel corporation, Suddhasattwa Nad of Chandler AZ (US) for intel corporation
IPC Code(s): G02B6/43, G02B6/122, G02B6/30
Abstract: microelectronic assemblies, related devices and methods, are disclosed herein. in some embodiments, a photonic assembly may include a substrate having a core with a surface, wherein a material of the core includes glass; and a dielectric material on a portion of the surface of the core, the dielectric material including conductive pathways; a photonic integrated circuit (pic) electrically coupled to the conductive pathways in the dielectric material; a first optical component between the pic and the surface of the core, wherein the first optical component is along a perimeter of the core; and a second optical component coupled to the first optical component, wherein the second optical component is optically coupled to the pic by an optical pathway through the first optical component.
Inventor(s): Benjamin DUONG of Phoenix AZ (US) for intel corporation, Kristof DARMAWIKARTA of Chandler AZ (US) for intel corporation, Tolga ACIKALIN of San Jose CA (US) for intel corporation, Harel FRISH of Albuquerque NM (US) for intel corporation, Sandeep GAAN of Chandler AZ (US) for intel corporation, John HECK of Berkeley CA (US) for intel corporation, Eric J. M. MORET of Beaverton OR (US) for intel corporation, Suddhasattwa NAD of Chandler AZ (US) for intel corporation, Haisheng RONG of Pleasanton CA (US) for intel corporation
IPC Code(s): G02F1/01, G02B6/125
Abstract: embodiments disclosed herein include a package substrate. in an embodiment, the package substrate comprises a core where the core comprises glass. in an embodiment, the package substrate further comprises an optical waveguide over the core, and an optical phase change material over the optical waveguide.
Inventor(s): Hong Shan Neoh of San Carlos CA (US) for intel corporation
IPC Code(s): G06F7/78
Abstract: a circuit system includes a memory block and first and second processing circuits. the first and second processing circuits store a matrix in the memory block by concurrently writing first and second rows or columns of the matrix to first and second regions of storage in the memory block, respectively. the first and second processing circuits transpose the matrix to generate a transposed matrix by concurrently reading first and second rows or columns of the transposed matrix from third and fourth regions of storage in the memory block, respectively.
Inventor(s): Martin Langhammer of Alderbury (GB) for intel corporation, Dongdong Chen of San Jose CA (US) for intel corporation, Jason R. Bergendahl of Cupertino CA (US) for intel corporation
IPC Code(s): G06F9/30, G06F7/483, G06F7/50, G06F7/523, G06F7/556, G06F30/34, G06F30/343, G06F30/38, G06N20/00, H03K19/177, H03K19/17748, H03M7/24
Abstract: the present disclosure describes a digital signal processing (dsp) block that includes a plurality of columns of weight registers and a plurality of inputs configured to receive a first plurality of values and a second plurality of values. the first plurality of values is stored in the plurality of columns of weight registers after being received. additionally, the dsp block includes a plurality of multipliers configured to simultaneously multiply each value of the first plurality of values by each value of the second plurality of values.
Inventor(s): Vincent ZIMMER of Issaquah WA (US) for intel corporation, Subrata BANIK of Bangalore KA (IN) for intel corporation, Rajaram REGUPATHY of Bangalore, KA (IN) for intel corporation, Salil MATHACHAN THOMAS of Bangalore (IN) for intel corporation
IPC Code(s): G06F9/4401, G06F9/455, G06F13/42
Abstract: various examples of the present disclosure relate to a computing device, and to a method and computer program for initializing a computing device. the computing device comprises a memory device, configured to store firmware for at least a first processing unit and a second processing unit. the computing device comprises a first processing unit, configured to obtain the firmware for the first processing unit from the memory device, and to initialize itself using the firmware obtained from the memory device. the computing device comprises a second processing unit, configured to obtain the firmware for the second processing unit from the memory device, and to initialize itself using the firmware obtained from the memory device.
20240176665.NOISY NEIGHBOR DETECTION_simplified_abstract_(intel corporation)
Inventor(s): Adrian Stanciu of Craiova (RO) for intel corporation
IPC Code(s): G06F9/50
Abstract: a processor may aggregate cache misses in a cache, the cache shared by a plurality of input/output (i/o) sources. the processor may aggregate cache occupancy in the cache by the plurality of vo sources. the processor may and identify, based on the aggregating, a first i/o source of the plurality of i/o sources as impacting the cache.
Inventor(s): Krishna Kumar SIMMADHARI RAMADASS of Bangalore (IN) for intel corporation, Rajesh BANGINWAR of Bangalore (IN) for intel corporation
IPC Code(s): G06F12/0817, G06F12/0877, G06F13/28
Abstract: a high availability system including multiple host systems includes a host managed device memory that is shared between the multiple host systems allowing faster communication between the host systems. access to the host managed device memory in a memory expander card is via direct memory access from the host system. memory expander card control circuitry in the memory expander card performs memory translation, gatekeeping and synchronization. a host system can access the host managed device memory in the memory expander card directly using cxl.cache and cxl.mem protocols. from the host system perspective, the host managed device memory in the memory expander card is directly attached using a memory mapped interface.
Inventor(s): Siddhartha Chhabra of Portland OR (US) for intel corporation, David M. Durham of Beaverton OR (US) for intel corporation
IPC Code(s): G06F12/14, G06F21/52, G06F21/53, G06F21/60, G06F21/64, G06F21/71, G06F21/72, H04L9/06, H04L9/08, H04L9/14, H04L9/32, H04L9/40
Abstract: in one embodiment, a multi-tenant computing system includes a processor including a plurality of cores on which agents of tenants of the multi-tenant computing system are to execute, a configuration storage, and a memory execution circuit. the configuration storage includes a first configuration register to store configuration information associated with the memory execution circuit. the first configuration register is to store a mode identifier to identify a mode of operation of the memory execution circuit. the memory execution circuit, in a first mode of operation, is to receive encrypted data of a first tenant, the encrypted data encrypted by the first tenant, generate an integrity value for the encrypted data, and send the encrypted data and the integrity value to a memory, the integrity value not visible to the software of the multi-tenant computing system. other embodiments are described and claimed.
20240176861.FLEXIBLE CONTAINER ATTESTATION_simplified_abstract_(intel corporation)
Inventor(s): Vincent R. Scarlata of Beaverton OR (US) for intel corporation, Carlos V. Rozas of Portland OR (US) for intel corporation, Baiju Patel of Portland OR (US) for intel corporation, Barry E. Huntley of Hillsboro OR (US) for intel corporation, Ravi L. Sahita of Portland OR (US) for intel corporation, Hormuzd M. Khosravi of Portland OR (US) for intel corporation
IPC Code(s): G06F21/44, G06F9/30
Abstract: data integrity logic is executable by a processor to generate a data integrity code using a hardware-based secret. a container manager, executable by the processor, creates a secured container including report generation logic that determines measurements of the secured container, generates a report according to a defined report format, and sends a quote request including the report. the defined report format includes a field to include the measurements and a field to include the data integrity code, and the report format is compatible for consumption by any one of a plurality of different quote creator types.
20240176941.PRINTED CIRCUIT BOARD PIN FIELD SIGNAL ROUTING_simplified_abstract_(intel corporation)
Inventor(s): Xiaoning Ye of Portland OR (US) for intel corporation, Jorge A. Alvarez of Zapopan (MX) for intel corporation, Jose de Jesus Jauregui Ruelas of Guadalajara (MX) for intel corporation, Vijaya K. Kunda of Portland OR (US) for intel corporation, Hong-Yi Luoh of Portland OR (US) for intel corporation, Yanwu Wang of Suzhou (CN) for intel corporation, Chunfei Ye of Lacey WA (US) for intel corporation
IPC Code(s): G06F30/3953, G06F30/392, G06F30/398, G06F119/10
Abstract: signal lines in the pin field of a printed circuit board layout are modified to reduce line impedance and improve signal integrity. the widths of signal lines are extended in the pin field to take full advantage of the available routing space between pads and adjacent signal lines. the signal line extension can be considered a subtractive approach in that the signal lines are extended to occupy the available muting space, with signal line extensions that would otherwise cause design rule violations being subtracted out. the edge of a signal line is extended to a keep-out region associated with a centerline that extends through a plurality of pads arranged in a line and located adjacent to the signal line. the edge of the signal line is also extended to keep-out regions associated with pads in the pin fields.
Inventor(s): Anbang YAO of Beijing (CN) for intel corporation, Hao ZHAO of Beijing (CN) for intel corporation, Ming LU of Beijing (CN) for intel corporation, Yiwen GUO of Beijing (CN) for intel corporation, Yurong CHEN of Beijing (CN) for intel corporation
IPC Code(s): G06N3/063, G06F18/214, G06N3/04, G06N3/08, G06V10/44, G06V10/764, G06V10/82, G06V10/94, G06V20/10, G06V20/40, G06V20/70
Abstract: methods and apparatus for discrimitive semantic transfer and physics-inspired optimization in deep learning are disclosed. a computation training method for a convolutional neural network (cnn) includes receiving a sequence of training images in the cnn of a first stage to describe objects of a cluttered scene as a semantic segmentation mask. the semantic segmentation mask is received in a semantic segmentation network of a second stage to produce semantic features. using weights from the first stage as feature extractors and weights from the second stage as classifiers, edges of the cluttered scene are identified using the semantic features.
Inventor(s): Joydeep RAY of Folsom CA (US) for intel corporation, Abhishek R. APPU of El Dorado Hills CA (US) for intel corporation, Altug KOKER of El Dorado Hills CA (US) for intel corporation, Balaji VEMBU of Folsom CA (US) for intel corporation
IPC Code(s): G06T1/20, G06F12/0811, G06F12/0815, G06F12/0831, G06F12/0875, G06F12/0888, G06T1/60
Abstract: an apparatus and method are described for managing data which is biased towards a processor or a gpu. for example, an apparatus comprises a processor comprising one or more cores, one or more cache levels, and cache coherence controllers to maintain coherent data in the one or more cache levels; a graphics processing unit (gpu) to execute graphics instructions and process graphics data, wherein the gpu and processor cores are to share a virtual address space for accessing a system memory; a gpu memory addressable through the virtual address space shared by the processor cores and gpu; and bias management circuitry to store an indication for whether the data has a processor bias or a gpu bias, wherein if the data has a gpu bias, the data is to be accessed by the gpu without necessarily accessing the processor's cache coherence controllers.
20240177395.TOPOLOGY SHADER TECHNOLOGY_simplified_abstract_(intel corporation)
Inventor(s): Hugues Labbe of Folsom CA (US) for intel corporation, Tomer Bar-On of Petah Tikva (IL) for intel corporation, Gabor Liktor of San Francisco CA (US) for intel corporation, Andrew T. Lauritzen of Victoria (CA) for intel corporation, John G. Gierach of Hillsboro OR (US) for intel corporation
IPC Code(s): G06T15/00, G06T15/30, G06T15/40
Abstract: systems, apparatuses and methods may provide for technology that receives, at a topology shader in a graphics pipeline, an object description and generates, at the topology shader, a set of polygons based on the object description. additionally, the set of polygons may be sent to a vertex shader.
Inventor(s): Akshay Jindal of Bellevue WA (US) for intel corporation
IPC Code(s): G06T15/04, G02B27/01, G06T7/40, G06T19/00, G06V10/74
Abstract: systems, apparatuses and methods may provide for technology that determines a texture similarity between a target output image and an initial rendered image, updates one or more scene parameters to increase the texture similarity between the target output image and the initial rendered image, generates a modified rendered image based on the updated scene parameter(s), and sends the modified rendered image to one or more displays of an augmented reality (ar) headset, wherein the modified rendered image visually blends with an environmental image to obtain the target output image.
Inventor(s): Yosef KORNBLUTH of Phoenix AZ (US) for intel corporation, Whitney BRYKS of Tempe AZ (US) for intel corporation, Ravindranadh ELURI of Tempe AZ (US) for intel corporation, Aaditya Anand CANDADAI of Chandler AZ (US) for intel corporation, Srinivas PIETAMBARAM of Chandler AZ (US) for intel corporation
IPC Code(s): H01F7/20, B32B3/18
Abstract: the present disclosure is directed to a carrier chuck having a base plate with a top surface, a plurality of first magnets positioned in a first region of the top surface, the plurality of first magnets configured to produce a first electromagnetic field to retain or suspend a panel placed on the carrier chuck during panel processing, wherein the first region corresponds to a region of the panel which comprises a magnetic material.
20240177918.GLASS EMBEDDED TRUE AIR CORE INDUCTORS_simplified_abstract_(intel corporation)
Inventor(s): Suddhasattwa NAD of Chandler AZ (US) for intel corporation, Brandon C. MARIN of Gilbert AZ (US) for intel corporation, Jeremy D. ECTON of Gilbert AZ (US) for intel corporation, Srinivas V. PIETAMBARAM of Chandler AZ (US) for intel corporation, Gang DUAN of Chandler AZ (US) for intel corporation, Mohammad Mamunur RAHMAN of Gilbert AZ (US) for intel corporation
IPC Code(s): H01F27/28, H01F27/30, H01F41/04, H01L23/08, H01L23/31
Abstract: embodiments disclosed herein include a package core. in an embodiment, the package core comprises a core substrate, a first opening through the core substrate, a second opening through the core substrate and adjacent to the first opening, and a first structure around the core substrate between the first opening and the second opening. in an embodiment, the first structure is electrically conductive. the package core may further comprise a second structure around the core substrate outside of the first opening and the second opening, where the second structure is electrically conductive.
Inventor(s): Jeffrey S. LEIB of Beaverton OR (US) for intel corporation, Srijit MUKHERJEE of Portland OR (US) for intel corporation, Vinay BHAGWAT of Hillsboro OR (US) for intel corporation, Michael L. HATTENDORF of Portland OR (US) for intel corporation, Christopher P. AUTH of Portland OR (US) for intel corporation
IPC Code(s): H01L21/8238, H01L21/033, H01L21/28, H01L21/285, H01L21/308, H01L21/311, H01L21/762, H01L21/768, H01L21/8234, H01L23/522, H01L23/528, H01L23/532, H01L27/092, H01L29/08, H01L29/417, H01L29/51, H01L29/66, H01L29/78, H10B10/00
Abstract: embodiments of the disclosure are in the field of advanced integrated circuit structure fabrication and, in particular, 10 nanometer node and smaller integrated circuit structure fabrication and the resulting structures. in an example, an integrated circuit structure includes a p-type semiconductor device above a substrate and including first and second semiconductor source or drain regions adjacent first and second sides of a first gate electrode. a first metal silicide layer is directly on the first and second semiconductor source or drain regions. an n-type semiconductor device includes third and fourth semiconductor source or drain regions adjacent first and second sides of a second gate electrode. a second metal silicide layer is directly on the third and fourth semiconductor source or drain regions, respectively. the first metal silicide layer comprises at least one metal species not included in the second metal silicide layer.
Inventor(s): Soham Agarwal of Chandler AZ (US) for intel corporation, Benjamin T. Duong of Phoenix AZ (US) for intel corporation
IPC Code(s): H01L23/15, H01L21/48, H01L23/00, H01L23/498, H01L25/065
Abstract: disclosed herein are microelectronic assemblies including strengthened glass cores, as well as related devices and methods. in some embodiments, a microelectronic assembly may include a core made of glass and having a surface, the core further including a first region having a first concentration of ions and a second region having a second concentration of ions at the surface of the core; and a third region having a third concentration of ions, wherein the second region is between the third region and the surface of the core, and wherein the third concentration of ions is less than the first and second concentrations of ions; a dielectric with a conductive pathway at the surface of the core; and a die electrically coupled to the conductive pathway in the dielectric at the surface of the core by an interconnect.
20240178097.PERMANENT LAYER FOR BUMP CHIP ATTACH_simplified_abstract_(intel corporation)
Inventor(s): Frederick Atadana of Hillsboro OR (US) for intel corporation, Jean Bosco Kana Kana of Chandler AZ (US) for intel corporation, Shripad Gokhale of Gilbert AZ (US) for intel corporation, Xavier F. Brun of Chandler AZ (US) for intel corporation
IPC Code(s): H01L23/373, H01L21/48, H01L23/00, H01L23/15, H01L23/538, H01L25/065
Abstract: disclosed herein are microelectronics package architectures utilizing glass layers and methods of manufacturing the same. the microelectronics packages may include a silicon layer, dies, and a glass layer. the silicon layer may include vias. the dies may be in electrical communication with vias. the glass layer may include interconnects in electrical communication with the vias.
Inventor(s): Tao CHU of Portland OR (US) for intel corporation, Guowei XU of Portland OR (US) for intel corporation, Feng ZHANG of Hillsboro OR (US) for intel corporation, Chiao-Ti HUANG of Portland OR (US) for intel corporation, Minwoo JANG of Portland OR (US) for intel corporation
IPC Code(s): H01L23/48, H01L27/088, H01L29/06, H01L29/417, H01L29/786
Abstract: integrated circuit structures having recessed trench contacts and deep boundary vias are described. for example, an integrated circuit structure includes a plurality of gate lines extending over a plurality of semiconductor nanowire stack channel structures. a plurality of trench contacts extends over a plurality of source or drain structures, where a first one of the plurality of trench contacts has a recess therein. a backside metal routing layer is extending beneath the plurality of gate lines and beneath the plurality of trench contacts. a conductive structure couples the backside metal routing layer to a second one of the one or more of the plurality of trench contacts. the conductive structure includes a pillar portion in contact with the second one of the plurality of trench contacts, the pillar portion on a line portion, the line portion in contact with and extending along the backside metal routing layer.
20240178119.RBTV IMPROVEMENT FOR GLASS CORE ARCHITECTURES_simplified_abstract_(intel corporation)
Inventor(s): Mohammad Mamunur RAHMAN of Gilbert AZ (US) for intel corporation, Jeremy D. ECTON of Gilbert AZ (US) for intel corporation, Gang DUAN of Chandler AZ (US) for intel corporation
IPC Code(s): H01L23/498, H01L23/00, H01L23/13, H01L23/15, H01L23/538
Abstract: embodiments disclosed herein include an interconnect. in an embodiment, the interconnect comprises a substrate and a pad over the substrate. in an embodiment, a hole is provided through the pad. in an embodiment, the hole exposes a portion of the substrate. in an embodiment, a solder is provided over the pad, and the solder bridges across the hole through the pad.
Inventor(s): Kristof DARMAWIKARTA of Chandler AZ (US) for intel corporation, Hiroki TANAKA of Chandler AZ (US) for intel corporation, Robert MAY of Chandler AZ (US) for intel corporation, Sameer PAITAL of Chandler AZ (US) for intel corporation, Bai NIE of Chandler AZ (US) for intel corporation, Jesse JONES of Chandler AZ (US) for intel corporation, Chung Kwang Christopher TAN of Chandler AZ (US) for intel corporation
IPC Code(s): H01L23/538, H01L23/00, H01L23/522
Abstract: embodiments include an electronic package with an embedded multi-interconnect bridge (emib) and methods of making such packages. embodiments include a first layer, that is an organic material and a second layer disposed over the first layer. in an embodiment, a cavity is formed through the second layer to expose a first surface of the first layer. a bridge substrate is in the cavity and is supported by the first surface of the first layer. embodiments include a first die over the second layer that is electrically coupled to a first contact on the bridge substrate, and a second die over the second layer that is electrically coupled to a second contact on the bridge substrate. in an embodiment the first die is electrically coupled to the second die by the bridge substrate.
Inventor(s): Benjamin T. Duong of Phoenix AZ (US) for intel corporation, Whitney Bryks of Tempe AZ (US) for intel corporation, Kristof Kuwawi Darmawikarta of Chandler AZ (US) for intel corporation, Srinivas V. Pietambaram of Chandler AZ (US) for intel corporation, Gang Duan of Chandler AZ (US) for intel corporation, Ravindranath Vithal Mahajan of Chandler AZ (US) for intel corporation
IPC Code(s): H01L23/538, H01L23/00, H01L23/15, H01L23/498, H01L25/065
Abstract: disclosed herein are microelectronic assemblies including strengthened glass cores, as well as related devices and methods. in some embodiments, a microelectronic assembly may include a glass core having a surface, a first region having a first concentration of ions extending from the surface of the core to a first depth; a second region having a second concentration of ions greater than the first concentration of ions, the second region between the first region and the surface of the core; a dielectric with a conductive pathway at the surface of the glass core; and a die electrically coupled to the conductive pathway in the dielectric at the surface of the core by an interconnect.
Inventor(s): Minglu LIU of Chandler AZ (US) for intel corporation, Alexander AGUINAGA of Phoenix AZ (US) for intel corporation, Gang DUAN of Chandler AZ (US) for intel corporation, Jung Kyu HAN of Chandler AZ (US) for intel corporation, Yosuke KANAOKA of Chandler AZ (US) for intel corporation, Yi LI of Chandler AZ (US) for intel corporation, Robin MCREE of Chandler AZ (US) for intel corporation, Hong Seung YEON of Chandler AZ (US) for intel corporation
IPC Code(s): H01L23/544, H01L23/15, H01L23/498
Abstract: embodiments disclosed herein include a package architecture. in an embodiment, the package architecture comprises a first substrate with a first fiducial mark on a surface of the first substrate. in an embodiment, the package architecture further comprises a second substrate over the first substrate, where the second substrate comprises glass and a second fiducial mark on the second substrate, and where a footprint of the second fiducial mark at least partially overlaps a footprint of the first fiducial mark.
Inventor(s): Vinith BEJUGAM of Chandler AZ (US) for intel corporation, Whitney BRYKS of Tempe AZ (US) for intel corporation, Brandon C. MARIN of Gilbert AZ (US) for intel corporation, Vishal Bhimrao ZADE of Chandler AZ (US) for intel corporation, Deniz TURAN of Chandler AZ (US) for intel corporation, Srinivas V. PIETAMBARAM of Chandler AZ (US) for intel corporation
IPC Code(s): H01L23/00, H01L23/498
Abstract: embodiments disclosed herein include package substrates. in a particular embodiment, the package substrate comprises a core. the core may be a glass core. in an embodiment, buildup layers are provided over the core, and a shape memory polymer (smp) is provided over the core.
Inventor(s): Jeremy Ecton of Gilbert AZ (US) for intel corporation, Aleksandar Aleksov of Chandler AZ (US) for intel corporation, Brandon C. Marin of Gilbert AZ (US) for intel corporation, Srinivas V. Pietambaram of Chandler AZ (US) for intel corporation, Hiroki Tanaka of Gilbert AZ (US) for intel corporation
IPC Code(s): H01L23/66, H01L23/13, H01L23/15, H01L23/498
Abstract: an integrated circuit (ic) package substrate including a glass core having a cavity filter structure, and related devices and methods, are disclosed herein. in some embodiments, an ic package substrate may include a core made of glass, and the core including a first core portion having a first surface and a trench and a ridge in the first surface, the trench and the ridge lined with a conductive material; and a second core portion having a second surface, the second surface lined with the conductive material, wherein the first surface of the first core portion is physically coupled to the second surface of the second core portion forming a cavity filter structure.
Inventor(s): Jeremy Ecton of Gilbert AZ (US) for intel corporation, Brandon C. Marin of Gilbert AZ (US) for intel corporation, Srinivas V. Pietambaram of Chandler AZ (US) for intel corporation, Gang Duan of Chandler AZ (US) for intel corporation, Suddhasattwa Nad of Chandler AZ (US) for intel corporation
IPC Code(s): H01L25/16, G02B6/42, H01L23/00, H01L23/15, H01L23/498
Abstract: microelectronic assemblies, related devices and methods, are disclosed herein. in some embodiments, a photonic assembly may include an interposer having a surface, wherein a material of the interposer includes glass and the interposer includes through-glass vias (tgvs); a photonic integrated circuit (pic) optically coupled to the surface of the interposer by optical glue or fusion bonding and electrically coupled to the tgvs in the interposer by hybrid bond interconnects; and an optical component optically coupled to the interposer, wherein the optical component is optically coupled to the pic by an optical pathway through the interposer.
Inventor(s): Leonard P. GULER of Hillsboro OR (US) for intel corporation, Michael K. HARPER of Hillsboro OR (US) for intel corporation, William HSU of Hillsboro OR (US) for intel corporation, Biswajeet GUHA of Hillsboro OR (US) for intel corporation, Tahir GHANI of Portland OR (US) for intel corporation, Niels ZUSSBLATT of Hillsboro OR (US) for intel corporation, Jeffrey Miles TAN of Hillsboro OR (US) for intel corporation, Benjamin KRIEGEL of Portland OR (US) for intel corporation, Mohit K. HARAN of Hillsboro OR (US) for intel corporation, Reken PATEL of Portland OR (US) for intel corporation, Oleg GOLONZKA of Beaverton OR (US) for intel corporation, Mohammad HASAN of Aloha OR (US) for intel corporation
IPC Code(s): H01L27/088, G11C5/06, H01L27/06, H01L29/06, H01L29/417, H01L29/66, H01L29/78
Abstract: gate-all-around integrated circuit structures having pre-spacer-deposition cut gates are described. for example, an integrated circuit structure includes a first vertical arrangement of horizontal nanowires and a second vertical arrangement of horizontal nanowires. a first gate stack is over the first vertical arrangement of horizontal nanowires, and a second gate stack is over the second vertical arrangement of horizontal nanowires. an end of the second gate stack is spaced apart from an end of the first gate stack by a gap. the integrated circuit structure also includes a dielectric structure having a first portion forming a gate spacer along sidewalls of the first gate stack, a second portion forming a gate spacer along sidewalls of the second gate stack, and a third portion completely filling the gap, the third portion continuous with the first and second portions.
Inventor(s): Venkata Aditya ADDEPALLI of Portland OR (US) for intel corporation, Shyam Benegal KADALI of Portland OR (US) for intel corporation
IPC Code(s): H01L27/092, H01L21/8238, H01L29/06, H01L29/423, H01L29/66, H01L29/775
Abstract: integrated circuit structures having uniformity among varying gate trench widths are described. for example, an integrated circuit structure includes a first fin, and a first gate trench over the first fin, the first gate trench having a first width. the integrated circuit structure also includes a second fin, and a second gate trench over the second fin, the second gate trench having a second width greater than the first width. the integrated circuit structure also includes a gate electrode layer having a first portion along a bottom and partially along sidewalls of the first trench, and the gate electrode layer having a second portion along a bottom and partially along sidewalls of the second trench, wherein the first portion extends along the sidewalls of the first trench to approximately the same extent as the second portion extends along the sidewalls of the second trench.
Inventor(s): Chiao-Ti HUANG of Portland OR (US) for intel corporation, Tao CHU of Portland OR (US) for intel corporation, Guowei XU of Portland OR (US) for intel corporation, Chung-Hsun LIN of Portland OR (US) for intel corporation, Brian Greene of Portland OR (US) for intel corporation
IPC Code(s): H01L29/06, H01L23/48, H01L27/088, H01L29/417, H01L29/786
Abstract: integrated circuit structures having source or drain contacts with enhanced contact area, and methods of fabricating integrated circuit structures having source or drain contacts with enhanced contact area, are described. for example, an integrated circuit structure includes a plurality of horizontally stacked nanowires. a gate structure is over the plurality of horizontally stacked nanowires. an epitaxial source or drain structure is at an end of the plurality of horizontally stacked nanowires. a conductive contact structure is vertically over the epitaxial source or drain structure. the conductive contact structure has a lower portion extending over the top and along upper portions of sides of the epitaxial source or drain structure, and has an upper portion on the lower portion. the upper portion has a maximum lateral width less than a maximum lateral width of the lower portion.
Inventor(s): Alexei Davydov of Nizhny Novgorod (RU) for intel corporation, Gang Xiong of Portland OR (US) for intel corporation, Bishwarup Mondal of San Ramon CA (US) for intel corporation, Dong Han of Sunnyvale CA (US) for intel corporation
IPC Code(s): H04L1/08
Abstract: various embodiments herein provide techniques for physical uplink shared channel (pusch) transmission with repetitions to multiple transmission-reception points (trps). for example, embodiments include enhancement of channel state information (csi) (e.g., aperiodic csi (a-csi) and/or semi-persistent csi (sp-csi)), configured grant (cg)-pusch, uplink power control (ulpc), beam switching gap, and phase tracking reference signal (ptrs)-demodulation reference signal (dmrs) association, among other issues for multi-trp pusch repetition. other embodiments may be described and claimed.
Inventor(s): Gang Xiong of Portland OR (US) for intel corporation, Yingyang Li of Beijing (CN) for intel corporation, Daewon Lee of Portland OR (US) for intel corporation, Alexei Davydov of Nizhny Novgorod (RU) for intel corporation
IPC Code(s): H04L1/1829
Abstract: various embodiments herein are directed to time domain bundling of hybrid automatic repeat request-acknowledgement (harq-ack) feedback. other embodiments may be disclosed or claimed.
Inventor(s): Toufiqul Islam of Santa Clara CA (US) for intel corporation, Debdeep Chatterjee of San Jose CA (US) for intel corporation, Sergey Panteleev of Maynooth (IE) for intel corporation, Salvatore Talarico of Los Gatos CA (US) for intel corporation, Gang Xiong of Beaverton OR (US) for intel corporation
IPC Code(s): H04L1/1867, H04L1/1812, H04W72/21
Abstract: a user equipment (ue) configured for operation in a fifth-generation new radio (5gnr) system may multiplex high-priority (hp) hybrid automatic repeat request acknowledge (harq-ack) bits corresponding to a first harq-ack code-book with low-priority (lp) harq-ack bits corresponding to a second harq-ack codebook onto a physical uplink control channel (pucch) transmission to a gnode b (gnb). the ue may be configured with the first harq-ack codebook and the second harq-ack codebook of different priorities. the hp harq-ack bits may be encoded with a first maximum code rate (maxcoderate) and the lp harq-ack bits may be encoded with a second maximum code rate. the maximum code rates may be configured to the ue via rrc signalling per pucch format.
Inventor(s): Yingyang Li of Beijing (CN) for intel corporation, Gang Xiong of Portland OR (US) for intel corporation, Daewon Lee of Portland OR (US) for intel corporation, Yi Wang of Beijing (CN) for intel corporation
IPC Code(s): H04L5/00, H04W72/0446, H04W72/23
Abstract: the present invention relates to an apparatus comprising: memory to store configuration information for a first search space set group (sssg) and a second sssg associated with respective first and second physical downlink control channel (pdcch) monitoring configurations; and processing circuitry, coupled with the memory, to retrieve the configuration information from the memory, and encode a message for transmission to a user equipment (ue) that includes the configuration information, wherein the configuration information includes an indication of a boundary for switching between the first sssg and the second sssg that is aligned with a boundary of a slot group.
20240178976.ENHANCED SRS CARRIER SWITCHING IN 5G NETWORKS_simplified_abstract_(intel corporation)
Inventor(s): Guotong Wang of Beijing (CN) for intel corporation, Alexei Davydov of Nizhny Novgorod (RU) for intel corporation
IPC Code(s): H04L5/00
Abstract: an apparatus and system are described to provide carrier switching rules for multiple aperiodic sounding reference signals (srs) resource sets triggered by a single downlink control information (dci). whether the user equipment (ue) retunes between a source component carrier (cc) and a target cc for an srs transmission is dependent on a time period between adjacent srs resource sets in addition to priorities of the srs transmission on the target cc and a simultaneous transmission on the source cc. in addition, timing of another dci scheduling the simultaneous transmission received prior to the associated srs transmission affects which of the simultaneous transmission or the associated srs transmission is transmitted.
Inventor(s): Xiaoyu RUAN of Folsom CA (US) for intel corporation, William STEVENS JR. of Folsom CA (US) for intel corporation
IPC Code(s): H04L9/32, H04L9/08
Abstract: various examples relate to an apparatus, a device, a method, and a computer program for a computing device, for providing a certificate chain, and to a computing device. an apparatus comprises processor circuitry to obtain information on an identity of a firmware being used to operate the computing device, generate a leaf certificate for the firmware being used to operate the computing device based on the identity of the firmware being used to operate the computing device and using an intermediate certificate being generated based on an identity of a firmware having been used during a cold boot of the computing device, and provide a certificate chain comprising the leaf certificate for an external verifier.
Inventor(s): FRANCESC GUIM BERNAT of BARCELONA (ES) for intel corporation, KSHITIJ A. DOSHI of TEMPE AZ (US) for intel corporation, DANIEL RIVAS BARRAGAN of COLOGNE (DE) for intel corporation, MARK A. SCHMISSEUR of PHOENIX AZ (US) for intel corporation, STEEN LARSEN of PORTLAND OR (US) for intel corporation
IPC Code(s): H04L41/5025, H04L41/0896, H04L43/0817, H04L43/16
Abstract: embodiments may be generally directed to techniques to cause communication of a registration request between a first end-point and a second end-point of an end-to-end path, the registration request to establish resource load monitoring for one or more resources of the end-to-end path, receive one or more acknowledgements indicating resource loads for each of the one or more resources of the end-to-end path, at least one of the acknowledgements to indicate a resource of the one or more resources is not meeting a threshold requirement for the end-to-end path, and perform an action for communication traffic utilizing the one or more resources based on the acknowledgement.
20240179160.BUS-OFF ATTACK PREVENTION CIRCUIT_simplified_abstract_(intel corporation)
Inventor(s): Marcio Rogerio Juliato of Portland OR (US) for intel corporation, Shabbir Ahmed of Beaverton OR (US) for intel corporation, Santosh Ghosh of Hillsboro OR (US) for intel corporation, Christopher Gutierrez of Hillsboro OR (US) for intel corporation, Manoj R. Sastry of Portland OR (US) for intel corporation
IPC Code(s): H04L9/40, H04L12/40
Abstract: various systems and methods for bus-off attack detection are described herein. an electronic device for bus-off attack detection and prevention includes bus-off prevention circuitry coupled to a protected node on a bus, the bus-off prevention circuitry to: detect a transmitted message from the protected node to the bus; detect a bit mismatch of the transmitted message on the bus; suspend further transmissions from the protected node while the bus is analyzed; determine whether the bit mismatch represents a bus fault or an active attack against the protected node; and signal the protected node indicating whether a fault has occurred.
Inventor(s): Chandra Sekhar U of Bangalore (IN) for intel corporation
IPC Code(s): H04W28/20, H04W4/80, H04W76/14
Abstract: for example, a bluetooth (bt) device may be capable of configuring a bt link for communication between the bt device and a keyboard device. for example, the bt device may be configured to identify a keypress attribute of keypresses on the keyboard device. for example, the bt device may be configured to identify the keypress attribute based on transmissions from the keyboard device to the bt device over the bt link between the bt device and the keyboard device. for example, the bt device may configure a bandwidth (bw) allocation for the bt link, for example, based on the keypress attribute.
Inventor(s): Akhilesh Shivanna Thyagaturu of Tampa FL (US) for intel corporation, Hassnaa Moustafa Ep. Yehia of San Jose CA (US) for intel corporation, Jing Zhu of Portland OR (US) for intel corporation, Karthik Kumar of Chandler AZ (US) for intel corporation, Shu-Ping Yeh of San Jose CA (US) for intel corporation, Henning Schroeder of Karlsruhe (DE) for intel corporation, Menglei Zhang of Portland OR (US) for intel corporation, Mohit Kumar Garg of Hisar (IN) for intel corporation, Shiva Radhakrishnan Iyer of Sunnyvale CA (US) for intel corporation, Francesc Guim Bernat of Barcelona (ES) for intel corporation
IPC Code(s): H04W28/26, H04W28/02, H04W28/084
Abstract: systems, apparatus, articles of manufacture, and methods are disclosed to manage network slices. an example apparatus includes interface circuitry to acquire network information, machine-readable instructions, and at least one processor circuit to be programmed by the machine-readable instructions to reserve first network slices to satisfy service level objectives (slos) corresponding to first nodes, reserve second network slices to satisfy slos corresponding to second nodes, and reconfigure the first network slices to accept network communications from the second nodes when the network communications from the second nodes exceed a performance metric threshold.
20240179689.TIME DOMAIN WINDOW FOR JOINT CHANNEL ESTIMATION_simplified_abstract_(intel corporation)
Inventor(s): Gang Xiong of Beaverton OR (US) for intel corporation, Yingyang LI of Beijing (CN) for intel corporation, Sergey Sosnin of Zavolzhie (RU) for intel corporation, Gregory Ermolaev of Nizhny Novgorod (RU) for intel corporation, Debdeep Chatterjee of San Jose CA (US) for intel corporation
IPC Code(s): H04W72/0446
Abstract: a computer-readable storage medium stores instructions to configure a ue for joint channel estimation of uplink transmissions in a fifth generation new radio (5g nr) and beyond wireless network, and to cause the ue to perform operations. the operations include decoding dci or higher layer signaling received from a base station. the dci or the higher layer signaling indicates a number of pusch repetitions forming the uplink transmissions. the operations further include decoding higher layer signaling received from the base station, the higher layer signaling indicating a size of a time domain window (tdw) associated with the uplink transmissions. the tdw has a number of slots equal to the size. each of the pusch repetitions within the tdw is associated with a same carrier phase and a same transmit power.
Inventor(s): Gang Xiong of Portland OR (US) for intel corporation, Debdeep Chatterjee of San Jose CA (US) for intel corporation, Gregory Ermolaev of Nizhny Novgorod (RU) for intel corporation, Sergey Sosnin of Zavolzhie (RU) for intel corporation, Jie Zhu of San Jose CA (US) for intel corporation
IPC Code(s): H04W72/0446
Abstract: various embodiments are directed to time-domain resource allocation for transport block over multiple slot (tboms) transmissions. an apparatus may comprise: memory to store configuration information that includes a shared time domain resource allocation (tdra) list associated with transport block over multiple slot (tboms) processing; and processing circuitry, coupled with the memory, to: retrieve the configuration information from the memory, wherein the tdra list includes an entry having an indication of a scheduling delay (k2) and number of slots (n) for a tboms transmission; and encode a message for transmission to a user equipment (ue) that includes the configuration information. other embodiments may be disclosed or claimed.
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