Intel Corporation patent applications on May 16th, 2024
Patent Applications by Intel Corporation on May 16th, 2024
Intel Corporation: 48 patent applications
Intel Corporation has applied for patents in the areas of G06T1/20 (10), G06N3/084 (7), H04W72/232 (6), G06N3/045 (6), G06N3/08 (4)
With keywords such as: data, device, based, processing, memory, embodiments, layer, cache, include, and methods in patent application abstracts.
Patent Applications by Intel Corporation
Inventor(s): Min LIU of Portland OR (US) for intel corporation, Jaemon FRANKO of Gig Harbor WA (US) for intel corporation, Xia JIN of Shanghai (CN) for intel corporation, Xiang LI of Shanghai (CN) for intel corporation, Jiaqi LIU of Shanghai (CN) for intel corporation, Krishna SURYA of Portland OR (US) for intel corporation
IPC Code(s): G01R31/3185
Abstract: a processing device () for reducing scan traffic is provided. the processing device () comprises one or more interfaces () configured to transmit information to at least one register access interface () and processing circuitry () configured to control the one or more interfaces. further, the processing circuitry () is configured to obtain register parameters of at least one functional unit () of a processing unit () and to generate an improved bulk register comprising the register parameters of the at least one functional unit.
20240160269.CONTROLLER AND METHODS THEREOF_simplified_abstract_(intel corporation)
Inventor(s): Satish JHA of Portland OR (US) for intel corporation, S M Iftekharul ALAM of Hillsboro OR (US) for intel corporation, Leonardo GOMES BALTAR of Muenchen (DE) for intel corporation, Suman SEHRA of Folsom CA (US) for intel corporation, Vesh Raj SHARMA BANJADE of Portland OR (US) for intel corporation, Andradige SILVA of Portland OR (US) for intel corporation, Kathiravetpillai SIVANESAN of Portland OR (US) for intel corporation, Soo Jin TAN of Shanghai (CN) for intel corporation, Arvind MERWADAY of Beaverton OR (US) for intel corporation
IPC Code(s): G06F1/3206, G08G1/01, H04L67/12
Abstract: a controller is provided. the controller comprises a processor configured to determine multiple power saving modes based on a power saving model of a network communicative road sensing system and on a power saving target assigned to the road sensing system; the multiple power saving modes comprising a first power saving mode for a first power consuming subsystem of the road sensing system and a second power saving mode for a second power consuming subsystem of the road sensing system; generate a recommendation for the road sensing system to operate in accordance with the multiple power saving modes.
Inventor(s): Brett SAIKI of Seattle WA (US) for intel corporation, William ZORN of Folsom CA (US) for intel corporation, Theo DRANE of El Dorado Hills CA (US) for intel corporation
IPC Code(s): G06F7/487
Abstract: computer computation of correctly rounded floating point summation is described. an example of apparatus includes a first circuit to sort multiple floating point (fp) values based on an exponent of each fp value and store the sorted fp values in a buffer, and to provide the plurality of fp values for summation sequentially in a sorted order starting with a fp value having a smallest exponent; a second circuit to iteratively sum the fp values and store an accumulated value, generate and store a residual value representing fully resolved bits from the accumulator, and generate an intermediate output including the residual value; and a third circuit to perform final rounding of the output, the final rounded output being a correctly rounded summation of the maximum floating point values.
20240160407.INTEGER SQUARE 1ULP HARDWARE MULTIPLIER_simplified_abstract_(intel corporation)
Inventor(s): Theo Drane of El Dorado Hills CA (US) for intel corporation
IPC Code(s): G06F7/533, G06F7/544, G06F30/327
Abstract: described herein is a truncated modified booth squarer that is commutative and accurate to 1 unit in the last place. in various embodiments, the truncated booth squarer is a radix-4 booth squarer or a radix-8 booth squarer. the truncated booth squarer can be included within integer, floating-point, or fixed-point units within a graphics processor or compute accelerator, including matrix accelerator units or tensor processors.
20240160431.TECHNOLOGIES TO UPDATE FIRMWARE AND MICROCODE_simplified_abstract_(intel corporation)
Inventor(s): Mohan J. KUMAR of Aloha OR (US) for intel corporation, Murugasamy K. NACHIMUTHU of Beaverton OR (US) for intel corporation, Daniel K. OSAWA of Tigard OR (US) for intel corporation, Maciej PLUCINSKI of Tigard OR (US) for intel corporation, Avinash CHANDRASEKARAN of Mountain View CA (US) for intel corporation
IPC Code(s): G06F8/65, G06F9/4401
Abstract: examples described herein relate to updating boot firmware code or microcode. in some examples, a management controller includes a memory and a system processor, coupled to the management controller, is to: based on a first configuration, perform a boot operation by a read of first boot firmware code from the memory of the management controller. based on a second configuration, the system processor is to perform a boot operation by a read of second boot firmware code from a flash memory.
Inventor(s): Kenneth DAXER of Sunnyvale CA (US) for intel corporation, Martin LANGHAMMER of Alderbury (GB) for intel corporation
IPC Code(s): G06F9/30, G06F9/38
Abstract: a processor to perform a complex number matrix multiplication instruction indicating a first source complex number matrix having m rows by k columns of complex numbers and a second source complex number matrix having k rows by n columns of complex numbers. the processor, for each row m of the first source matrix, and for each column n of the second source matrix, to generate k complex numbers by k complex multiplications of k complex numbers of the row m of the first source matrix with k corresponding complex numbers of the column n of the second source matrix, and to combine the k generated complex numbers to generate a complex number. the generated complex number may either be stored at, or the generated complex number may be combined with a complex number at, a row m and a column n of a destination complex number matrix.
Inventor(s): Jiasheng Chen of El Dorado Hills CA (US) for intel corporation, Chunhui Mei of San Diego CA (US) for intel corporation, Ben J. Ashbaugh of Folsom CA (US) for intel corporation, Naveen Matam of Folsom CA (US) for intel corporation, Joydeep Ray of Folsom CA (US) for intel corporation, Timothy Bauer of Hillsboro OR (US) for intel corporation, Guei-Yuan Lueh of San Jose CA (US) for intel corporation, Vasanth Ranganathan of El Dorado Hills CA (US) for intel corporation, Prashant Chaudhari of Folsom CA (US) for intel corporation, Vikranth Vemulapalli of Folsom CA (US) for intel corporation, Nishanth Reddy Pendluru of Folsom CA (US) for intel corporation, Piotr Reiter of Gdansk (PL) for intel corporation, Jain Philip of Bangalore (IN) for intel corporation, Marek Rudniewski of Gdansk (PL) for intel corporation, Christopher Spencer of Chuluota FL (US) for intel corporation, Parth Damani of Folsom CA (US) for intel corporation, Prathamesh Raghunath Shinde of Folsom CA (US) for intel corporation, John Wiegert of Aloha OR (US) for intel corporation, Fataneh Ghodrat of Hudson MA (US) for intel corporation
IPC Code(s): G06F9/50, G06F12/0875
Abstract: an apparatus to facilitate increasing processing resources in processing cores of a graphics environment is disclosed. the apparatus includes a plurality of processing resources to execute one or more execution threads; a plurality of message arbiter-processing resource (ma-pr) routers, wherein a respective ma-pr router of the plurality of ma-pr routers corresponds to a pair of processing resources of the plurality of processing resources and is to arbitrate routing of a thread control message from a message arbiter between the pair of processing resources; a plurality of local shared cache (lsc) sequencers to provide an interface between at least one lsc of the processing core and the plurality of processing resources; and a plurality of instruction caches (ics) to store instructions of the one or more execution threads, wherein a respective ic of the plurality of ics interfaces with a portion of the plurality of processing resources.
20240160488.DYNAMIC MICROSERVICES ALLOCATION MECHANISM_simplified_abstract_(intel corporation)
Inventor(s): Soham Jayesh Desai of Hillsboro OR (US) for intel corporation, Reshma Lal of Portland OR (US) for intel corporation
IPC Code(s): G06F9/50, G06F9/445, G06F9/48, G06F21/60, G06F21/72
Abstract: a computing platform comprising a plurality of disaggregated data center resources and an infrastructure processing unit (ipu), communicatively coupled to the plurality of resources, to compose a platform of the plurality of disaggregated data center resources for allocation of micro service s cluster.
Inventor(s): Kapil SOOD of Portland OR (US) for intel corporation, Lokpraveen MOSUR of Gilbert AZ (US) for intel corporation, Aneesh AGGARWAL of Portland OR (US) for intel corporation, Niall D. MCDONNELL of Limerick (IE) for intel corporation, Chitra NATARAJAN of Queens Village NY (US) for intel corporation, Ritu GUPTA of Cupertino CA (US) for intel corporation, Edwin VERPLANKE of Queen Creek AZ (US) for intel corporation, George Leonard TKACHUK of Phoenix AZ (US) for intel corporation
IPC Code(s): G06F12/0802
Abstract: examples include techniques associated with data movement to a cache in a disaggregated die system. examples include circuitry at a first die receiving and granting requests to move data to a first cache resident on the first die or to a second cache resident on a second die that also includes a core of a processor. the granting of the request based, at least in part, on a traffic source type associated with a source of the request.
Inventor(s): George Leonard TKACHUK of Phoenix AZ (US) for intel corporation, Aneesh AGGARWAL of Portland OR (US) for intel corporation, Niall D. MCDONNELL of Limerick (IE) for intel corporation, Youngsoo CHOI of Alameda CA (US) for intel corporation, Chitra NATARAJAN of Queens Village NY (US) for intel corporation, Prasad GHATIGAR of Shannon (IE) for intel corporation, Shrikant M. SHAH of Chandler AZ (US) for intel corporation
IPC Code(s): G06F12/0802
Abstract: mechanisms to identify key sections of input-output (io) packets and use for efficient io caching and associated apparatus and methods. data, such as packets, are received from an io device coupled to an io port on a processor including a cache domain including multiple caches, such as l1/l2 and l3 or last level cache (llc). the data are logically partitioned into cache lines and embedded logic on the processor is used to identify one or more important cache lines using a cache importance pattern. cache lines that are identified as important are written to a cache or a first cache level, while unimportant cache lines are written to memory or a second cache level that is higher than the first cache level. software running on one or more processor cores may be used to program cache importance patterns for one or more data types or transaction types.
Inventor(s): Gurpreet Singh KALSI of Portland OR (US) for intel corporation, Joshua FRYMAN of Corvallis OR (US) for intel corporation, Jason HOWARD of Portland OR (US) for intel corporation, Robert PAWLOWSKI of Beaverton OR (US) for intel corporation
IPC Code(s): G06F12/109, G06F9/50
Abstract: this disclosure describes systems, methods, and devices related to a global address space (vegas) approach. the device may execute at least two processes within a device in a computing environment, each process running on a respective compute block of at least two compute blocks. the device may manage allocations of virtual memory spaces for the least two compute blocks using an independent logical system separate from the at least two compute blocks. the device may isolate the virtual memory spaces of the at least two processes by allowing each compute block to access only its own allocated virtual memory space.
20240160581.CACHE OPTIMIZATION MECHANISM_simplified_abstract_(intel corporation)
Inventor(s): Marcin Andrzej Chrapek of Zurich (CH) for intel corporation, Reshma Lal of Portland OR (US) for intel corporation
IPC Code(s): G06F12/14, G06F12/0842
Abstract: an apparatus includes a central processing unit (cpu), including a plurality of processing cores, each having a cache memory, a fabric interconnect coupled to the plurality of processing cores and cryptographic circuitry, coupled to the fabric interconnect including mesh stop station to receive memory data and determine a destination of the memory data and encryption circuitry to encrypt/decrypt the memory data based on a destination of the memory data.
20240160585.SHARING MEMORY AND I/O SERVICES BETWEEN NODES_simplified_abstract_(intel corporation)
Inventor(s): Debendra Das Sharma of Saratoga CA (US) for intel corporation, Robert G. Blankenship of Tacoma WA (US) for intel corporation, Suresh S. Chittor of Portland OR (US) for intel corporation, Kenneth C. Creta of Gig Harbor WA (US) for intel corporation, Balint Fleischer of Groton MA (US) for intel corporation, Michelle C. Jen of Mountain View CA (US) for intel corporation, Mohan J. Kumar of Aloha OR (US) for intel corporation, Brian S. Morris of Santa Clara CA (US) for intel corporation
IPC Code(s): G06F13/16, G06F12/14, G06F13/38, G06F13/42
Abstract: a first die has a port to couple the first die to a second die over a die-to-die interconnect. the port includes circuitry to implement a physical layer of the die-to-die interconnect, send first protocol identification data over the physical layer to identify a first protocol in a plurality of protocols, send first data over the interconnect to the second die, wherein the first data comprise data of the first protocol, send second protocol identification data over the physical layer to identify a different second protocol in the plurality of protocols, and send second data over the interconnect to the second die, wherein the second data comprise flits of the second protocol.
Inventor(s): Dinakar Kondru of Frisco TX (US) for intel corporation, Deepak Abraham Mathaikutty of Chandler AZ (US) for intel corporation, Arnab Raha of San Jose CA (US) for intel corporation, Umer Iftikhar Cheema of Hillsboro OR (US) for intel corporation
IPC Code(s): G06F17/17, G06F1/035
Abstract: a non-linear activation function may be approximated by linear functions. the input range of the activation function may be divided into input segments. one or more input segments may be selected based on statistical analysis of input data elements in the input range. a parameter of a first linear function that approximates the activation function for at least part of a selected input segment may be stored in a first portion of a first look-up table (lut). the first portion of the first lut is dedicated to a first group of post processing engines (ppes). a parameter of a second linear function that approximates the activation function for at least part of an unselected input segment may be stored in a shared pool of lut entries, which includes a second portion of the first lut and a portion of a second lut and is shared by multiple groups of ppes.
Inventor(s): Yeluri Raghuram of Sunyvale CA (US) for intel corporation, Haidong Xia of Folsom CA (US) for intel corporation, Uttam Shetty of Granite Bay CA (US) for intel corporation, Anil Rao of Menlo Park CA (US) for intel corporation, Sudhir Subbarao Bangalore of Bangalore (IN) for intel corporation, Raghavender Nagarajan of Bangalore (IN) for intel corporation, Kekuut Hoomkwap of Clarksburg VA (US) for intel corporation, Wei Peng of Folsom CA (US) for intel corporation
IPC Code(s): G06F21/33, G06F21/53, G06F21/57
Abstract: various systems and methods are described for implementing trust authority or trust attestation verification operations, including for trust-as-a-service or attestation-as-a-service implementations, in accordance with the techniques discussed herein. in various examples, operations and configurations are described to enable service-to-service attestation using a trust authority, to operate an attestation service, and to coordinate trust operations between relying and requesting parties.
20240160739.NFT-based Firmware Management_simplified_abstract_(intel corporation)
Inventor(s): Ke HAN of Shanghai (CN) for intel corporation, Weize YE of Shanghai (CN) for intel corporation, Ling YUE of Shanghai (CN) for intel corporation
IPC Code(s): G06F21/57, G06F8/61, G06F8/71
Abstract: various examples relate to methods, apparatuses, devices and computer programs for a client device and a firmware management device, to the client device and the firmware management device, and to a system. the method for the client device comprises determining, on a blockchain, a non-fungible token (nft) specifying a firmware for the client device, with the client device being set as owner of the nft and managing a firmware of the client device based on the firmware specified by the nft.
Inventor(s): Uzi Sarel of Zichron-Yaakov (IL) for intel corporation, Ehud Cohen of Kiryat Motskin (IL) for intel corporation, Tomer Schwartz of Even Yehuda (IL) for intel corporation, Amitai Armon of Tel-Aviv (IL) for intel corporation, Yahav Shadmiy of Ramat Gan (IL) for intel corporation, Amit Bleiweiss of Yad Binyamin (IL) for intel corporation, Gal Leibovich of Kiryat Yam (IL) for intel corporation, Jeremie Dreyfuss of Raanana (IL) for intel corporation, Lev Faivishevsky of Kfar Saba (IL) for intel corporation, Tomer Bar-On of Petah Tikva (IL) for intel corporation, Yaniv Fais of Tel Aviv (IL) for intel corporation, Jacob Subag of Kiryat Haim (IL) for intel corporation
IPC Code(s): G06N3/063, G06F9/30, G06N3/044, G06N3/045, G06N3/084
Abstract: in an example, an apparatus comprises a plurality of execution units comprising at least a first type of execution unit and a second type of execution unit and logic, at least partially including hardware logic, to expose embedded cast operations in at least one of a load instruction or a store instruction; determine a target precision level for the cast operations; and load the cast operations at the target precision level. other embodiments are also disclosed and claimed.
Inventor(s): Abhisek KUNDU of Bangalore (IN) for intel corporation, NAVEEN MELLEMPUDI of Bangalore (IN) for intel corporation, DHEEVATSA MUDIGERE of Bangalore (IN) for intel corporation, Dipankar DAS of Pune (IN) for intel corporation
IPC Code(s): G06N3/08, G06F9/46, G06N3/044, G06N3/045, G06N3/063, G06N3/084, G06N5/04, G06T15/00
Abstract: one embodiment provides for a computer-readable medium storing instructions that cause one or more processors to perform operations comprising determining a per-layer scale factor to apply to tensor data associated with layers of a neural network model and converting the tensor data to converted tensor data. the tensor data may be converted from a floating point datatype to a second datatype that is an 8-bit datatype. the instructions further cause the one or more processors to generate an output tensor based on the converted tensor data and the per-layer scale factor.
20240161077.Concept for Performing Operations on an Asset_simplified_abstract_(intel corporation)
Inventor(s): Clair Michael BOWMAN of Boise ID (US) for intel corporation, Prakash NARAYANA MOORTHY of Beaverton OR (US) for intel corporation, Bruno VAVALA of Hillsboro OR (US) for intel corporation, Marcela S. MELARA of Beaverton OR (US) for intel corporation
IPC Code(s): G06Q20/12, G06Q20/10, G06Q20/38
Abstract: various examples relate to methods, apparatuses, device, computer programs, computer systems and systems. a method comprises obtaining, by a non-fungible token (nft) smart contract being executed in a trusted execution environment, a request to perform an operation using the asset, providing, by the nft smart contract, the request for a service for providing access to the asset if the request is obtained from a current owner of the nft smart contract, obtaining, by the nft smart contract, a result provided by the service for providing access to the asset, the result being based on the request, and providing, by the nft smart contract, the result for the current owner of the nft smart contract.
20240161226.MEMORY PREFETCHING IN MULTIPLE GPU ENVIRONMENT_simplified_abstract_(intel corporation)
Inventor(s): Joydeep Ray of Folsom CA (US) for intel corporation, Aravindh Anantaraman of Folsom CA (US) for intel corporation, Valentin Andrei of San Jose CA (US) for intel corporation, Abhishek R. Appu of El Dorado Hills CA (US) for intel corporation, Nicolas Galoppo von Borries of Portland OR (US) for intel corporation, Varghese George of Folsom CA (US) for intel corporation, Altug Koker of El Dorado Hills CA (US) for intel corporation, Elmoustapha Ould-Ahmed-Vall of Chandler AZ (US) for intel corporation, Mike Macpherson of Portland OR (US) for intel corporation, Subramaniam Maiyuran of Gold River CA (US) for intel corporation
IPC Code(s): G06T1/20, G06F9/38, G06T1/60, G06T15/00
Abstract: embodiments are generally directed to memory prefetching in multiple gpu environment. an embodiment of an apparatus includes multiple processors including a host processor and multiple graphics processing units (gpus) to process data, each of the gpus including a prefetcher and a cache; and a memory for storage of data, the memory including a plurality of memory elements, wherein the prefetcher of each of the gpus is to prefetch data from the memory to the cache of the gpu; and wherein the prefetcher of a gpu is prohibited from prefetching from a page that is not owned by the gpu or by the host processor.
Inventor(s): Abhishek Appu of El Dorado Hills CA (US) for intel corporation, Subramaniam Maiyuran of Gold River CA (US) for intel corporation, Mike Macpherson of Portland OR (US) for intel corporation, Fangwen Fu of Folsom CA (US) for intel corporation, Jiasheng Chen of El Dorado Hills CA (US) for intel corporation, Varghese George of Folsom CA (US) for intel corporation, Vasanth Ranganathan of El Dorado Hills CA (US) for intel corporation, Ashutosh Garg of Folsom CA (US) for intel corporation, Joydeep Ray of Folsom CA (US) for intel corporation
IPC Code(s): G06T1/20, G06F7/544, G06F9/50, G06F12/0806, G06F15/80, G06F17/16, G06N3/048, G06N3/08, G06N3/084
Abstract: embodiments described herein include software, firmware, and hardware logic that provides techniques to perform arithmetic on sparse data via a systolic processing unit. one embodiment provides for data aware sparsity via compressed bitstreams. one embodiment provides for block sparse dot product instructions. one embodiment provides for a depth-wise adapter for a systolic array.
Inventor(s): Hongzhai Tao of Beijing (CN) for intel corporation, Yikai Fang of Bejing (CN) for intel corporation, Longwei Fang of Beijing (CN) for intel corporation
IPC Code(s): G06T7/246, G06T7/277, G06T7/73, G06V10/74
Abstract: a method and system of image processing with multi-skeleton tracking uses a temporal object key point loss metric.
Inventor(s): Karthik Vaidyanathan of Berkeley CA (US) for intel corporation, Prasoonkumar Surti of Folsom CA (US) for intel corporation, Hugues Labbe of Folsom CA (US) for intel corporation, Atsuo Kuwahara of Portland OR (US) for intel corporation, Sameer KP of Bangalore (IN) for intel corporation, Jonathan Kennedy of Bristol (GB) for intel corporation, Murali Ramadoss of Folsom CA (US) for intel corporation, Michael Apodaca of Folsom CA (US) for intel corporation, Abhishek Venkatesh of Hillsboro OR (US) for intel corporation
IPC Code(s): G06T11/00, G06T1/20, G06T1/60, G06T15/00
Abstract: systems, apparatuses and methods may provide for technology that determines a stencil value and uses the stencil value to control, via a stencil buffer, a coarse pixel size of a graphics pipeline. additionally, the stencil value may include a first range of bits defining a first dimension of the coarse pixel size and a second range of bits defining a second dimension of the coarse pixel size. in one example, the coarse pixel size is controlled for a plurality of pixels on a per pixel basis.
20240161387.DEEP GEOMETRIC MODEL FITTING_simplified_abstract_(intel corporation)
Inventor(s): Rene Ranftl of Munich (DE) for intel corporation, Vladlen Koltun of Santa Clara CA (US) for intel corporation
IPC Code(s): G06T15/10, G06N3/045, G06N20/00, G06T1/20, G06T3/08, G06T7/20, G06T7/593, G06T17/10
Abstract: systems, apparatuses and methods may provide for technology that generates, by a first neural network, an initial set of model weights based on input data and iteratively generates, by a second neural network, an updated set of model weights based on residual data associated with the initial set of model weights and the input data. additionally, the technology may output a geometric model of the input data based on the updated set of model weights. in one example, the first neural network and the second neural network reduce the dependence of the geometric model on the number of data points in the input data.
20240161494.METHODS AND DEVICES FOR GESTURE RECOGNITION_simplified_abstract_(intel corporation)
Inventor(s): Ping GUO of Beijing (CN) for intel corporation, Sangeeta MANEPALLI of Chandler AZ (US) for intel corporation, Lidan ZHANG of Beijing (CN) for intel corporation, Peng WANG of Beijing (CN) for intel corporation, Yimin ZHANG of Beijing (CN) for intel corporation
IPC Code(s): G06V10/98, G06T5/50, G06T5/73, G06T7/70, G06V10/77, G06V10/82, G06V40/20
Abstract: disclosed herein is a gesture recognition device that includes an input interface configured to receive a sequence of images, each image showing a body part with which a gesture is performed from a viewpoint of a camera. the gesture recognition device also generates a sequence of motion-compensated images from the sequence comprising generating a motion-compensated image for an image of the sequence by compensating the movement of the camera viewpoint from a reference camera viewpoint to the viewpoint from which the image shows the body part based on the image and a motion-compensated image of the sequence generated for a preceding image of the sequence which precedes the image in the sequence and estimate the gesture from the sequence of motion-compensated images.
Inventor(s): Christopher J. Jezewski of Portland OR (US) for intel corporation
IPC Code(s): H01L21/67, H01J37/32, H01L21/3213, H01L21/683, H01L23/528
Abstract: disclosed herein are tools and methods for subtractively patterning metals. these tools and methods may permit the subtractive patterning of metal (e.g., copper, platinum, etc.) at pitches lower than those achievable by conventional etch tools and/or with aspect ratios greater than those achievable by conventional etch tools. the tools and methods disclosed herein may be cost-effective and appropriate for high-volume manufacturing, in contrast to conventional etch tools.
20240162134.VARIED BALL BALL-GRID-ARRAY (BGA) PACKAGES_simplified_abstract_(intel corporation)
Inventor(s): Xiao LU of Chandler AZ (US) for intel corporation, Jiongxin LU of Chandler AZ (US) for intel corporation, Christopher COMBS of Portland OR (US) for intel corporation, Alexander HUETTIS of Aloha OR (US) for intel corporation, John HARPER of Chandler AZ (US) for intel corporation, Jieping ZHANG of Mesa AZ (US) for intel corporation, Nachiket R. RARAVIKAR of Gilbert AZ (US) for intel corporation, Pramod MALATKAR of Chandler AZ (US) for intel corporation, Steven A. KLEIN of Chandler AZ (US) for intel corporation, Carl DEPPISCH of Tempe AZ (US) for intel corporation, Mohit SOOD of Chandler AZ (US) for intel corporation
IPC Code(s): H01L23/498, B23K3/06, H01L23/538
Abstract: embodiments disclosed herein include electronic packages. in an embodiment, the electronic package comprises a first substrate; a second substrate; and an array of interconnects electrically coupling the first substrate to the second substrate. in an embodiment, the array of interconnects comprises first interconnects, wherein the first interconnects have a first volume and a first material composition, and second interconnects, wherein the second interconnects have a second volume and a second material composition, and wherein the first volume is different than the second volume and/or the first material composition is different than the second material composition.
Inventor(s): Ehren MANNEBACH of Beaverton OR (US) for intel corporation, Aaron LILAK of Beaverton OR (US) for intel corporation, Hui Jae YOO of Portland OR (US) for intel corporation, Patrick MORROW of Portland OR (US) for intel corporation, Anh PHAN of Beaverton OR (US) for intel corporation, Willy RACHMADY of Beaverton OR (US) for intel corporation, Cheng-Ying HUANG of Portland OR (US) for intel corporation, Gilbert DEWEY of Beaverton OR (US) for intel corporation, Rishabh MEHANDRU of Portland OR (US) for intel corporation
IPC Code(s): H01L23/522, H01L21/8234, H01L25/16, H01L29/06
Abstract: embodiments disclosed herein include electronic systems with vias that include a horizontal and vertical portion in order to provide interconnects to stacked components, and methods of forming such systems. in an embodiment, an electronic system comprises a board, a package substrate electrically coupled to the board, and a die electrically coupled to the package substrate. in an embodiment the die comprises a stack of components, and a via adjacent to the stack of components, wherein the via comprises a vertical portion and a horizontal portion.
20240162157.BUMPLESS HYBRID ORGANIC GLASS INTERPOSER_simplified_abstract_(intel corporation)
Inventor(s): Jeremy D. Ecton of Gilbert AZ (US) for intel corporation, Brandon Christian Marin of Gilbert AZ (US) for intel corporation, Aleksandar Aleksov of Chandler AZ (US) for intel corporation, Srinivas V. Pietambaram of Chandler AZ (US) for intel corporation, Haobo Chen of Chandler AZ (US) for intel corporation
IPC Code(s): H01L23/538, H01L21/48, H01L23/15, H01L23/498
Abstract: a bumpless hybrid organic glass interposer. one or more high density pattern (hdp) routing layers are placed on a functional, thin, carrier, separate from the intended organic substrate patch or package. the hdp layer(s) is/are then attached to the substrate package. the interposers achieve electrical connections between the hdp layer and underlying routing layer of the substrate package by utilizing a self-align dry etch process through landing pads connected to the hdp routing.
Inventor(s): Brandon C. Marin of Gilbert AZ (US) for intel corporation, Gang Duan of Chandler AZ (US) for intel corporation, Jeremy Ecton of Gilbert AZ (US) for intel corporation, Sashi Shekhar Kandanur of Phoenix AZ (US) for intel corporation, Ravindranath Vithal Mahajan of Chandler AZ (US) for intel corporation, Suddhasattwa Nad of Chandler AZ (US) for intel corporation, Srinivas V. Pietambaram of Chandler AZ (US) for intel corporation, Hiroki Tanaka of Gilbert AZ (US) for intel corporation
IPC Code(s): H01L23/538, B81B1/00, H01L23/31, H01L23/467, H01L23/498
Abstract: embodiments of a microelectronic assembly includes: an interposer comprising a first portion in contact along an interface with a second portion; a first integrated circuit (ic) die embedded in a dielectric material in the first portion of the interposer; and a second ic die coupled to the first portion of the interposer opposite to the second portion, wherein: the second portion comprises a glass substrate with a channel within the glass substrate, a portion of the channel has an opening at the interface, a conductive pad in the first portion is exposed in the opening, and the conductive pad is coupled to a circuit in at least one of the first ic die or the second ic die.
Inventor(s): Jeremy Ecton of Gilbert AZ (US) for intel corporation, Changhua Liu of Chandle AZ (US) for intel corporation, Brandon C. Marin of Gilbert AZ (US) for intel corporation, Srinivas V. Pietambaram of Chandler AZ (US) for intel corporation, Mohammad Mamunur Rahman of Gilbert AZ (US) for intel corporation
IPC Code(s): H01L25/065, H01L23/498, H01L23/538, H01L23/552
Abstract: embodiments of a package substrate includes: a conductive via in a first layer, the first layer comprising a positive-type photo-imageable dielectric; a conductive trace in a second layer, the second layer comprising a negative-type photo-imageable dielectric; and an insulative material between the first layer and the second layer, the insulative material configured to absorb electromagnetic radiation in a wavelength range between 10 nanometers and 800 nanometers. the conductive via is directly attached to the conductive trace through the insulative material, the positive-type photo-imageable dielectric is soluble in a photoresist developer upon exposure to the electromagnetic radiation, and the negative-type photo-imageable dielectric is insoluble in the photoresist developer upon exposure to the electromagnetic radiation.
Inventor(s): Sean T. Ma of Portland OR (US) for intel corporation, Andy Chih-Hung Wei of Yamhill OR (US) for intel corporation, Guillaume Bouche of Portland OR (US) for intel corporation
IPC Code(s): H01L29/06, H01L23/00
Abstract: disclosed herein are source/drain regions in integrated circuit (ic) structures, as well as related methods and components. for example, in some embodiments, an ic structure may include: an array of channel regions, including a first channel region and an adjacent second channel region; a first source/drain region proximate to the first channel region; a second source/drain region proximate to the second channel region; and an insulating material region at least partially between the first source/drain region and the second source/drain region.
Inventor(s): Subhash M. JOSHI of Hillsboro OR (US) for intel corporation, Jeffrey S. LEIB of Beaverton OR (US) for intel corporation, Michael L. HATTENDORF of Portland OR (US) for intel corporation
IPC Code(s): H01L29/66, H01L21/02, H01L21/033, H01L21/28, H01L21/285, H01L21/308, H01L21/311, H01L21/762, H01L21/768, H01L21/8234, H01L21/8238, H01L23/522, H01L23/528, H01L23/532, H01L27/02, H01L27/088, H01L27/092, H01L29/06, H01L29/08, H01L29/165, H01L29/167, H01L29/417, H01L29/51, H01L29/78, H10B10/00
Abstract: embodiments of the disclosure are in the field of advanced integrated circuit structure fabrication and, in particular, 10 nanometer node and smaller integrated circuit structure fabrication and the resulting structures. in an example, an integrated circuit structure includes a fin. a gate dielectric layer is over the top of the fin and laterally adjacent the sidewalls of the fin. a gate electrode is over the gate dielectric layer over the top of the fin and laterally adjacent the sidewalls of the fin. first and second semiconductor source or drain regions are adjacent the first and second sides of the gate electrode, respectively. first and second trench contact structures are over the first and second semiconductor source or drain regions, respectively, the first and second trench contact structures both comprising a u-shaped metal layer and a t-shaped metal layer on and over the entirety of the u-shaped metal layer.
Inventor(s): Nicholas Whinnett of Bath and North East Somerset (GB) for intel corporation, Dawei Ying of Hillsboro OR (US) for intel corporation, Bishwarup Mondal of San Ramon CA (US) for intel corporation, Jan Schreck of San Jose CA (US) for intel corporation, Jaemin Han of Portland OR (US) for intel corporation, Leifeng Ruan of Beijing (CN) for intel corporation, Jianli Sun of Beaverton OR (US) for intel corporation
IPC Code(s): H04B7/06, H04B7/0452
Abstract: various embodiments herein are directed to beamforming associated with multiple-input multiple-output (mimo) modes in open radio access network (o-ran) systems. in one embodiment, an apparatus comprises: memory to store beamforming configuration information associated with a plurality mimo modes; and processing circuitry, coupled with the memory to: retrieve the beamforming configuration information from the memory; request, based on the beamforming configuration information, measurements associated with the plurality of mimo modes; receive the measurements associated with the plurality of mimo modes; and based on the received measurements, train an artificial intelligence/machine learning (ai/ml) model that is to predict relative beamforming performance between the plurality of mimo modes.
Inventor(s): Anshu AGARWAL of Bangalore (IN) for intel corporation, Chandrashekar GOWDA of Bangalore (IN) for intel corporation, Barath C. PETIT of Bangalore (IN) for intel corporation, Suranjan CHAKRABORTY of Bangalore (IN) for intel corporation, Naveen MANOHAR of Bangalore (IN) for intel corporation, Amit Singh CHANDEL of Bhoganhalli (IN) for intel corporation, Mythili HEGDE of Bangalore (IN) for intel corporation
IPC Code(s): H04J3/06, H04W56/00
Abstract: the present disclosure relates to a device including a processor configured to: detect a failed reception of time synchronization information at a follower device, wherein the time synchronization information provides an update of a clock of the follower device for synchronization to a clock of a leader device; determine whether a clock drift between the clock of the follower device and the clock of the leader device is less than a predefined drift threshold; and in the case that the clock drift is less than the predefined drift threshold, instruct an update of the clock of the follower device based on time synchronization information previously received at the follower device.
Inventor(s): Yingyang Li of Beijing (CN) for intel corporation, Daewon Lee of Portland OR (US) for intel corporation, Gang Xiong of Beaverton OR (US) for intel corporation, Debdeep Chatterjee of San Jose CA (US) for intel corporation
IPC Code(s): H04L1/1829
Abstract: a user equipment (ue) configured for operation in a 5generation (5g) new radio (nr) system (5gs) (5g nr) in which a multi-transmission time interval (tti) dci schedules multiple physical downlink shared channels (pdschs), generates a type-1 harq-ack codebook for candidate pdsch reception occasions corresponding to an uplink slot. the ue determines a set of downlink (de) slots for the multiple scheduled pdschs and a set of a start and length indicator values (slivs) for the de slots based on configured slot timing values (k1) and a configured time domain resource allocation (tdra) table.
Inventor(s): Jing ZHU of Portland OR (US) for intel corporation, Pengfei ZHAO of Beijing (CN) for intel corporation, Nageen HIMAYAT of Danville CA (US) for intel corporation, Vered BAR BRACHA of Somerville MA (US) for intel corporation
IPC Code(s): H04L1/1867, H04L1/00, H04L1/1607, H04L43/0829, H04L47/2483, H04W24/10
Abstract: packet recovery mechanisms for wireless networks, which improve end-to-end (e2e) reliability, are provided. first embodiments include packet retransmission between a receiver and a transmitter, wherein, if the transmitter cannot find a lost packet in its transmission buffer, the transmitter sends a first sequence number (fsn) report to the receiver to notify the receiver of a sequence number (sn) of an oldest (acknowledged) packet in the buffer. in response, the receiver does not report lost packets whose sn is older than the fsn. second embodiments involve using a network coding algorithm to recover lost packets, wherein the transmitter sends a control message to the receiver that includes a coded packet to be recovered and information for decoding the coded packet. other embodiments may be described and/or claimed.
20240163221.MANAGEMENT OF PACKET TRANSMISSION AND RESPONSES_simplified_abstract_(intel corporation)
Inventor(s): Hossein FARROKHBAKHT of Toronto (CA) for intel corporation, Fabrizio PETRINI of Menlo Park CA (US) for intel corporation
IPC Code(s): H04L47/32, H04L49/109
Abstract: examples described herein relate to a router. in some examples, the router includes an interface and circuitry coupled to the interface. in some examples, the circuitry is to: based on detection of a drop of a packet of a flow: drop subsequently received packets of the flow and based on receipt of a packet associated with the dropped packet of the flow, forward the received packet and subsequent received packets of the flow.
Inventor(s): Ned M. Smith of Beaverton OR (US) for intel corporation
IPC Code(s): H04L9/40, H04L67/142
Abstract: various systems and methods of establishing and providing credential dependency information in restful transactions are described. in an example, accessing credential resource dependencies may be performed by a credential management service (cms) or other server, with operations including: receiving a request for a credential resource in a representation state transfer (restful) communication; identifying the credential resource which has a credential path that indicates a dependency associated with a credential; identifying dependency characteristics of the credential resource, based on the dependency; populating the credential resource to include a dependent credential, based on the dependency characteristics; and transmitting the populated credential resource in response to the request. in further examples, the credential resource and the credential path within the credential resource may be established, such as by defining paths to trust anchor entries, or dependencies to a trusted computing key of a trusted computing module that attests to trust properties.
Inventor(s): Joydeep Ray of Folsom CA (US) for intel corporation, Travis T. Schluessler of Hillsboro OR (US) for intel corporation, Prasoonkumar Surti of Folsom CA (US) for intel corporation, John H. Feit of Folsom CA (US) for intel corporation, Nikos Kaburlasos of Lincoln CA (US) for intel corporation, Jacek Kwiatkowski of Santa Clara CA (US) for intel corporation, Abhishek R. Appu of El Dorado Hills CA (US) for intel corporation, James M. Holland of Folsom CA (US) for intel corporation, Jeffery S. Boles of Folsom CA (US) for intel corporation, Jonathan Kennedy of Bristol (GB) for intel corporation, Louis Feng of San Jose CA (US) for intel corporation, Atsuo Kuwahara of Hillsboro OR (US) for intel corporation, Barnan Das of San Jose CA (US) for intel corporation, Narayan Biswal of Folsom CA (US) for intel corporation, Stanley J. Baran of Elk Grove CA (US) for intel corporation, Gokcen Cilingir of Sunnyvale CA (US) for intel corporation, Nilesh V. Shah of Folsom CA (US) for intel corporation, Archie Sharma of Folsom CA (US) for intel corporation, Mayuresh M. Varerkar of Folsom CA (US) for intel corporation
IPC Code(s): H04S7/00, G06F3/01, G06T1/20, G06T15/06, G09B21/00, H04R1/40, H04R3/00
Abstract: systems, apparatuses and methods may provide away to render augmented reality (ar) and/or virtual reality (vr) sensory enhancements using ray tracing. more particularly, systems, apparatuses and methods may provide a way to normalize environment information captured by multiple capture devices, and calculate, for an observer, the sound sources or sensed events vector paths. the systems, apparatuses and methods may detect and/or manage one or more capture devices and assign one or more the capture devices based on one or more conditions to provide observer an immersive vr/ar experience.
Inventor(s): Anshu AGARWAL of Bangalore (IN) for intel corporation, Krishna Chaitanya SUDI of Bellandur (IN) for intel corporation, Mythili HEGDE of Bangalore (IN) for intel corporation, Ingolf KARLS of Feldkirchen (DE) for intel corporation
IPC Code(s): H04W24/08, H04W24/10
Abstract: a device for operating a radio communication network may include a processor configured to receive radio communication network operational data from at least one communication terminal in accordance with a communication device management protocol, and determine communication network operation parameters to control the operation of the communication network based on the received radio communication network operational data, and may include a memory to store the radio communication network operational data.
Inventor(s): Gang Xiong of Beaverton OR (US) for intel corporation
IPC Code(s): H04W72/1268, H04B7/06, H04L5/00, H04W72/232, H04W76/20
Abstract: a user equipment (ue) configured for multi-beam operation in a fifth-generation new radio (5g-nr) system may decode a physical downlink control channel (pdcch). when a dci format for a configured grant (cg) based small data transmission (sdt) (cg-sdt) is detected and a transport block (tb) is received in a corresponding physical downlink shared channel (pdsch), the ue may assume that a demodulation reference signal (dm-rs) antenna port associated with pdcch receptions and a dm-rs antenna port associated with pdsch receptions are quasi co-located (qcl) with a synchronization signal/physical broadcast channel (ss/pbch) associated with a physical uplink shared channel (pusch) resource for the cg-sdt. during the cg-sdt, the ue may encode a pucch for transmission using a same spatial domain transmission filter as a last pusch transmission.
Inventor(s): Gang Xiong of Portland OR (US) for intel corporation, Yingyang Li of Santa Clara CA (US) for intel corporation, Gregory Morozov of Santa Clara CA (US) for intel corporation, Daewon Lee of Portland OR (US) for intel corporation
IPC Code(s): H04W72/23, H04L1/1812, H04L5/00, H04W72/0446
Abstract: various embodiments herein are directed to multi-transmission time interval (tti) scheduling for data transmission for system operating above the 52.6 ghz carrier frequency. other embodiments may be disclosed and/or claimed.
Inventor(s): Guotong Wang of Beijing (CN) for intel corporation, Alexei Davydov of Nizhny Novgorod (RU) for intel corporation
IPC Code(s): H04W72/232, H04W72/1273
Abstract: an apparatus and system for aperiodic sounding reference signals (srs) transmission are described. downlink control information (dci) format 2_3 indicates a transmission configuration indicator (tci) state for beam indication for transmission of an srs triggered by the dci. an explicit field is added to the dci to indicate the tci state or the tci state of the scheduling carrier used to transmit the dci is used for the srs. the tci state indicates a joint uplink/downlink tci state or a separate uplink or downlink tci state. the dci indicates an available slot to use for the srs explicitly in a dci field or implicitly based on the component carrier used for transmission of the srs, the slotoffset parameter, or the first available slot.
Inventor(s): Alexei Davydov of Nizhny Novgorod (RU) for intel corporation, Dong Han of Sunnyvale CA (US) for intel corporation, Bishwarup Mondal of San Ramon CA (US) for intel corporation
IPC Code(s): H04W72/232, H04B7/0456, H04W72/1268
Abstract: various embodiments herein are directed to scheduling single-dci-based physical uplink shared channel (pusch) transmissions. other embodiments may be disclosed or claimed.
20240164010.RADIO FREQUENCY FRONT-END STRUCTURES_simplified_abstract_(intel corporation)
Inventor(s): Sidharth Dalmia of Portland OR (US) for intel corporation, Zhenguo Jiang of Chandler AZ (US) for intel corporation, William J. Lambert of Chandler AZ (US) for intel corporation, Kirthika Nahalingam of San Jose CA (US) for intel corporation, Swathi Vijayakumar of Folsom CA (US) for intel corporation
IPC Code(s): H05K1/02, G06F1/16, H01F5/04, H05K1/18
Abstract: disclosed herein are radio frequency (rf) front-end structures, as well as related methods and devices. in some embodiments, an rf front-end package may include an rf package substrate including an embedded passive circuit element. at least a portion of the embedded passive circuit element may be included in a metal layer of the rf package substrate. the rf package substrate may also include a ground plane in the metal layer.
Inventor(s): Samarth Alva of Bangalore (IN) for intel corporation, Prakash Kurma Raju of Bangalore (IN) for intel corporation, Shivaraju Neerati of Bhupalpalle (IN) for intel corporation, Navneet Singh of Bangalore (IN) for intel corporation, Ravishankar Srikanth of Bengaluru (IN) for intel corporation
IPC Code(s): H05K7/20, G06F1/16, H05K5/02
Abstract: an electronic device or a component thereof is described, which may include communication and/or thermal interconnects. the device may include hingedly coupled portions, where the interconnects are axially arranged (e.g., coincident) with respect to a hinge axis of the foldable electronic device.
20240164080.CHANNEL DEPOPULATION FOR FORKSHEET TRANSISTORS_simplified_abstract_(intel corporation)
Inventor(s): Peng ZHENG of Portland OR (US) for intel corporation, Varun MISHRA of Hillsboro OR (US) for intel corporation, Harold W. KENNEL of Portland OR (US) for intel corporation, Eric A. KARL of Portland OR (US) for intel corporation, Tahir GHANI of Portland OR (US) for intel corporation
IPC Code(s): H10B10/00, H01L29/06, H01L29/10
Abstract: embodiments disclosed herein include forksheet transistor devices with depopulated channels. in an example, an integrated circuit structure includes a backbone. a first transistor device includes a first vertical stack of semiconductor channels adjacent to a first edge of the backbone. the first vertical stack of semiconductor channels includes first semiconductor channels and a second semiconductor channel over or beneath the first semiconductor channels. a concentration of a dopant in the first semiconductor channels is less than a concentration of the dopant in the second semiconductor channel. a second transistor device includes a second vertical stack of semiconductor channels adjacent to a second edge of the backbone opposite the first edge.
- Intel Corporation
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