Intel Corporation patent applications on March 28th, 2024
Patent Applications by Intel Corporation on March 28th, 2024
Intel Corporation: 99 patent applications
Intel Corporation has applied for patents in the areas of H01L23/528 (13), H01L29/06 (13), H01L29/0673 (12), H01L29/775 (12), H01L29/423 (11)
With keywords such as: structure, material, gate, data, device, layer, between, semiconductor, contact, and include in patent application abstracts.
Patent Applications by Intel Corporation
Inventor(s): Jeremy D. Ecton of Gilbert AZ (US) for intel corporation, Brandon C. Marin of Gilbert AZ (US) for intel corporation, Srinivas Venkata Ramanuja Pietambaram of Chandler AZ (US) for intel corporation, Oladeji Fadayomi of Maricopa AZ (US) for intel corporation, Oscar Ojeda of Chandler AZ (US) for intel corporation
IPC Code(s): B81B7/00, B81C1/00
Abstract: disclosed herein are microelectronics package architectures having self-aligned air gaps and methods of manufacturing the same. the microelectronics packages may include first and second substrates, first and second traces, and a photosensitive material. the first trace may be attached to the first substrate and comprise a first sidewall. the second trace may be attached to the first substrate and comprise a second sidewall. the second traced may be spaced a distance from the first trace with the second sidewall facing the first sidewall. first and second portions of the photosensitive material may be attached to the first and second sidewalls, respectively. the second substrate may be attached to the first and second traces. the first and second substrates and the first and second traces may form the air gap in between the first and second traces.
Inventor(s): Sreejith Satheesakurup of Cherthala (IN) for intel corporation, Rekha Bhagat of Orissa (IN) for intel corporation, Shailendra Singh Chauhan of Bengaluru (IN) for intel corporation
IPC Code(s): F25B21/02, G06F1/20, G06F1/3296, H01L23/38
Abstract: systems, apparatuses and methods may provide for technology that includes a peltier module and a subsystem thermally coupled and electrically coupled to the peltier module, the subsystem to monitor an operational state of the subsystem, place the peltier module in a first power mode if the operational state indicates that a demand spike exists with respect to the subsystem, and place the peltier module in a second power mode if the operational state indicates that the demand spike does not exist with respect to the subsystem, wherein the second power mode is associated with a lower level of system power consumption than the first power mode.
20240103072.TESTING A SEMICONDUCTOR DEVICE USING X-RAYS_simplified_abstract_(intel corporation)
Inventor(s): Patrick PARDY of Hillsboro OR (US) for intel corporation, Kimberlee CELIO of Portland OR (US) for intel corporation, Sanchari SEN of Beaverton OR (US) for intel corporation, May Ling OH of Portland OR (US) for intel corporation, Shuai ZHAO of Beaverton OR (US) for intel corporation, Joshua W. KEVEK of Portland OR (US) for intel corporation, Evgeny Gregory NISENBOIM of Haifa (IL) for intel corporation, Amir RAVEH of Haifa (IL) for intel corporation, Boris SIMKHOVICH of Haifa (IL) for intel corporation, Charles A. PETERSON of Hillsboro OR (US) for intel corporation, Kevin JOHNSON of Portland OR (US) for intel corporation, Martin Eric Gostasson VON HAARTMAN of Portland OR (US) for intel corporation, Eli ABU AYOB of Haifa (IL) for intel corporation, Xianghong TONG of Portland OR (US) for intel corporation
IPC Code(s): G01R31/302
Abstract: embodiments described herein may be related to apparatuses, processes, systems, and/or techniques for using x-rays to alter or observe circuits within a semiconductor device before, during or after a test of the semiconductor device. other embodiments may be described and/or claimed.
Inventor(s): Patrick PARDY of Hillsboro OR (US) for intel corporation, Robert WADELL of Sacramento CA (US) for intel corporation, Tewodros WONDIMU of Hillsboro OR (US) for intel corporation, Michael APODACA of West Roxbury MA (US) for intel corporation, Joshua FREIER of Portland OR (US) for intel corporation, Amir RAVEH of Haifa (IL) for intel corporation, Eric BRUMMER of Orangevale CA (US) for intel corporation
IPC Code(s): G01R31/307, H01L23/467
Abstract: embodiments described herein may be related to apparatuses, processes, systems, and/or techniques for an enclosure, which may be referred to as a cartridge, that surrounds a semiconductor device prior to the semiconductor device being bombarded with an electron beam during operational testing. in embodiments, the enclosure may include a cooling plate that includes a thermal cooling mechanism that is thermally coupled with the semiconductor device to control the temperature of the semiconductor device during testing. the thermal cooling mechanism may include a manifold that extends through the plate through which a cooled fluid, cooled air, or some other cool material may be circulated to cool the semiconductor device. other embodiments may be described and/or claimed.
Inventor(s): Rakesh KANDULA of Bangalore (IN) for intel corporation, Sankaran MENON of Austin TX (US) for intel corporation, Rolf KUEHNIS of Portland OR (US) for intel corporation
IPC Code(s): G01R31/3185, G01R31/319
Abstract: time to read the data registers in a remote test access port (tap) in a subsystem in a system-on-chip (soc) is reduced by reading multiple data registers in remote test access ports in parallel. a test access port bridge provides access to multiple same width data registers in parallel. the same width data registers can be for the same function or different functions. the subsystems with a remote test access port in the soc can include peripheral component interconnect express (pcie), voltage droop monitors (vdms), in-die variation (idv) monitor fub-lets, temperature sensors, performance monitors and telemetry subsystems.
Inventor(s): Rakesh Kandula of Doddakannelli Bangalore (IN) for intel corporation, Sankaran Menon of Austin TX (US) for intel corporation, Rolf Kuehnis of Portland OR (US) for intel corporation
IPC Code(s): G01R31/3185
Abstract: embodiments described herein may include apparatus, systems, techniques, and/or processes that are directed to performing testing of a device while a system is operational. a device may include computing circuitry and host connectivity registers. host connectivity registers contain configuration and memory mapping data programmed by system software upon power up of the device and computing system. the data contained in host connectivity registers should be always maintained while the computing system is operational. scan test circuitry may be implemented, providing the ability to test the device while the system is operational. preservation circuitry preserves or maintains the data stored in host connectivity registers allowing in-operation testing of the device, ensuring the device the ability to return to full operation at the end of in-operation testing without requiring system software to reprogram the host connectivity registers. by using scan-sealing methods and/or preserving the data in host connectivity registers during in-operation testing, performance and user experience are not degraded.
Inventor(s): Sagar SUTHRAM of Portland OR (US) for intel corporation, John HECK of Berkeley CA (US) for intel corporation, Ling LIAO of Fremont CA (US) for intel corporation, Mengyuan HUANG of Cupertino CA (US) for intel corporation, Wilfred GOMES of Portland OR (US) for intel corporation, Pushkar RANADE of San Jose CA (US) for intel corporation, Abhishek Anil SHARMA of Portland OR (US) for intel corporation
IPC Code(s): G02B6/12, H01L25/16
Abstract: embodiments disclosed herein include through silicon waveguides and methods of forming such waveguides. in an embodiment, a through silicon waveguide comprises a substrate, where the substrate comprises silicon. in an embodiment, a waveguide is provided through the substrate. in an embodiment, the waveguide comprises a waveguide structure. and a cladding around the waveguide structure.
Inventor(s): Sagar SUTHRAM of Portland OR (US) for intel corporation, John HECK of Berkeley CA (US) for intel corporation, Ling LIAO of Fremont CA (US) for intel corporation, Mengyuan HUANG of Cupertino CA (US) for intel corporation, Wilfred GOMES of Portland OR (US) for intel corporation, Pushkar RANADE of San Jose CA (US) for intel corporation, Abhishek Anil SHARMA of Portland OR (US) for intel corporation
IPC Code(s): G02F1/025
Abstract: embodiments disclosed herein include a photonics module and methods of forming photonics modules. in an embodiment, the photonics module comprises a waveguide, and a modulator adjacent to the waveguide. in an embodiment, the modulator comprises a pn junction with a p-doped region and an n-doped region, where the pn junction is vertically oriented so that the p-doped region is over the n-doped region.
Inventor(s): Priyanka Mudgal of Portland OR (US) for intel corporation, Mark Yarvis of Portland OR (US) for intel corporation, Rita H. Wouhaybi of Portland OR (US) for intel corporation
IPC Code(s): G05B23/02
Abstract: systems, apparatus, articles of manufacture, and methods are disclosed to identify causes of defects in industrial environments. an example apparatus includes interface circuitry to access data associated with an object in an environment and programmable circuitry to utilize machine-readable instructions. for example, the programmable circuitry is to identify a cause of a defect of the object based on a timeline of the object in the environment, the timeline based on the data.
Inventor(s): Francesc Guim Bernat of Barcelona (ES) for intel corporation, Karthik Kumar of Chandler AZ (US) for intel corporation, Akhilesh S. Thyagaturu of Tempe AZ (US) for intel corporation, Mario Jose Divan of Hillsboro OR (US) for intel corporation, Matthew Henry Birkner of Las Vegas NV (US) for intel corporation
IPC Code(s): G06F3/06
Abstract: systems, apparatus, articles of manufacture, and methods are disclosed to store data based on an environmental impact of a storage device. an example apparatus to store data, the apparatus includes programmable circuitry to at least one of instantiate or execute the machine readable instructions to determine a first environmental impact associated with storing the data in a first storage device, determine a second environmental impact associated with storing the data in a second storage device, and cause the data to be stored in one of the first storage device or the second storage device based on the first environmental impact and the second environmental impact.
Inventor(s): Jiasheng Chen of El Dorado Hills CA (US) for intel corporation, Supratim Pal of Folsom CA (US) for intel corporation, Changwon Rhee of Rocklin CA (US) for intel corporation, Hong Jiang of Los Altos CA (US) for intel corporation, Kevin Hurd of Flagler Beach FL (US) for intel corporation, Shuai Mu of San Diego CA (US) for intel corporation
IPC Code(s): G06F7/544, G06F7/57, G06F17/16
Abstract: an apparatus to facilitate supporting vector multiply add with double accumulator access in a graphics environment is disclosed. the apparatus includes a processor comprising processing resources, the processing resources comprising multiplier circuitry to: receive operands for a matrix multiplication operation, wherein the operands comprising two source matrices to be multiplied as part of the matrix multiplication operation; and issue a multiply and add vector (madv) instruction for the multiplication operation utilizing a double accumulator access output, wherein the madv instruction to multiply two vectors of the two source matrices in a single floating point (fp) pipeline of the processor.
Inventor(s): Cunming LIANG of Shanghai (CN) for intel corporation, Ping YU of Shanghai (CN) for intel corporation, Zongmin GU of Shanghai (CN) for intel corporation
IPC Code(s): G06F8/65
Abstract: examples relate to apparatuses, devices, methods and computer programs for modifying a target application. an apparatus for a computer system comprises memory circuitry, machine-readable instructions, and processor circuitry to execute the machine-readable instructions to launch, using a loader application, a target application, obtain, by the loader application, information on a kernel system call having been made by the target application, and modify, by the loader application and based on the information on the kernel system call having been made by the target application, an instruction of the target application, wherein the modified instruction is configured to trigger an operation being equivalent to the kernel system call, with the operation being equivalent to the kernel system call while avoiding a context switch.
Inventor(s): Akhilesh S. THYAGATURU of Ruskin FL (US) for intel corporation, Francesc GUIM BERNAT of Barcelona (ES) for intel corporation, Karthik KUMAR of Chandler AZ (US) for intel corporation, Mohit Kumar GARG of Hisar (IN) for intel corporation
IPC Code(s): G06F9/30
Abstract: an apparatus is described. the apparatus includes a memory module. the memory module includes a memory. the memory module includes function execution circuitry. the function execution circuitry is configurable to execute a producer function and a consumer function of a multi-function process. the memory module includes an interface to be coupled to a memory controller.
Inventor(s): Bret TOLL of Hillsboro OR (US) for intel corporation, Christopher J. HUGHES of Santa Clara CA (US) for intel corporation, Dan BAUM of Haifa (IL) for intel corporation, Elmoustapha OULD-AHMED-VALL of Gilbert AZ (US) for intel corporation, Raanan SADE of Portland OR (US) for intel corporation, Robert VALENTINE of Kiryat Tivon (IL) for intel corporation, Mark J. CHARNEY of Lexington MA (US) for intel corporation, Alexander F. HEINECKE of San Jose CA (US) for intel corporation
IPC Code(s): G06F9/30
Abstract: disclosed embodiments relate to systems for performing instructions to quickly convert and use matrices (tiles) as one-dimensional vectors. in one example, a processor includes fetch circuitry to fetch an instruction having fields to specify an opcode, locations of a two-dimensional (2d) matrix and a one-dimensional (1d) vector, and a group of elements comprising one of a row, part of a row, multiple rows, a column, part of a column, multiple columns, and a rectangular sub-tile of the specified 2d matrix, and wherein the opcode is to indicate a move of the specified group between the 2d matrix and the 1d vector, decode circuitry to decode the fetched instruction; and execution circuitry, responsive to the decoded instruction, when the opcode specifies a move from 1d, to move contents of the specified 1d vector to the specified group of elements.
20240103868.Virtual Idle Loops_simplified_abstract_(intel corporation)
Inventor(s): Andreas Kleen of Portland OR (US) for intel corporation, Jason W. Brandt of Austin TX (US) for intel corporation, Gilbert Neiger of Portland OR (US) for intel corporation, Ittai Anati of Ramat Hasharon (IL) for intel corporation
IPC Code(s): G06F9/30, G06F9/455
Abstract: techniques relating to virtual idle loops are described. in an embodiment, decoder circuitry decodes a single instruction. the single instruction includes a field for an identifier of a first source operand, a field for an identifier of a second source operand, a field for an identifier of a destination operand, and a field for an opcode. execution circuitry executes the decoded instruction according to the opcode to: write the first source operand to a memory location identified by the second source operand; compute an index into a control array based at least in part on the destination operand; and determine whether to exit to a hypervisor of a virtual machine (vm) based at least in part on data stored at a location in the control array, wherein the location is to be identified by the computed index. other embodiments are also disclosed and claimed.
Inventor(s): Niranjan Kumar Soundararajan of Bengaluru (IN) for intel corporation, Sreenivas Subramoney of Bangalore (IN) for intel corporation, Jayesh Gaur of Bangalore (IN) for intel corporation
IPC Code(s): G06F9/38, G06F9/30, G06F9/32
Abstract: methods and apparatus for instruction elimination through hardware driven memoization of loop instances. a hardware-based loop memoization technique learns repeating sequences of loops and transparently removes instructions for the loop instructions from instruction sequences while making their output available to dependent instructions as if the loop instructions had been executed. a path-based predictor is implemented at the front-end to predict these loop instances and remove their instructions from instruction sequences. a novel memoization prediction micro-operation (uop) is inserted into the instruction sequence for instances of loops that are predicted to be memoized. the memoization prediction uop is used to compare the input signature (expected set of input values for the loop) with the actual signature to determine correct and incorrect predictions. the input signature learnt is based on all live-ins of a loop, both explicit register-based live-ins as well as loads to memory in the loop body that determine code path and outputs.
Inventor(s): Jayesh Gaur of Bangalore (IN) for intel corporation, Sufiyan Syed of Chennai (IN) for intel corporation, Adithya Ranganathan of Bengaluru (IN) for intel corporation, Sreenivas Subramoney of Bangalore (IN) for intel corporation
IPC Code(s): G06F9/38
Abstract: an example of an integrated circuit may include a first execution cluster, a second execution cluster that is one or more of narrower and shallower as compared to the first execution cluster, and circuitry to selectively steer instructions to the first execution cluster and the second execution cluster based on branch misprediction information. other embodiments are disclosed and claimed.
Inventor(s): Valentin Andrei of San Jose CA (US) for intel corporation, Subramaniam Maiyuran of Gold River CA (US) for intel corporation, SungYe Kim of Folsom CA (US) for intel corporation, Varghese George of Folsom CA (US) for intel corporation, Altug Koker of El Dorado Hills CA (US) for intel corporation, Aravindh Anantaraman of Folsom CA (US) for intel corporation
IPC Code(s): G06F9/48, G06F9/52, G06F15/80, G06T1/20
Abstract: apparatuses to synchronize lanes that diverge or threads that drift are disclosed. in one embodiment, a graphics multiprocessor includes a queue having an initial state of groups with a first group having threads of first and second instruction types and a second group having threads of the first and second instruction types. a regroup engine (or regroup circuitry) regroups threads into a third group having threads of the first instruction type and a fourth group having threads of the second instruction type.
Inventor(s): Russell J. Fenger of Beaverton OR (US) for intel corporation, Rajshree A. Chabukswar of Sunnyvale CA (US) for intel corporation, Benjamin Graniello of Gilbert AZ (US) for intel corporation, Monica Gupta of Hilsboro OR (US) for intel corporation, Guy M. Therien of Sherwood OR (US) for intel corporation, Michael W. Chynoweth of Placitas NM (US) for intel corporation
IPC Code(s): G06F9/48, G06F1/3228
Abstract: in one embodiment, a processor includes: a plurality of cores to execute instructions; at least one monitor coupled to the plurality of cores to measure at least one of power information, temperature information, or scalability information; and a control circuit coupled to the at least one monitor. based at least in part on the at least one of the power information, the temperature information, or the scalability information, the control circuit is to notify an operating system that one or more of the plurality of cores are to transition to a forced idle state in which non-affinitized workloads are prevented from being scheduled. other embodiments are described and claimed.
Inventor(s): Michael LeMay of Hillsboro OR (US) for intel corporation, David M. Durham of Beaverton OR (US) for intel corporation
IPC Code(s): G06F12/02, G06F12/14
Abstract: a processor includes a processing core having a register to store an encoded pointer for a memory address to a memory allocation of a memory, the encoded pointer including a first even odd slot (eos) bit set to a first value and a second eos bit set to a second value; and circuitry to receive a memory access request based on the encoded pointer; and in response to determining that the first value matches the second value, perform a memory operation corresponding to the memory access request.
20240104022.MULTI-LEVEL CACHE DATA TRACKING AND ISOLATION_simplified_abstract_(intel corporation)
Inventor(s): Aneesh Aggarwal of Portland OR (US) for intel corporation, Georgii Tkachuk of Phoenix AZ (US) for intel corporation, Subhiksha Ravisundar of Gilbert AZ (US) for intel corporation, Youngsoo Choi of Alameda CA (US) for intel corporation, Niall McDonnell of Limerick (IE) for intel corporation
IPC Code(s): G06F12/0897, G06F12/06
Abstract: an example of an apparatus may include a first cache organized as two or more portions, a second cache, and circuitry coupled to the first cache and the second cache to determine a designated portion allocation for data transferred from the first cache to the second cache, and track the designated portion allocation for the data transferred from the first cache to the second cache. other examples are disclosed and claimed.
20240104025.PREFETCH AWARE LRU CACHE REPLACEMENT POLICY_simplified_abstract_(intel corporation)
Inventor(s): Biju George of Folsom CA (US) for intel corporation, Zamshed I. Chowdhury of Folsom CA (US) for intel corporation, Prathamesh Raghunath Shinde of Folsom CA (US) for intel corporation, Chunhui Mei of San Diego CA (US) for intel corporation, Fangwen Fu of Folsom CA (US) for intel corporation
IPC Code(s): G06F12/123, G06F12/0862
Abstract: prefetch aware lru cache replacement policy is described. an example of an apparatus includes one or more processors including a graphic processor, the graphics processor including a load store cache having multiple cache lines (cls), each including bits for a cache line level (cl level) and one or more sectors for data storage; wherein the graphics processor is to receive one or more data elements for storage in the cache; set a cl level to track each cl receiving data, including setting cl level 1 for a cl receiving data in response to a miss in the cache and setting a cl level 2 for a cl receiving prefetched data in response to a prefetch request, and, upon determining that space is required in the cache to store data, apply a cache replacement policy, the policy being based at least in part on set cl levels for the cls.
Inventor(s): Santosh Ghosh of Hillsboro OR (US) for intel corporation, Christoph Dobraunig of St. Veit an der Glan (AT) for intel corporation, Michael LeMay of Hillsboro OR (US) for intel corporation, David M. Durham of Beaverton OR (US) for intel corporation
IPC Code(s): G06F12/14
Abstract: in one embodiment, a processor includes a cache and a core. the core includes an execution unit and cryptographic computing circuitry to encrypt plaintext data output by the execution unit and store the encrypted data in the cache and decrypt encrypted data accessed from the cache and provide the decrypted data to the execution unit for processing. the encryption and decryption are based on both a stream cipher and a block cipher. in some embodiments, the encryption is based on providing an output of the stream cipher to the block cipher and the decryption is based on providing an output of the block cipher to the stream cipher.
Inventor(s): Shailendra Singh Chauhan of Bangalore (IN) for intel corporation, Nirmala Bailur of Bangalore (IN) for intel corporation, Reza M. Zamani of Hillsboro OR (US) for intel corporation, Jackson Chung Peng Kong of Penang (MY) for intel corporation, Charuhasini Sunder Raman of Bangalore (IN) for intel corporation, Venkataramani Gopalakrishnan of Folsom CA (US) for intel corporation, Chuen Ming Tan of Penang (MY) for intel corporation, Sreejith Satheesakurup of Cherthala (IN) for intel corporation, Karthi Kaliswamy of Bangalore (IN) for intel corporation, Venkata Mahesh Gunnam of Bangalore (IN) for intel corporation, Yi Jen Huang of Kaohsiung City (TW) for intel corporation, Kie Woon Lim of Penang (MY) for intel corporation, Dhinesh Sasidaran of Penang (MY) for intel corporation, Pik Shen Chee of Penang (MY) for intel corporation, Venkataramana Kotakonda of Bangalore (IN) for intel corporation, Kunal A. Shah of Bangalore (IN) for intel corporation, Ramesh Vankunavath of Bangalore (IN) for intel corporation, Siva Prasad Jangili Ganga of Jagityal (IN) for intel corporation, Ravali Pampala of Bangalore (IN) for intel corporation, Uma Medepalli of El Dorado CA (US) for intel corporation, Tomer Savariego of Lavon (IL) for intel corporation, Naznin Banu Wahab of Bangalore (IN) for intel corporation, Sindhusha Kodali of Bangalore (IN) for intel corporation, Manjunatha Venkatarauyappa of Bangalore (IN) for intel corporation, Surendar Jeevarathinam of Bangalore (IN) for intel corporation, Madhura Shetty of Udupi (IN) for intel corporation, Deepak Sharma of Bangalore (IN) for intel corporation, Rohit Sharad Mahajan of Bangalore (IN) for intel corporation
IPC Code(s): G06F13/40, G06F13/42
Abstract: embodiments herein relate to a module which can be inserted into or removed from a computing device by a user. the module includes an input-output port which is configured for a desired specification, such as usb-a, usb-c, thunderbolt, displayport or hdmi. the port can be provided on an expansion card such as an m.2 card for communicating with a host platform. the host platform can communicate with different types of modules in a standardized way so that complexity and costs are reduced. in another aspect, with a dual port module, the host platform can concurrently send/receive power through one port and send/receive data from the other port.
Inventor(s): Erik Rijshouwer of Nuenen (NL) for intel corporation, Jeroen Leijten of Hulsel (NL) for intel corporation, Bert Schellekens of Hertogenbosch (NL) for intel corporation, Zoran Zivkovic of Hertogenbosch (NL) for intel corporation
IPC Code(s): G06F15/80, G06F9/30
Abstract: techniques are disclosed for a programmable processor array architecture that enables synchronized broadcasting of operation results to register files with the operation results. the architecture advantageously enables writing of operation results of a given operation to multiple destination registers in a single clock cycle for processors with partitioned register files by using common data stationary instruction encoding. this combination brings improved performance by reducing the need for costly copy operations that would otherwise occupy issue slots and thus schedule space while at the same time minimizing code size overhead. the performance gains of broadcasting are especially emphasized in highly parallel and heavily partitioned register file architectures.
20240104138.APPARATUS, METHOD, AND SYSTEM_simplified_abstract_(intel corporation)
Inventor(s): Robert VAUGHN of Portland OR (US) for intel corporation
IPC Code(s): G06F16/901
Abstract: it is provided an apparatus comprising interface circuitry, machine-readable instructions, and processing circuitry to execute the machine-readable instructions. the machine-readable instructions comprise instructions to obtain a first hash value of a first data record which is part of a first sequence of chained data records. the machine-readable instructions comprise instructions to obtain a second hash value of a second data record which is part of a second sequence of chained data records. the machine-readable instructions comprise instructions to generate a new data record comprising a hash value which is based on the first hash value of the first sequence of chained data records and on the second hash value of the second sequence of chained data records. the machine-readable instructions comprise instructions to add the new data record to the first sequence. the new data record following the first data record in the first sequence.
Inventor(s): Michael LeMay of Hillsboro OR (US) for intel corporation, Barry E. Huntley of Hillsboro OR (US) for intel corporation, Ravi Sahita of Portland OR (US) for intel corporation
IPC Code(s): G06F21/53, G06F9/50, G06F12/00, G06F21/12, G06F21/74
Abstract: technologies for memory management with memory protection extension include a computing device having a processor with one or more protection extensions. the processor may load a logical address including a segment base, effective limit, and effective address and generate a linear address as a function of the logical address with the effective limit as a mask. the processor may switch to a new task described by a task state segment extension. the task state extension may specify a low-latency segmentation mode. the processor may prohibit access to a descriptor in a local descriptor table with a descriptor privilege level lower than the current privilege level of the processor. the computing device may load a secure enclave using secure enclave support of the processor. the secure enclave may load an unsandbox and a sandboxed application in a user privilege level of the processor. other embodiments are described and claimed.
Inventor(s): Ernesto Zamora Ramos of Folsom CA (US) for intel corporation, Kylan Race of Austin TX (US) for intel corporation, Jeremy Bottleson of North Plains OR (US) for intel corporation, Jingyi Jin of San Jose CA (US) for intel corporation
IPC Code(s): G06F21/60, H04L9/00, H04L9/08
Abstract: an improved search operation includes receiving, by a server computing device, an encrypted search query and cleartext metadata associated with the encrypted search query from a client computing device; performing a search using the encrypted search query to generate encrypted search results; and sending the encrypted search results to the client computing device.
Inventor(s): Pradeep M. Pappachan of Tualatin OR (US) for intel corporation, Luis S. Kida of Beaverton OR (US) for intel corporation, Reshma Lal of Portland OR (US) for intel corporation
IPC Code(s): G06F21/60, G06F12/1009, G06F12/14, G06F21/78, G06T1/20, H04L9/14
Abstract: embodiments are directed to trusted local memory management in a virtualized gpu. an embodiment of an apparatus includes one or more processors including a trusted execution environment (tee); a gpu including a trusted agent; and a memory, the memory including gpu local memory, the trusted agent to ensure proper allocation/deallocation of the local memory and verify translations between graphics physical addresses (pas) and pas for the apparatus, wherein the local memory is partitioned into protection regions including a protected region and an unprotected region, and wherein the protected region to store a memory permission table maintained by the trusted agent, the memory permission table to include any virtual function assigned to a trusted domain, a per process graphics translation table to translate between graphics virtual address (va) to graphics guest pa (gpa), and a local memory translation table to translate between graphics gpas and pas for the local memory.
20240104378.DYNAMIC QUANTIZATION OF NEURAL NETWORKS_simplified_abstract_(intel corporation)
Inventor(s): Michael E. Deisher of Hillsboro OR (US) for intel corporation
IPC Code(s): G06N3/08, G06F5/01, G06F7/544, G06F7/57, G06N3/02, G06N3/044, G06N3/045, G06N3/048, G06N3/063
Abstract: an apparatus for applying dynamic quantization of a neural network is described herein. the apparatus includes a scaling unit and a quantizing unit. the scaling unit is to calculate an initial desired scale factors of a plurality of inputs, weights and a bias and apply the input scale factor to a summation node. also, the scaling unit is to determine a scale factor for a multiplication node based on the desired scale factors of the inputs and select a scale factor for an activation function and an output node. the quantizing unit is to dynamically requantize the neural network by traversing a graph of the neural network.
Inventor(s): Anthony Rhodes of Portland OR (US) for intel corporation, Manan Goel of Portland OR (US) for intel corporation
IPC Code(s): G06N3/08, G06N5/046, G06N20/00, G06T7/10, G06V10/44, G06V10/82
Abstract: methods, systems and apparatuses may provide for technology that trains a neural network by inputting video data to the neural network, determining a boundary loss function for the neural network, and selecting weights for the neural network based at least in part on the boundary loss function, wherein the neural network outputs a pixel-level segmentation of one or more objects depicted in the video data. the technology may also operate the neural network by accepting video data and an initial feature set, conducting a tensor decomposition on the initial feature set to obtain a reduced feature set, and outputting a pixel-level segmentation of object(s) depicted in the video data based at least in part on the reduced feature set.
Inventor(s): Todor Mladenov of Portland OR (US) for intel corporation, Sahar Daraeizadeh of Lake Oswego OR (US) for intel corporation, Anne Matsuura of Portland OR (US) for intel corporation
IPC Code(s): G06N10/20
Abstract: technologies for a hybrid digital/analog processor for a quantum computer are disclosed. in the illustrative embodiment, a hybrid digital/analog processor may be able to process digital instructions as well as analog instructions. the digital instructions may be, e.g., read from or write to memory or registers, perform an arithmetic operation, perform a branch, etc. the analog instructions may be to, e.g., provide an analog voltage to a particular electrode of a qubit, provide an analog pulse to a qubit, measure a reflection of an analog signal from a qubit, etc. the integration of analog operations in the hybrid digital/analog processor can improve performance by, e.g., lowering latency and lowering power usage.
Inventor(s): Mario Jose DIVAN of Hillsboro OR (US) for intel corporation, Marcos E. CARRANZA of Portland OR (US) for intel corporation, Francesc GUIM BERNAT of Barcelona (ES) for intel corporation, Cesar Ignacio MARTINEZ SPESSOT of Hillsboro OR (US) for intel corporation, Mateo GUZMAN of Beaverton OR (US) for intel corporation
IPC Code(s): G06Q30/015, H04L41/0823
Abstract: a method is described. the method includes a service provider accessing data indicating that at least a portion of an information systems infrastructure that is managed by the service provider and is installed at a tenant's location to perform information services for the tenant is available to perform information services for entities other than the tenant. the method includes the service provider providing information services to at least one of the entities with the portion of the information systems infrastructure.
Inventor(s): Qiang Li of Beijing (CN) for intel corporation, Xiaofeng Tong of Beijing (CN) for intel corporation, Yikai Fang of Beijing (CN) for intel corporation, Chen Ling of Beijing (CN) for intel corporation, Wenlong Li of Beijing (CN) for intel corporation
IPC Code(s): G06T7/13, G06F18/25, G06V10/80, G06V20/52, G06V20/64, G06V40/10, H04N13/282
Abstract: a mechanism is described for facilitating real-time multi-view detection of objects in multi-camera environments, according to one embodiment. a method of embodiments, as described herein, includes mapping first lines associated with objects to a ground plane; and forming clusters of second lines corresponding to the first lines such that an intersection point in a cluster represents a position of an object on the ground plane.
Inventor(s): Karol SZERSZEN of Hillsboro CA (US) for intel corporation, Prasoonkumar SURTI of Folsom CA (US) for intel corporation, Gabor LIKTOR of San Francisco CA (US) for intel corporation, Karthik VAIDYANATHAN of San Francisco CA (US) for intel corporation, Sven WOOP of Voelklingen (DE) for intel corporation
IPC Code(s): G06T15/06, G06T1/20, G06T15/00, G06T15/08, G06T17/10
Abstract: apparatus and method for grouping rays based on quantized ray directions. for example, one embodiment of an apparatus comprises: an apparatus comprising: a ray generator to generate a plurality of rays; ray direction evaluation circuitry/logic to generate approximate ray direction data for each of the plurality of rays; ray sorting circuitry/logic to sort the rays into a plurality of ray queues based, at least in part, on the approximate ray direction data.
Inventor(s): Anthony Daniel Rhodes of Portland OR (US) for intel corporation, Byungsu Min of Monroeville PA (US) for intel corporation, Subarna Tripathi of San Diego CA (US) for intel corporation, Giuseppe Raffa of Portland OR (US) for intel corporation, Sovan Biswas of Bonn (DE) for intel corporation
IPC Code(s): G06V10/82, G06V10/75, G06V10/86, G06V20/40
Abstract: machine learning models can process a video and generate outputs such as action segmentation assigning portions of the video to a particular action, or action classification assigning an action class for each frame of the video. some machine learning models can accurately make predictions for short videos but may not be particularly suited for performing action segmentation for long duration, structured videos. an effective machine learning model may include a hybrid architecture involving a temporal convolutional network and a bi-directional graph neural network. the machine learning model can process long duration structured videos by using a temporal convolutional network as a first pass action segmentation model to generate rich, frame-wise features. the frame-wise features can be converted into a graph having forward edges and backward edges. a graph neural network can process the graph to refine a final fine-grain per-frame action prediction.
Inventor(s): Haim Barad of Zichron Yaakov (IL) for intel corporation, Barak Hurwitz of Kibbutz Alonim (IL) for intel corporation, Uzi Sarel of Zichron-Yaakov (IL) for intel corporation, Eran Geva of Haifa (IL) for intel corporation, Eli Kfir of Yakir (IL) for intel corporation, Moshe Island of Tel Mond (IL) for intel corporation
IPC Code(s): G06V10/82, G06F30/33, G06N3/04, G06V10/44, G06V10/94
Abstract: systems, apparatuses and methods may provide for technology that processes an inference workload in a first subset of layers of a neural network that prevents or inhibits data dependent branch operations, conducts an exit determination as to whether an output of the first subset of layers satisfies one or more exit criteria, and selectively bypasses processing of the output in a second subset of layers of the neural network based on the exit determination. the technology may also speculatively initiate the processing of the output in the second subset of layers while the exit determination is pending. additionally, when the inference workloads include a plurality of batches, the technology may mask one or more of the plurality of batches from processing in the second subset of layers.
20240105248.TCAM WITH HYSTERETIC OXIDE MEMORY CELLS_simplified_abstract_(intel corporation)
Inventor(s): Abhishek Anil Sharma of Portland OR (US) for intel corporation, Tahir Ghani of Portland OR (US) for intel corporation, Sagar Suthram of Portland OR (US) for intel corporation, Anand Murthy of Portland OR (US) for intel corporation, Wilfred Gomes of Portland OR (US) for intel corporation, Pushkar Ranade of San Jose CA (US) for intel corporation
IPC Code(s): G11C11/22, H01L27/11587, H01L27/1159, H01L29/66, H01L29/78
Abstract: an integrated circuit (ic) die includes a substrate and an array of memory cells formed in or on the substrate with a memory cell of the array of memory cells that includes a storage circuit that comprises a hysteretic-oxide material. a ternary content-addressable memory (tcam) may utilize hysteretic-oxide memory cells. other embodiments are disclosed and claimed.
Inventor(s): Shida TAN of Saratoga CA (US) for intel corporation, Richard H. LIVENGOOD of San Jose CA (US) for intel corporation
IPC Code(s): H01J37/305, H01L21/02, H01L29/04
Abstract: embodiments described herein may be related to apparatuses, processes, systems, and/or techniques for altering an operational characteristic of a semiconductor device by exposing one or more locations within the semiconductor device to a focused ion beam. in embodiments, the ions in the focused ion beam may be light-element ions, which may include helium ions or neon ions. other embodiments may be described and/or claimed.
20240105452.GATE CUTS WITH SELF-FORMING POLYMER LAYER_simplified_abstract_(intel corporation)
Inventor(s): Reza Bayati of Portland OR (US) for intel corporation, Matthew J. Prince of Portland OR (US) for intel corporation, Alison V. Davis of Portland OR (US) for intel corporation, Chun C. Kuo of Hillsboro OR (US) for intel corporation, Andrew Arnold of Hillsboro OR (US) for intel corporation, Ramy Ghostine of Portland OR (US) for intel corporation, Li Huey Tan of Hillsboro OR (US) for intel corporation
IPC Code(s): H01L21/28, H01L21/8238, H01L27/092, H01L29/06, H01L29/423, H01L29/66, H01L29/775
Abstract: techniques are provided to form semiconductor devices that include one or more gate cuts having a layer of polymer material at edges of the gate cut. the polymer layer may be provided as a byproduct of the etching process used to form the gate cut recess through the gate structure, and can protect any exposed portions of the source or drain regions from certain subsequent processes. the gate structure may be interrupted between two transistors with a gate cut that extends through an entire thickness of the gate structure and includes a dielectric material to electrically isolate the portions of the gate structure on either side of the gate cut. the edges of the gate cut may be lined with a polymer layer that is also on any exposed portions of the source or drain regions that were exposed during the etching process used to form the gate cut recess.
20240105453.HIGH ASPECT RATIO METAL GATE CUTS_simplified_abstract_(intel corporation)
Inventor(s): Reza Bayati of Portland OR (US) for intel corporation, Matthew J. Prince of Portland OR (US) for intel corporation, Alison V. Davis of Portland OR (US) for intel corporation, Ramy Ghostine of Portland OR (US) for intel corporation, Piyush M. Sinha of Portland OR (US) for intel corporation, Oleg Golonzka of Beaverton OR (US) for intel corporation, Swapnadip Ghosh of Hillsboro OR (US) for intel corporation, Manish Sharma of Portland OR (US) for intel corporation
IPC Code(s): H01L21/28, H01L21/02, H01L21/311, H01L21/8238, H01L27/092, H01L29/06, H01L29/423, H01L29/66, H01L29/775
Abstract: techniques are provided herein to form semiconductor devices that include one or more gate cuts having a very high aspect ratio (e.g., an aspect ratio of 5:1 or greater, such as 10:1). in an example, a semiconductor device includes a conductive material that is part of a transistor gate structure around or otherwise on a semiconductor region. the semiconductor region can be, for example, a fin of semiconductor material that extends between a source region and a drain region, or one or more nanowires or nanoribbons of semiconductor material that extend between a source region and a drain region. the gate structure may be interrupted between two transistors with a gate cut that extends through an entire thickness of the gate structure. a particular plasma etching process may be performed to form the gate cut with a very high height-to-width aspect ratio so as to enable densely integrated devices.
20240105476.SYSTEM FOR COATING METHOD_simplified_abstract_(intel corporation)
Inventor(s): Whitney BRYKS of Tempe AZ (US) for intel corporation, Thomas HEATON of Gilbert AZ (US) for intel corporation, Joshua STACEY of Chandler AZ (US) for intel corporation, Dilan SENEVIRATNE of Phoenix AZ (US) for intel corporation, Cansu ERGENE of Chandler AZ (US) for intel corporation
IPC Code(s): B05C13/02, B05C5/02, B05D1/26
Abstract: the present disclosure is directed to a coating module including: a coating stage and a plurality of vertical guides configured to perpendicularly extend from the coating stage; a vertical movement mechanism configured to lower a framed panel along the plurality of vertical guides onto the coating stage; an optical alignment tool configured to provide feedback on a lateral alignment between an edge of the coating stage and the framed panel; and a dispensing unit configured to coat a surface of the panel.
Inventor(s): Jitendra Kumar Jha of Hillsboro OR (US) for intel corporation, Justin Mueller of Portland OR (US) for intel corporation, Nazila Haratipour of Portland OR (US) for intel corporation, Gilbert W. Dewey of Beaverton OR (US) for intel corporation, Chi-Hing Choi of Portland OR (US) for intel corporation, Jack T. Kavalieros of Portland OR (US) for intel corporation, Siddharth Chouksey of Portland OR (US) for intel corporation, Nancy Zelick of Portland OR (US) for intel corporation, Jean-Philippe Turmaud of Portland OR (US) for intel corporation, I-Cheng Tung of Hillsboro OR (US) for intel corporation, Blake Bluestein of Hillsboro OR (US) for intel corporation
IPC Code(s): H01L21/768, H01L29/49
Abstract: disclosed herein are integrated circuit (ic) devices with contacts using nitridized molybdenum. for example, a contact arrangement for an ic device may include a semiconductor material and a contact extending into a portion of the semiconductor material. the contact may include molybdenum. the molybdenum may be in a first layer and a second layer, where the second layer may further include nitrogen. the first layer may have a thickness between about 5 nanometers and 16 nanometers, and the second layer may have a thickness between about 0.5 nanometers to 2.5 nanometers. the contact may further include a fill material (e.g., an electrically conductive material) and the second layer may be in contact with the fill material. the molybdenum may have a low resistance, and thus may improve the electrical performance of the contact. the nitridized molybdenum may prevent oxidation during the fabrication of the contact.
Inventor(s): Anthony ST. AMOUR of Portland OR (US) for intel corporation, Michael L. HATTENDORF of Portland OR (US) for intel corporation, Christopher P. AUTH of Portland OR (US) for intel corporation
IPC Code(s): H01L21/8234, H01L21/033, H01L21/28, H01L21/285, H01L21/308, H01L21/311, H01L21/762, H01L21/768, H01L21/8238, H01L23/522, H01L23/528, H01L23/532, H01L27/088, H01L27/092, H01L29/08, H01L29/417, H01L29/51, H01L29/66, H01L29/78, H10B10/00
Abstract: embodiments of the disclosure are in the field of advanced integrated circuit structure fabrication and, in particular, 10 nanometer node and smaller integrated circuit structure fabrication and the resulting structures. in an example, an integrated circuit structure includes a fin comprising silicon. a plurality of gate structures is over the fin, individual ones of the plurality of gate structures along a direction orthogonal to the fin and having a pair of dielectric sidewall spacers. a trench contact structure is over the fin and directly between the dielectric sidewalls spacers of a first pair of the plurality of gate structures. a contact plug is over the fin and directly between the dielectric sidewalls spacers of a second pair of the plurality of gate structures, the contact plug comprising a lower dielectric material and an upper hardmask material.
Inventor(s): Brandon C. MARIN of Gilbert AZ (US) for intel corporation, Haobo CHEN of Gilbert AZ (US) for intel corporation, Bai NIE of Chandler AZ (US) for intel corporation, Srinivas V. PIETAMBARAM of Chandler AZ (US) for intel corporation, Gang DUAN of Chandler AZ (US) for intel corporation, Jeremy D. ECTON of Gilbert AZ (US) for intel corporation, Suddhasattwa NAD of Chandler AZ (US) for intel corporation
IPC Code(s): H01L23/498, H01L21/48
Abstract: embodiments disclosed herein include glass cores and methods of forming glass cores. in an embodiment, a core for an electronic package comprises a substrate with a first surface and a second surface opposite from the first surface, where the substrate comprises glass, in an embodiment, a via opening is provided through the substrate, and a diffusion layer is along the first surface, the second surface, and the via opening.
20240105572.GROUND VIA CLUSTERING FOR CROSSTALK MITIGATION_simplified_abstract_(intel corporation)
Inventor(s): Zhiguo QIAN of Chandler AZ (US) for intel corporation, Kemal AYGUN of Tempe AZ (US) for intel corporation, Yu ZHANG of Raleigh NC (US) for intel corporation
IPC Code(s): H01L23/498
Abstract: embodiments of the present disclosure are directed towards techniques and configurations for ground via clustering for crosstalk mitigation in integrated circuit (ic) assemblies. in some embodiments, an ic package assembly may include a first package substrate configured to route input/output (i/o) signals and ground between a die and a second package substrate. the first package substrate may include a plurality of contacts disposed on one side of the first package substrate and at least two ground vias of a same layer of vias, and the at least two ground vias may form a cluster of ground vias electrically coupled with an individual contact. other embodiments may be described and/or claimed.
20240105575.ELECTROLYTIC SURFACE FINISH ARCHITECTURE_simplified_abstract_(intel corporation)
Inventor(s): Jason M. GAMBA of Gilbert AZ (US) for intel corporation, Haifa HARIRI of Phoenix AZ (US) for intel corporation, Kristof DARMAWIKARTA of Chandler AZ (US) for intel corporation, Srinivas V. PIETAMBARAM of Chandler AZ (US) for intel corporation, Hiroki TANAKA of Gilbert AZ (US) for intel corporation, Kyle MCELHINNY of Tempe AZ (US) for intel corporation, Xiaoying GUO of Chandler AZ (US) for intel corporation, Steve S. CHO of Chandler AZ (US) for intel corporation, Ali LEHAF of Phoenix AZ (US) for intel corporation, Haobo CHEN of Gilbert AZ (US) for intel corporation, Bai NIE of Chandler AZ (US) for intel corporation, Numair AHMED of Chandler AZ (US) for intel corporation
IPC Code(s): H01L23/498, C25D3/12, C25D3/48, C25D3/50, C25D7/12, H01L21/48
Abstract: embodiments disclosed herein include package substrates and methods of forming package substrates. in an embodiment, the package substrate comprises a core, and a pad over the core, where the pad has a first width. in an embodiment, a surface finish is over the pad, where the surface finish has a second width that is substantially equal to the first width. in an embodiment, the package substrate further comprises a solder resist over the pad, where the solder resist comprises an opening that exposes a portion of the surface finish. in an embodiment, the opening has a third width that is smaller than the second width.
Inventor(s): Kyle MCELHINNY of Tempe AZ (US) for intel corporation, Xiaoying GUO of Chandler AZ (US) for intel corporation, Hiroki TANAKA of Gilbert AZ (US) for intel corporation, Haobo CHEN of Gilbert AZ (US) for intel corporation
IPC Code(s): H01L23/498, C25D3/12, C25D3/48, C25D3/50, C25D7/12, H01L21/48
Abstract: embodiments disclosed herein include package substrates and methods of forming package substrates. in an embodiment, the package substrate comprises a core and a pad over the core. in an embodiment, a solder resist is over the pad, and an opening into the solder resist exposes a portion of the pad. in an embodiment, the package substrate further comprises a surface finish over the pad and within the opening.
Inventor(s): Zhenguo Jiang of Chandler AZ (US) for intel corporation, Zhiguo Qian of Chandler AZ (US) for intel corporation, Jiwei Sun of Chandler AZ (US) for intel corporation, Babita Dhayal of Aloha OR (US) for intel corporation
IPC Code(s): H01L23/498, H01L21/48
Abstract: methods, systems, apparatus, and articles of manufacture to produce integrated circuit packages with grounding members are disclosed. an example semiconductor die disclosed herein includes a semiconductor substrate, metal interconnects proximate a first side of the semiconductor substrate, a metal contact proximate a second side of the semiconductor substrate opposite the first side, a first grounding member extending from a grounding interconnect of the metal interconnects to a first distal point in the semiconductor substrate, and a second grounding member extending from the metal contact to a second distal point in the semiconductor substrate, the first distal point closer to the first side of the semiconductor substrate than the second distal point is to the first side of the semiconductor substrate.
20240105580.SURFACE FINISH WITH METAL DOME_simplified_abstract_(intel corporation)
Inventor(s): Kristof DARMAWIKARTA of Chandler AZ (US) for intel corporation, Srinivas V. PIETAMBARAM of Chandler AZ (US) for intel corporation, Kyle MCELHINNY of Tempe AZ (US) for intel corporation, Hiroki TANAKA of Gilbert AZ (US) for intel corporation
IPC Code(s): H01L23/498, H01L21/48, H01L23/13, H01L23/15
Abstract: embodiments disclosed herein include electronic packages and methods of forming such packages. in an embodiment, the electronic package comprises a core, and a pad over the core. in an embodiment, a shell is around the core, and a surface finish is over the shell. in an embodiment, the electronic package further comprises a solder resist over the pad, where an opening is formed through the solder resist to expose the surface finish.
Inventor(s): Abhishek Anil Sharma of Portland OR (US) for intel corporation, Tahir Ghani of Portland OR (US) for intel corporation, Anand Murthy of Portland OR (US) for intel corporation, Wilfred Gomes of Portland OR (US) for intel corporation, Sagar Suthram of Portland OR (US) for intel corporation, Pushkar Ranade of San Jose CA (US) for intel corporation
IPC Code(s): H01L23/522, H01L23/473, H01L23/50
Abstract: an integrated circuit die includes a first conductive structure for an input of a capacitively coupled device, a second conductive structure aligned with the first conductive structure for a signal to be capacitively coupled to the input of the capacitively coupled device, a first insulator material disposed between the first conductive structure and the second conductive structure, wherein the first insulator material comprises high gain insulator material, and a cooling structure operable to remove heat from the capacitively coupled device to achieve an operating temperature at or below 0� c. other embodiments are disclosed and claimed.
Inventor(s): Abhishek Anil Sharma of Portland OR (US) for intel corporation, Tahir Ghani of Portland OR (US) for intel corporation, Anand Murthy of Portland OR (US) for intel corporation, Wilfred Gomes of Portland OR (US) for intel corporation, Sagar Suthram of Portland OR (US) for intel corporation, Pushkar Ranade of San Jose CA (US) for intel corporation
IPC Code(s): H01L23/522, H01L21/768
Abstract: an integrated circuit (ic) die includes a plurality of front-side metallization layers including a first front-side metallization layer and one or more additional front-side metallization layers, a plurality of back-side metallization layers formed on the plurality front side metallization layers including a first back-side metallization layer and one or more additional back-side metallization layers, wherein the first front-side metallization layer is proximate to the first back-side metallization layer, and a vertical metallization structure formed through at least the first front-side metallization layer and the first back-side metallization layer, wherein the vertical metallization structure electrically connects a first metallization structure on one of the one or more additional front-side metallization layers to a second metallization structure on one of the one or more additional back-side metallization layers. other embodiments are disclosed and claimed.
Inventor(s): Abhishek Anil Sharma of Portland OR (US) for intel corporation, Pushkar Ranade of San Jose CA (US) for intel corporation, Tahir Ghani of Portland OR (US) for intel corporation, Wilfred Gomes of Portland OR (US) for intel corporation, Sagar Suthram of Portland OR (US) for intel corporation, Anand Murthy of Portland OR (US) for intel corporation
IPC Code(s): H01L23/522, H01L23/427
Abstract: an embodiment of a capacitor in the back-side layers of an ic die may comprise any type of solid-state electrolyte material disposed between electrodes of the capacitor. another embodiment of a capacitor anywhere in an ic die may include one or more materials selected from the group of indium oxide, indium nitride, gallium oxide, gallium nitride, zinc oxide, zinc nitride, tungsten oxide, tungsten nitride, tin oxide, tin nitride, nickel oxide, nickel nitride, niobium oxide, niobium nitride, cobalt oxide, and cobalt nitride between electrodes of the capacitor. other embodiments are disclosed and claimed.
Inventor(s): Ilya V. Karpov of Portland OR (US) for intel corporation, Shafaat Ahmed of Albuquerque NM (US) for intel corporation, Matthew V. Metz of Portland OR (US) for intel corporation, Darren Anthony Denardis of Albuquerque NM (US) for intel corporation, Nafees Aminul Kabir of Hillsboro OR (US) for intel corporation, Tristan A. Tronic of Aloha OR (US) for intel corporation
IPC Code(s): H01L23/522, H01L21/768, H01L23/528, H01L23/532
Abstract: an ic device includes a multilayer metal line that is at least partially surrounded by one or more electrical insulators. the multilayer metal line may be formed by stacking four layers on top of one another. the four layers may include a first layer between a second layer and a third layer. the first layer may include al. the second or third layer may include w. the fourth layer may be a conductive or dielectric layer. the second layer, third layer, and fourth layer can protect the first layer from defects in al core layer during fabrication or operation of the multilayer metal line. substrative etch may be performed on the stack of the four layers to form openings. an electrical insulator may be deposited into to the openings to form multiple metal lines that are separated by the electrical insulator. a via may be formed over the third layer.
Inventor(s): Shao Ming Koh of Tigard OR (US) for intel corporation, Patrick Morrow of Portland OR (US) for intel corporation, June Choi of Portland OR (US) for intel corporation, Sukru Yemenicioglu of Portland OR (US) for intel corporation, Nikhil Jasvant Mehta of Portland OR (US) for intel corporation
IPC Code(s): H01L23/522, H01L21/768, H01L23/48, H01L23/528
Abstract: an ic device includes a metal layer that includes staggered metal lines. the metal lines are in two or more levels along a direction. there may be one or more metal lines in each level. at least some of the metal lines are aligned along the direction so that widths of the metal lines may be maximized for a given total width of the metal layer. the alignment of the metal lines may be achieved through dsa of a diblock copolymer. the metal layer may be connected to vias in two or more levels. the vias may be also connected to another metal layer or a semiconductor device in a feol section of the ic device. a via and the metal line connected to the via may be formed through a same recess and deposition process to eliminate interface between the via and metal line.
Inventor(s): Abhishek A. Sharma of Hillsboro OR (US) for intel corporation, Tahir Ghani of Portland OR (US) for intel corporation, Wilfred Gomes of Portland OR (US) for intel corporation, Anand S. Murthy of Portland OR (US) for intel corporation, Shem Ogadhoh of West Linn OR (US) for intel corporation, Pushkar Sharad Ranade of San Jose CA (US) for intel corporation, Sagar Suthram of Portland OR (US) for intel corporation, Elliot Tan of Portland OR (US) for intel corporation
IPC Code(s): H01L23/528, H01L23/498
Abstract: ic devices with angled interconnects are disclosed herein. an interconnect, specifically a trench or line interconnect, is referred to as an “angled interconnect” if the interconnect is neither perpendicular nor parallel to any edges of front or back faces of the support structure, or if the interconnect is not parallel or perpendicular to interconnect in another region of an interconnect layer. angled interconnects may be used to decrease the area of pitch transition regions. angled interconnects may also be used to decrease the area of pitch offset regions.
Inventor(s): Leonard P. GULER of Hillsboro OR (US) for intel corporation, Robert JOACHIM of Beaverton OR (US) for intel corporation, Shengsi LIU of Portland OR (US) for intel corporation, Tahir GHANI of Portland OR (US) for intel corporation, Charles H. WALLACE of Portland OR (US) for intel corporation
IPC Code(s): H01L23/528, H01L23/532
Abstract: embodiments of the disclosure are in the field of integrated circuit structure fabrication. in an example, an integrated circuit structure includes a plurality of conductive lines along a same direction, one of the conductive lines having a break therein. an inter-layer dielectric (ild) structure has portions between adjacent ones of the plurality of conductive lines and has a dielectric plug portion in a location of the break in the one of the conductive lines. the dielectric plug portion of the ild structure is continuous with one or more of the portions of the ild structure between adjacent ones of the plurality of conductive lines. the dielectric plug portion of the ild structure has an inwardly tapering profile from top to bottom.
Inventor(s): Leonard P. GULER of Hillsboro OR (US) for intel corporation, Tahir GHANI of Portland OR (US) for intel corporation, Charles H. WALLACE of Portland OR (US) for intel corporation
IPC Code(s): H01L23/528, H01L21/768, H01L23/532
Abstract: embodiments of the disclosure are in the field of integrated circuit structure fabrication. in an example, an integrated circuit structure includes a plurality of conductive lines on a same level and along a same direction, a first one of the plurality of conductive lines having a first width and a first composition, and a second one of the plurality of conductive lines having a second width and a second composition. the second width greater than the first width, and the second composition is different than the first composition. the integrated circuit structure also includes an inter-layer dielectric (ild) structure having portions between adjacent ones of the plurality of conductive lines.
Inventor(s): Leonard P. GULER of Hillsboro OR (US) for intel corporation, Vishal TIWARI of Hillsboro OR (US) for intel corporation, Tahir GHANI of Portland OR (US) for intel corporation, Mohit K. HARAN of Hillsboro OR (US) for intel corporation, Desalegne B. TEWELDEBRHAN of Sherwood OR (US) for intel corporation
IPC Code(s): H01L23/528, H01L29/423
Abstract: mushroomed via structures for trench contact or gate contact are described. in an example, an integrated circuit structure includes a trench contact structure over an epitaxial source or drain structure. a dielectric layer is over the trench contact structure. a trench contact via is in an opening in the dielectric layer, the trench contact via in contact with the trench contact structure. a trench contact via extension is on the trench contact via. the trench contact via extension above the dielectric layer and extending laterally beyond the trench contact via.
Inventor(s): Robert Alan MAY of Chandler AZ (US) for intel corporation, Kristof DARMAWIKARTA of Chandler AZ (US) for intel corporation, Sri Ranga Sai Sai BOYAPATI of Chandler AZ (US) for intel corporation
IPC Code(s): H01L23/532, H01L23/29, H01L23/522
Abstract: a die interconnect substrate comprises a bridge die comprising at least one bridge interconnect connecting a first bridge die pad of the bridge die to a second bridge die pad of the bridge die. the die interconnect substrate comprises a multilayer substrate structure comprising a substrate interconnect. the bridge die is embedded in the multilayer substrate structure. the substrate interconnect extends from a level above the bridge die to a level below the bridge die. the multilayer substrate structure further comprises an electrically insulating layer comprising a first electrically insulating material. the multilayer substrate structure further comprises an electrically insulating filler structure located laterally between the bridge die and the electrically insulating layer, wherein the electrically insulating filler structure comprises a second electrically insulating material different from the first electrically insulating material.
20240105625.OPEN CAVITY INTERCONNECTS FOR MIB CONNECTIONS_simplified_abstract_(intel corporation)
Inventor(s): Brandon C. Marin of Gilbert AZ (US) for intel corporation, Kristof Darmawikarta of Chandler AZ (US) for intel corporation, Benjamin Duong of Phoenix AZ (US) for intel corporation, Srinivas Venkata Ramanuja Pietambaram of Chandler AZ (US) for intel corporation, Gang Duan of Chandler AZ (US) for intel corporation
IPC Code(s): H01L23/538, H01L21/48, H01L23/498, H01L25/065
Abstract: disclosed herein are microelectronics package architectures utilizing open cavity interconnects for multi-die interconnect bridges and methods of manufacturing the same. the microelectronics packages may include a substrate, a first die, a solder resist layer, a first pad, and a bridge. the substrate may have a substrate surface. the solder resist layer may be connected to the substrate and may define an opening. the first pad may protrude from the substrate surface. the bridge may be located at least partially within the opening and in between the first die and the substrate. the bridge may include a first via that forms a first electrical pathway from the first pad to the first die.
Inventor(s): Abhishek Anil Sharma of Portland OR (US) for intel corporation, Wilfred Gomes of Portland OR (US) for intel corporation, Tahir Ghani of Portland OR (US) for intel corporation, Anand Murthy of Portland OR (US) for intel corporation, Sagar Suthram of Portland OR (US) for intel corporation, Pushkar Ranade of San Jose CA (US) for intel corporation
IPC Code(s): H01L23/544, H01L21/02, H01L21/306, H01L21/3205, H01L23/48, H01L23/532
Abstract: an integrated circuit (ic) die includes a first layer with conductive structures formed in a interlayer dielectric (ild) material, with a portion of the conductive structures at a first surface of the first layer, a self-alignment layer in contact with non-conductive regions at the first surface of the first layer, a second layer with ild material in contact with the self-alignment layer and the portion of the conductive structures at the first surface of the first layer, and conductive vias through the self-alignment layer and the second layer in contact with the portion of the conductive structures at the first surface of the first layer. the self-alignment layer may include a first material where the self-alignment layer is in contact with the conductive vias and a second material where the self-alignment layer is not in contact with the conductive vias. other embodiments are disclosed and claimed.
Inventor(s): Brandon C. Marin of Gilbert AZ (US) for intel corporation, Kristof Kuwawi Darmawikarta of Chandler AZ (US) for intel corporation, Srinivas V. Pietambaram of Chandler AZ (US) for intel corporation, Gang Duan of Chandler AZ (US) for intel corporation, Suddhasattwa Nad of Chandler AZ (US) for intel corporation, Jeremy Ecton of Gilbert AZ (US) for intel corporation
IPC Code(s): H01L23/00, H01L23/13, H01L23/498, H01L23/538, H01L25/065
Abstract: microelectronic assemblies, related devices and methods, are disclosed herein. in some embodiments, a microelectronic assembly may include a conductive pad having a first surface and an opposing second surface; a conductive via coupled to the first surface of the conductive pad; a microelectronic component having a conductive contact, the conductive contact of the microelectronic component electrically coupled, by an interconnect, to the second surface of the conductive pad, wherein a material of the interconnect includes nickel or tin; and a liner between the interconnect and the second surface of the conductive pad, and wherein a material of the liner includes nickel, palladium, or gold. in some embodiments, a bottom surface of the liner is curved outward towards the conductive pad. in some embodiments, the liner also may be on side surfaces of the interconnect.
Inventor(s): Abhishek Anil Sharma of Portland OR (US) for intel corporation, Tahir Ghani of Portland OR (US) for intel corporation, Sagar Suthram of Portland OR (US) for intel corporation, Anand Murthy of Portland OR (US) for intel corporation, Wilfred Gomes of Portland OR (US) for intel corporation, Pushkar Ranade of San Jose CA (US) for intel corporation
IPC Code(s): H01L25/065, H01L23/00, H01L23/427, H01L25/00
Abstract: an integrated circuit device includes a first ic die with a first front surface, a first back surface, and a first side surface along opposed edges of the first front surface and the first back surfaces of the first ic die, a second ic die with a second front surface, a second back surface, and a second side surface along opposed edges of the second front surface and second back surface of the second ic die, a substrate coupled to the first side surface of the first ic die and the second side surface of the second ic die, and fill material between one of the first front surface and the first back surface of the first ic die and one of the second front surface and second back surface of the second ic die. other embodiments are disclosed and claimed.
Inventor(s): Abhishek Anil Sharma of Portland OR (US) for intel corporation, Tahir Ghani of Portland OR (US) for intel corporation, Anand Murthy of Portland OR (US) for intel corporation, Wilfred Gomes of Portland OR (US) for intel corporation, Sagar Suthram of Portland OR (US) for intel corporation, Pushkar Ranade of San Jose CA (US) for intel corporation
IPC Code(s): H01L25/18, H01L21/768, H01L23/00, H01L23/48, H01L23/528, H01L25/00, H01L25/065
Abstract: an embodiment of an integrated circuit (ic) device may include a plurality of layers of wide bandgap (wbg)-based circuitry and a plurality of layers of silicon (si)-based circuitry monolithically bonded to the plurality of layers of wbg-based circuitry, with one or more electrical connections between respective wbg-based circuits in the plurality of layers of wbg-based circuitry and si-based circuits in the plurality of layers of si-based circuitry. in some embodiments, a wafer-scale wbg-based ic is hybrid bonded or layer transfer bonded to a wafer-scale si-based ic. other embodiments are disclosed and claimed.
Inventor(s): Leonard P. GULER of Hillsboro OR (US) for intel corporation, Sukru YEMENICIOGLU of Portland OR (US) for intel corporation, Mohit K. HARAN of Hillsboro OR (US) for intel corporation, Stephen M. CEA of Hillsboro OR (US) for intel corporation, Charles H. WALLACE of Portland OR (US) for intel corporation, Tahir GHANI of Portland OR (US) for intel corporation, Shengsi LIU of Portland OR (US) for intel corporation, Saurabh ACHARYA of Hillsboro OR (US) for intel corporation, Thomas O'BRIEN of Portland OR (US) for intel corporation, Nidhi KHANDELWAL of Portland OR (US) for intel corporation, Marie T. CONTE of Hillsboro OR (US) for intel corporation, Prabhjot LUTHRA of Hillsboro OR (US) for intel corporation
IPC Code(s): H01L27/088, H01L21/8234
Abstract: integrated circuit structures having uniform grid metal gate and trench contact cut, and methods of fabricating integrated circuit structures having uniform grid metal gate and trench contact cut, are described. for example, an integrated circuit structure includes a vertical stack of horizontal nanowires. a gate electrode is over the vertical stack of horizontal nanowires. a conductive trench contact is adjacent to the gate electrode. a dielectric sidewall spacer is between the gate electrode and the conductive trench contact. a first dielectric cut plug structure extends through the gate electrode, through the dielectric sidewall spacer, and through the conductive trench contact. a second dielectric cut plug structure extends through the gate electrode, through the dielectric sidewall spacer, and through the conductive trench contact, the second dielectric cut plug structure laterally spaced apart from and parallel with the first dielectric cut plug structure.
Inventor(s): Tao Chu of Portland OR (US) for intel corporation, Guowei Xu of Portland OR (US) for intel corporation, Minwoo Jang of Portland OR (US) for intel corporation, Yanbin Luo of Portland OR (US) for intel corporation, Feng Zhang of Hillsboro OR (US) for intel corporation, Ting-Hsiang Hung of Beaverton OR (US) for intel corporation, Chia-Ching Lin of Portland OR (US) for intel corporation
IPC Code(s): H01L27/088, H01L21/8234, H01L29/06, H01L29/08, H01L29/778, H01L29/786
Abstract: methods for fabricating an integrated circuit (ic) device with a protection liner between doped semiconductor regions are provided. an example ic device includes a channel material having a first face and a second face opposite the first face, a first doped region and a second doped region in the channel material, extending from the second face towards the first face by a first distance; and an insulator structure in a portion of the channel material between the first and second doped regions, the insulator structure extending from the second face towards the first face by a second distance greater than the first distance. the insulator structure includes a first portion between the second face and the first distance and a second portion between first distance and the second distance. the insulator structure includes a liner material on sidewalls of the first portion but absent on sidewalls of the second portion.
Inventor(s): Tao CHU of Portland OR (US) for intel corporation, Guowei XU of Portland OR (US) for intel corporation, Chia-Ching LIN of Portland OR (US) for intel corporation, Minwoo JANG of Portland OR (US) for intel corporation, Feng ZHANG of Hillsboro OR (US) for intel corporation, Ting-Hsiang HUNG of Beaverton OR (US) for intel corporation
IPC Code(s): H01L29/06, H01L21/8234, H01L29/778, H01L29/786
Abstract: embodiments disclosed herein include transistors and methods of forming transistors. in an embodiment, a transistor comprises a source, a drain, and a pair of spacers between the source and the drain. in an embodiment, a semiconductor channel is between the source and the drain, where the semiconductor channel passes through the pair of spacers. in an embodiment, the semiconductor channel has a first thickness within the pair of spacers and a second thickness between the pair of spacers, where the second thickness is less than the first thickness. in an embodiment, the transistor further comprises a gate stack over the semiconductor channel between the pair of spacers.
Inventor(s): Leonard P. GULER of Hillsboro OR (US) for intel corporation, Sean PURSEL of Hillsboro OR (US) for intel corporation, Tsuan-Chung CHANG of Portland OR (US) for intel corporation, Tahir GHANI of Portland OR (US) for intel corporation
IPC Code(s): H01L29/06, H01L27/088, H01L29/78
Abstract: integrated circuit structures having channel cap reduction, and methods of fabricating integrated circuit structures having channel cap reduction, are described. for example, an integrated circuit structure includes a sub-fin structure beneath a stack of nanowires, the stack of nanowires having a first end and a second end. a dielectric cap has a first portion vertically over the first end of the stack of nanowires and has a second portion vertically over the second end of the stack of nanowires. the dielectric cap is not vertically over a location between the first end and the second end of the stack of nanowires. a gate electrode is over and around the stack of nanowires and laterally between the first and second portions of the dielectric cap. a gate dielectric structure is between the gate electrode and the stack of nanowires.
Inventor(s): Leonard P. GULER of Hillsboro OR (US) for intel corporation, Mohammad HASAN of Aloha OR (US) for intel corporation, Aryan NAVABI-SHIRAZI of Portland OR (US) for intel corporation, Jessica PANELLA of Banks OR (US) for intel corporation, Saurabh ACHARYA of Hillsboro OR (US) for intel corporation, Desalegne B. TEWELDEBRHAN of Sherwood OR (US) for intel corporation, Madeleine BEASLEY of Beaverton OR (US) for intel corporation
IPC Code(s): H01L29/08, H01L21/8238, H01L27/092, H01L29/06, H01L29/417, H01L29/423, H01L29/66, H01L29/775
Abstract: integrated circuit structures having uniform epitaxial source or drain cut are described. for example, an integrated circuit structure includes a first sub-fin structure beneath a first stack of nanowires. a second sub-fin structure is beneath a second stack of nanowires. a first epitaxial source or drain structure is at an end of the first stack of nanowires, the first epitaxial source or drain structure having a first lateral sidewall having a flat vertical surface, and having a second lateral sidewall opposite the first lateral sidewall. a second epitaxial source or drain structure is at an end of the second stack of nanowires, the second epitaxial source or drain structure having a first lateral sidewall having a flat vertical surface, and having a second lateral sidewall opposite the first lateral sidewall, the first lateral sidewall of the second epitaxial source or drain structure laterally spaced apart from the second lateral sidewall of the first epitaxial source or drain structure.
20240105800.MULTI-STAGE MASK ETCH PROCESS_simplified_abstract_(intel corporation)
Inventor(s): Reza Bayati of Portland OR (US) for intel corporation, Alison V. Davis of Portland OR (US) for intel corporation, Ramy Ghostine of Portland OR (US) for intel corporation, Matthew J. Prince of Portland OR (US) for intel corporation
IPC Code(s): H01L29/423, H01L21/8234, H01L29/06, H01L29/786
Abstract: techniques are described to form semiconductor devices that include one or more gate cuts having a very high aspect ratio (e.g., an aspect ratio of 5:1 or greater). a semiconductor device includes a conductive material that is part of a transistor gate structure around or otherwise on a semiconductor region. the gate structure may be interrupted between two transistors with a gate cut that extends through an entire thickness of the gate structure. a plasma etching process may be performed to form the gate cut with a very high height-to-width aspect ratio with little to no tapering in its sidewall profile, so as to enable densely integrated devices. furthermore, an etching process may be performed on a gate masking structure used to pattern the location of the gate cuts to ensure that the gate masking structure has low sidewall taper and sufficiently opened enough to expose the underlying gate.
Inventor(s): Leonard P. GULER of Hillsboro OR (US) for intel corporation, Sukru YEMENICIOGLU of Portland OR (US) for intel corporation, Raghuram GANDIKOTA of Portland OR (US) for intel corporation, Krishna GANESAN of Portland OR (US) for intel corporation, Sean PURSEL of Hillsboro OR (US) for intel corporation
IPC Code(s): H01L29/423, H01L29/06, H01L29/40, H01L29/66, H01L29/775
Abstract: integrated circuit structures having gate volume reduction, and methods of fabricating integrated circuit structures having gate volume reduction, are described. for example, an integrated circuit structure includes a sub-fin structure beneath a stack of nanowires, the stack of nanowires having a first side and a second side. a dielectric backbone structure is along the first side of the stack of nanowires. the dielectric backbone structure has a bottom above a bottom of the sub-fin. a gate electrode is over the stack of nanowires and is along the second side of the stack of nanowires. a gate dielectric structure is between the gate electrode and the stack of nanowires.
Inventor(s): Leonard P. GULER of Hillsboro OR (US) for intel corporation, Marie CONTE of Hillsboro OR (US) for intel corporation, Charles H. WALLACE of Portland OR (US) for intel corporation, Robert JOACHIM of Beaverton OR (US) for intel corporation, Shengsi LIU of Portland OR (US) for intel corporation, Saurabh ACHARYA of Hillsboro OR (US) for intel corporation, Nidhi KHANDELWAL of Portland OR (US) for intel corporation, Kyle T. HORAK of Portland OR (US) for intel corporation, Robert ROBINSON of Beaverton OR (US) for intel corporation, Brandon PETERS of Darien IL (US) for intel corporation
IPC Code(s): H01L29/423, H01L29/06, H01L29/78, H01L29/786
Abstract: integrated circuit structures having gate cut plugs removed from trench contacts, and methods of fabricating integrated circuit structures having gate cut plugs removed from trench contacts, are described. for example, an integrated circuit structure includes a vertical stack of horizontal nanowires. a gate electrode is over the vertical stack of horizontal nanowires. a conductive trench contact is adjacent to the gate electrode. a dielectric sidewall spacer is between the gate electrode and the conductive trench contact. a gate cut plug extends through the gate electrode and the dielectric sidewall spacer. the gate cut plug extends into but not entirely through the conductive trench contact.
Inventor(s): Leonard P. GULER of Hillsboro OR (US) for intel corporation, Dan S. LAVRIC of Beaverton OR (US) for intel corporation, Charles H. WALLACE of Portland OR (US) for intel corporation, Tahir GHANI of Portland OR (US) for intel corporation, Saurabh ACHARYA of Hillsboro OR (US) for intel corporation, Thomas O'BRIEN of Portland OR (US) for intel corporation
IPC Code(s): H01L29/423, H01L29/06, H01L29/78, H01L29/786
Abstract: integrated circuit structures having trench contact depopulation structures, and methods of fabricating integrated circuit structures having trench contact depopulation structures, are described. for example, an integrated circuit structure includes a vertical stack of horizontal nanowires. a gate stack is over the vertical stack of horizontal nanowires. a dielectric trench structure is adjacent to the gate stack. a dielectric sidewall spacer is between the gate stack and the dielectric trench structure. a dielectric gate cut plug is extending through the gate stack, the dielectric sidewall spacer, and the dielectric trench structure.
Inventor(s): Leonard P. GULER of Hillsboro OR (US) for intel corporation, Sean PURSEL of Hillsboro OR (US) for intel corporation, Dan S. LAVRIC of Beaverton OR (US) for intel corporation, Allen B. GARDINER of Portland OR (US) for intel corporation, Jonathan HINKE of Portland OR (US) for intel corporation, Wonil CHUNG of Hillsboro OR (US) for intel corporation
IPC Code(s): H01L29/423, H01L29/06, H01L29/775, H01L29/786
Abstract: integrated circuit structures having fin isolation regions bound by gate cuts are described. in an example, an integrated circuit structure includes a vertical stack of horizontal nanowires over a first sub-fin. a gate structure is over the vertical stack of horizontal nanowires and on the first sub-fin. a dielectric structure is laterally spaced apart from the gate structure. the dielectric structure is not over a channel structure but is on a second sub-fin. a gate cut is between the gate structure and the dielectric structure.
Inventor(s): Rachel A. Steinhardt of Beaverton OR (US) for intel corporation, Ian Alexander Young of Olympia WA (US) for intel corporation, Dmitri Evgenievich Nikonov of Beaverton OR (US) for intel corporation, Marko Radosavljevic of Portland OR (US) for intel corporation, Matthew V. Metz of Portland OR (US) for intel corporation, John J. Plombon of Portland OR (US) for intel corporation, Raseong Kim of Portland OR (US) for intel corporation, Kevin P. O'Brien of Portland OR (US) for intel corporation, Scott B. Clendenning of Portland OR (US) for intel corporation, Tristan A. Tronic of Aloha OR (US) for intel corporation, Dominique A. Adams of Portland OR (US) for intel corporation, Carly Rogan of North Plains OR (US) for intel corporation, Arnab Sen Gupta of Hillsboro OR (US) for intel corporation, Brandon Holybee of Portland OR (US) for intel corporation, Punyashloka Debashis of Hillsboro OR (US) for intel corporation, I-Cheng Tung of Hillsboro OR (US) for intel corporation, Gauri Auluck of Hillsboro OR (US) for intel corporation
IPC Code(s): H01L29/51, H01L29/66, H01L29/78
Abstract: in one embodiment, transistor device includes a first source or drain material on a substrate, a semiconductor material on the first source or drain material, a second source or drain material on the semiconductor material, a dielectric layer on the substrate and adjacent the first source or drain material, a ferroelectric (fe) material on the dielectric layer and adjacent the semiconductor material, and a gate material on or adjacent to the fe material. the fe material may be a perovskite material and may have a lattice parameter that is less than a lattice parameter of the semiconductor material.
Inventor(s): Abhishek Anil Sharma of Portland OR (US) for intel corporation, Sagar Suthram of Portland OR (US) for intel corporation, Tahir Ghani of Portland OR (US) for intel corporation, Anand Murthy of Portland OR (US) for intel corporation, Wilfred Gomes of Portland OR (US) for intel corporation, Pushkar Ranade of San Jose CA (US) for intel corporation
IPC Code(s): H01L29/51, H01L21/28, H01L27/11507, H01L27/1159
Abstract: an integrated circuit (ic) die includes a plurality of ferroelectric tunnel junction (ftj) devices, where at least one ftj of the plurality of ftj devices comprises first electrode, a second electrode, ferroelectric material disposed between the first and second electrodes, and interface material disposed between at least one of the first and second electrodes and the ferroelectric material. other embodiments are disclosed and claimed.
Inventor(s): Kevin P. O'Brien of Portland OR (US) for intel corporation, Brandon Holybee of Portland OR (US) for intel corporation, Carly Rogan of North Plains OR (US) for intel corporation, Dmitri Evgenievich Nikonov of Beaverton OR (US) for intel corporation, Punyashloka Debashis of Hillsboro OR (US) for intel corporation, Rachel A. Steinhardt of Beaverton OR (US) for intel corporation, Tristan A. Tronic of Aloha OR (US) for intel corporation, Ian Alexander Young of Olympia WA (US) for intel corporation, Marko Radosavljevic of Portland OR (US) for intel corporation, John J. Plombon of Portland OR (US) for intel corporation
IPC Code(s): H01L29/775, H01L29/06, H01L29/24, H01L29/423, H01L29/49, H01L29/66
Abstract: a transistor device may include a first perovskite gate material, a first perovskite ferroelectric material on the first gate material, a first perovskite semiconductor material on the first ferroelectric material, a second perovskite ferroelectric material on the first semiconductor material, a second perovskite gate material on the second ferroelectric material, a third perovskite ferroelectric material on the second gate material, a second perovskite semiconductor material on the third ferroelectric material, a fourth perovskite ferroelectric material on the second semiconductor material, a third perovskite gate material on the fourth ferroelectric material, a first source/drain metal adjacent a first side of each of the first semiconductor material and the second semiconductor material, a second source/drain metal adjacent a second side opposite the first side of each of the first semiconductor material and the second semiconductor material, and dielectric materials between the source/drain metals and the gate materials.
20240105852.TOP-GATE DOPED THIN FILM TRANSISTOR_simplified_abstract_(intel corporation)
Inventor(s): Abhishek A. Sharma of Portland OR (US) for intel corporation, Sean T. Ma of Portland OR (US) for intel corporation, Van H. Le of Beaverton OR (US) for intel corporation, Jack T. Kavalieros of Portland OR (US) for intel corporation, Gilbert Dewey of Beaverton OR (US) for intel corporation
IPC Code(s): H01L29/786, H01L29/06, H01L29/423, H01L29/49, H01L29/66
Abstract: top-gate thin film transistor (tfts) structures. thin film transistors when in the top-gate configuration suffer from contact resistance. an example tft includes a semiconductor layer doped with one or more dopant elements. a gate dielectric layer is on the semiconductor layer, and a gate electrode is on the gate dielectric layer. the semiconductor layer is doped with the one or more dopant elements beneath the gate dielectric layer. the tft may further include one or more contacts and/or one or more gate spacers, and the semiconductor layer may further be doped with the one or more dopant elements beneath the contact(s) and/or gate spacer(s).
Inventor(s): Gilbert Dewey of Hillsboro OR (US) for intel corporation, Abhishek Sharma of Hillsboro OR (US) for intel corporation, Van Le of Beaverton OR (US) for intel corporation, Jack Kavalieros of Portland OR (US) for intel corporation, Shriram Shivaraman of Hillsboro OR (US) for intel corporation, Seung Hoon Sung of Portland OR (US) for intel corporation, Tahir Ghani of Portland OR (US) for intel corporation, Arnab Sen Gupta of Beaverton OR (US) for intel corporation, Nazila Haratipour of Hillsboro OR (US) for intel corporation, Justin Weber of Portland OR (US) for intel corporation
IPC Code(s): H01L29/786, H01L21/8238, H01L27/092, H01L29/221
Abstract: transistor structures may include a metal oxide contact buffer between a portion of a channel material and source or drain contact metallization. the contact buffer may improve control of transistor channel length by limiting reaction between contact metallization and the channel material. the channel material may be of a first composition and the contact buffer may be of a second composition.
Inventor(s): Abhishek Anil Sharma of Portland OR (US) for intel corporation, Tahir Ghani of Portland OR (US) for intel corporation, WIlfred Gomes of Portland OR (US) for intel corporation, Anand Murthy of Portland OR (US) for intel corporation, Sagar Suthram of Portland OR (US) for intel corporation, Pushkar Ranade of San Jose CA (US) for intel corporation
IPC Code(s): H01L29/93, H01L21/28, H01L29/51, H01L29/66
Abstract: an integrated circuit (ic) die includes a plurality of varactor devices, where at least one varactor of the plurality of varactor devices comprises a first electrode, a second electrode, and a multi-layer stack of ferroelectric material (e.g., ferroelectric variable capacitance material) disposed between the first and second electrodes. other embodiments are disclosed and claimed.
Inventor(s): Zhen ZHOU of Chandler AZ (US) for intel corporation, Tolga ACIKALIN of San Jose CA (US) for intel corporation, Kenneth FOUST of Beaverton OR (US) for intel corporation, Shuhei YAMADA of Vancouver WA (US) for intel corporation, Tae Young YANG of Portland OR (US) for intel corporation, Timothy F. COX of Palo Alto CA (US) for intel corporation, Renzhi LIU of Portland OR (US) for intel corporation, Richard DORRANCE of Hillsboro OR (US) for intel corporation, Johanny ESCOBAR PELAEZ of Zapopan (MX) for intel corporation
IPC Code(s): H01Q9/04, H01Q1/22
Abstract: a communication system, including a first carrier and a first antenna mounted on the first carrier; a second carrier and a second antenna mounted on the second carrier, wherein the first antenna and the second antenna are arranged relative to each other that the first antenna and the second antenna can establish wireless link; a third carrier and a third antenna mounted on the third carrier; a fourth carrier and a fourth antenna mounted on the fourth carrier, wherein the third antenna and the fourth antenna are arranged relative to each other that the third antenna and the fourth antenna can establish wireless link; and a transmission structure, within which the signal propagate through, connects the second antenna and the third antenna.
Inventor(s): Jiun Hann SIR of Gelugor (MY) for intel corporation, Eng Huat GOH of Ayer Itam (MY) for intel corporation, Poh Boon KHOO of Perai (MY) for intel corporation, Chin Mian CHOONG of Georgetown (MY) for intel corporation, Jooi Wah WONG of Bukit Mertajam (MY) for intel corporation, Jia Yun WONG of Pulau (MY) for intel corporation
IPC Code(s): H01R12/57, H01L25/065, H01L25/10, H01R12/52, H01R12/79, H01R13/03, H01R13/508, H01R43/20
Abstract: embodiments herein relate to systems, apparatuses, or processes for a connector for a modular memory package that includes one or more memory dies on a substrate, where the connector directly electrically couples electrical contacts at an edge and on each side the substrate of the memory package to electrical contacts at an edge and on each side of another substrate that includes a compute die. the connector may include a first plurality of leads that are substantially parallel with each other, and a second plurality of leads that are substantially parallel with each other that are below the first plurality of leads and electrically couple the two substrates. other embodiments may be described and/or claimed.
20240106625.SECURING AUDIO COMMUNICATIONS_simplified_abstract_(intel corporation)
Inventor(s): Pradeep M. Pappachan of Tualatin OR (US) for intel corporation, Reshma Lal of Portland OR (US) for intel corporation, Rakesh A. Ughreja of Bangalore (IN) for intel corporation, Kumar N. Dwarakanath of Folsom CA (US) for intel corporation, Victoria C. Moore of Phoenix AZ (US) for intel corporation
IPC Code(s): H04L9/00, G06F9/54, G06F21/44, G06F21/57, G06F21/60, G06F21/83, G06F21/84, H04L9/08, H04L9/40
Abstract: systems and methods include establishing a cryptographically secure communication between an application module and an audio module. the application module is configured to execute on an information-handling machine, and the audio module is coupled to the information-handling machine. the establishment of the cryptographically secure communication may be at least partially facilitated by a mutually trusted module.
Inventor(s): Santosh Ghosh of Hillsboro OR (US) for intel corporation
IPC Code(s): H04L9/06
Abstract: a system and method for generating, from a permutation of a first input state, a first output state, a first rate and a first capacity, the first rate including a first portion of the first output state and the first capacity including a second portion of the first output state; storing the first output state; generating a first block of ciphertext data of a first packet from xoring the first rate and a first block of plaintext data of the first packet; generating a permutation of a value of the first block of ciphertext data of the first packet concatenated with the first capacity, and generating a second block of ciphertext data of the first packet from xor of the permutation of the value of the first block of ciphertext data of the first packet concatenated with the first capacity.
Inventor(s): Aditya Katragada of Austin TX (US) for intel corporation, Geoffrey Strongin of Tigard OR (US) for intel corporation, Prakash Iyer of Portland OR (US) for intel corporation, Rajesh Banginwar of Bangalore (IN) for intel corporation, Poh Thiam Teoh of Penang (MY) for intel corporation, Gary Wallichs of San Jose CA (US) for intel corporation
IPC Code(s): H04L9/08
Abstract: a system and method of enhancing the mitigation of side channel attacks on platform interconnects using endpoint hw based detection, synchronization, and re-keying include generating a set of keys for link encryption based on a high entropy seed, storing the set of keys in a deterministic order in a register, detecting that a re-key programmable threshold is met during link encryption with a device, identifying a synchronization point associated with the device, where the synchronization point indicates the device is ready to switch a current key used for link encryption, and synchronizing a rekeying event with the device.
Inventor(s): Ilan HAMAMI of Tel Mond (IL) for intel corporation, Ehud RESHEF of KIRYAT TIVON (IL) for intel corporation, Ofer HAREUVENI of Haifa (IL) for intel corporation, Menashe Shani BEN-HAIM of Tel Aviv (IL) for intel corporation, Nevo IDAN of Zichron Ya'akov (IL) for intel corporation
IPC Code(s): H04L45/302, H04L47/74
Abstract: various examples relate to apparatuses, devices, methods and computer-readable media for handling connectivity packages. an apparatus for a gateway device comprises interface circuitry, machine-readable instructions, and processor circuitry to execute the machine-readable instructions to obtain information on a plurality of available connectivity packages, with each connectivity package defining a connection between the gateway device and an endpoint of an internet service provider, and with each connectivity package being characterized by one or more connection performance parameters, select one or more connectivity packages of the available connectivity packages for data traffic of a client device, and route the data traffic of the client device via one or more connections between the gateway device and a corresponding endpoint of the internet service provider associated with a respective connectivity package of the selected one or more connectivity packages.
Inventor(s): Nayan Amrutlal SUTHAR of Bangalore (IN) for intel corporation, Uri ELZUR of San Jose CA (US) for intel corporation, Josh D. COLLIER of Royersford PA (US) for intel corporation
IPC Code(s): H04L45/00, H04L45/24, H04L45/42
Abstract: examples include techniques for multipathing over reliable paths and completion reporting. example techniques include examples of providing reliability over multiple paths routed through a network between a source and a target of a message. example techniques also include examples of completion reporting for messages sent via packets routed through a network over multiple paths.
Inventor(s): Kylan Race of Austin TX (US) for intel corporation, Ernesto Zamora Ramos of Folsom CA (US) for intel corporation, Jeremy Bottleson of North Plains OR (US) for intel corporation, Bradley Smith of Hillsboro OR (US) for intel corporation
IPC Code(s): H04L9/40, H04L9/00, H04L67/131
Abstract: an improved ar/vr operation includes receiving, by a server computing device, encrypted ar/vr user data and cleartext metadata associated with the encrypted ar/vr user data from a client computing device; getting server data based at least in part on cleartext metadata; encoding the server data; performing an ar/vr process on the encrypted ar/vr user data and the encoded server data to generate encrypted ar/vr results; and sending the encrypted ar/vr results to the client computing device.
Inventor(s): ERNESTO ZAMORA RAMOS of Folsom CA (US) for intel corporation, KYLAN RACE of Austin TX (US) for intel corporation, JEREMY BOTTLESON of North Plains OR (US) for intel corporation
IPC Code(s): H04L9/40, G06T7/70, G06V20/40, G10L25/57, H04L9/00
Abstract: a method comprises receiving, from a remote device, an audio/video input signal, identifying one or more objects in the audio/video input signal tagged as a sensitive object, evaluating a set of workload requirements for a set of processing workloads comprising portions of the audio/video input signal, selecting one or more heavy processing workloads in the set of processing workloads to send to a compute service provider, in response to a determination that the one or more heavy processing workloads comprises one or more objects tagged as a sensitive object, encrypting the one or more objects tagged as a sensitive object using a homomorphic encryption protocol to generate a first homomorphically encrypted string, and sending the first homomorphically encrypted string to the compute service provider via a privacy protected communication channel.
Inventor(s): Ned M. Smith of Beaverton OR (US) for intel corporation, Sunil Cheruvu of Tempe AZ (US) for intel corporation, Gerald Alan Rogers of Chandler AZ (US) for intel corporation, Victor Medrano of Marana AZ (US) for intel corporation, Kshitij Arun Doshi of Tempe AZ (US) for intel corporation
IPC Code(s): H04L9/40
Abstract: various systems and methods are described to enable cyber-physical protections in edge computing platforms, including with countermeasures that mitigate and halt a variety of digital or real-world attacks. in an example, an attack detection and response engine is used to monitor processing circuitry, with operations that: identify operational data from processing circuitry that operates multiple layers (e.g., of an ip block) to perform compute operations, with trust of the processing circuitry established based on attestation of a hardware root of trust (rot); evaluate the operational data to identify an attack condition at the processing circuitry, based on monitoring an operational layer of the multiple layers; and provide a digital attack response to the processing circuitry, in response to identifying the attack condition, to deploy the digital attack response and cause a countermeasure at the operational layer of the processing circuitry.
Inventor(s): Kannan Babu Ramia of Bangalore (IN) for intel corporation, Palaniappan Ramanathan of Bengaluru (IN) for intel corporation, Deepak S of Bangalore (IN) for intel corporation, Bhavik Dhandhalya of Bhavnagar (IN) for intel corporation
IPC Code(s): H04L67/14
Abstract: methods, apparatus, systems, and articles of manufacture to add a non-native node to a cluster are disclosed. an example apparatus includes programmable circuitry to at least one of instantiate a first agent to interface with a management application to obtain a request from a node to join a cluster of nodes, the first agent to interface with the management application using a first protocol; and instantiate a second agent which employs a second protocol different than the first protocol: responsive to an authentication of an identity credential of the node, obtain a secret credential; and cause the first agent to pass the secret credential to the node via the management application to enable the node to join the cluster of nodes.
Inventor(s): Stanley Baran of Chandler AZ (US) for intel corporation, Jason Tanner of Folsom CA (US) for intel corporation, Venkateshan Udhayan of Portland OR (US) for intel corporation, Chia-Hung S. Kuo of Folsom CA (US) for intel corporation
IPC Code(s): H04N19/159, G06T7/62, H04N19/167
Abstract: an example apparatus determines a size of a dirty region of a video frame; after the size of the dirty region satisfies a threshold: encode the dirty region of the video frame to generate an encoded dirty region; and cause storing of the dirty region in the cache; and after the size of the dirty region does not satisfy the threshold: cause storing of the video frame in a volatile memory that is separate from the cache; and encode the video frame via inter-encoding to generate an encoded video frame.
Inventor(s): Minzhi Sun of Bellevue WA (US) for intel corporation, Ximin Zhang of San Jose CA (US) for intel corporation, Yi-jen Chiu of San Jose CA (US) for intel corporation
IPC Code(s): H04N19/86, H04N19/124, H04N19/176
Abstract: methods, articles, and systems of image processing comprise obtaining image data of frames of a video sequence. the method also includes determining multiple reference frames of a current frame in the video sequence. the multiple reference frames each have at least one motion compensated (mc) block of image data. also, the method then includes generating a weight that factors noise, distortion variance, and dispersion distribution between the same mc block position and the current block. thereafter, the method includes generating denoised filtered image data comprising applying one of the weights to the image data of the motion compensated (mc) block.
Inventor(s): Emily H. QI of Gig Harbor WA (US) for intel corporation, Po-Kai HUANG of San Jose CA (US) for intel corporation, Laurent CARIOU of Milizac (FR) for intel corporation, Hassan YAGHOOBI of San Jose CA (US) for intel corporation, Carlos CORDEIRO of Camas WA (US) for intel corporation
IPC Code(s): H04W48/16, H04W72/0453, H04W76/14
Abstract: this disclosure describes systems, methods, and devices related to neighbor awareness networking (nan) operations in the 6 ghz frequency band. a nan device may generate a first nan frame including a first indication of a nan operation capability, and a second indication of a transmit power of the nan device. the nan device may send the first nan frame and may identify a second nan frame received from a second nan device, the second nan frame including a third indication of the nan operation capability, and a fourth indication of a transmit power of the second nan device. the nan device may determine, based on the transmit power of the nan device and the transmit power of the second nan device, an operation parameter for the 6 ghz frequency band. the nan device may establish, based on the operation parameter, a nan connection using the 6 ghz frequency band.
Inventor(s): Vaibhav SINGH of New Delhi (IN) for intel corporation, Christian MACIOCCO of Portland OR (US) for intel corporation
IPC Code(s): H04W52/02, H04B7/0413, H04B7/06, H04B7/08
Abstract: a device may include a memory and a processor configured to determine, based on first cell data representative of conditions of a cell of a mobile communication network at a first stage associated with a first instance of time, a set of configurations for an antenna array comprising a plurality of antenna elements, wherein each configuration of the set of configurations comprises a configuration in which a subset of the plurality of antenna elements are to be used to perform communications within the cell, and select one or more antenna configurations for the antenna array from the determined set of configurations, wherein each antenna configuration of the one or more antenna configurations are selected based on further cell data representative of the conditions of the cell at a further stage associated with a further instance of time after the first instance of time.
20240107448.TRAFFIC INDICATION MAP PIGGYBACKING_simplified_abstract_(intel corporation)
Inventor(s): Laurent Cariou of Milizac (FR) for intel corporation, Po-Kai Huang of San Jose OR (US) for intel corporation, Alexander Min of Portland OR (US) for intel corporation, Minyoung Park of San Ramon CA (US) for intel corporation, Rath Vannithamby of Portland OR (US) for intel corporation
IPC Code(s): H04W52/02, H04L1/1607, H04W72/0446, H04W72/0453
Abstract: this disclosure describes systems, methods, and devices related to traffic indication map (tim) piggybacking. a device may determine a frame including one or more tims indicating that the device has data to send in a first frequency band of a plurality of supported frequency bands. the device may cause to send the frame in a second frequency band of the plurality of supported frequency bands, wherein the first frequency band is different from the second frequency band, wherein the frame indicates a request for a first station device to be awake in the first frequency band to receive the data. the device may cause to send the data using the first frequency band.
Inventor(s): Abhishek A. Sharma of Hillsboro OR (US) for intel corporation, Tahir Ghani of Portland OR (US) for intel corporation, Wilfred Gomes of Portland OR (US) for intel corporation, Anand S. Murthy of Portland OR (US) for intel corporation, Sagar Suthram of Portland OR (US) for intel corporation
IPC Code(s): H01L27/108, G11C5/02, G11C11/404
Abstract: various arrangements for ic devices implementing memory with one access transistor for multiple capacitors are disclosed. an example ic device includes a memory array of m memory units, where each memory unit includes an access transistor and n capacitors coupled to the access transistor. a portion of the capacitors are formed in one or more layers above the access transistor, and a portion of the capacitors are formed in one or more layers below the access transistor. the capacitors in a particular memory unit may be coupled to a single via or to individual vias. in some embodiments, some of the vias are backside vias.
Inventor(s): Shayan Kaviani of Phoenix AZ (US) for intel corporation, Benjamin Duong of Phoenix AZ (US) for intel corporation, Miranda Ngan of Chandler AZ (US) for intel corporation, Mahdi Mohammadighaleni of Phoenix AZ (US) for intel corporation
IPC Code(s): H01L51/44
Abstract: methods, apparatus, systems, and articles of manufacture utilizing conjugated polymers in integrated circuit packages with glass substrates are disclosed. a disclosed integrated circuit (ic) package includes: a glass substrate; a first electrode; an organic material; and a second electrode. the first electrode is between the glass substrate and the organic material. the organic material includes at least one of a conjugated polymer or a metal-organic supramolecule. the organic material is between the first electrode and the second electrode.
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