Intel Corporation patent applications on March 14th, 2024
Patent Applications by Intel Corporation on March 14th, 2024
Intel Corporation: 54 patent applications
Intel Corporation has applied for patents in the areas of G06T1/20 (14), G06T1/60 (12), H01L29/06 (11), H01L29/0673 (9), G06F9/50 (7)
With keywords such as: memory, device, structure, data, region, gate, semiconductor, example, structures, and having in patent application abstracts.
See the following report for Intel Corporation patent applications on March 14th, 2024: Intel Corporation patent applications on March 14th, 2024
Patent Applications by Intel Corporation
Inventor(s): Jianwei Dai of Portland OR (US) for intel corporation, Yashwitha Suvarna of Union City CA (US) for intel corporation, Boon Hui Ang of Bukit Mertajam (MY) for intel corporation, Pranali Shah of Hillsboro OR (US) for intel corporation
IPC Code(s): G06F1/3296, G06F9/52
Abstract: embodiments described herein may include apparatus, systems, techniques or processes that are directed to chiplet state aware and dynamic prioritization of voltage regulator event indication handling. an intelligent arbiter notifies chiplets of vr events in a dynamic priority scheme that considers multiple factors such as chiplet state (for example, active, sleep, deep sleep, and the like), chiplet power consumption and time frame for transitioning to an active state, outstanding vr requests, chiplet latency sensitivity and the like in its prioritization of chiplet notifications. as chiplet states themselves are dynamic with a chiplet transitioning between multiple states during operation, the intelligent arbiter may also utilize a dynamic prioritization scheme to maximize efficiency and minimize power consumption.
Inventor(s): Praveen MOSALIKANTI of Portland OR (US) for intel corporation, Nasser A. KURD of Portland OR (US) for intel corporation, Alexander GENDLER of Kiriat Motzkin (IL) for intel corporation
IPC Code(s): G06F1/3296, G01R19/25, H03K5/24, H03K19/20, H03L7/093, H03L7/095
Abstract: an apparatus and method are described, which prior to an event that could result in frequency overshoot, sends a signal to a voltage regulator or generator requesting a temporary supply voltage and/or current boost. this enables a clocking source, such as a phase locked loop (pll) to lock fast while not needing any long-term voltage guard bands. the apparatus and scheme allows for on-the-fly change in supply voltage and/or clock frequency for a processor with little to no impact on vmin. during the clock frequency overshoot, the supply voltage is temporarily boosted and then reduced down to the expected voltage level of the power supply. such boost allows for absorbing the clock frequency overshoot impact. the supply voltage level can be reduced in a step-wise fashion to avoid any potential undershoot in clock frequency.
20240086064.OFFSET SCALING IN LOAD/STORE MESSAGES_simplified_abstract_(intel corporation)
Inventor(s): John Wiegert of Aloha OR (US) for intel corporation, Joydeep Ray of Folsom CA (US) for intel corporation, Timothy Bauer of Hillsboro OR (US) for intel corporation, James Valerio of North Plains OR (US) for intel corporation
IPC Code(s): G06F3/06, G06T1/20, G06T1/60
Abstract: embodiments described herein enable the offload of address calculations required to access a data element within an array of data elements from primary compute resources of a graphics processor to the memory access circuitry of the graphics processor. the memory access circuitry is configured to receive a message to access a data element of an array of data elements in the memory, the message to include an index of the data element in the array of data elements, calculate a byte address for the data element based in part on the index of the data element in the array of data elements, and submit a memory access request to the memory to access the data element at the byte address.
Inventor(s): Rizwana Begum of Sachse TX (US) for intel corporation, Rohit Sharad Phatak of Hillsboro OR (US) for intel corporation, Eric Heit of Hillsboro OR (US) for intel corporation, Xiangdong Lou of Poway CA (US) for intel corporation
IPC Code(s): G06F3/06
Abstract: embodiments described herein may include apparatus, systems, techniques, and/or processes that are directed to optimizing memory frequency based on the bandwidth and latency needs of heterogeneous processing cores in a computer system. according to various embodiments, adjustments to the frequency of memory may be applied differently depending on the type of core requesting more bandwidth and/or faster response. according to various embodiments, the frequency is increased more sparingly for energy-efficient cores, while the frequency is increased more generously for high-performance cores. additionally, when memory traffic decreases, the frequency of memory is decreased more generously when the previous request for higher frequency was from an energy-efficient core than a high-performance core. by considering the type of core that is requesting more bandwidth and/or faster response, performance and power consumption may be more optimally balanced.
20240086138.Regional Adjustment of Render Rate_simplified_abstract_(intel corporation)
Inventor(s): Eric J. Asperheim of El Dorado Hills CA (US) for intel corporation, Subramaniam Maiyuran of Gold River CA (US) for intel corporation, Kiran C. Veernapu of Bangalore (IN) for intel corporation, Sanjeev S. Jahagirdar of Folsom CA (US) for intel corporation, Balaji Vembu of Folsom CA (US) for intel corporation, Devan Burke of Portland OR (US) for intel corporation, Philip R. Laws of Santa Clara CA (US) for intel corporation, Kamal Sinha of Rancho Cordova CA (US) for intel corporation, Abhishek R. Appu of El Dorado Hills CA (US) for intel corporation, Elmoustapha Ould-Ahmed-Vall of Chandler AZ (US) for intel corporation, Peter L. Doyle of El Dorado Hills CA (US) for intel corporation, Joydeep Ray of Folsom CA (US) for intel corporation, Travis T. Schluessler of Hillsboro OR (US) for intel corporation, John H. Feit of Folsom CA (US) for intel corporation, Nikos Kaburlasos of Lincoln CA (US) for intel corporation, Jacek Kwiatkowski of Santa Clara CA (US) for intel corporation, Altug Koker of El Dorado Hills CA (US) for intel corporation
IPC Code(s): G06F3/14, G06F3/01, G06F3/0484, G09G5/391
Abstract: in accordance with some embodiments, the render rate is varied across and/or up and down the display screen. this may be done based on where the user is looking in order to reduce power consumption and/or increase performance. specifically the screen display is separated into regions, such as quadrants. each of these regions is rendered at a rate determined by at least one of what the user is currently looking at, what the user has looked at in the past and/or what it is predicted that the user will look at next. areas of less focus may be rendered at a lower rate, reducing power consumption in some embodiments.
Inventor(s): Theo Drane of El Dorado Hills CA (US) for intel corporation, Emiliano Morini of Folsom CA (US) for intel corporation, Jordan Schmerge of Folsom CA (US) for intel corporation, Samuel Coward of London (GB) for intel corporation
IPC Code(s): G06F8/41, G06F30/327
Abstract: described herein is a technique for automatic generation of optimized rtl via redundant code removal. by automatically introducing local mutations into the original rtl and using equivalence checking tools to confirm that the functionality it is not affected, optimized rtl can be produced automatically without requiring human intervention.
Inventor(s): Ahmad Yasin of Haifa (IL) for intel corporation
IPC Code(s): G06F9/30, G06F9/38, G06F11/30
Abstract: a processor includes a front end, an execution unit, a retirement stage, a counter, and a performance monitoring unit. the front end includes logic to receive an event instruction to enable supervision of a front end event that will delay execution of instructions. the execution unit includes logic to set a register with parameters for supervision of the front end event. the front end further includes logic to receive a candidate instruction and match the candidate instruction to the front end event. the counter includes logic to generate the front end event upon retirement of the candidate instruction.
Inventor(s): Balaji Vembu of Folsom CA (US) for intel corporation, Abhishek R. Appu of El Dorado Hills CA (US) for intel corporation, Joydeep Ray of Folsom CA (US) for intel corporation, Altug Koker of El Dorado Hills CA (US) for intel corporation
IPC Code(s): G06F9/38, G06F9/46, G06F9/48, G06F9/50, G06F9/52, G06F9/54, G06F12/0842, G06F12/0866, G06F12/0897, G06F15/16, G06F15/76, G06T1/20, G06T1/60
Abstract: an apparatus to facilitate thread scheduling is disclosed. the apparatus includes logic to store barrier usage data based on a magnitude of barrier messages in an application kernel and a scheduler to schedule execution of threads across a plurality of multiprocessors based on the barrier usage data.
20240086243.OFFLOAD COMPUTING PROTOCOL_simplified_abstract_(intel corporation)
Inventor(s): Fearghal O'Hare of Leixlip DC (US) for intel corporation, Michael Nolan of Maynooth (IE) for intel corporation, James A. O'Neill of Meath (IE) for intel corporation
IPC Code(s): G06F9/50, H04L67/00, H04L67/10, H04L67/1001
Abstract: systems and methods for are provided for offloading computing tasks from constrained devices. an example apparatus includes an offload computing protocol (ocp) enabled device. the ocp enabled device includes ocp extensions to the operating system to enable the offloading of computing tasks. a proximity locator may use a radio transceiver to locate an ocp device that can accept a computing task. the ocp enabled device may include an ocp bundle comprising code and data, wherein the ocp bundle is to be sent to the ocp device.
Inventor(s): Reshma Lal of Portland OR (US) for intel corporation, Pradeep Pappachan of Tualatin OR (US) for intel corporation, Luis Kida of Beaverton OR (US) for intel corporation, Soham Jayesh Desai of Rochester MN (US) for intel corporation, Sujoy Sen of Beaverton OR (US) for intel corporation, Selvakumar Panneer of Portland OR (US) for intel corporation, Robert Sharp of Austin TX (US) for intel corporation
IPC Code(s): G06F9/50, G06F9/38, G06T1/20, G06T1/60
Abstract: an apparatus to facilitate disaggregated computing for a distributed confidential computing environment is disclosed. the apparatus includes one or more processors to facilitate receiving a manifest corresponding to graph nodes representing regions of memory of a remote client machine, the graph nodes corresponding to a command buffer and to associated data structures and kernels of the command buffer used to initialize a hardware accelerator and execute the kernels, and the manifest indicating a destination memory location of each of the graph nodes and dependencies of each of the graph nodes; identifying, based on the manifest, the command buffer and the associated data structures to copy to the host memory; identifying, based on the manifest, the kernels to copy to local memory of the hardware accelerator; and patching addresses in the command buffer copied to the host memory with updated addresses of corresponding locations in the host memory.
20240086291.SELECTIVE CHECKING FOR ERRORS_simplified_abstract_(intel corporation)
Inventor(s): Francesc Guim Bernat of Barcelona (ES) for intel corporation, Karthik Kumar of Chandler AZ (US) for intel corporation, Amruta Misra of Bangalore (IN) for intel corporation
IPC Code(s): G06F11/30, G06F11/07, G06F11/10
Abstract: an apparatus comprising first circuitry to process a request generated by a first device, the request specifying a memory address range of a second device to monitor for errors; and second circuitry to, based on a determination that a read request targets the memory address range of the second device, compare first data read from the second device with second data read from a memory to determine whether an error has occurred.
20240086329.INSTRUCTION PREFETCH MECHANISM_simplified_abstract_(intel corporation)
Inventor(s): Vasileios Porpodas of San Jose CA (US) for intel corporation, Guei-Yuan Lueh of San Jose CA (US) for intel corporation, Subramaniam Maiyuran of Gold River CA (US) for intel corporation, Wei-Yu Chen of San Jose CA (US) for intel corporation
IPC Code(s): G06F12/0862, G06F8/41, G06F9/30, G06F12/0875
Abstract: an apparatus to facilitate data prefetching is disclosed. the apparatus includes a cache, one or more execution units (eus) to execute program code, prefetch logic to maintain tracking information of memory instructions in the program code that trigger a cache miss and compiler logic to receive the tracking information, insert one or more pre-fetch instructions in updated program code to prefetch data from a memory for execution of one or more of the memory instructions that triggered a cache miss and download the updated program code for execution by the one or more eus.
Inventor(s): Benjamin Graniello of Gilbert AZ (US) for intel corporation, Francesc Guim Bernat of Barcelona (ES) for intel corporation, Karthik Kumar of Chandler AZ (US) for intel corporation, Thomas Willhalm of Sandhausen (DE) for intel corporation
IPC Code(s): G06F13/16, G06F3/06, G06F9/50, G06F11/30, G06F12/02, G06F15/78
Abstract: methods, apparatus and systems for adaptive fabric allocation for local and remote emerging memories-based prediction schemes. in conjunction with performing memory transfers between a compute host and memory device connected via one or more interconnect segments, memory read and write traffic is monitored for at least one interconnect segment having reconfigurable upstream lanes and downstream lanes. predictions of expected read and write bandwidths for the at least one interconnect segment are then made. based on the expected read and write bandwidths, the upstream lanes and downstream lanes are dynamically reconfigured. the interconnect segments include interconnect links such as compute exchange link (cxl) flex buses and memory channels for local memory implementations, and fabric links for remote memory implementations. for local memory, management messages may be used to provide telemetry information containing the expected read and write bandwidths. for remote memory, telemetry information is provided to a fabric management component that is used to dynamically reconfigure one or more fabric links.
Inventor(s): Taner Sumesaglam of Folsom CA (US) for intel corporation
IPC Code(s): G06F13/38, H03K5/1252
Abstract: an improved circuit for crosstalk cancellation may be used to provide improved receiver crosstalk cancelation. these solutions may include a high-pass filter that is configured to be matched to victim path. these solutions may reduce or eliminate the use of a unity gain buffer and in-line high-pass filter, which may reduce design complexity and improve performance. these solutions provide crosstalk cancellation that requires less power, is less complex, is less sensitive to temperature and voltage, and is more effective at providing crosstalk cancellation. this improved crosstalk cancellation further provides channel eye height improvement, reduced ehi temperature sensitivity, reduced ehi voltage sensitivity, reduced design complexity, and reduced silicon circuit area.
20240086356.INSTRUCTION BASED CONTROL OF MEMORY ATTRIBUTES_simplified_abstract_(intel corporation)
Inventor(s): Joydeep Ray of Folsom CA (US) for intel corporation, Altug Koker of El Dorado Hills CA (US) for intel corporation, Varghese George of Folsom CA (US) for intel corporation, Mike Macpherson of Portland OR (US) for intel corporation, Aravindh Anantaraman of Folsom CA (US) for intel corporation, Abhishek R. Appu of El Dorado Hills CA (US) for intel corporation, Elmoustapha Ould-Ahmed-Vall of Chandler AZ (US) for intel corporation, Nicolas Galoppo von Borries of Portland OR (US) for intel corporation, Ben J. Ashbaugh of Folsom CA (US) for intel corporation
IPC Code(s): G06F15/78, G06F7/544, G06F7/575, G06F7/58, G06F9/30, G06F9/38, G06F9/50, G06F12/02, G06F12/06, G06F12/0802, G06F12/0804, G06F12/0811, G06F12/0862, G06F12/0866, G06F12/0871, G06F12/0875, G06F12/0882, G06F12/0888, G06F12/0891, G06F12/0893, G06F12/0895, G06F12/0897, G06F12/1009, G06F12/128, G06F15/80, G06F17/16, G06F17/18, G06T1/20, G06T1/60, H03M7/46
Abstract: embodiments described herein provide techniques to facilitate instruction-based control of memory attributes. one embodiment provides a graphics processor comprising a processing resource, a memory device, a cache coupled with the processing resources and the memory, and circuitry to process a memory access message received from the processing resource. the memory access message enables access to data of the memory device. to process the memory access message, the circuitry is configured to determine one or more cache attributes that indicate whether the data should be read from or stored the cache. the cache attributes may be provided by the memory access message or stored in state data associated with the data to be accessed by the access message.
Inventor(s): Altug Koker of El Dorado Hills CA (US) for intel corporation, Joydeep Ray of Folsom CA (US) for intel corporation, Aravindh Anantaraman of Folsom CA (US) for intel corporation, Valentin Andrei of San Jose CA (US) for intel corporation, Abhishek Appu of El Dorado Hills CA (US) for intel corporation, Sean Coleman of Folsom CA (US) for intel corporation, Nicolas Galoppo Von Borries of Portland OR (US) for intel corporation, Varghese George of Folsom CA (US) for intel corporation, Pattabhiraman K of Bangalore (IN) for intel corporation, SungYe Kim of Folsom CA (US) for intel corporation, Mike Macpherson of Portland OR (US) for intel corporation, Subramaniam Maiyuran of Gold River CA (US) for intel corporation, Elmoustapha Ould-Ahmed-Vall of Chandler AZ (US) for intel corporation, Vasanth Ranganathan of El Dorado Hills CA (US) for intel corporation, James Valerio of North Plains OR (US) for intel corporation
IPC Code(s): G06F15/78, G06F7/544, G06F7/575, G06F7/58, G06F9/30, G06F9/38, G06F9/50, G06F12/02, G06F12/06, G06F12/0802, G06F12/0804, G06F12/0811, G06F12/0862, G06F12/0866, G06F12/0871, G06F12/0875, G06F12/0882, G06F12/0888, G06F12/0891, G06F12/0893, G06F12/0895, G06F12/0897, G06F12/1009, G06F12/128, G06F15/80, G06F17/16, G06F17/18, G06T1/20, G06T1/60, H03M7/46
Abstract: systems and methods for updating remote memory side caches in a multi-gpu configuration are disclosed herein. in one embodiment, a graphics processor for a multi-tile architecture includes a first graphics processing unit (gpu) having a first memory, a first memory side cache memory, a first communication fabric, and a first memory management unit (mmu). the graphics processor includes a second graphics processing unit (gpu) having a second memory, a second memory side cache memory, a second memory management unit (mmu), and a second communication fabric that is communicatively coupled to the first communication fabric. the first mmu is configured to control memory requests for the first memory, to update content in the first memory, to update content in the first memory side cache memory, and to determine whether to update the content in the second memory side cache memory.
20240086683.NEURAL NETWORK SCHEDULING MECHANISM_simplified_abstract_(intel corporation)
Inventor(s): Liwei Ma of Beijing (CN) for intel corporation, Nadathur Rajagopalan Satish of Santa Clara CA (US) for intel corporation, Jeremy Bottleson of Rancho Cordova CA (US) for intel corporation, Farshad Akhbari of Chandler AZ (US) for intel corporation, Eriko Nurvitadhi of Hillsboro OR (US) for intel corporation, Chandrasekaran Sakthivel of Sunnyvale CA (US) for intel corporation, Barath Lakshmanan of Chandler AZ (US) for intel corporation, Jingyi Jin of Folsom CA (US) for intel corporation, Justin E. Gottschlich of Santa Clara CA (US) for intel corporation, Michael Strickland of Sunnyvale CA (US) for intel corporation
IPC Code(s): G06N3/044, G06F9/50, G06N3/045, G06N3/063, G06N3/084
Abstract: an apparatus to facilitate workload scheduling is disclosed. the apparatus includes one or more clients, one or more processing units to processes workloads received from the one or more clients, including hardware resources and scheduling logic to schedule direct access of the hardware resources to the one or more clients to process the workloads.
Inventor(s): Yiwen GUO of Beijing (CN) for intel corporation, Yuqing Hou of Beijing (CN) for intel corporation, Anbang YAO of Beijing (CN) for intel corporation, Dongqi Cai of Beijing (CN) for intel corporation, Lin Xu of Beijing (CN) for intel corporation, Ping Hu of Beijing (CN) for intel corporation, Shandong Wang of Shanghai (CN) for intel corporation, Wenhua Cheng of Shanghai (CN) for intel corporation, Yurong Chen of Beijing (CN) for intel corporation, Libin Wang of Beijing (CN) for intel corporation
IPC Code(s): G06N3/063, G06F18/21, G06F18/213, G06F18/214, G06N3/044, G06N3/045, G06N3/08, G06V10/44, G06V10/764, G06V10/82, G06V10/94, G06V20/00
Abstract: methods and systems for budgeted and simplified training of deep neural networks (dnns) are disclosed. in one example, a trainer is to train a dnn using a plurality of training sub-images derived from a down-sampled training image. a tester is to test the trained dnn using a plurality of testing sub-images derived from a down-sampled testing image. in another example, in a recurrent deep q-network (rdqn) having a local attention mechanism located between a convolutional neural network (cnn) and a long-short time memory (lstm), a plurality of feature maps are generated by the cnn from an input image. hard-attention is applied by the local attention mechanism to the generated plurality of feature maps by selecting a subset of the generated feature maps. soft attention is applied by the local attention mechanism to the selected subset of generated feature maps by providing weights to the selected subset of generated feature maps in obtaining weighted feature maps. the weighted feature maps are stored in the lstm. a q value is calculated for different actions based on the weighted feature maps stored in the lstm.
20240087077.MERGING ATOMICS TO THE SAME CACHE LINE_simplified_abstract_(intel corporation)
Inventor(s): Joydeep Ray of Folsom CA (US) for intel corporation, Abhishek R. Appu of El Dorado Hills CA (US) for intel corporation, Prathamesh Raghunath Shinde of Folsom CA (US) for intel corporation, John Wiegert of Aloha OR (US) for intel corporation
IPC Code(s): G06T1/60, G06T1/20
Abstract: embodiments described herein provide a technique to merge partial cache line writes to a cache memory. one embodiment provides a graphics processor comprising a graphics core, a cache coupled with the graphics core, and memory access circuitry to process memory access messages received from the graphics core. the memory access circuitry includes partial cache line write merge circuitry configured to merge a first partial write to a cache line of the cache with a second partial write to the cache line of the cache.
Inventor(s): Sven WOOP of Völklingen (DE) for intel corporation, Attila AFRA of Satu Mare (SE) for intel corporation, Carsten BENTHIN of Voelklingen (DE) for intel corporation, Ingo WALD of Salt Lake City UT (US) for intel corporation, Johannes GUENTHER of Munich (DE) for intel corporation
IPC Code(s): G06T15/00, G06T1/20, G06T15/06
Abstract: a graphics processing apparatus comprising bounding volume hierarchy (bvh) construction circuitry to perform a spatial analysis and temporal analysis related to a plurality of input primitives and responsively generate a bvh comprising spatial, temporal, and spatial-temporal components that are hierarchically arranged, wherein the spatial components include a plurality of spatial nodes with children, the spatial nodes bounding the children using spatial bounds, and the temporal components comprise temporal nodes with children, the temporal nodes bounding their children using temporal bounds and the spatial-temporal components comprise spatial-temporal nodes with children, the spatial-temporal nodes bounding their children using spatial and temporal bounds; and ray traversal/intersection circuitry to traverse a ray or a set of rays through the bvh in accordance with the spatial and temporal components.
Inventor(s): Brandon C. MARIN of Gilbert AZ (US) for intel corporation, Gang DUAN of Chandler AZ (US) for intel corporation, Srinivas V. PIETAMBARAM of Chandler AZ (US) for intel corporation, Kristof DARMAWIKARTA of Chandler AZ (US) for intel corporation, Jeremy D. ECTON of Gilbert AZ (US) for intel corporation, Suddhasattwa NAD of Chandler AZ (US) for intel corporation, Hiroki TANAKA of Gilbert AZ (US) for intel corporation, Pooya TADAYON of Portland OR (US) for intel corporation
IPC Code(s): H01L23/15, H01L23/00, H01L23/538
Abstract: embodiments disclosed herein include interposers and methods of forming interposers. in an embodiment, an interposer comprises a substrate with a first surface and a second surface opposite from the first surface, where the substrate comprises glass. in an embodiment, the interposer further comprises a cavity into the first surface of the substrate, a via through the substrate below the cavity, a first pad in the cavity over the via, and a second pad on the second surface of the substrate under the via.
Inventor(s): Abhishek A. Sharma of Hillsboro OR (US) for intel corporation, Tahir Ghani of Portland OR (US) for intel corporation, Wilfred Gomes of Portland OR (US) for intel corporation, Anand S. Murthy of Portland OR (US) for intel corporation, Pushkar Sharad Ranade of San Jose CA (US) for intel corporation, Sagar Suthram of Portland OR (US) for intel corporation
IPC Code(s): H01L23/522, H01L21/768, H01L49/02
Abstract: described herein are full wafer devices that include passive devices formed in one or more interconnect layers. interconnect layers are formed over a front side of the full wafer device. a passive device is formed using an additive process that results in a seam running through the passive device. the seam may be, for example, an air gap, a change in material structure, or a region with a different chemical makeup from the surrounding passive device. in some embodiments, the passive devices are formed in global interconnect layers coupling multiple does of the full wafer device.
Inventor(s): Abhishek A. Sharma of Hillsboro OR (US) for intel corporation, Tahir Ghani of Portland OR (US) for intel corporation, Wilfred Gomes of Portland OR (US) for intel corporation, Anand S. Murthy of Portland OR (US) for intel corporation, Sagar Suthram of Portland OR (US) for intel corporation
IPC Code(s): H01L23/528, H01L23/522
Abstract: described herein are full wafer devices that include interconnect layers on a back side of the device. the backside interconnect layers couple together different dies of the full wafer device. the backside interconnect layers include an active layer that includes active devices, such as transistors. the active devices may act as switches, e.g., to control routing of signals between different dies of the full wafer device.
Inventor(s): Abhishek A. Sharma of Hillsboro OR (US) for intel corporation, Tahir Ghani of Portland OR (US) for intel corporation, Wilfred Gomes of Portland OR (US) for intel corporation, Anand S. Murthy of Portland OR (US) for intel corporation
IPC Code(s): H01L23/528, H01L21/768, H01L23/522
Abstract: described herein are full wafer devices that include passive devices formed in a power delivery structure. power is delivered to the full wafer device on a backside of the full wafer device. a passive device in a backside layer is formed using an additive process that results in a seam running through the passive device. the seam may be, for example, an air gap, a change in material structure, or a region with a different chemical makeup from the surrounding passive device.
Inventor(s): Sanka Ganesan of Chandler AZ (US) for intel corporation, Robert L. Sankman of Phoenix AZ (US) for intel corporation, Arghya Sain of Chandler AZ (US) for intel corporation, Sri Chaitra Jyotsna Chavali of Chandler AZ (US) for intel corporation, Lijiang Wang of Chandler AZ (US) for intel corporation, Cemil Geyik of Gilbert AZ (US) for intel corporation
IPC Code(s): H01L23/538, H01L23/498
Abstract: embodiments disclosed herein include electronic packages. in an embodiment, an electronic package comprises a package substrate, wherein the package substrate comprises a first routing architecture. in an embodiment, the electronic package further comprises a first die on the package substrate, a second die on the package substrate, wherein the first die is electrically coupled to the second die by a bridge embedded in the package substrate, and a routing patch on the package substrate. in an embodiment, the routing patch is electrically coupled to the second die, and wherein the routing patch comprises a second routing architecture that is different than the first routing architecture.
Inventor(s): Bai NIE of Chandler AZ (US) for intel corporation, Gang DUAN of Chandler AZ (US) for intel corporation, Srinivas PIETAMBARAM of Chandler AZ (US) for intel corporation, Jesse JONES of Chandler AZ (US) for intel corporation, Yosuke KANAOKA of Chandler AZ (US) for intel corporation, Hongxia FENG of Chandler AZ (US) for intel corporation, Dingying XU of Chandler AZ (US) for intel corporation, Rahul MANEPALLI of Chandler AZ (US) for intel corporation, Sameer PAITAL of Chandler AZ (US) for intel corporation, Kristof DARMAWIKARTA of Chandler AZ (US) for intel corporation, Yonggang LI of Chandler AZ (US) for intel corporation, Meizi JIAO of Chandler AZ (US) for intel corporation, Chong ZHANG of Chandler AZ (US) for intel corporation, Matthew TINGEY of Hillsboro OR (US) for intel corporation, Jung Kyu HAN of Chandler AZ (US) for intel corporation, Haobo CHEN of Gilbert AZ (US) for intel corporation
IPC Code(s): H01L23/538, H01L21/48, H01L21/56, H01L21/78, H01L23/00, H01L23/31
Abstract: a die assembly is disclosed. the die assembly includes a die, one or more die pads on a first surface of the die and a die attach film on the die where the die attach film includes one or more openings that expose the one or more die pads and that extend to one or more edges of the die.
20240088069.INTEGRATED CIRCUIT SUPPORTS WITH MICROSTRIPS_simplified_abstract_(intel corporation)
Inventor(s): Wenzhi Wang of Shanghai (CN) for intel corporation, Xiaoning Ye of Portland OR (US) for intel corporation, Yunhui Chu of Hillsboro OR (US) for intel corporation, Chunfei Ye of Lacey WA (US) for intel corporation, James A. McCall of Portland OR (US) for intel corporation
IPC Code(s): H01L23/66, H01L23/498, H01L23/538, H01L25/18, H10B80/00
Abstract: disclosed herein are integrated circuit (ic) supports with microstrips, and related embodiments. for example, an ic support may include a plurality of microstrips and a plurality of conductive segments. individual ones of the conductive segments may be at least partially over at least two microstrips, a dielectric material may be between the plurality of microstrips and the plurality of conductive segments, and the conductive segments are included in a tape.
Inventor(s): Srinivas PIETAMBARAM of Gilbert AZ (US) for intel corporation, Robert Alan MAY of Chandler AZ (US) for intel corporation, Kristof DARMAWIKARTA of Chandler AZ (US) for intel corporation, Hiroki TANAKA of Chandler AZ (US) for intel corporation, Rahul N. MANEPALLI of Chandler AZ (US) for intel corporation, Sri Ranga Sai BOYAPATI of Chandler AZ (US) for intel corporation
IPC Code(s): H01L25/00, H01L21/48, H01L23/498, H01L23/538, H01L25/065
Abstract: techniques for a patch to couple one or more surface dies to an interposer or motherboard are provided. in an example, the patch can include multiple embedded dies. in an example, a microelectronic device can be formed to include a patch on an interposer, where the patch can include multiple embedded dies and each die can have a different thickness.
20240088131.DIODES WITH BACKSIDE CONTACT_simplified_abstract_(intel corporation)
Inventor(s): Nicholas A. Thomson of Hillsboro OR (US) for intel corporation, Kalyan C. Kolluru of Portland OR (US) for intel corporation, Ayan Kar of Portland OR (US) for intel corporation, Mauro J. Kobrinsky of Portland OR (US) for intel corporation
IPC Code(s): H01L27/02, H01L29/06, H01L29/861
Abstract: an integrated circuit structure includes a sub-fin having at least a portion that is doped with a first type of dopant, and a diffusion region doped with a second type of dopant. the diffusion region is in contact with the sub-fin and extends upward from the sub-fin. the first type of dopant is one of a p-type or an n-type dopant, and the second type of dopant is the other of the p-type or the n-type dopant. in an example, a first conductive contact is above and on the diffusion region, and a second conductive contact is in contact with the portion of the sub-fin. in an example, the diffusion region is at least a part of one of an anode or a cathode of a diode, and the portion of the sub-fin is at least a part of the other of the anode or the cathode of the diode.
20240088132.WIDE CHANNEL DIODE STRUCTURE INCLUDING SUB-FIN_simplified_abstract_(intel corporation)
Inventor(s): Nicholas A. Thomson of Hillsboro OR (US) for intel corporation, Kalyan C. Kolluru of Portland OR (US) for intel corporation, Ayan Kar of Portland OR (US) for intel corporation, Chu-Hsin Liang of Santa Cruz CA (US) for intel corporation, Benjamin Orr of Beaverton OR (US) for intel corporation, Biswajeet Guha of Hillsboro OR (US) for intel corporation, Brian Greene of Portland OR (US) for intel corporation, Chung-Hsun Lin of Portland OR (US) for intel corporation, Sabih U. Omar of Hillsboro OR (US) for intel corporation, Sameer Jayanta Joglekar of Beaverton OR (US) for intel corporation
IPC Code(s): H01L27/02, H01L29/06, H01L29/861
Abstract: an integrated circuit structure includes a sub-fin having (i) a first portion including a p-type dopant and (ii) a second portion including an n-type dopant. a first body of semiconductor material is above the first portion of the sub-fin, and a second body of semiconductor material is above the second portion of the sub-fin. in an example, the first portion of the sub-fin and the second portion of the sub-fin are in contact with each other, to form a pn junction of a diode. for example, the first portion of the sub-fin is part of an anode of the diode, and wherein the second portion of the sub-fin is part of a cathode of the diode.
20240088133.TRANSISTOR DEVICES WITH INTEGRATED DIODES_simplified_abstract_(intel corporation)
Inventor(s): Nicholas A. Thomson of Hillsboro OR (US) for intel corporation, Ayan Kar of Portland OR (US) for intel corporation, Kalyan C. Kolluru of Portland OR (US) for intel corporation, Mauro J. Kobrinksy of Portland OR (US) for intel corporation, Benjamin Orr of Beaverton OR (US) for intel corporation
IPC Code(s): H01L27/02, H01L23/528, H01L29/06, H01L29/861
Abstract: an integrated circuit structure includes a sub-fin having a first type of dopant, a first diffusion region having the first type of dopant and in contact with the sub-fin, and a second diffusion region and a third diffusion region having a second type of dopant and in contact with the sub-fin. the first type of dopant is one of p-type or n-type dopant, and where the second type of dopant is the other of the p-type or n-type dopant. a first body of semiconductor material extends from the second diffusion region to the third diffusion region, and a second body of semiconductor material extends from the first diffusion region towards the second diffusion region. the first diffusion region is a tap diffusion region contacting the sub-fin. in an example, the first diffusion region facilitates formation of a diode for electrostatic discharge (esd) protection of the integrated circuit structure.
20240088134.TARGETED SUB-FIN ETCH DEPTH_simplified_abstract_(intel corporation)
Inventor(s): Nicholas A. Thomson of Hillsboro OR (US) for intel corporation, Ayan Kar of Portland OR (US) for intel corporation, Kalyan C. Kolluru of Portland OR (US) for intel corporation, Mauro J. Kobrinsky of Portland OR (US) for intel corporation
IPC Code(s): H01L27/02, H01L21/8234
Abstract: an integrated circuit structure includes laterally adjacent first and second devices. the first device has (i) a first diffusion region, (ii) a first body including semiconductor material extending laterally from the first diffusion region, and (iii) a first gate structure on the first body. the first diffusion region has a first lower section that extends below a lower surface of the first gate structure, the first lower section having a first height. the second device has (i) a second diffusion region, (ii) a second body including semiconductor material extending laterally from the second diffusion region, and (iii) a second gate structure on the second body. the second diffusion region has a second lower section that extends below a lower surface of the second gate structure, the second lower section having a second height. in an example, the first height is at least 2 nanometers greater than the second height.
20240088136.TRANSISTOR DEVICES WITH EXTENDED DRAIN_simplified_abstract_(intel corporation)
Inventor(s): Ayan Kar of Portland OR (US) for intel corporation, Nicholas A. Thomson of Hillsboro OR (US) for intel corporation, Kalyan C. Kolluru of Portland OR (US) for intel corporation, Benjamin Orr of Beaverton OR (US) for intel corporation
IPC Code(s): H01L27/02
Abstract: an integrated circuit structure includes a sub-fin, a source region in contact with a first portion of the sub-fin, and a drain region in contact with a second portion of the sub-fin. a body including semiconductor material is above the sub-fin, where the body extends laterally between the source region and the drain region. a gate structure is on the body and includes (i) a gate electrode, and (ii) a gate dielectric between the gate electrode and the body. in an example, a first distance between the drain region and the gate electrode is at least two times a second distance between the source region and the gate electrode, where the first and second distances are measured in a same horizontal plane that runs in a direction parallel to the body. in an example, the body is a nanoribbon, a nanosheet, a nanowire, or a fin.
Inventor(s): Leonard P. GULER of Hillsboro OR (US) for intel corporation, Biswajeet GUHA of Hillsboro OR (US) for intel corporation, Tahir GHANI of Portland OR (US) for intel corporation, Swaminathan SIVAKUMAR of Beaverton OR (US) for intel corporation
IPC Code(s): H01L27/088, H01L21/8234, H01L29/06, H01L29/08, H01L29/423, H01L29/66, H01L29/78
Abstract: neighboring gate-all-around integrated circuit structures having disjoined epitaxial source or drain regions, and methods of fabricating neighboring gate-all-around integrated circuit structures having disjoined epitaxial source or drain regions, are described. for example, a structure includes first and second vertical arrangements of nanowires, the nanowires of the second vertical arrangement of nanowires having a horizontal width greater than a horizontal width of the nanowires of the first vertical arrangement of nanowires. first and second gate stacks are over the first and second vertical arrangements of nanowires, respectively. first epitaxial source or drain structures are at ends of the first vertical arrangement of nanowires, and second epitaxial source or drain structures are at ends of the second vertical arrangement of nanowires. an intervening dielectric structure is between neighboring ones of the first epitaxial source or drain structures and of the second epitaxial source or drain structures.
Inventor(s): Szuya S. Liao of Portland OR (US) for intel corporation, Scott B. CLENDENNING of Portland OR (US) for intel corporation, Jessica TORRES of Portland OR (US) for intel corporation, Lukas BAUMGARTEL of Portland OR (US) for intel corporation, Kiran CHIKKADI of Hillsboro OR (US) for intel corporation, Diane LANCASTER of Hillsboro OR (US) for intel corporation, Matthew V. METZ of Portland OR (US) for intel corporation, Florian GSTREIN of Portland OR (US) for intel corporation, Martin M. MITAN of Beaverton OR (US) for intel corporation, Rami HOURANI of Beaverton OR (US) for intel corporation
IPC Code(s): H01L27/088, H01L21/762, H01L21/8234, H01L21/8238, H01L23/538, H01L27/092
Abstract: self-aligned gate endcap (sage) architectures without fin end gaps, and methods of fabricating self-aligned gate endcap (sage) architectures without fin end gaps, are described. in an example, an integrated circuit structure includes a semiconductor fin having a cut along a length of the semiconductor fin. a gate endcap isolation structure has a first portion parallel with the length of the semiconductor fin and is spaced apart from the semiconductor fin. the gate endcap isolation structure also has a second portion in a location of the cut of the semiconductor fin and in contact with the semiconductor fin.
Inventor(s): Nicole THOMAS of Portland OR (US) for intel corporation, Ehren MANNEBACH of Beaverton OR (US) for intel corporation, Cheng-Ying HUANG of Portland OR (US) for intel corporation, Marko RADOSAVLJEVIC of Portland OR (US) for intel corporation
IPC Code(s): H01L27/092, H01L21/02, H01L21/8238, H01L29/06, H01L29/417, H01L29/423, H01L29/66, H01L29/786
Abstract: gate-all-around integrated circuit structures having depopulated channel structures, and methods of fabricating gate-all-around integrated circuit structures having depopulated channel structures using a selective bottom-up approach, are described. for example, an integrated circuit structure includes a vertical arrangement of nanowires above a substrate. the vertical arrangement of nanowires has one or more active nanowires above one or more oxide nanowires. a first gate stack is over and around the one or more active nanowires. a second gate stack is over and around the one or more oxide nanowires.
20240088199.TECHNOLOGIES FOR GLASS CORE INDUCTOR_simplified_abstract_(intel corporation)
Inventor(s): Brandon Christian Marin of Gilbert AZ (US) for intel corporation, Suddhasattwa Nad of Chandler AZ (US) for intel corporation, Srinivas V. Pietambaram of Chandler AZ (US) for intel corporation, Jeremy D. Ecton of Gilbert AZ (US) for intel corporation, Mohammad Rahman of Gilbert AZ (US) for intel corporation, Gang Duan of Chandler AZ (US) for intel corporation
IPC Code(s): H01L49/02, H01F27/29, H01L23/498, H01L25/065, H01L25/16, H01L25/18
Abstract: techniques for a glass core inductor are disclosed. in the illustrative embodiment, an integrated circuit component includes a glass substrate and a fully-integrated voltage regulator (fivr). the fivr includes a glass core inductor that is embedded in the glass substrate. each inductor turn of the inductor includes two angled through-glass vias and a trace on top of the glass substrate connecting the angled through-glass vias, resulting in an inductor with a cross-section in the shape of a triangle or trapezoid. the inductor may have a relatively large inductance per unit area, requiring less space or allowing for a larger inductance.
20240088217.BARRIER LAYER FOR DIELECTRIC RECESS MITIGATION_simplified_abstract_(intel corporation)
Inventor(s): Tao Chu of Portland OR (US) for intel corporation, Minwoo Jang of Portland OR (US) for intel corporation, Chia-Ching Lin of Portland OR (US) for intel corporation, Yanbin Luo of Portland OR (US) for intel corporation, Ting-Hsiang Hung of Beaverton OR (US) for intel corporation, Feng Zhang of Hillsboro OR (US) for intel corporation, Guowei Xu of Portland OR (US) for intel corporation
IPC Code(s): H01L29/06, H01L21/762, H01L29/78
Abstract: techniques are provided herein to form semiconductor devices that include a layer across an upper surface of a dielectric fill between devices and configured to prevent or otherwise reduce recessing of the dielectric fill. in this manner, the layer may be referred to as a barrier layer or recess-inhibiting layer. the semiconductor regions of the devices extend above a subfin region that may be native to the substrate. these subfin regions are separated from one another using a dielectric fill that acts as a shallow trench isolation (sti) structure to electrically isolate devices from one another. a barrier layer is formed over the dielectric fill early in the fabrication process to prevent or otherwise reduce the dielectric fill from recessing during subsequent processing. the layer may include oxygen and a metal, such as aluminum.
Inventor(s): Shao-Ming Koh of Tigard OR (US) for intel corporation, Leonard P. Guler of Hillsboro OR (US) for intel corporation, Gurpreet Singh of Beaverton OR (US) for intel corporation, Manish Chandhok of Beaverton OR (US) for intel corporation, Matthew J. Prince of Portland OR (US) for intel corporation
IPC Code(s): H01L29/06, H01L21/8234, H01L27/088, H01L29/08, H01L29/778, H01L29/786
Abstract: techniques are provided herein to form an integrated circuit having a grating pattern of gate cut structures such that a gate cut structure extends between the gate layers of adjacent semiconductor devices and between the source or drain regions (e.g., epitaxial regions) of the adjacent semiconductor devices. in an example, neighboring semiconductor devices each include a semiconductor region extending between a source region and a drain region, and a gate structure extending over the semiconductor regions of the neighboring semiconductor devices. in some such examples, a gate cut structure is present between each pair of neighboring semiconductor devices thus interrupting the gate structure and isolating the gate electrode of one semiconductor device from the gate electrode of the other semiconductor device. the gate cut structure further extends to separate the source or drain regions of the neighboring semiconductor devices. subsequent processes allow neighboring gate or source or drain regions connections.
Inventor(s): Tanuj TRIVEDI of Hillsboro OR (US) for intel corporation, Rahul RAMASWAMY of Portland OR (US) for intel corporation, Jeong Dong KIM of Scappoose OR (US) for intel corporation, Babak FALLAHAZAD of Portland OR (US) for intel corporation, Hsu-Yu CHANG of Hillsboro OR (US) for intel corporation, Ting CHANG of Portland OR (US) for intel corporation, Nidhi NIDHI of Hillsboro OR (US) for intel corporation, Walid M. HAFEZ of Portland OR (US) for intel corporation
IPC Code(s): H01L29/423, H01L21/02, H01L29/06, H01L29/10, H01L29/165, H01L29/66
Abstract: gate-all-around integrated circuit structures having dual nanowire/nanoribbon channel structures, and methods of fabricating gate-all-around integrated circuit structures having dual nanowire/nanoribbon channel structures, are described. for example, an integrated circuit structure includes a first vertical arrangement of nanowires above a substrate. a dielectric cap is over the first vertical arrangement of nanowires. a second vertical arrangement of nanowires is above the substrate. individual ones of the second vertical arrangement of nanowires are laterally staggered with individual ones of the first vertical arrangement of nanowires and the dielectric cap.
Inventor(s): Aaron D. Lilak of Beaverton OR (US) for intel corporation, Rishabh MEHANDRU of Portland OR (US) for intel corporation, Cory WEBER of Hillsboro OR (US) for intel corporation, Willy RACHMADY of Beaverton OR (US) for intel corporation, Varun MISHRA of Hillsboro OR (US) for intel corporation
IPC Code(s): H01L29/423, H01L21/02, H01L21/8234, H01L29/06, H01L29/08, H01L29/10, H01L29/165, H01L29/66, H01L29/78, H01L29/786
Abstract: gate-all-around integrated circuit structures having an insulator fin on an insulator substrate, and methods of fabricating gate-all-around integrated circuit structures having an insulator fin on an insulator substrate, are described. for example, an integrated circuit structure includes an insulator fin on an insulator substrate. a vertical arrangement of horizontal semiconductor nanowires is over the insulator fin. a gate stack surrounds a channel region of the vertical arrangement of horizontal semiconductor nanowires, and the gate stack is overlying the insulator fin. a pair of epitaxial source or drain structures is at first and second ends of the vertical arrangement of horizontal semiconductor nanowires and at first and second ends of the insulator fin.
Inventor(s): Tao Chu of Portland OR (US) for intel corporation, Guowei Xu of Portland OR (US) for intel corporation, Feng Zhang of Hillsboro OR (US) for intel corporation, Ting-Hsiang Hung of Beaverton OR (US) for intel corporation, Chia-Ching Lin of Portland OR (US) for intel corporation
IPC Code(s): H01L29/66, H01L29/06, H01L29/786
Abstract: techniques are provided herein to form semiconductor devices having epitaxial growth laterally extending between inner spacer structures to mitigate issues caused by the inner spacer structures either being too thick or too thin. a directional etch is performed along the side of a multilayer fin to create a relatively narrow opening for a source or drain region to increase the usable fin space for forming the inner spacer structures. after the inner spacer structures are formed around ends of the semiconductor layers within the fin, the exposed ends of the semiconductor layers are laterally recessed inwards from the outermost sidewalls of the inner spacer structures. accordingly, the epitaxial source or drain region is grown from the recessed semiconductor ends and thus fills in the recessed regions between the spacer structures.
Inventor(s): Tao CHU of Portland OR (US) for intel corporation, Feng ZHANG of Hillsboro OR (US) for intel corporation, Minwoo JANG of Portland OR (US) for intel corporation, Yanbin LUO of Portland OR (US) for intel corporation, Chia-Ching LIN of Portland OR (US) for intel corporation, Ting-Hsiang HUNG of Beaverton OR (US) for intel corporation
IPC Code(s): H01L29/78, H01L27/11
Abstract: fin trim plug structures with metal for imparting channel stress are described. in an example, an integrated circuit structure includes a fin including silicon, the fin having a top and sidewalls, wherein the top has a longest dimension along a direction. a first isolation structure is over a first end of the fin. a gate structure including a gate electrode is over the top of and laterally adjacent to the sidewalls of a region of the fin. the gate structure is spaced apart from the first isolation structure along the direction. a second isolation structure is over a second end of the fin, the second end opposite the first end, the second isolation structure spaced apart from the gate structure along the direction. the first isolation structure and the second isolation structure both include a dielectric material laterally surrounding an isolated metal structure.
Inventor(s): Erica J. THOMPSON of Beaverton OR (US) for intel corporation, Aditya Kasukurti of Hillsboro OR (US) for intel corporation, Jun Sung Kang of Portland OR (US) for intel corporation, Kai Loon Cheong of Beaverton OR (US) for intel corporation, Biswajeet Guha of Hillsboro OR (US) for intel corporation, William Hsu of Hillsboro OR (US) for intel corporation, Bruce Beattie of Portland OR (US) for intel corporation
IPC Code(s): H01L29/78, H01L29/06, H01L29/10, H01L29/66
Abstract: a nanowire device includes one or more nanowire having a first end portion, a second end portion, and a body portion between the first end portion and the second end portion. a first conductive structure is in contact with the first end portion and a second conductive structure is in contact with the second end portion. the body portion of the nanowire has a first cross-sectional shape and the first end portion has a second cross-sectional shape different from the first cross-sectional shape. integrated circuits including the nanowire device and a method of cleaning a semiconductor structure are also disclosed.
Inventor(s): Naoki Matsumura of San Jose CA (US) for intel corporation, Colin Carver of Hillsboro OR (US) for intel corporation, Tod Schiff of Portland OR (US) for intel corporation
IPC Code(s): H02J7/00, G01R31/389
Abstract: a constant voltage may be used during battery charging to reduce or avoid the formation of a dendrite, such as a stepped constant voltage. for each charging period, each level of the stepped constant voltage may be calculated to ensure a corresponding current level within each period remains below a safe current limit. a voltage transition between any two periods may occur in response to expiration of a predetermined time, or in response to a determination that the current level has fallen below a lower current limit. a current level during each period may be maintained such that the battery heat is maintained below a reference heat level, which may increase battery cycle life (e.g., battery capacity or maximum recharging cycles). the battery heat may be measured directly or indirectly, or may be estimated based on other measured or controlled values.
20240088887.TRANSISTOR OVER-VOLTAGE PROTECTION_simplified_abstract_(intel corporation)
Inventor(s): Dharmaray Nedalgi of Bangalore (IN) for intel corporation, Lavanya Manohar Nirikhi of Bangalore (IN) for intel corporation
IPC Code(s): H03K17/082
Abstract: an apparatus comprises a first supply node to provide a first voltage and a second supply node to provide a second voltage lower than the first voltage. first and second transistors, of a first conductivity type, are coupled in series at a first common node, wherein the first transistor is coupled to the first supply node, and the second transistor is coupled to an output node. third and fourth transistors, of a second conductivity type, coupled in series at a second common node, wherein the fourth transistor is coupled to a third node that is to provide a third voltage, and the third transistor is coupled to the output node. first impedance circuitry is coupled to a gate terminal of the second transistor, the second supply node, and to a gate terminal of the first transistor.
20240089082.PRIVACY PRESERVING DIGITAL PERSONAL ASSISTANT_simplified_abstract_(intel corporation)
Inventor(s): Jeremy Bottleson of North Plains OR (US) for intel corporation, Ernesto Zamora Ramos of Folsom CA (US) for intel corporation, Kylan Race of Austin TX (US) for intel corporation, Fillipe Dias Moreira de Souza of Folsom CA (US) for intel corporation, Hubert de Lassus of Folsom CA (US) for intel corporation, Jingyi Jin of San Jose CA (US) for intel corporation
IPC Code(s): H04L9/00, G10L15/26, H04L9/08
Abstract: a method comprises receiving, from an input device, an input speech signal, encoding the input speech signal to generate a first homomorphically encrypted string, sending the homomorphically encrypted string to a remote device via communication link, receiving, from the remote device, a reply comprising a second homomorphically encrypted string, decoding the second homomorphically encrypted string into an output speech signal, and outputting the output speech signal on an audio output device.
Inventor(s): Kylan Race of Austin TX (US) for intel corporation, Ernesto Zamora Ramos of Folsom CA (US) for intel corporation, Jeremy Bottleson of North Plains OR (US) for intel corporation, Jingyi Jin of San Jose CA (US) for intel corporation
IPC Code(s): H04L9/00, H04L9/06
Abstract: a method comprises receiving, from a remote device, a first encrypted data set encrypted using a first encryption scheme, performing a set of computations on the first encrypted data set to generate a first set of encrypted results, encrypting the first set of encrypted results using a second encryption scheme to generate a second set of encrypted results, sending the second set of encrypted results to the remote device, receiving, from the remote device, third set of encrypted results in which the first encryption scheme has been decrypted, and generating a set of decrypted results by applying a decryption algorithm to the third set of encrypted results to decrypt the second encryption scheme.
Inventor(s): Patrick CONNOR of Beaverton OR (US) for intel corporation, Andrey CHILIKIN of Limerick (IE) for intel corporation, Brendan RYAN of Limerick (IE) for intel corporation, Chris MACNAMARA of Limerick (IE) for intel corporation, John J. BROWNE of Limerick (IE) for intel corporation, Krishnamurthy JAMBUR SATHYANARAYANA of Limerick (IE) for intel corporation, Stephen DOYLE of Ennis (IE) for intel corporation, Tomasz KANTECKI of Ennis (IE) for intel corporation, Anthony KELLY of Limerick (IE) for intel corporation, Ciara LOFTUS of Tuam (IE) for intel corporation, Fiona TRAHE of Ennis (IE) for intel corporation
IPC Code(s): H04L47/125, G06F8/76, G06F9/455, H04L43/0817, H04L47/2441
Abstract: a computing device includes an appliance status table to store at least one of reliability and performance data for one or more network functions virtualization (nfv) appliances and one or more legacy network appliances. the computing device includes a load controller to configure an internet protocol (ip) filter rule to select a packet for which processing of the packet is to be migrated from a selected one of the one or more legacy network appliances to a selected one of the one or more nfv appliances, and to update the appliance status table with received at least one of reliability and performance data for the one or more legacy network appliances and the one or more nfv appliances. the computing device includes a packet distributor to receive the packet, to select one of the one or more nfv appliances based at least in part on the appliance status table, and to send the packet to the selected nfv appliance. other embodiments are described herein.
20240089219.PACKET BUFFERING TECHNOLOGIES_simplified_abstract_(intel corporation)
Inventor(s): Md Ashiqur RAHMAN of Phoenix AZ (US) for intel corporation, Roberto PENARANDA CEBRIAN of Santa Clara CA (US) for intel corporation, Anil VASUDEVAN of Portland OR (US) for intel corporation, Allister ALEMANIA of North Plains OR (US) for intel corporation, Pedro YEBENES SEGURA of San Jose CA (US) for intel corporation
IPC Code(s): H04L49/20, H04L47/62, H04L49/90
Abstract: examples described herein relate to a switch. in some examples, the switch includes circuitry that is configured to: based on receipt of a packet and a level of a first queue, select among a first memory and a second memory device among multiple second memory devices to store the packet, based on selection of the first memory, store the packet in the first memory, and based on selection of the second memory device among multiple second memory devices, store the packet into the selected second memory device. in some examples, the packet is associated with an ingress port and an egress port, and the selected second memory device is associated with a third port that is different than the ingress port or the egress port associated with the packet.
Inventor(s): Utkarsh Y. KAKAIYA of Folsom CA (US) for intel corporation
IPC Code(s): H04L9/40, G06F21/53, H04L9/32
Abstract: examples include techniques for a trusted execution environment (tee) at a compute server to request a service to be performed by an accelerator that is located at or with a service server. examples are described of the tee at the compute server authenticating the remote accelerator to enable establishment of one or more secure communication sessions for the accelerator to decrypt encrypted data, perform a transformation on the decrypted data and then re-encrypt the transformed data. examples are also described of the tee at the compute server authenticating a service tee at the service server as well as the accelerator to enable the service tee and the accelerator to collaboratively decrypt encrypted data, perform a transformation on the decrypted data and then re-encrypt the transformed data.
Inventor(s): Avinash Kumar of Karnataka (IN) for intel corporation
IPC Code(s): H04N23/695, G06V10/44, G06V10/74
Abstract: multi-camera dynamic calibration can be performed using three or more images, each from a separate camera viewing the same 3d scene. multi-camera translation magnitude can be determined by incorporating information from an additional image. a relative translation scale is determined for a configuration of three cameras using a ratio of translation magnitudes. the translation scale can be expanded to configurations having more than three cameras using the relative scale of the pair-wise camera translations to determine translation scales for a multi-camera set-up. if the ground-truth translation is known for a pair of cameras, then the translation magnitude can be determined for all pairs of cameras to ground-truth accuracy. multi-camera scale estimation is divided into smaller overlapping triplet-camera scale estimation, and the translation scale determination corresponding to each image pair is applied iteratively to overlapping sets of three images. the estimates can be merged by linearly aligning overlapping sets of estimates.
20240089715.BLUETOOTH REPORT EVENTS FOR ULTRA LOW LATENCY_simplified_abstract_(intel corporation)
Inventor(s): Oren HAGGAI of Kefar Sava (IL) for intel corporation, Yashodhara DEVADIGA of San Diego CA (US) for intel corporation, Nir Yizhak BALABAN of Kfar Netter (IL) for intel corporation, Prasanna DESAI of Elfin Forest CA (US) for intel corporation
IPC Code(s): H04W4/80
Abstract: the present disclosure relates to a method of managing a data transmission from a second device to a first device, the method including: determining a reference time point for the data transmission from the second device to the first device; determining a time offset associated with the second device, wherein the reference time point and the time offset define a starting time point for the second device to start the data transmission; and carrying out the data transmission from the second device to the first device in accordance with the starting time point, wherein the data transmission includes transmitting isochronous data from the second device to the first device.
Inventor(s): Laurent Cariou of Milizac (FR) for intel corporation, Thomas J. Kenney of Portland OR (US) for intel corporation, Dmitry Akhmetov of Hillsboro OR (US) for intel corporation, Dibakar Das of Hillsboro OR (US) for intel corporation
IPC Code(s): H04W74/08
Abstract: for example, an access point (ap) may be configured to transmit a frame including a prioritized-access enabled/disabled field to indicate whether a prioritized-access contention mechanism is to be enabled or disabled over a wireless medium. for example, the prioritized-access contention mechanism may be configured to allow a prioritized station (sta) to transmit a reservation signal over the wireless medium at a reservation signal transmission time, and to contend the wireless medium according to a high-priority contention policy to obtain a transmit opportunity (txop) after transmission of the reservation signal. for example, the reservation signal transmission time may be based on an end of a predefined time duration from a start of a contention period. for example, the reservation signal may be configured to indicate a busy clear channel assessment (cca) to a receiving sta.
- Intel Corporation
- G06F1/3296
- G06F9/52
- Intel corporation
- G01R19/25
- H03K5/24
- H03K19/20
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- H03L7/095
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