Intel Corporation patent applications on June 6th, 2024
Patent Applications by Intel Corporation on June 6th, 2024
Intel Corporation: 65 patent applications
Intel Corporation has applied for patents in the areas of H01L23/00 (11), H01L23/498 (7), H01L21/48 (7), H04W72/232 (6), H04L5/00 (6)
With keywords such as: layer, data, structure, substrate, device, apparatus, based, semiconductor, core, and structures in patent application abstracts.
Patent Applications by Intel Corporation
20240181572.DRY METHOD FOR METAL-DEFINED PAD FORMATION_simplified_abstract_(intel corporation)
Inventor(s): Tchefor NDUKUM of Chandler AZ (US) for intel corporation, Deniz TURAN of Chandler AZ (US) for intel corporation, Yonggang LI of Chandler AZ (US) for intel corporation
IPC Code(s): B23K26/40, B23K26/0622, B23K26/082
Abstract: the present disclosure generally relates to a method. the method may include providing a substrate and forming a seed layer on the substrate. the method may further include forming a first metal layer on selected portions of the seed layer to form exposed portions of the seed layer. the method may also include scanning a laser beam across the substrate to remove the exposed portions of the seed layer to form exposed portions of the substrate.
Inventor(s): Vikrant Thigle of Bangalore (IN) for intel corporation, Vijay Anand Mathiyalagan of Austin TX (US) for intel corporation, Anand Haridass of Bangalore (IN) for intel corporation, Arun Chandrasekhar of Bangalore (IN) for intel corporation, Gerald Pasdast of San Jose CA (US) for intel corporation
IPC Code(s): G01R19/00, G01R19/25, G05F1/46
Abstract: embodiments herein relate to a chiplet or other die which includes multiple sense points within the die and components for digitizing and outputting sensed voltages of the sense points. in one approach, an analog-to-digital converter (adc) is coupled to each sense point, and a multiplexer is coupled to the outputs of the adcs. a select signal for the multiplexer can be received from an external control unit which selects one of the sense points based on information such as a current workflow of the die. the selected sense point can change as the workflow changes. the optimal sense point can be determined by comparing the voltage of each sense point and selecting the sense point with the lowest voltage. the sensed voltage is provided to a voltage regulator as a feedback signal to optimize control of the power supply of the die.
20240184048.OPTICAL MODE CONVERTOR_simplified_abstract_(intel corporation)
Inventor(s): Harel Frish of Albuquerque NM (US) for intel corporation, Pegah Seddighian of San Jose CA (US) for intel corporation, Kelly Magruder of Albuquerque NM (US) for intel corporation, Olufemi Dosunmu of San Jose CA (US) for intel corporation
IPC Code(s): G02B6/14, G02B6/122
Abstract: embodiments relate to an apparatus that includes: an input stage with an input si slab height, an input si waveguide height, and an input height difference between the input si slab height and the input si waveguide height; an output stage with an output si slab height that is different from the input si slab height, an output si waveguide height that is different from the input si waveguide height, and an output height difference between the output si slab height and the output si waveguide height that is different from the input height difference; and a transition stage positioned between the input stage and the output stage, wherein the transition stage has a transition si slab height, a transition si waveguide height, and a transition height difference between the transition si slab height and the transition si waveguide height. other embodiments may be described and/or claimed.
Inventor(s): Nicholas D. PSAILA of Livingston (GB) for intel corporation, Richard LAMING of Livingston (GB) for intel corporation
IPC Code(s): G02B6/36, G02B6/42
Abstract: an apparatus for positioning one or more optical fibers relative to the apparatus, comprises a body comprising material, and one or more fiber alignment structures defined in the material of the body. each fiber alignment structure comprises a groove and a corresponding passage. the groove and the corresponding passage are arranged end-to-end. each fiber alignment structure is configured to accommodate a corresponding optical fiber extending along the groove and the corresponding passage. the groove of each fiber alignment structure may serve or help to guide an end of a corresponding fiber into the corresponding passage during assembly. the groove of each fiber alignment structure may help to support the end of the corresponding optical fiber. the groove of each fiber alignment structure can assist with maintaining a position of the corresponding optical fiber when ribbonised or non-ribbonised optical fiber is used.
20240184064.OPTICAL FIBER POSITIONING APPARATUS_simplified_abstract_(intel corporation)
Inventor(s): Richard Laming of Livingston (GB) for intel corporation, Nicholas D. Psaila of Lanark (GB) for intel corporation
IPC Code(s): G02B6/42
Abstract: an apparatus for positioning one or more optical fibers relative to the apparatus, comprises a body comprising material, and one or more fiber alignment structures defined in the material of the body, wherein each fiber alignment structure is configured to accommodate a corresponding optical fiber, and wherein each fiber alignment structure is configured to induce one or more bends along the corresponding optical fiber. when an optical fiber is located in such a fiber alignment structure, the optical fiber may be forced into contact with the fiber alignment structure in one or more known regions so that the corresponding optical fiber is located at a more predictable position relative to the corresponding fiber alignment structure in the one or more known regions than is the case for known fiber alignment structures. the location of the corresponding optical fiber at a more predictable position may improve the optical coupling efficiency achievable between the optical fiber and an optical component and/or a photonic chip.
Inventor(s): Changhua LIU of Chandler AZ (US) for intel corporation, Bai NIE of Chandler AZ (US) for intel corporation, Robert MAY of Chandler AZ (US) for intel corporation
IPC Code(s): G03F7/20, G03F7/00
Abstract: the present disclosure is directed to a lithographic patterning system including a stage for supporting a substrate with a photo-definable polymer layer, a first actinic radiation source, which is configured to propagate light along a first optical axis, a first mask for patterning the propagated light from the first actinic radiation source, a second actinic radiation source, which is configured to propagate light along a second optical axis, and a second mask for patterning the propagated light from the second actinic radiation source. in a method, first and second propagated lights form an intersection in the photo-definable polymer layer, and a patterned semiconductor component is formed at the intersection.
Inventor(s): Mohammad Mamunur RAHMAN of Gilbert AZ (US) for intel corporation, Omesh TICKOO of Portland OR (US) for intel corporation, Nilesh AHUJA of Cupertino CA (US) for intel corporation, Ergin U GENC of Portland OR (US) for intel corporation, Julianne TROIANO of Scottsdale AZ (US) for intel corporation, Ibrahima NDIOUR of Portland OR (US) for intel corporation
IPC Code(s): G05B19/418
Abstract: a method for identifying a tool anomaly of an printed circuit board (pcb) manufacturing process comprising a plurality of phases, the method comprising the steps of: obtaining image data of at least one tool of the pcb manufacturing process; inputting the image data to a machine learning module, the machine learning module configured to perform the following steps: extracting, from the image data, a tool feature image data of the at least one tool; classifying the image data into a phase of the plurality of phases; and determining, based on the classified image data and the tool feature image data, an anomaly state of the at least one tool.
Inventor(s): Bin Wang of Beijing (CN) for intel corporation, Bo Peng of Beijing (CN) for intel corporation, Xiaoyun Wang of Beijing (CN) for intel corporation
IPC Code(s): G06F7/49
Abstract: methods, apparatus, systems, and articles of manufacture are disclosed for mixed radix fast fourier transform (fft) calculations of graphics processing units (gpus). an example apparatus disclosed herein includes at least one memory, machine readable instructions in the apparatus, and at least one processor circuitry to execute the machine readable instructions to at least factorize input data to identify one or more radix-r blocks for the parallel mixed radix calculation, perform at least one of a decimal-to-base or a base-to-base conversion of the input data prior to a bit reverse routine, the bit reverse routine to yield an output data set, cause a lookup table to be loaded into a memory structure based on a lookup table length, the lookup table populated with the output data set, and perform the parallel mixed radix calculation of the one or more radix-r blocks using the lookup table loaded into the memory structure.
Inventor(s): Himanshu Kaul of Portland OR (US) for intel corporation, Mark A. Anders of Hillsboro OR (US) for intel corporation, Sanu K. Mathew of Hillsboro OR (US) for intel corporation, Anbang Yao of Beijing (CN) for intel corporation, Joydeep Ray of Folsom CA (US) for intel corporation, Ping T. Tang of Edison NJ (US) for intel corporation, Michael S. Strickland of Sunnyvale CA (US) for intel corporation, Xiaoming Chen of Shanghai (CN) for intel corporation, Tatiana Shpeisman of Menlo Park CA (US) for intel corporation, Abhishek R. Appu of El Dorado Hills CA (US) for intel corporation, Altug Koker of El Dorado Hills CA (US) for intel corporation, Kamal Sinha of Rancho Cordova CA (US) for intel corporation, Balaji Vembu of Folsom CA (US) for intel corporation, Nicolas C. Galoppo Von Borries of Portland OR (US) for intel corporation, Eriko Nurvitadhi of Hillsboro OR (US) for intel corporation, Rajkishore Barik of Santa Clara CA (US) for intel corporation, Tsung-Han Lin of Campbell CA (US) for intel corporation, Vasanth Ranganathan of El Dorado Hills CA (US) for intel corporation, Sanjeev Jahagirdar of Folsom CA (US) for intel corporation
IPC Code(s): G06F9/30, G06F7/483, G06F7/544, G06F9/38, G06F17/16, G06N3/044, G06N3/045, G06N3/063, G06N3/08, G06N20/00, G06T15/00, G09G5/393
Abstract: one embodiment provides for a graphics processing unit to accelerate machine-learning operations, the graphics processing unit comprising a multiprocessor having a single instruction, multiple thread (simt) architecture, the multiprocessor to execute at least one single instruction; and a first compute unit included within the multiprocessor, the at least one single instruction to cause the first compute unit to perform a two-dimensional matrix multiply and accumulate operation, wherein to perform the two-dimensional matrix multiply and accumulate operation includes to compute an intermediate product of 16-bit operands and to compute a 32-bit sum based on the intermediate product.
Inventor(s): Hao CHANG of Shanghai (CN) for intel corporation, Geoffrey LANGDALE of Camperdown (AU) for intel corporation, Xiang WANG of Shanghai (CN) for intel corporation, Yang HONG of Shanghai (CN) for intel corporation, Wenjun ZHU of Shanghai (CN) for intel corporation, Kun QIU of Shanghai (CN) for intel corporation, Xusheng LU of Mesa AZ (US) for intel corporation
IPC Code(s): G06F9/30, G06F9/38, G06F15/80
Abstract: methods and embodiments of a high-performance parallel multi-literal matching algorithm called neoharry. a chunk of data comprising a character string comprising n bytes is sampled for a byte stream, and data in the sampled chunk are pre-shifted to create shifted copies of data at multiple sampled locations. a mask table is generated having column vectors containing match indicia identifying potential character matches. a look up of the mask table at multiple sampled locations using the pre-shifted data is performed for a target literal character pattern. the mask table lookup results are combined to generate match candidates and exact match verification is performed to identify any generated match candidates that match the target literal character pattern. neoharry uses a column-vector-based shift-or model and implements a cross-domain shift algorithm under which character patterns spanning two domains are identified.
20240184585.BFLOAT16 COMPARISON INSTRUCTIONS_simplified_abstract_(intel corporation)
Inventor(s): Alexander HEINECKE of San Jose CA (US) for intel corporation, Menachem ADELMAN of Haifa (IL) for intel corporation, Robert VALENTINE of Kiryat Tivon (IL) for intel corporation, Zeev SPERBER of Zikhron Yaakov (IL) for intel corporation, Amit GRADSTEIN of Binyamina (IL) for intel corporation, Mark CHARNEY of Lexington MA (US) for intel corporation, Evangelos GEORGANAS of San Mateo CA (US) for intel corporation, Dhiraj KALAMKAR of Bangalore (IN) for intel corporation, Christopher HUGHES of Santa Clara CA (US) for intel corporation, Cristina ANDERSON of Hillsboro OR (US) for intel corporation
IPC Code(s): G06F9/30
Abstract: techniques for comparing bf16 data elements are described. an exemplary bf16 comparison instruction includes fields for an opcode, an identification of a location of a first packed data source operand, and an identification of a location of a second packed data source operand, wherein the opcode is to indicate that execution circuitry is to perform, for a particular data element position of the packed data source operands, a comparison of a data element at that position, and update a flags register based on the comparison.
Inventor(s): Yigang ZHOU of Shanghai (CN) for intel corporation, Cunming LIANG of Shanghai (CN) for intel corporation
IPC Code(s): G06F9/455, G06F12/0802, G06F13/24, G06F13/28
Abstract: an example electronic apparatus is for accelerating a para-virtualization network interface. the electronic apparatus includes a descriptor hub performing bi-directionally communication with a guest memory accessible by a guest and with a host memory accessible by a host. the guest includes a plurality of virtual machines. the host includes a plurality of virtual function devices. the virtual machines are communicatively coupled to the electronic apparatus through a central processing unit. the communication is based upon para-virtualization packet descriptors and network interface controller virtual function-specific descriptors. the electronic apparatus also includes a device association table communicatively coupled to the descriptor hub and to store associations between the virtual machines and the virtual function devices. the electronic apparatus further includes an input-output memory map unit (iommu) to perform direct memory access (dma) remapping and interrupt remapping.
Inventor(s): Sarathy JAYAKUMAR of Portland OR (US) for intel corporation, Zijian YOU of Shanghai (CN) for intel corporation, Karthik GOPALAKRISHNAN of Folsom CA (US) for intel corporation, Erik KANEDA of Hood River OR (US) for intel corporation, Dan WILLIAMS of Forest Grove OR (US) for intel corporation
IPC Code(s): G06F9/48, G06F9/52
Abstract: various examples relate to a firmware apparatus (), firmware device, firmware method, and computer program for a computer system () comprising processing circuitry (), and to a corresponding computer system (). the firmware apparatus () comprises an interface () for accessing functionality of the firmware apparatus () from an operating system of the computer system (). the firmware apparatus () comprises control circuitry (), configured to identify one or more processing functionalities being supported by the processing circuitry () of the computer system (), provide information on the one or more processing functionalities via the interface () to a user mode interface of the operating system of the computer system (), and provide access to the one or more processing functionalities for application programs being executed in the operation system, the access being based on the information on the one or more processing functionalities provided to the user mode interface.
Inventor(s): Reshma Lal of Portland OR (US) for intel corporation, Pradeep Pappachan of Tualatin OR (US) for intel corporation, Luis Kida of Beaverton OR (US) for intel corporation, Soham Jayesh Desai of Rochester MN (US) for intel corporation, Sujoy Sen of Beaverton OR (US) for intel corporation, Selvakumar Panneer of Portland OR (US) for intel corporation, Robert Sharp of Austin TX (US) for intel corporation
IPC Code(s): G06F9/50, G06F9/38, G06T1/20, G06T1/60
Abstract: an apparatus to facilitate disaggregated computing for a distributed confidential computing environment is disclosed. the apparatus includes one or more processors to facilitate receiving a manifest corresponding to graph nodes representing regions of memory of a remote client machine, the graph nodes corresponding to a command buffer and to associated data structures and kernels of the command buffer used to initialize a hardware accelerator and execute the kernels, and the manifest indicating a destination memory location of each of the graph nodes and dependencies of each of the graph nodes; identifying, based on the manifest, the command buffer and the associated data structures to copy to the host memory; identifying, based on the manifest, the kernels to copy to local memory of the hardware accelerator; and patching addresses in the command buffer copied to the host memory with updated addresses of corresponding locations in the host memory.
Inventor(s): Carlos V. Rozas of Portland OR (US) for intel corporation, Mona Vij of Hillsboro OR (US) for intel corporation, Rebekah M. Leslie-Hurd of Portland OR (US) for intel corporation, Krystof C. Zmudzinski of Forest Grove OR (US) for intel corporation, Somnath Chakrabarti of Portland OR (US) for intel corporation, Francis X. Mckeen of Portland OR (US) for intel corporation, Vincent R. Scarlata of Beaverton OR (US) for intel corporation, Simon P. Johnson of Beaverton OR (US) for intel corporation, Ilya Alexandrovich of Yokneam Illit (IL) for intel corporation, Gilbert Neiger of Portland OR (US) for intel corporation, Vedvyas Shanbhogue of Austin TX (US) for intel corporation, Ittai Anati of Ramat Hasharon (IL) for intel corporation
IPC Code(s): G06F12/14, G06F8/41, G06F9/30, G06F9/455, G06F21/53, G06F21/60
Abstract: a processor includes a decode unit to decode an instruction that is to indicate a page of a protected container memory, and a storage location outside of the protected container memory. an execution unit, in response to the instruction, is to ensure that there are no writable references to the page of the protected container memory while it has a write protected state. the execution unit is to encrypt a copy of the page of the protected container memory. the execution unit is to store the encrypted copy of the page to the storage location outside of the protected container memory, after it has been ensured that there are no writable references. the execution unit is to leave the page of the protected container memory in the write protected state, which is also valid and readable, after the encrypted copy has been stored to the storage location.
20240184739.DYNAMIC MEMORY RECONFIGURATION_simplified_abstract_(intel corporation)
Inventor(s): Joydeep RAY of Folsom CA (US) for intel corporation, Niranjan COORAY of Folsom CA (US) for intel corporation, Subramaniam MAIYURAN of Gold River CA (US) for intel corporation, Altug KOKER of El Dorado Hills CA (US) for intel corporation, Prasoonkumar SURTI of Folsom CA (US) for intel corporation, Varghese GEORGE of Folsom CA (US) for intel corporation, Valentin ANDREI of San Jose CA (US) for intel corporation, Abhishek APPU of El Dorado Hills CA (US) for intel corporation, Guadalupe GARCIA of Chandler AZ (US) for intel corporation, Pattabhiraman K of Bangalore (IN) for intel corporation, Sungye KIM of Folsom CA (US) for intel corporation, Sanjay KUMAR of Bangalore (IN) for intel corporation, Pratik MAROLIA of Hillsboro OR (US) for intel corporation, Elmoustapha OULD-AHMED-VALL of Chandler AZ (US) for intel corporation, Vasanth RANGANATHAN of El Dorado Hills CA (US) for intel corporation, William SADLER of Folsom CA (US) for intel corporation, Lakshminarayanan STRIRAMASSARMA of Folsom CA (US) for intel corporation
IPC Code(s): G06F15/78, G06F7/544, G06F7/575, G06F7/58, G06F9/30, G06F9/38, G06F9/50, G06F12/02, G06F12/06, G06F12/0802, G06F12/0804, G06F12/0811, G06F12/0862, G06F12/0866, G06F12/0871, G06F12/0875, G06F12/0882, G06F12/0888, G06F12/0891, G06F12/0893, G06F12/0895, G06F12/0897, G06F12/1009, G06F12/128, G06F15/80, G06F17/16, G06F17/18, G06N3/08, G06T1/20, G06T1/60, G06T15/06, H03M7/46
Abstract: embodiments described herein provide techniques to enable the dynamic reconfiguration of memory on a general-purpose graphics processing unit. one embodiment described herein enables dynamic reconfiguration of cache memory bank assignments based on hardware statistics. one embodiment enables for virtual memory address translation using mixed four kilobyte and sixty-four kilobyte pages within the same page table hierarchy and under the same page directory. one embodiment provides for a graphics processor and associated heterogenous processing system having near and far regions of the same level of a cache hierarchy.
Inventor(s): Anbang Yao of Beijing (CN) for intel corporation, Yiwen Guo of Beijing 11 (CN) for intel corporation, Yurong Chen of Beijing (CN) for intel corporation
IPC Code(s): G06N3/082, G06F18/241, G06V10/764, G06V10/82
Abstract: systems, apparatuses and methods may provide for conducting an importance measurement of a plurality of parameters in a trained neural network and setting a subset of the plurality of parameters to zero based on the importance measurement. additionally, the pruned neural network may be re-trained. in one example, conducting the importance measurement includes comparing two or more parameter values that contain covariance matrix information.
Inventor(s): Priyanka Mudgal of Portland OR (US) for intel corporation, Caleb Mark McMillan of Forest Grove OR (US) for intel corporation, Rita Hanna Wouhaybi of Portland OR (US) for intel corporation, Mark David Yarvis of Portland OR (US) for intel corporation, Jennifer Williams of Hillsboro OR (US) for intel corporation, Greeshma Pisharody of Portland OR (US) for intel corporation
IPC Code(s): G06N20/00
Abstract: methods, apparatus, systems, and articles of manufacture to facilitate collaborative learning in a multi-sensor environment are disclosed. an example computer readable medium comprises instructions at least one programmable circuit to after determining that first data from a first device conflicts with second data from a second device: validate the first device based on third data from a validated device; and mitigate the second device based on the third data.
Inventor(s): Peixi Xiong of Hillsboro OR (US) for intel corporation, Nilesh Jain of Portland OR (US) for intel corporation
IPC Code(s): G06T11/60, G06F40/205, G06F40/284
Abstract: technology as described herein provides for generating an image via a generator network, including extracting structural relationship information from a text prompt, wherein the structural relationship information includes sentence features and token features, generating encoded text features based on the sentence features and on relation-related tokens, wherein the relation-related tokens are identified based on parsing text dependency information in the token features, and generating an output image based on combining, via self attention and cross-attention layers, the encoded text features and encoded image features from an input image canvas. embodiments further include applying a gating function to modify image features based on text features. the self attention and cross-attention layers can be applied via a cross-modality network, the gating function can be applied via a residual gating network, and the relation-related tokens can be further identified via an attention matrix.
20240185527.TILE SEQUENCING MECHANISM_simplified_abstract_(intel corporation)
Inventor(s): Subramaniam Maiyuran of GOLD RIVER CA (US) for intel corporation, Saurabh Sharma of El Dorado Hills CA (US) for intel corporation, Jorge F. Garcia Pabon of Folsom CA (US) for intel corporation, Raghavendra Kamath Miyar of BANGALORE (IN) for intel corporation, Sudheendra Srivathsa of BANGALORE (IN) for intel corporation, Justin Decell of SAN FRANCISCO CA (US) for intel corporation, Aditya Navale of Folsom CA (US) for intel corporation
IPC Code(s): G06T17/20, G06T1/20, G06T15/00
Abstract: an apparatus to facilitate graphics rendering is disclosed. the apparatus comprises sequencer hardware to operate in a tile mode to render objects, including performing batch formation to generate one or more batches of received objects, performing tile sequencing for each of the objects to compute tile fill intersects for each of the objects and performing a play sequencing of each of the objects.
Inventor(s): Shao-Wen Yang of San Jose CA (US) for intel corporation, Yen-Kuang Chen of Palo Alto CA (US) for intel corporation, Addicam V. Sanjay of Gilbert AZ (US) for intel corporation
IPC Code(s): G06V10/82, G06F9/48, G06F9/50, G06F18/241, G06F18/2413, G06F21/60, G06F21/62, G06Q50/26, G06V10/44, G06V10/764, G06V20/52, G06V40/10, G08G1/09, G11B27/031, H04N7/18
Abstract: in one embodiment, an apparatus comprises a processor to: identify a workload comprising a plurality of tasks; generate a workload graph based on the workload, wherein the workload graph comprises information associated with the plurality of tasks; identify a device connectivity graph, wherein the device connectivity graph comprises device connectivity information associated with a plurality of processing devices; identify a privacy policy associated with the workload; identify privacy level information associated with the plurality of processing devices; identify a privacy constraint based on the privacy policy and the privacy level information; and determine a workload schedule, wherein the workload schedule comprises a mapping of the workload onto the plurality of processing devices, and wherein the workload schedule is determined based on the privacy constraint, the workload graph, and the device connectivity graph. the apparatus further comprises a communication interface to send the workload schedule to the plurality of processing devices.
Inventor(s): Satish JHA of Portland OR (US) for intel corporation, Kathiravetpillai SIVANESAN of Portland OR (US) for intel corporation, S M Iftekharul ALAM of Hillsboro OR (US) for intel corporation, Kuilin Clark CHEN of Portland OR (US) for intel corporation, Kshitij DOSHI of Tempe AZ (US) for intel corporation, Leonardo GOMES BALTAR of Munich (DE) for intel corporation, Francesc GUIM BERNAT of Barcelona (ES) for intel corporation, Arvind MERWADAY of Beaverton OR (US) for intel corporation, Markus Dominik MUECK of Unterhaching (DE) for intel corporation, Suman A. SEHRA of Folsom CA (US) for intel corporation, Vesh Raj SHARMA BANJADE of Portland OR (US) for intel corporation, Soo Jin TAN of Shanghai (CN) for intel corporation
IPC Code(s): G08G1/087, G01C21/34, G08G1/00, G08G1/09
Abstract: the disclosure relates to systems, methods, and devices for managing traffic through a road segment and/or intersection. the traffic management system may place traffic objects in a collaboration group for coordinating movements in the road segment and/or intersection in response to a received indication that an emergency vehicle has a planned route that includes the road segment and/or intersection. the traffic management system may determine a movement plan for each traffic object in the collaboration group based on received measurements about the road segment and the planned route of the emergency vehicle. the traffic management system may control a transmitter to send the movement plan to each traffic object in the collaboration group.
Inventor(s): Jacek Ossowski of Gdansk (PL) for intel corporation, Tobias Bocklet of Munich (DE) for intel corporation, Kuba Lopatka of Gdansk (PL) for intel corporation
IPC Code(s): G10L15/22, G10L15/08, G10L17/00
Abstract: techniques related to a method and system of audio false keyphrase rejection using speaker recognition are described herein. such techniques use speaker recognition of a computer originated voice to omit actions triggered when a keyphrase is present in captured audio and omitted when speech of the captured audio was spoken by the computer originated voice.
Inventor(s): Shuo LIU of Shanghai (CN) for intel corporation, Yao Zu DONG of Shanghai (CN) for intel corporation, Qing HUANG of Shanghai (CN) for intel corporation, Kevin Yufu LI of Shanghai (CN) for intel corporation, Yipeng YAO of Shanghai (CN) for intel corporation, Jie YU of Shanghai (CN) for intel corporation
IPC Code(s): G11C11/406, G11C11/408, G11C11/4096
Abstract: a memory device comprises an input interface configured to receive an erase request indicating a memory portion to be erased and control circuitry configured to trigger erasing information stored by memory cells of at least a part of the indicated memory portion of the memory device by writing a predefined pattern into the memory cells during an automatic refresh cycle.
Inventor(s): Ilya V. Karpov of Portland OR (US) for intel corporation, Aaron A. Budrevich of Portland OR (US) for intel corporation, Gilbert Dewey of Beaverton OR (US) for intel corporation, Matthew V. Metz of Portland OR (US) for intel corporation, Jack T. Kavalieros of Portland OR (US) for intel corporation, Dan S. Lavric of Portland OR (US) for intel corporation
IPC Code(s): H01J37/34, C23C14/34, H01L21/285, H01L29/08, H01L29/45
Abstract: an integrated circuit structure includes a source or drain region, and a contact coupled to the source or drain region. sputter targets that include metals doped with the appropriate dopant types are used to deposit a conductive layer on the source or drain region that is annealed to form a region including metals and semiconductor materials between the source or drain region and the contact. a first dopant is within the source or drain region, and a second dopant is within the region. in one example, the first dopant is elementally different from the second dopant. in another example, the first dopant is elementally the same as the second dopant, wherein a concentration of the first dopant within a section of the source or drain region is within 20% of a concentration of the second dopant within the region.
Inventor(s): Mahdi Mohammadighaleni of Phoenix AZ (US) for intel corporation, Whitney M. Bryks of Tempe AZ (US) for intel corporation, Shayan Kaviani of Phoenix AZ (US) for intel corporation, Joshua J. Stacey of Chandler AZ (US) for intel corporation, Thomas S. Heaton of Gilbert AZ (US) for intel corporation
IPC Code(s): H01L21/02, C23C16/02
Abstract: in one embodiment, an integrated circuit apparatus (e.g., package substrate) includes a polymeric layer between a metal and a dielectric or between a metal and a glass. the polymeric layer may be conformally deposited using a vacuum-based vapor deposition technique, e.g., initiated chemical vapor deposition (icvd).
Inventor(s): Aaditya Anand CANDADAI of Chandler AZ (US) for intel corporation, Nicholas HAEHN of Scottsdale AZ (US) for intel corporation, Ao WANG of Chandler AZ (US) for intel corporation, Whitney BRYKS of Tempe AZ (US) for intel corporation, Srinivas PIETAMBARAM of Chandler AZ (US) for intel corporation
IPC Code(s): H01L23/16
Abstract: the present disclosure is directed to a semiconductor panel providing a laminated structure and a plurality of electrically isolated structures distributed throughout the laminated structure to increase an attraction between the laminated structure and an electrostatic chuck. in an aspect, the electrically isolated structures are positioned in spaces in the semiconductor panel without electrically active devices and interconnects. in yet another aspect, the present method provides a semiconductor panel and forming a plurality of electrically isolated structures in selected positions on the semiconductor panel and an electrostatic chuck configured to carry an electrostatic charge for producing an electrostatic force at its top surface, placing the semiconductor panel on the electrostatic chuck, and activating the electrostatic chuck to induce polarization at the top surface to produce an attractive force having a greater magnitude at the positions with the plurality of electrically isolated structures.
20240186202.PACKAGE WITH UNDERFILL CONTAINMENT BARRIER_simplified_abstract_(intel corporation)
Inventor(s): Rahul JAIN of Gilbert AZ (US) for intel corporation, Kyu Oh LEE of Chandler AZ (US) for intel corporation, Siddharth K. ALUR of Chandler AZ (US) for intel corporation, Wei-Lun K. JEN of Chandler AZ (US) for intel corporation, Vipul V. MEHTA of Chandler AZ (US) for intel corporation, Ashish DHALL of Chandler AZ (US) for intel corporation, Sri Chaitra J. CHAVALI of Chandler AZ (US) for intel corporation, Rahul N. MANEPALLI of Chandler AZ (US) for intel corporation, Amruthavalli P. ALUR of Tempe AZ (US) for intel corporation, Sai VADLAMANI of Gilbert AZ (US) for intel corporation
IPC Code(s): H01L23/31, H01L21/48, H01L21/56, H01L23/00, H01L23/498, H01L23/532, H01L23/538, H01L25/065
Abstract: an apparatus is provided which comprises: a substrate, a die site on the substrate to couple with a die, a die side component site on the substrate to couple with a die side component, and a raised barrier on the substrate between the die and die side component sites to contain underfill material disposed at the die site, wherein the raised barrier comprises electroplated metal. other embodiments are also disclosed and claimed.
Inventor(s): Satish PRATHABAN of Beaverton OR (US) for intel corporation, Ramaswamy PARTHASARATHY of Bangalore (IN) for intel corporation, Biswajit PATRA of Bangalore (IN) for intel corporation, Tongyan ZHAI of Portland OR (US) for intel corporation, Jeff KU of Taipei City (TW) for intel corporation, Min Suet LIM of Penang (MY) for intel corporation, Yi HUANG of Shanghai (CN) for intel corporation, Kai XIAO of Portland OR (US) for intel corporation, Gene F. YOUNG of St. Augustine FL (US) for intel corporation, Weimin SHI of Tigard OR (US) for intel corporation
IPC Code(s): H01L23/367, H01L23/00, H01L23/427, H01L25/065, H01L25/18, H05K1/02
Abstract: systems, apparatuses and methods may provide for technology that includes a voltage regulator, a board assembly including a die and a circuit board electrically coupled to a first side of the die, and a thermal dissipation assembly thermally and electrically coupled to a second side of the die, wherein the thermal dissipation assembly is further electrically coupled to the voltage regulator. in one example, the thermal dissipation assembly includes a vapor chamber and the technology further includes a plurality of copper plates electrically coupled to the voltage regulator and a package substrate containing the die, wherein the plurality of copper plates are further thermally coupled to the vapor chamber.
Inventor(s): Haobo Chen of Chandler AZ (US) for intel corporation, Bohan Shan of Chandler AZ (US) for intel corporation, Kyle J. Arrington of Gilbert AZ (US) for intel corporation, Kristof Darmawikarta of Chandler AZ (US) for intel corporation, Gang Duan of Chandler AZ (US) for intel corporation, Jeremy D. Ecton of Gilbert AZ (US) for intel corporation, Hongxia Feng of Chandler AZ (US) for intel corporation, Xiaoying Guo of Chandler AZ (US) for intel corporation, Ziyin Lin of Chandler AZ (US) for intel corporation, Brandon Christian Marin of Gilbert AZ (US) for intel corporation, Srinivas V. Pietambaram of Chandler AZ (US) for intel corporation, Dingying Xu of Chandler AZ (US) for intel corporation
IPC Code(s): H01L23/498, H01L21/48, H01L23/00, H01L23/538, H01L23/64, H01L25/065, H05K1/02, H05K1/03, H05K1/11, H05K1/18, H05K3/46
Abstract: in one embodiment, an integrated circuit package substrate includes a core layer comprising a plurality of metal vias electrically coupling a first side of the core layer and a second side of the core layer opposite the first side. the package substrate further includes a build-up layer on the first side of the core layer, the build-up layer comprising metal vias within a dielectric material and electrically connected to the metal vias of the core layer. the dielectric material includes silicon, oxygen, and at least one of boron or phosphorus.
Inventor(s): Haobo Chen of Chandler AZ (US) for intel corporation, Bohan Shan of Chandler AZ (US) for intel corporation, Kyle J. Arrington of Gilbert AZ (US) for intel corporation, Yiqun Bai of Chandler AZ (US) for intel corporation, Kristof Darmawikarta of Chandler AZ (US) for intel corporation, Gang Duan of Chandler AZ (US) for intel corporation, Jeremy D. Ecton of Gilbert AZ (US) for intel corporation, Hongxia Feng of Chandler AZ (US) for intel corporation, Xiaoying Guo of Chandler AZ (US) for intel corporation, Ziyin Lin of Chandler AZ (US) for intel corporation, Brandon Christian Marin of Gilbert AZ (US) for intel corporation, Bai Nie of Chandler AZ (US) for intel corporation, Srinivas V. Pietambaram of Chandler AZ (US) for intel corporation, Dingying Xu of Chandler AZ (US) for intel corporation
IPC Code(s): H01L23/498, H01L21/48
Abstract: in one embodiment, an integrated circuit package substrate includes a core layer comprising a dielectric material and a plurality of metal vias within the core layer. the dielectric material includes silicon, oxygen, and at least one of boron or phosphorus. the metal vias electrically couple a first side of the core layer and a second side of the core layer opposite the first side. the package substrate further includes a plurality of build-up layers on the core layer, the build-up layers comprising metal vias electrically connected to the metal vias of the core layer.
Inventor(s): Whitney M. Bryks of Tempe AZ (US) for intel corporation, Mahdi Mohammadighaleni of Phoenix AZ (US) for intel corporation, Joshua J. Stacey of Chandler AZ (US) for intel corporation
IPC Code(s): H01L23/498, H01L21/48
Abstract: in one embodiment, an integrated circuit package substrate includes a core layer comprising silicon and oxygen and a plurality of metal vias electrically coupling a first side of the core layer and a second side of the core layer opposite the first side. the package substrate further includes a build-up layer on the first side of the core layer. the build-up layer includes metal pads and metal traces within a dielectric material that are electrically connected to the metal vias of the core layer, the dielectric material comprising silicon, oxygen, and at least one of boron or phosphorus.
Inventor(s): Jeremy D. Ecton of Gilbert AZ (US) for intel corporation, Brandon Christian Marin of Gilbert AZ (US) for intel corporation, Srinivas V. Pietambaram of Chandler AZ (US) for intel corporation, Tarek A. Ibrahim of Mesa AZ (US) for intel corporation, Suddhasattwa Nad of Chandler AZ (US) for intel corporation, Gang Duan of Chandler AZ (US) for intel corporation, Haobo Chen of Chandler AZ (US) for intel corporation, Hiroki Tanaka of Gilbert AZ (US) for intel corporation
IPC Code(s): H01L23/538, H01L21/48
Abstract: a microelectronic assembly includes a substrate comprising: a panel including glass and defining an opening therein; an interconnect bridge (ib) in the opening and including interconnect pathways and ib through vias (ibtvs); and electrically conductive structures at a lower surface of the substrate to electrically couple the substrate to another component, at least some of the electrically conductive structures coupled to the ibtvs to form respective vertical electrical connections between the lower surface of the substrate and an upper surface of the substrate; and an electronic component (ec) layer on the upper surface of the substrate, the ec layer including a first active ec (aec) and a second aec electrically coupled to one another through the interconnect pathways, at least one of the first aec or the second aecs further electrically coupled to one or more of the at least some of the electrically conductive structures.
Inventor(s): Minglu LIU of Chandler AZ (US) for intel corporation, YANG WU of Chandler AZ (US) for intel corporation, Yuting WANG of Chandler AZ (US) for intel corporation, Lawrence ROSS of Chandler AZ (US) for intel corporation, Mine KAYA of Scottsdale AZ (US) for intel corporation, Gang DUAN of Chandler AZ (US) for intel corporation, Edvin CETEGEN of Chandler AZ (US) for intel corporation, Alexander AGUINAGA of Phoenix AZ (US) for intel corporation
IPC Code(s): H01L23/538, H01L23/00, H01L23/13, H01L25/065
Abstract: embodiments disclosed herein include package architectures. in an embodiment, the package architecture comprises a package substrate, a first bridge in the package substrate, where the first bridge includes conductive routing, and a second bridge in the package substrate. in an embodiment, the package architecture further comprises a third bridge in the package substrate, where the second bridge and the third bridge are positioned symmetrically about the first bridge.
20240186263.STRUCTURE AND PROCESS FOR WARPAGE REDUCTION_simplified_abstract_(intel corporation)
Inventor(s): Hong Seung YEON of Chandler AZ (US) for intel corporation, Liang HE of Chandler AZ (US) for intel corporation, Whitney BRYKS of Tempe AZ (US) for intel corporation, Jung Kyu HAN of Chandler AZ (US) for intel corporation, Gang DUAN of Chandler AZ (US) for intel corporation
IPC Code(s): H01L23/00
Abstract: the present disclosure is directed to a semiconductor carrier platform having a support panel with a top surface and a bottom surface, with the top surface providing a working surface for assembling ic packages using panel-level packaging technology. in an aspect, a backside molding layer may be positioned on the bottom surface of the support panel to prevent or correct any panel warpage. in another aspect, a removable film may be positioned between the bottom surface of the support panel and the backside molding layer to allow the support panel to be readily cleaned and reused.
Inventor(s): Yi Yang of Gilbert AZ (US) for intel corporation, Eungnak Han of Portland OR (US) for intel corporation, Suddhasattwa Nad of Chandler AZ (US) for intel corporation, Marcel A. Wall of Phoenix AZ (US) for intel corporation
IPC Code(s): H01L23/00, B32B17/10, C09D201/00, H01L21/48, H01L23/15, H01L23/498
Abstract: in one embodiment, an apparatus includes a glass substrate, a metal, and a polymeric layer between the metal and the glass substrate. the polymeric layer includes polymer molecules with an r1 group, an r2 group, a polymer backbone between the r1 group and r2 group, and an r3 group side-attached to the polymer backbone. the polymeric layer is bonded to the glass substrate via the r1 groups and bonded to the metal via the r2 groups.
Inventor(s): Srinivas V. Pietambaram of Chandler AZ (US) for intel corporation, Claudio A. Alvarez Barros of Santiago (CL) for intel corporation, Beomseok Choi of Chandler AZ (US) for intel corporation, Gang Duan of Chandler AZ (US) for intel corporation, Jeremy D. Ecton of Gilbert AZ (US) for intel corporation, Brandon Christian Marin of Gilbert AZ (US) for intel corporation, Suddhasattwa Nad of Chandler AZ (US) for intel corporation, Hiroki Tanaka of Gilbert AZ (US) for intel corporation
IPC Code(s): H01L23/64, H01F10/32, H01L21/48, H01L23/498
Abstract: a microelectronic structure, a semiconductor package, an ic device assembly, and a method. the structure includes a core layer including an electrically non-conductive material; electrically conductive through core vias (tcvs) through the core layer; a dielectric layer on the core layer with electrically conductive structures extending therethrough and electrically coupled to the tcvs; and a magnetic inductor (mi) within at least one of the core layer or the build-up layer and including an antiferromagnetic (af) structure. the af structure includes a first ferromagnetic (fm) layer; an exchange coupling (ec) layer on the first fm layer and including a non-magnetic metal material; a second fm layer on the ec layer, the ec layer between the first fm layer and the second fm layer; and a pinning (p) layer including manganese and at least one of platinum or iridium, the second fm layer between the ec layer and the p layer.
Inventor(s): Minglu LIU of Chandler AZ (US) for intel corporation, Yosuke KANAOKA of Chandler AZ (US) for intel corporation, Jung Kyu HAN of Chandler AZ (US) for intel corporation, Gang DUAN of Chandler AZ (US) for intel corporation, Ziyin LIN of Chandler AZ (US) for intel corporation
IPC Code(s): H01L23/00, B32B37/12
Abstract: the present disclosure relates to a system. the system may include a stage configured to support a substrate. the system may also include a bondhead configured to press a device against the substrate. the system may further include a light source configured to emit uv light towards the stage.
Inventor(s): Minglu LIU of Chandler AZ (US) for intel corporation, Andrey GUNAWAN of Paradise Valley AZ (US) for intel corporation, Gang DUAN of Chandler AZ (US) for intel corporation, Edvin CETEGEN of Chandler AZ (US) for intel corporation, Yuting WANG of Chandler AZ (US) for intel corporation, Mine KAYA of Scottsdale AZ (US) for intel corporation, Kartik SRINIVASAN of Gilbert AZ (US) for intel corporation, Mihir OKA of Chandler AZ (US) for intel corporation, Anurag TRIPATHI of Gilbert AZ (US) for intel corporation
IPC Code(s): H01L23/00
Abstract: the present disclosure is directed to an apparatus having a bond head configured to heat and compress a semiconductor package assembly, and a bonding stage configured to hold the semiconductor package assembly, wherein the bonding stage comprises a ceramic material including silicon and either magnesium or indium.
Inventor(s): Minglu LIU of Chandler AZ (US) for intel corporation, Andrey GUNAWAN of Paradise Valley AZ (US) for intel corporation, Gang DUAN of Chandler AZ (US) for intel corporation
IPC Code(s): H01L23/00, H01L25/00
Abstract: the present disclosure is directed to a thermocompression bonding tool having a bond head with a surface for compression and heating and a sensor, a stage for compression and heating, and a controller, and a method for its use for chip gap height and alignment control. for chip gap height and alignment control, the controller is provided with a recipe displacement and temperature profile and measured offsets.
Inventor(s): Hwichan Jun of Portland OR (US) for intel corporation, Guillaume Bouche of Portland OR (US) for intel corporation
IPC Code(s): H01L27/12, H01L21/8234, H01L27/088
Abstract: techniques are provided herein to form semiconductor devices having different gate oxide thicknesses. a first semiconductor device includes a first gate structure around a first plurality of semiconductor nanoribbons and a second semiconductor device includes a second gate structure around a second plurality of semiconductor nanoribbons. the first gate structure includes at least a first gate oxide layer and a first gate electrode, and the second gate structure includes at least a second gate oxide layer and a second gate electrode. the first gate oxide layer is thicker than the second gate oxide layer. a high-k dielectric layer may be formed over the first and second gate oxide layers or may be formed over the second gate oxide layer, but not over the first gate oxide layer.
Inventor(s): Cory BOMBERGER of Portland OR (US) for intel corporation, Anand MURTHY of Portland OR (US) for intel corporation, Susmita GHOSE of Hillsboro OR (US) for intel corporation, Siddharth CHOUKSEY of Portland OR (US) for intel corporation
IPC Code(s): H01L29/08, H01L21/02, H01L21/027, H01L21/306, H01L21/66, H01L29/06, H01L29/10, H01L29/165, H01L29/167, H01L29/32, H01L29/423, H01L29/66, H01L29/78
Abstract: gate-all-around integrated circuit structures having embedded gesnb source or drain structures, and methods of fabricating gate-all-around integrated circuit structures having embedded gesnb source or drain structures, are described. for example, an integrated circuit structure includes a vertical arrangement of horizontal nanowires above a fin, the fin including a defect modification layer on a first semiconductor layer, and a second semiconductor layer on the defect modification layer. a gate stack is around the vertical arrangement of horizontal nanowires. a first epitaxial source or drain structure is at a first end of the vertical arrangement of horizontal nanowires, and a second epitaxial source or drain structure is at a second end of the vertical arrangement of horizontal nanowires.
20240186395.LINED CONDUCTIVE STRUCTURES FOR TRENCH CONTACT_simplified_abstract_(intel corporation)
Inventor(s): Krishna GANESAN of Portland OR (US) for intel corporation, Ala ALAZIZI of Portland OR (US) for intel corporation, Ankit Kirit LAKHANI of Hillsboro OR (US) for intel corporation, Peter P. SUN of Beaverton OR (US) for intel corporation, Diana Ivonne PAREDES of Portland OR (US) for intel corporation
IPC Code(s): H01L29/423, H01L29/66, H01L29/775, H01L29/78, H01L29/786
Abstract: lined conductive via structures for trench contact are described. in an example, an integrated circuit structure includes a plurality of gate structures over corresponding ones of a plurality of vertical stacks of horizontal nanowires. the integrated circuit structure also includes a plurality of conductive trench contact structures alternating with the plurality of gate structures, each of the plurality of conductive contact structures having an upper portion over a lower portion, the upper portion of each of the plurality of conductive trench contact structures having a length between ends. the integrated circuit structure also includes a dielectric liner in lateral contact with sides along the length of the upper portion of each of the plurality of conductive contact structures, wherein the dielectric liner is not in contact with the ends of the upper portion of each of the plurality of conductive contact structures.
Inventor(s): Aaron D. LILAK of Beaverton OR (US) for intel corporation, Anh PHAN of Beaverton OR (US) for intel corporation, Rishabh MEHANDRU of Portland OR (US) for intel corporation, Stephen M. CEA of Hillsboro OR (US) for intel corporation, Patrick MORROW of Portland OR (US) for intel corporation, Jack T. KAVALIEROS of Portland OR (US) for intel corporation, Justin WEBER of Portland OR (US) for intel corporation, Salim BERRADA of Hillsboro OR (US) for intel corporation
IPC Code(s): H01L29/49, H01L21/28, H01L27/092, H01L29/06, H01L29/423, H01L29/51, H01L29/66, H01L29/775
Abstract: integrated circuit structures having cavity spacers, and methods of fabricating integrated circuit structures having cavity spacers, are described. for example, an integrated circuit structure includes a sub-fin structure over a stack of nanowires. a gate structure is vertically around the stack of nanowires. an internal gate spacer is between vertically adjacent ones of the nanowires and adjacent to the gate structure. a trench contact structure is laterally adjacent to a side of the gate structure. a cavity spacer is laterally between the gate structure and the trench contact structure.
Inventor(s): Jeffrey S. LEIB of Beaverton OR (US) for intel corporation, Jenny HU of Santa Clara CA (US) for intel corporation, Anindya DASGUPTA of Portland OR (US) for intel corporation, Michael L. HATTENDORF of Portland OR (US) for intel corporation, Christopher P. AUTH of Portland OR (US) for intel corporation
IPC Code(s): H01L29/66, H01L21/02, H01L21/033, H01L21/28, H01L21/285, H01L21/308, H01L21/311, H01L21/762, H01L21/768, H01L21/8234, H01L21/8238, H01L23/00, H01L23/522, H01L23/528, H01L23/532, H01L27/02, H01L27/088, H01L27/092, H01L29/06, H01L29/08, H01L29/165, H01L29/167, H01L29/417, H01L29/51, H01L29/78, H10B10/00
Abstract: embodiments of the disclosure are in the field of advanced integrated circuit structure fabrication and, in particular, 10 nanometer node and smaller integrated circuit structure fabrication and the resulting structures. in an example, an integrated circuit structure includes a semiconductor substrate comprising an n well region having a semiconductor fin protruding therefrom. a trench isolation layer is on the semiconductor substrate around the semiconductor fin, wherein the semiconductor fin extends above the trench isolation layer. a gate dielectric layer is over the semiconductor fin. a conductive layer is over the gate dielectric layer over the semiconductor fin, the conductive layer comprising titanium, nitrogen and oxygen. a p-type metal gate layer is over the conductive layer over the semiconductor fin.
20240186416.TMD INVERTED NANOWIRE INTEGRATION_simplified_abstract_(intel corporation)
Inventor(s): Kevin P. O'Brien of Portland OR (US) for intel corporation, Carl NAYLOR of Portland OR (US) for intel corporation, Chelsey DOROW of Portland OR (US) for intel corporation, Kirby MAXEY of Hillsboro OR (US) for intel corporation, Tanay GOSAVI of Portland OR (US) for intel corporation, Ashish Verma PENUMATCHA of Beaverton OR (US) for intel corporation, Shriram SHIVARAMAN of Hillsboro OR (US) for intel corporation, Chia-Ching LIN of Portland OR (US) for intel corporation, Sudarat LEE of Hillsboro OR (US) for intel corporation, Uygar E. AVCI of Portland OR (US) for intel corporation
IPC Code(s): H01L29/78, H01L21/02, H01L29/06, H01L29/24, H01L29/423, H01L29/66
Abstract: embodiments disclosed herein comprise semiconductor devices with two dimensional (2d) semiconductor channels and methods of forming such devices. in an embodiment, the semiconductor device comprises a source contact and a drain contact. in an embodiment, a 2d semiconductor channel is between the source contact and the drain contact. in an embodiment, the 2d semiconductor channel is a shell.
Inventor(s): Matteo CAMPONESCHI of Villach (AT) for intel corporation, Albert MOLINA of Novelda (ES) for intel corporation, Kannan RAJAMANI of Basking Ridge NJ (US) for intel corporation, Martin CLARA of Santa Clara CA (US) for intel corporation
IPC Code(s): H03M1/06, H03M1/10, H03M1/18
Abstract: an analog-to-digital converter (adc) system is provided. the adc system includes a first signal path. the first signal path includes a first adc configured to generate first digital data based on an input signal. the first adc is a time-interleaved adc including a plurality of sub-adcs. the first signal path further includes circuitry configured to output activity data indicating at least which of the plurality of sub-adcs is currently active. the adc system further includes a correction circuit configured to output digital correction data based on the activity data. further, the adc system includes a second signal path coupled in parallel to the first signal path. the second signal path includes a second adc configured to generate second digital data based on the input signal and a combiner circuit configured to generate modified second digital data by combining the second digital data and the correction data. the adc system further includes an equalizer configured to generate an equalized output signal of the adc system based on the first digital data. the equalizer is configured to adjust, based on the modified second digital data, at least one equalization parameter used for generating the equalized output signal of the adc system.
Inventor(s): Hua LI of Beijing (CN) for intel corporation, Meng ZHANG of Beijing (CN) for intel corporation, Andrey CHERVYAKOV of Maynooth (IE) for intel corporation, Rui HUANG of Beijing (CN) for intel corporation
IPC Code(s): H04B7/06, H04L5/00, H04W24/10
Abstract: this disclosure describes systems, methods, and devices related to channel state information reference signal (csi-rs) configuration. a device may establish a first measurement window for a first csi-rs associated with a first type of measurement in a measurement object (mo). the device may identify a measurement gap associated a second type of measurement. the device may perform adjustment to avoid a collision between the first measurement window and the measurement gap. the device may detect the first csi-rs within the first measurement window.
Inventor(s): Alexei Davydov of Nizhny Novgorod (RU) for intel corporation, Bishwarup Mondal of San Ramon CA (US) for intel corporation, Dong Han of Sunnyvale CA (US) for intel corporation
IPC Code(s): H04L5/00, H04L1/00, H04W72/044, H04W72/1273
Abstract: various embodiments herein relate to a technique to be performed by a user equipment (ue) in a cellular network. the technique may include identifying, in a downlink control information (dci) received from a first transmission and reception point (trp), an indication of whether the ue is to operate in accordance with a single-trp physical uplink shared channel (pusch) mode or a multi-trp pusch mode: identifying, based on the indication, one or more resources for pusch transmission; and transmitting, based on the indication and the one or more resources, a first repetition of the pusch transmission and a second repetition of the pusch transmission. other embodiments may be described and/or claimed.
Inventor(s): Guotong Wang of Beijing (CN) for intel corporation, Alexei Davydov of Nizhny Novgorod (RU) for intel corporation
IPC Code(s): H04L5/00, H04W72/23
Abstract: systems, apparatuses, methods, and computer-readable media are provided for srs configuration for antenna switching and/or carrier switching. the described techniques may be used in multi-trp and/or single trp communication. also described are techniques for beam configuration for srs with antenna switching. for example, embodiments provide techniques for beam configuration/update for srs antenna switching considering the beam change signaling received during the antenna switching procedure. other embodiments may be described and claimed.
Inventor(s): Gang Xiong of Beaverton OR (US) for intel corporation, Yingyang Li of Beijing (CN) for intel corporation, Yi Wang of Beijing (CN) for intel corporation
IPC Code(s): H04L5/00, H04L1/1822, H04W72/232
Abstract: a ue configured for operation in a 5gnr system may decode a first dci scheduling a first pusch transmission with transport-block processing over multiple slots (tboms) and a second dci scheduling a second pusch transmission with tboms. the ue may check timing relations of the scheduled first and second pusch transmissions with tboms for validity. when the timing relations are valid, the ue may transmit the first pusch transmission in multiple slots in accordance with the first dci and may transmit the second pusch transmission in multiple slots in accordance with the second dci. the first dci may be received in a first pdcch and the second dci may be received in a second pdcch. when the first pdcch ends at a first symbol and the ue is scheduled to start the first pusch transmission with tboms at a second symbol, the second pusch transmission with tboms is not expected to be scheduled to start earlier than an end of the first pusch transmission with tboms when the second pdcch that scheduled the second pusch transmission with tboms ends at a symbol later than the first symbol.
20240187191.ENHANCED PREAMBLE FOR 60 GIGAHERTZ OPERATION_simplified_abstract_(intel corporation)
Inventor(s): Thomas J. KENNEY of Portland OR (US) for intel corporation, Shahrnaz AZIZI of Cupertino CA (US) for intel corporation, Laurent CARIOU of Milizac (FR) for intel corporation, Juan FANG of Portland OR (US) for intel corporation
IPC Code(s): H04L5/00
Abstract: this disclosure describes systems, methods, and devices related to enhanced 60 gigahertz (ghz) preamble. a device may generate a frame for 60 ghz transmission, the frame comprising one or more fields to carry information associated with one or more station devices (stas). the device may generate a modified legacy signal (l-sig) field comprising one or more subfields for operation in the 60 ghz transmission. the device may generate a modified legacy long training field (l-ltf) for operation in the 60 ghz transmission. the device may utilize 56 subcarriers in the modified l-ltf in the frame. the device may cause to send the frame comprising the modified l-ltf and the modified l-sig to the one or more stas.
Inventor(s): Malini K. Bhandaru of San Jose CA (US) for intel corporation, Ned M. Smith of Beaverton OR (US) for intel corporation, Sunil K. Cheruvu of Tempe AZ (US) for intel corporation, Anahit Tarkhanyan of Cupertino CA (US) for intel corporation, Mats Agerstam of Portland OR (US) for intel corporation
IPC Code(s): H04L41/147, H04L67/12
Abstract: systems, apparatus, articles of manufacture, and methods are disclosed to monitor telemetry data in computing system. an example apparatus includes interface circuitry to obtain telemetry data; computer readable instructions; and programmable circuitry to instantiate: aggregation circuitry to analyze the telemetry data using an artificial intelligence model to detect an event; and action controller circuitry to: determine a telemetry collection resolution associated with the event; and instruct a telemetry collection operation associated with the telemetry data to adjust collection of the telemetry data according to the determined telemetry collection resolution.
Inventor(s): Zongrui DING of Portland OR (US) for intel corporation, Qian LI of Beaverton OR (US) for intel corporation, Ching-Yu LIAO of Portland OR (US) for intel corporation, Alexandre Saso STOJANOVSKI of Paris (FR) for intel corporation, Sudeep PALAT of Cheltenham (GB) for intel corporation, Thomas LUETZENKIRCHEN of Taufkirchen (DE) for intel corporation, Abhijeet KOLEKAR of Portland OR (US) for intel corporation, Sangeetha BANGOLAE of Portland OR (US) for intel corporation, Youn Hyoung HEO of Seoul (KR) for intel corporation, Xiaopeng TONG of Beijing (CN) for intel corporation
IPC Code(s): H04L45/0377, H04L45/50
Abstract: this disclosure describes systems, methods, and devices related to service function chaining in wireless networks. a communications system may include a communication control function to select one or multiple communication service functions associated with establishing service function chaining (sfc) services for telecommunications; a service orchestration and chaining function (socf) to establish the sfc services; and a service orchestration exposure function (soef) to expose the sfc services to an application function (af) of the system.
Inventor(s): Zongrui DING of Portland OR (US) for intel corporation, Qian LI of Portland OR (US) for intel corporation, Alexandre Saso STOJANOVSKI of Paris (FR) for intel corporation, Sudeep PALAT of Cheltenham (GB) for intel corporation, Thomas LUETZENKIRCHEN of Taufkirchen (DE) for intel corporation, Abhijeet KOLEKAR of Portland OR (US) for intel corporation, Ching-Yu LIAO of Portland OR (US) for intel corporation, Sangeetha BANGOLAE of Portland OR (US) for intel corporation, Youn Hyoung HEO of Seoul (KR) for intel corporation, Xiaopeng TONG of Beijing (CN) for intel corporation
IPC Code(s): H04L45/655, H04L69/22, H04W40/02
Abstract: this disclosure describes systems, methods, and devices related to service function chaining classification in wireless networks. a communications network system may include a first cellular network device configured to: receive service data adaptation protocol (sdap) data from a user equipment (ue) device, the sdap data comprising a sdap header; identify a service chaining function (sfc) service identifier of the sdap header; determine that the sfc service identifier is indicative of a sfc service profile, the sfc service profile indicative of quality of service (qos) traffic characteristics; identify a sfc traffic flow associated with the sfc service identifier; and transmit the sdap data to a second cellular network device; and wherein the second cellular network device is configured to: receive the sdap data from the first cellular network device; and transmit the sdap data to a service function of the system.
Inventor(s): Ozgur Oyman of Palo Alto CA (US) for intel corporation, Gang Shen of Hillsboro OR (US) for intel corporation, Wenqing Fu of Portland OR (US) for intel corporation, Wei Zong of Beijing (CN) for intel corporation, Juan Zhao of Shanghai (CN) for intel corporation
IPC Code(s): H04L65/65, G06T7/80, H04L65/61, H04L67/141, H04L67/142
Abstract: various embodiments herein provide techniques for session description protocol (sdp)-based signaling of camera calibration parameters for multiple video streams. in embodiments, a device may receive an sdp attribute to indicate that a bitstream included in a real-time transport protocol (rtp)-based media stream includes camera calibration parameters. the device may obtain the camera calibration parameters based on the sdp attribute, and process the rtp-based media stream based on the camera calibration parameters. in embodiments, the camera calibration parameters may be used to stitch together (e.g., align and/or synchronize) the multiple video streams. in embodiments, the stitched video streams may form an immersive video content (e.g., 360-degree video content). other embodiments may be described and claimed.
Inventor(s): Dong HAN of San Jose CA (US) for intel corporation, Bishwarup MONDAL of San Ramon CA (US) for intel corporation, Youn Hyoung HEO of Seoul (KR) for intel corporation, Guotong WANG of Beijing (CN) for intel corporation, Yujian ZHANG of Beijing (CN) for intel corporation, Alexei DAVYDOV of Nizhny Novgorod (RU) for intel corporation, Seunghee HAN of San Jose CA (US) for intel corporation
IPC Code(s): H04W52/36, H04W52/08, H04W52/24, H04W52/42
Abstract: the disclosure is directed to systems and methods systems and methods for a user equipment and a power headroom report including detecting a triggering of a plurality of pathloss references from a plurality of transmission reception points (trps) between activation of successive power headroom reporting instances: tracking a power headroom concurrently for the plurality of trps during multiple transmission reception point (mtrp) operation to enable power headroom reporting for each respective trp: tracking power headroom concurrently for each trp of the plurality of trps in use during mtrp operation upon detection of the triggering of the plurality of pathloss references: and providing a power headroom determination and a power headroom report to each of the plurality of trps in use during mtrp operation based on the triggered plurality of pathloss references.
Inventor(s): Marta Martinez Tarradell of Portland OR (US) for intel corporation, Sudeep Palat of Cheltenham (GB) for intel corporation, Jaemin Han of Santa Clara CA (US) for intel corporation
IPC Code(s): H04W68/02, H04W76/27
Abstract: the present disclosure is generally related to wireless and cellular communication, communication system implementations, and in particular, to support for mobile terminated small data transmission (mt-sdt) in 5g systems (5gs). a ue initiates a radio resource control (rrc) resume procedure with a resume cause value of “mt-sdt” in an rrc resume request when a mobile terminated small data transmission (mt-sdt) indication for the ue is included in a received paging message and a set of conditions for initiating mt-sdt have been fulfilled. the ue initiates the rrc resume procedure with a resume cause value of “mt-access” in the rrc resume request message when the set of conditions for initiating mt-sdt have not been fulfilled. other embodiments may be described and/or claimed.
Inventor(s): Dave CAVALCANTI of Portland OR (US) for intel corporation, Javier PEREZ-RAMIREZ of North Plains OR (US) for intel corporation, Juan FANG of Portland OR (US) for intel corporation, Susruth SUDHAKARAN of Portland OR (US) for intel corporation, Mark EISEN of Beaverton OR (US) for intel corporation, Mikhail GALEEV of Beaverton OR (US) for intel corporation
IPC Code(s): H04W72/0446, H04W28/02, H04W72/51, H04W84/12
Abstract: this disclosure describes systems, methods, and devices related to enhanced time-sensitive networking (tsn) configuration. a device may identify a frame received from a tsn domain comprising wired and wireless tsn traffic. the device may decode the frame to extract one or more fields, wherein the one or more fields comprise bridge parameters. the device may determine based on the bridge parameters whether a port associated with the device is wireless capable.
Inventor(s): Yingyang Li of Beijing (CN) for intel corporation, Yi Wang of Beijing (CN) for intel corporation, Gang Xiong of Beaverton OR (US) for intel corporation, Daewon Lee of Portland OR (US) for intel corporation, Debdeep Chatterjee of San Jose CA (US) for intel corporation
IPC Code(s): H04W72/1273, H04L1/1812, H04L27/26, H04W72/0457, H04W72/1268, H04W72/232
Abstract: a computer-readable storage medium stores instructions to configure a ue for cross-carrier scheduling of data transmissions in a 5g nr and beyond wireless network, and to cause the ue to perform operations including decoding configuration signaling received from a base station. the configuration signaling indicates a first numerology parameter for a scheduling cell of the base station and a second numerology parameter for a scheduled cell of the base station. dci is received via a pdcch of the scheduling cell. the dci schedules a dl data transmission in the scheduled cell of the base station. the dl data transmission is received via a pdsch of the scheduled cell when a difference between the first numerology parameter and the second numerology parameter is smaller than or equal to a pre-configured numerology threshold value. the ue refrains from decoding the dl data transmission when the difference is greater than the threshold value.
20240188097.DEFAULT BEAM OPERATIONS FOR UPLINK TRANSMISSIONS_simplified_abstract_(intel corporation)
Inventor(s): Guotong Wang of Beijing (CN) for intel corporation, Alexei Davydov of Nizhny Novgorod (RU) for intel corporation, Bishwarup Mondal of San Ramon CA (US) for intel corporation
IPC Code(s): H04W72/232, H04B7/024, H04B7/06, H04L5/00, H04W72/044
Abstract: various embodiments herein may relate to default beam operations for uplink transmissions. in particular, some embodiments are directed to default beam operations for physical uplink shared channel (pusch), physical uplink control channel (pucch) or sounding reference signal (srs) transmissions in multi-transmission reception point (trp) scenarios. other embodiments may be disclosed or claimed.
Inventor(s): Mohammad Mamunur Rahman of Gilbert AZ (US) for intel corporation, Brandon Christian Marin of Gilbert AZ (US) for intel corporation, Gang Duan of Chandler AZ (US) for intel corporation, Srinivas V. Pietambaram of Chandler AZ (US) for intel corporation, Suddhasattwa Nad of Chandler AZ (US) for intel corporation, Rahul Manepalli of Chandler AZ (US) for intel corporation
IPC Code(s): H05K1/02, H01L23/00, H01L23/427, H01L23/498, H05K1/11, H05K3/46
Abstract: in one embodiment, an integrated circuit package substrate includes a core layer and a plurality of build-up layers on the core layer, each build-up layer comprising a dielectric and metal. the package substrate also includes a cavity, wherein a first portion of the cavity is defined in a first build-up layer, a second portion of the cavity is defined in a second build-up layer, and a third portion of the cavity connects the first portion with the second portion through at least one layer other than first build-up layer and the second build-up layer.
20240188222.METHOD OF FORMING A PACKAGE SUBSTRATE_simplified_abstract_(intel corporation)
Inventor(s): Rahul MANEPALLI of Chandler AZ (US) for intel corporation, Srinivas PIETAMBARAM of Chandler AZ (US) for intel corporation, Darko GRUJICIC of Chandler AZ (US) for intel corporation, Marcel WALL of Phoenix AZ (US) for intel corporation, Jason STEILL of Phoenix AZ (US) for intel corporation
IPC Code(s): H05K3/22, H05K1/03, H05K1/11, H05K3/00
Abstract: the present disclosure is directed to a method providing a substrate core having a glass core layer with top and bottom surfaces and a build-up process performing operations to form a plurality of through-glass vias formed through the glass core layer and a plurality of conductive layers on the top and bottom surfaces of the glass core layer. as an integral part of the build-up process, a defect detection method may be used to detect defects in the glass core layer. the inspection for defects may be performed after selected operations. after one or more defect (e.g., crack) is uncovered, a repair process may be performed to repair the defects in the glass core layer. the repair of a defect may be performed immediately upon detection or after selected operations as a comprehensive repair of a group of defects.
20240188223.MATERIAL DEPOSITION APPARATUS AND METHOD_simplified_abstract_(intel corporation)
Inventor(s): Zhixin XIE of Chandler AZ (US) for intel corporation, Jung Kyu HAN of Chandler AZ (US) for intel corporation, Gang DUAN of Chandler AZ (US) for intel corporation
IPC Code(s): H05K3/28, B29C70/70
Abstract: there may be provided an apparatus. the apparatus may include a first dispensing unit and a second dispensing unit. the apparatus may further include a connection assembly coupled to the first dispensing unit and the second dispensing unit in a manner such that a position of the first dispensing unit or the second dispensing unit relative to the other of said first dispensing unit or second dispensing unit may be adjustable via the connection assembly.
Inventor(s): Vinith BEJUGAM of Chandler AZ (US) for intel corporation, Rengarajan SHANMUGAM of Tempe AZ (US) for intel corporation, Srinivas PIETAMBARAM of Chandler AZ (US) for intel corporation, Mao-Feng TSENG of Tempe AZ (US) for intel corporation, Yonggang LI of Chandler AZ (US) for intel corporation
IPC Code(s): H05K3/40, C23C18/18, C23C18/38, H05K1/03, H05K1/11, H05K3/18
Abstract: a method for manufacturing a structured substrate is provided, the method including: forming a plurality of openings extending from a first surface of a substrate towards a second surface of the substrate, wherein the first surface is coplanar to the second surface, wherein the substrate comprises glass, and wherein each of the openings comprises a sidewall; forming a first layer at least on the sidewall of the openings; forming a second layer on the first layer, wherein the second layer comprises titanium; and depositing metal on the second layer to at least partially fill the openings.
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