Intel Corporation patent applications on June 27th, 2024
Patent Applications by Intel Corporation on June 27th, 2024
Intel Corporation: 88 patent applications
Intel Corporation has applied for patents in the areas of H01L23/00 (10), H01L23/498 (10), H01L23/538 (9), H01L25/065 (8), G06F9/30 (6) H01L23/5389 (3), G06F9/30145 (2), H03M1/0604 (2), H04W72/1268 (2), H04L5/005 (1)
With keywords such as: layer, signal, based, die, substrate, circuit, data, memory, embodiment, and device in patent application abstracts.
Patent Applications by Intel Corporation
20240210185.ENTITY ALLOCATION FOR NAVIGATED ROUTES_simplified_abstract_(intel corporation)
Inventor(s): Raghavendra Bhat of Bangalore (IN) for intel corporation, Pravin Chander Chandran of Fremont CA (US) for intel corporation, Sean Lawrence of Bangalore (IN) for intel corporation
IPC Code(s): G01C21/34, G01C21/36
CPC Code(s): G01C21/3461
Abstract: techniques are provided to calculate a “complexity score” (cs) and qualifying allocation score, which aims to address the gap between a performance score, which may represent a driver score of other suitable entity-based performance score. the cs may be calculated based upon the particular agent (e.g. a vehicle, an autonomous mobile robot (amr), etc.), such as via the use of vehicle-based alerts, other types of alerts, environment-based data, etc., which are collected for specific navigation segments. the cs is then combined with the performance score to provide a qualifying allocation score, which is a context-sensitive view of the performance score. this context-sensitive view of the performance score may then be utilized for a determination regarding how to allocate the most well-suited entity (a driver, vehicle, amr, etc.) to a subsequent route that includes the navigation segments.
Inventor(s): Andres MALDONADO of Beaverton OR (US) for intel corporation, Steve HERNDON of Chandler AZ (US) for intel corporation, Thomas POMPL of Landshut (DE) for intel corporation
IPC Code(s): G01R31/28, H01L21/66
CPC Code(s): G01R31/2879
Abstract: this disclosure describes systems, methods, and devices related to testing an integrated circuit for defects. a method may include applying a nominal voltage to the integrated circuit for a first time period; applying a dynamic voltage greater than the nominal voltage to the integrated circuit for a second time period after the first time period; applying a static voltage greater than the dynamic voltage to the integrated circuit for a third time period after the second time period, wherein the static voltage is a target static voltage less than a target voltage; and applying the dynamic voltage to the integrated circuit during a fourth time period after the third time period.
Inventor(s): Nir BONE of Afula (IL) for intel corporation, David TURJEMAN of Zikhron Ya'akov (IL) for intel corporation, Hussein DEEB of Judaida Macker (IL) for intel corporation
IPC Code(s): G01R31/3177, G06F30/333
CPC Code(s): G01R31/3177
Abstract: this disclosure describes systems, methods, and devices related to diagnose a broken scan chain and isolate the broken cell. a device may perform a functional test on a plurality of central processing unit (cpu) cells in a chain. the device may propagate data through a combinatoric logic. the device may capture results in sequential flip-flops associated with scan. the device may utilize the results in a next combinatoric logic. the device may utilize shifted-out data to isolate a first broken cell based on the functional test.
20240210536.TIME OF FLIGHT DISTANCE DETERMINATIONS_simplified_abstract_(intel corporation)
Inventor(s): Shabbir AHMED of Beaverton OR (US) for intel corporation, Vuk LESI of Cornelius OR (US) for intel corporation, Christopher Noe GUTIERREZ of Hillsboro IN (US) for intel corporation, Ignacio J. ALVAREZ of Portland OR (US) for intel corporation
IPC Code(s): G01S7/4865, G01S17/14
CPC Code(s): G01S7/4865
Abstract: a device includes a sensor, configured to detect electromagnetic radiation originating from a source external to the device and reflected from an object; and to generate an electrical signal representing the detected electromagnetic radiation; and a processor, configured to determine a distance between the device and the object based on the electrical signal.
Inventor(s): Zhixin XIE of Chandler AZ (US) for intel corporation, Jung Kyu HAN of Chandler AZ (US) for intel corporation, Gang DUAN of Chandler AZ (US) for intel corporation
IPC Code(s): G02B6/42, G02B1/04, G02B3/00
CPC Code(s): G02B6/4206
Abstract: embodiments disclosed herein include a package substrate. in an embodiment, the package substrate comprises a substrate and an optical fiber in the substrate. in an embodiment, a lens is optically coupled to the optical fiber. in an embodiment, the lens is a gradient index (grin) lens.
Inventor(s): Charles Cameron Mokhtarzadeh of Portland OR (US) for intel corporation, James Blackwell of Portland OR (US) for intel corporation, Scott Semproni of Portland OR (US) for intel corporation, Scott B. Clendenning of Portland OR (US) for intel corporation, Lauren Elizabeth Doyle of () for intel corporation
IPC Code(s): G03F7/00, G03F7/038, G03F7/16, G03F7/20, G03F7/40
CPC Code(s): G03F7/0032
Abstract: precursors and methods related to a bismuth oxy-carbide-based photoresist are disclosed herein. in some embodiments, a method for forming a bismuth oxy-carbide-based photoresist may include exposing a bismuth-containing precursor and a co-reagent to a substrate to form a bismuth oxy-carbide-based photoresist having a formula biocon the substrate, where x is 1 or 2, y is between 2 and 4, and z is between 1 and 5, the bismuth-containing precursor having a formula r′bi(nr)or r′binrwhere r includes methyl, ethyl, isopropyl, tert-butyl, or trimethylsilyl, or nris piperidine, and r′ includes methyl, ethyl, isopropyl, tert-butyl, cyclo-pentyl, cyclo-hexyl, methyl trimethylsilyl, methyl 2-butyl, benzyl, 1-methyl 2-dimethyl propyl, or cyclopentadienyl. in some embodiments, the co-reagent includes water, hydrogen peroxide, oxygen, ozone, formic acid, maleic acid, or an alcohol.
Inventor(s): Joseph Bloxham of Laveen AZ (US) for intel corporation
IPC Code(s): G03F7/40, G03F7/20, G03F7/32
CPC Code(s): G03F7/40
Abstract: systems, apparatuses, and methods related to reducing the degradation of recycled developer solution are disclosed herein. in some embodiments, an apparatus may include a developer chamber, a process tank including a developer solution, a delivery stream coupling the process tank and the developer chamber to flow developer solution from the process tank to the developer chamber, a return stream coupling the developer chamber and the process tank to flow developer solution from the developer chamber to the process tank; and a light source exposing the developer solution to uv light or white light, wherein the light source exposes the developer solution to uv light or white light in the process tank, in the return stream, or the delivery stream.
Inventor(s): David Pidwerbecki of Portland OR (US) for intel corporation, Arvind S of Bangalore (IN) for intel corporation, Jeff Ku of Taipei City (TW) for intel corporation, Juha Tapani Paavola of Hillsboro OR (US) for intel corporation, Prakash Kurma Raju of Bangalore (IN) for intel corporation, Amruta Krishnakumar Ranade of Bengaluru (IN) for intel corporation, Sudheera Sudhakar of Bangalore (IN) for intel corporation, Mousumi Deka of Bangalore (IN) for intel corporation, Snehal Chaudhari of Bangalore (IN) for intel corporation, Akarsha R. Kadadevaramath of Tumkur (IN) for intel corporation
IPC Code(s): G06F1/16, B32B5/02, B32B5/26, C23C14/20, C23C14/35, C23C16/06
CPC Code(s): G06F1/1615
Abstract: systems, apparatus, articles of manufacture, and methods are disclosed related to composite materials for electronic device chassis. an example electronic device includes a chassis including a layer of a magnesium alloy or a layer of polyether ether ketone and carbon fiber reinforced plastic and an anodized aluminum coating.
Inventor(s): Vijay Anand MATHIYALAGAN of Austin TX (US) for intel corporation, Michelle M. WIGTON of Timnath CO (US) for intel corporation
IPC Code(s): G06F1/3234, G06F1/3228
CPC Code(s): G06F1/3275
Abstract: a system includes a resource controller that can determine if a memory has been idle for longer than a threshold. the resource controller is at the system level, above the memory subsystem. in response to determining the memory has been idle for at least the threshold, the resource controller can trigger the memory controller to send a shallow self-refresh command, which is self-refresh without clock stop.
Inventor(s): Gregory HENRY of Hillsboro OR (US) for intel corporation, Alexander HEINECKE of San Jose CA (US) for intel corporation
IPC Code(s): G06F9/30, G06F1/16, G06F7/483, G06F7/485, G06F7/487, G06F7/53, G06F7/544, G06F17/16
CPC Code(s): G06F9/30014
Abstract: embodiments detailed herein relate to arithmetic operations of float-point values. an exemplary processor includes decoding circuitry to decode an instruction, where the instruction specifies locations of a plurality of operands, values of which being in a floating-point format. the exemplary processor further includes execution circuitry to execute the decoded instruction, where the execution includes to: convert the values for each operand, each value being converted into a plurality of lower precision values, where an exponent is to be stored for each operand; perform arithmetic operations among lower precision values converted from values for the plurality of the operands; and generate a floating-point value by converting a resulting value from the arithmetic operations into the floating-point format and store the floating-point value.
20240211253.ACCELERATING KECCAK ALGORITHMS_simplified_abstract_(intel corporation)
Inventor(s): Santosh Ghosh of Hillsboro OR (US) for intel corporation, Christoph Dobraunig of St. Veit an der Glan (AT) for intel corporation, Manoj Sastry of Portland OR (US) for intel corporation, Andrew H. Reinders of Portland OR (US) for intel corporation, Regev Shemy of Kiryat Ata (IL) for intel corporation, Qian Wang of Portland OR (US) for intel corporation, Rotem Ohana Peretz of Kfar Zeitim Lower Galili (IL) for intel corporation, Wing Shek Wong of Austin TX (US) for intel corporation, Wajdi Feghali of Boston MA (US) for intel corporation
IPC Code(s): G06F9/30, G06F9/38
CPC Code(s): G06F9/30029
Abstract: a method comprises fetching, by fetch circuitry, an encoded parity instruction comprising at least one opcode, a first source identifier for a first source, a second source identifier for a second source, a third source identifier for a third source, and a destination identifier for a destination, decoding, by decode circuitry, the encoded parity instruction to generate a decoded parity instruction; and executing, by execution circuitry, the decoded parity instruction to retrieve operands representing a first register from the first source, a second register from the second source, a third register from the third source, and an index from the third source, perform an xor operation of four words of data from the first register and single word of data from the second register in a position represented by the index to generate a parity value, and store the parity value in a the first register in a position represented by the index.
Inventor(s): Yuvraj Dhillon of Hillsboro OR (US) for intel corporation, Doddaballapur Jayasimha of Saratoga CA (US) for intel corporation, Aravindh V. Anantaraman of Folsom CA (US) for intel corporation, Yongsheng Liu of San Diego CA (US) for intel corporation
IPC Code(s): G06F9/30, G06F11/34, G06F12/02
CPC Code(s): G06F9/30047
Abstract: remote atomics for clustered processing operations are described. an example of a graphics processor includes a clustered processing architecture including multiple clusters and one or more memory elements, including a first memory element containing a home agent, the apparatus to receive, at a first caching agent for a first cluster, a request for performance of an atomic operation requiring a data stored in a cacheline at a memory address associated with the home agent; evaluate one or more factors including a current ownership of the memory address; and, based at least in part on the factors, determine whether to perform the atomic operation at the first caching agent or to forward the atomic operation to the home agent for performance of the atomic operation.
Inventor(s): Santosh Ghosh of Hillsboro OR (US) for intel corporation, Christoph Dobraunig of St. Veit an der Glan (AT) for intel corporation, Manoj Sastry of Portland OR (US) for intel corporation
IPC Code(s): G06F9/30
CPC Code(s): G06F9/30145
Abstract: a method comprises fetching, by fetch circuitry, an encoded xor3p instruction comprising at least one opcode, a first source identifier to identify a first register, a second source identifier to identify a second register, a third source identifier to identifier a third register, and a fourth source identifier to identify a fourth operand, wherein the first register is to store a first value, the second register is to store a second value, and the third register is to store a third value, decoding, by decode circuitry, the encoded xor3p instruction to generate a decoded xor3p instruction, and executing, by execution circuitry, to execute the decoded xor3p instruction to perform a rotate operation on the third value based on the fourth operand to generate a rotated third value, perform an xor operation on the first value, the second value, and the rotated third value to generate an xor result, perform a rotate operation on the xor result based on the fourth operand to generate a rotated xor, and store the rotated xor result.
Inventor(s): Ahmad YASIN of Haifa (IL) for intel corporation, Raanan SADE of Portland OR (US) for intel corporation, Liron ZUR of Haifa (IL) for intel corporation, Igor YANOVER of Yokneam Illit (IL) for intel corporation, Joseph NUZMAN of Haifa (IL) for intel corporation
IPC Code(s): G06F9/30, G06F9/54, G06F11/30, G06F11/34
CPC Code(s): G06F9/30145
Abstract: systems, methods, and apparatuses relating to circuitry to precisely monitor memory store accesses are described. in one embodiment, a system includes a memory, a hardware processor core comprising a decoder to decode an instruction into a decoded instruction, an execution circuit to execute the decoded instruction to produce a resultant, a store buffer, and a retirement circuit to retire the instruction when a store request for the resultant from the execution circuit is queued into the store buffer for storage into the memory, and a performance monitoring circuit to mark the retired instruction for monitoring of post-retirement performance information between being queued in the store buffer and being stored in the memory, enable a store fence after the retired instruction to be inserted that causes previous store requests to complete within the memory, and on detection of completion of the store request for the instruction in the memory, store the post-retirement performance information in storage of the performance monitoring circuit.
20240211268.ACCELERATING EIGHT-WAY PARALLEL KECCAK EXECUTION_simplified_abstract_(intel corporation)
Inventor(s): Santosh Ghosh of Hillsboro OR (US) for intel corporation, Christoph Dobraunig of St. Veit an der Glan (AT) for intel corporation, Manoj Sastry of Portland OR (US) for intel corporation
IPC Code(s): G06F9/38, G06F9/30
CPC Code(s): G06F9/3885
Abstract: a method comprises fetching, by fetch circuitry, an encoded xor3p instruction comprising at least one opcode, a first source identifier to identify a first register, a second source identifier to identify a second register, a third source identifier to identifier a third register, and a fourth source identifier to identify a fourth operand, wherein the first register is to store a first value, the second register is to store a second value, and the third register is to store a third value, decoding, by decode circuitry, the encoded xor3pp instruction to generate a decoded xor3pp instruction; and executing, by execution circuitry, the decoded xor3pp instruction to determine a first rotational value and a second rotational value, perform a rotate operation on at least a portion of the first value based on the first rotational value to generate a rotated third value, perform an xor operation on at least a portion of the first value, at least a portion of the second value, and the rotated third value to generate an xor result, perform a rotate operation on the xor result based on the second rotational value to generate a rotated xor; and store the rotated xor result.
Inventor(s): Zhao LIU of Shanghai (CN) for intel corporation, Zhenyu WANG of Shanghai CA (US) for intel corporation
IPC Code(s): G06F9/455
CPC Code(s): G06F9/45558
Abstract: a method for a primary virtual machine (vm) to schedule a sibling vm task executed by a hypervisor. upon request of the sibling vm, the hypervisor creates a sibling task which includes a hypervisor id. the hypervisor id is then communicated to the primary vm. subsequently, the primary vm creates a broker task, identified by its broker id, and based on the received hypervisor id for the sibling vm task. the primary vm then communicates to the hypervisor a mapping of the broker id to the corresponding hypervisor id. finally, the primary vm executes the broker task when instructed by a scheduler of the primary vm. the broker task then triggers the hypervisor to run the corresponding sibling task based on the mapping.
Inventor(s): Francesc Guim Bernat of Barcelona (ES) for intel corporation, Kshitij A. Doshi of Tempe AZ (US) for intel corporation, Daniel Rivas Barragan of Cologne, NW (DE) for intel corporation, Alejandro Duran Gonzalez of Esplugues de Llobregat (ES) for intel corporation, Harald Servat of Barcelona (ES) for intel corporation
IPC Code(s): G06F9/50, H04L45/745, H04L61/103, H04L67/1004, H04L67/1097, H04L67/51, H04L67/566, H04W8/22
CPC Code(s): G06F9/5005
Abstract: technologies for dynamically sharing remote resources include a computing node that sends a resource request for remote resources to a remote computing node in response to a determination that additional resources are required by the computing node. the computing node configures a mapping of a local address space of the computing node to the remote resources of the remote computing node in response to sending the resource request. in response to generating an access to the local address, the computing node identifies the remote computing node based on the local address with the mapping of the local address space to the remote resources of the remote computing node and performs a resource access operation with the remote computing node over a network fabric. the remote computing node may be identified with system address decoders of a caching agent and a host fabric interface. other embodiments are described and claimed.
Inventor(s): Divya GUPTA of Hillsboro OR (US) for intel corporation, Shubhada PUGAONKAR of Portland OR (US) for intel corporation, Raed AL-OMARI of Round Rock TX (US) for intel corporation, Mariecel TORRES-YOUNG of Portland OR (US) for intel corporation, Ayman G. ABDO of Lake Oswego OR (US) for intel corporation, John R. AYERS of Portland OR (US) for intel corporation, Chih-Cheh CHEN of Portland OR (US) for intel corporation, Wilfredo FIGUEROA MARTINEZ of Hillsboro OR (US) for intel corporation, Girish CHANDRASEKARAN of Hillsboro OR (US) for intel corporation
IPC Code(s): G06F11/07
CPC Code(s): G06F11/0772
Abstract: examples include techniques to collecting and providing error related information for a multi-die system-on-a-chip (soc) computing system following a critical or catastrophic error. examples include circuitry on a first die that is configured to receive an indication of a critical or catastrophic error and cause error related information to be stored to a volatile memory at the first die that is arranged to continually maintain power during a global reset of the soc. the circuitry can also be configured to provide the stored error related information to a requestor following the global reset of the soc.
Inventor(s): Kuljit S. BAINS of Olympia WA (US) for intel corporation, Kjersten E. CRISS of Portland OR (US) for intel corporation, Rajat AGARWAL of Portland OR (US) for intel corporation, Omar AVELAR SUAREZ of Zapopan (MX) for intel corporation, Subhankar PANDA of Portland OR (US) for intel corporation, Theodros YIGZAW of Sherwood OR (US) for intel corporation, Rebecca Z. LOOP of Portland OR (US) for intel corporation, John G. HOLM of Beaverton OR (US) for intel corporation, Gaurav PORWAL of Portland OR (US) for intel corporation
IPC Code(s): G06F11/10, G11C29/02
CPC Code(s): G06F11/106
Abstract: a memory subsystem with error checking and scrubbing (ecs) logic on-device on the memory can adapt the rate of ecs operations in response to detection of errors in the memory when the memory device is in automatic ecs mode. the ecs logic can include an indication of rows of memory that have been offlined by the host. the ecs logic can skip the offlined rows in ecs operation counts. the ecs logic can include requests or hints by the host to have ecs operations performed. an internal address generator of the ecs logic can select between generated addresses and the hints. the system can allow a memory controller to detect multibit errors (mbes) related to a specific address of the associated memory. when the detected mbes indicate a pattern of errors, the memory controller triggers a row hammer response for the specific address.
20240211392.BUFFER ALLOCATION_simplified_abstract_(intel corporation)
Inventor(s): Salma Mirza JOHNSON of Littleton MA (US) for intel corporation, Jose NIELL of Franklin MA (US) for intel corporation, Bradley A. BURRES of Newton MA (US) for intel corporation, Jackson ELLIS of Fort Collins CO (US) for intel corporation, Yadong LI of Portland OR (US) for intel corporation, Jayaram BHAT of Cedar Park TX (US) for intel corporation, Tony HURSON of Austin TX (US) for intel corporation
IPC Code(s): G06F12/02
CPC Code(s): G06F12/0246
Abstract: examples described herein relate to circuitry to allocate an non-volatile memory express (nvme) bounce buffer in virtual memory that is associated with an nvme command and perform an address translation to an nvme bounce buffer based on receipt of a response to the nvme command from an nvme target. in some examples, the circuitry is to translate the virtual address to a physical address for the nvme bounce buffer based on receipt of a response to the nvme command from an nvme target.
Inventor(s): Israel Diamand of Aderet M (IL) for intel corporation, Randy B. Osborne of Beaverton OR (US) for intel corporation, Aravindh V. Anantaraman of Folsom CA (US) for intel corporation, Nadav Bonen of Ofer Z (IL) for intel corporation
IPC Code(s): G06F12/0815
CPC Code(s): G06F12/0815
Abstract: in one embodiment, a semiconductor package comprises: a first die comprising: a plurality of cores; and memory circuitry comprising a memory controller and a memory side cache controller to maintain tag information and state information for a data array; and a second die coupled to the first die, the second die comprising the data array to cache data for at least one accelerator, the at least one accelerator remote from the first die. the memory side cache controller may be configured to control the data array. other embodiments are described and claimed.
20240211403.LOAD STORE MICROARCHITECTURE CACHE ENHANCEMENTS_simplified_abstract_(intel corporation)
Inventor(s): Abhishek R. Appu of El Dorado Hills CA (US) for intel corporation, Joydeep Ray of Folsom CA (US) for intel corporation, Karthik Vaidyanathan of San Francisco CA (US) for intel corporation, Sreedhar Chalasani of Folsom CA (US) for intel corporation, Eric Liskay of Folsom CA (US) for intel corporation, Prathamesh Raghunath Shinde of Folsom CA (US) for intel corporation, Vasanth Ranganathan of El Dorado Hills CA (US) for intel corporation, Michael J. Norris of Folsom CA (US) for intel corporation, Rajasekhar Pantangi of Fremont CA (US) for intel corporation, Altug Koker of El Dorado Hills CA (US) for intel corporation
IPC Code(s): G06F12/0837, G06F12/0811
CPC Code(s): G06F12/0837
Abstract: one embodiment provides a graphics processor comprising memory access circuitry configured to generate a virtual address for pixel data at a pixel coordinate on a surface in memory to facilitate the caching of the pixel data in a cache memory before the actual memory address of the pixel coordinate is able to be determined.
Inventor(s): JOYDEEP RAKSHIT of Bengaluru (IN) for intel corporation, ANANT VITHAL NORI of Banglore (IN) for intel corporation, SREENIVAS SUBRAMONEY of Bangalore (IN) for intel corporation, HANNA ALAM of Jish (IL) for intel corporation, JOSEPH NUZMAN of Haifa (IL) for intel corporation
IPC Code(s): G06F12/0891, G06F12/1009
CPC Code(s): G06F12/0891
Abstract: apparatus and method for probabilistic cacheline replacement for accelerating address translation. for example, one embodiment of a processor comprises: a plurality of cores, each core to process instructions; a cache to be shared by a subset of the plurality of cores, the cache comprising an n-way set associative cache for storing page table entry (pte) cachelines and non-pte cachelines; and a cache manager to implement a pte-aware eviction policy for evicting cachelines from the cache, the pte-aware eviction policy to cause a reduction of evictions of pte cachelines during non-pte cacheline fills.
Inventor(s): Marius Arvinte of Portland OR (US) for intel corporation, Brandon Edwards of Portland OR (US) for intel corporation, Cory Cornelius of Portland OR (US) for intel corporation, Jason Martin of Beaverton OR (US) for intel corporation, Sebastian Szyller of Helsinki (FI) for intel corporation, Micah Sheller of Hillsboro OR (US) for intel corporation, Nageen Himayat of Danville CA (US) for intel corporation
IPC Code(s): G06F21/10
CPC Code(s): G06F21/101
Abstract: an example apparatus includes interface circuitry, machine-readable instructions, and at least one processor circuit to be programmed by the machine-readable instructions to access a first set of samples associated with a diffusion model, the first set of samples including a plurality of input data samples, generate a representation of the first set of samples, sample the representation of the first set of samples to generate a representation of a second set of samples, and generate the second set of samples from the representation of the second set of samples, the second set of samples including a plurality of output data samples, an output data sample corresponding to an input data sample and being different from the corresponding input data sample.
Inventor(s): Alexander EYDELBERG of Daly City CA (US) for intel corporation, Salessawi Ferede YITBAREK of Hillsboro OR (US) for intel corporation, David B. SHEFFIELD of Portland OR (US) for intel corporation, Xiang ZOU of Portland OR (US) for intel corporation
IPC Code(s): G06F21/45
CPC Code(s): G06F21/45
Abstract: an apparatus and method for improved processor security and authenticated code execution. for example, one embodiment of a processor comprises: a secure memory to store an authenticated code module (acm); and security hardware logic to select a mode of operation for processing the acm based on a microarchitecture of the processor, the security hardware logic to validate the acm and parse a header of the acm to determine an entry point for processing the acm in accordance with the microarchitecture.
Inventor(s): Rita CHATTOPADHYAY of Chandler AZ (US) for intel corporation, Stanley MO of Portland OR (US) for intel corporation, Matias ALMADA of South Lake Tahoe CA (US) for intel corporation, Steven KREBS of Maricopa AZ (US) for intel corporation
IPC Code(s): G06N3/045
CPC Code(s): G06N3/045
Abstract: a computer-implemented system, platform, device, and method of audio processing comprises receiving, by processor circuitry, a mixed audio signal having a plurality of audio sources, and separating the mixed audio signal into at least one separate target audio source signal; and determining whether or not the at least one separate target audio source signal is associated with at least one target audio source. this also comprises inputting at least one of the separate target audio source signals into a classifying neural network.
20240211774.GEOGRAPHIC HEAT OR COLD DISTRIBUTION MODEL_simplified_abstract_(intel corporation)
Inventor(s): Cornelius Buerkle of Karlsruhe (DE) for intel corporation, Ignacio Alvarez of Portland OR (US) for intel corporation, Fabian Oboril of Karlsruhe (DE) for intel corporation, Frederik Pasch of Karlesruhe (DE) for intel corporation
IPC Code(s): G06N5/022
CPC Code(s): G06N5/022
Abstract: an apparatus, including: an interface operable to receive heat factor information for a geographic area; processing circuitry operable to: generate a digital twin of the geographic area, wherein the digital twin is a virtual representation of the geographic area, and based on the received heat factor information, spawns a heat distribution model that mirrors a heat distribution of the geographic area; and perform an action based on the heat distribution model.
20240212083.TRAFFIC ANOMALY SCENE RECONSTRUCTION_simplified_abstract_(intel corporation)
Inventor(s): Frederik Pasch of Karlsruhe (DE) for intel corporation, Cornelius Buerkle of Karlsruhe (DE) for intel corporation, Fabian Oboril of Karlsruhe (DE) for intel corporation
IPC Code(s): G06Q50/26, G06F21/62, G08G1/01
CPC Code(s): G06Q50/265
Abstract: an apparatus, including: an interface operable to receive from traffic actors, information related to a traffic anomaly in a traffic scene; processing circuitry operable to: generate a digital twin of the traffic scene, wherein the digital twin is a virtual representation of the traffic scene; fuse the received traffic anomaly information; and reconstruct the traffic scene by the digital twin incorporating the fused traffic anomaly information.
Inventor(s): Niloufar Pourian of Los Gatos CA (US) for intel corporation
IPC Code(s): G06T5/00
CPC Code(s): G06T5/00
Abstract: this disclosure describes systems, methods, and devices related to video background matte generation. a method may include receiving, by a first neural network trained to generate alpha mattes and foreground multi-camera images, first inputs generated by a second neural network; receiving, by the first neural network, second inputs comprising grayscale images and depth maps of the multi-camera images; and generating, by the first neural network, based on the first inputs and the second inputs, multi-view alpha mattes and multi-view foreground estimates for the multi-camera images.
Inventor(s): Yuxin TIAN of Beijing (CN) for intel corporation, Xuesong SHI of Beijing (CN) for intel corporation, Peng WANG of Beijing (CN) for intel corporation, Yujie WANG of Beijing (CN) for intel corporation
IPC Code(s): G06T7/73, G06T7/11
CPC Code(s): G06T7/73
Abstract: the disclosure provides techniques for map optimization for a localization and mapping system. the map optimization method includes segmenting, based on a preset segmentation condition, a trajectory tracked by the localization and mapping system to obtain a plurality of segments of the trajectory, each segment being partitioned into a head part, an interior part and a tail part; performing a global optimization process based on frames in the head and tail parts of each segment to obtain optimized mapping results for the frames in the head and tail parts of the segment; estimating optimized mapping results for frames in the interior part of each segment based on the optimized mapping results for the frames in the head and tail parts of the segment; and updating a map built by the localization and mapping system according to the optimized mapping results for the frames in each segment.
Inventor(s): Jia BAO of Shanghai (CN) for intel corporation, Chao XIE of Shanghai (CN) for intel corporation, Yu CHEN of Shanghai City (CN) for intel corporation, Xiaocheng MAO of Shanghai (CN) for intel corporation, Changliang WANG of Bellevue WA (US) for intel corporation, Yong YAO of SAN JOSE CA (US) for intel corporation, Qiming SHI of Shanghai (CN) for intel corporation, Dongjie TANG of Shanghai (CN) for intel corporation, Hongyu ZHANG of Shanghai (CN) for intel corporation
IPC Code(s): G06T15/04, A63F13/52, A63F13/95
CPC Code(s): G06T15/04
Abstract: examples relate to a caching apparatus, a driver apparatus, a transcoding apparatus and to corresponding devices, methods, and computer programs. the caching apparatus comprises an interface for communicating with one or more cloud gaming instances and processing circuitry that is configured to obtain requests for cached transcoded versions of textures to be used in the one or more cloud gaming instances, and to provide the cached transcoded versions of the textures to the one or more cloud gaming instances.
Inventor(s): Matthew J. Prince of Portland OR (US) for intel corporation, Lawrence Zaino of Beaverton OR (US) for intel corporation, Barry B. Butler of Hillsboro OR (US) for intel corporation, Girish Sharma of Hillsboro OR (US) for intel corporation, Robert R. Mitchell of Portland OR (US) for intel corporation, Rajaram A. Pai of Lake Oswego OR (US) for intel corporation, Niels Sveum of Portland OR (US) for intel corporation, Alison V. Davis of Portland OR (US) for intel corporation, Chun Chen Kuo of Portland OR (US) for intel corporation, Reza Bayati of Portland OR (US) for intel corporation, Swapnadip Ghosh of Hillsboro OR (US) for intel corporation
IPC Code(s): H01L21/28, B24B37/04, H01L21/8238, H01L27/092, H01L29/06, H01L29/417, H01L29/423, H01L29/66, H01L29/775
CPC Code(s): H01L21/28123
Abstract: techniques are provided herein to form semiconductor devices that include a gate cut formed after the formation of source or drain contacts and with a top surface that is substantially coplanar with a top surface of the source or drain contacts. an example semiconductor device includes a gate structure around or otherwise on a semiconductor region and a dielectric layer present on a top surface of the gate structure. conductive contacts are formed over source and drain regions along a source/drain contact recess or trench. the gate structure may be interrupted with a gate cut that extends through an entire thickness of the gate structure and includes a dielectric material. a top surface of the gate cut may be polished until it is substantially coplanar with a top surface of the dielectric layer over the gate structure and a top surface of the source or drain contacts.
Inventor(s): Mark SALTAS of Chandler AZ (US) for intel corporation, Edvin CETEGEN of Chandler AZ (US) for intel corporation, Tony DAMBRAUSKAS of Chandler AZ (US) for intel corporation, Albert KAMGA of Phoenix AZ (US) for intel corporation, Mine KAYA of Scottsdale AZ (US) for intel corporation, James MELLODY of Phoenix AZ (US) for intel corporation, Rajesh Kumar NEERUKATTI of Chandler AZ (US) for intel corporation
IPC Code(s): H01L21/683, B25J15/06
CPC Code(s): H01L21/6838
Abstract: this disclosure describes nozzle designs for holding disaggregated die flat in a bonding process. the nozzle designs may have trenches extending radially outward from the center of the nozzle to the corners, such as in a snowflake pattern. the trenches may be positioned to be axially unaligned with any mold dishes of the disaggregated die when lifting the disaggregated die. the trenches may have a depth of at least 200 micrometers to allow for sufficient air flow to prevent warpage of the disaggregated die.
20240213100.METAL GATE CUT WITH HYBRID MATERIAL FILL_simplified_abstract_(intel corporation)
Inventor(s): Swapnadip Ghosh of Hillsboro OR (US) for intel corporation, Yulia Gotlib of Hillsboro OR (US) for intel corporation, Chiao-ti Huang of Portland OR (US) for intel corporation, Bishwajit Debnath of Hillsboro OR (US) for intel corporation, Anupama Bowonder of Portland OR (US) for intel corporation, Matthew J. Prince of Portland OR (US) for intel corporation
IPC Code(s): H01L21/8238, H01L21/28, H01L27/092, H01L29/06, H01L29/423, H01L29/66, H01L29/775
CPC Code(s): H01L21/823878
Abstract: techniques are provided herein to form semiconductor devices that include one or more gate cuts having a hybrid material structure. a semiconductor device includes a gate structure around or otherwise on a semiconductor region. the gate structure includes a gate dielectric and a gate electrode. the gate structure may be interrupted, for example, between two transistors with a gate cut that includes a hybrid structure having both a low-k dielectric material and a high-k dielectric material. the gate cut includes an outer layer having a high-k dielectric material and a dielectric fill on the dielectric layer having a low-k dielectric material. the inclusion of low-k dielectric material reduces the parasitic capacitance between adjacent conductive layers around or within the gate cut.
Inventor(s): Mohammad Mamunur RAHMAN of Gilbert AZ (US) for intel corporation, Je-Young CHANG of Tempe AZ (US) for intel corporation, Jeremy D. ECTON of Gilbert AZ (US) for intel corporation, Rahul N. MANEPALLI of Chandler AZ (US) for intel corporation, Srinivas V. PIETAMBARAM of Chandler AZ (US) for intel corporation, Gang DUAN of Chandler AZ (US) for intel corporation, Brandon C. MARIN of Gilbert AZ (US) for intel corporation, Suddhasattwa NAD of Chandler AZ (US) for intel corporation
IPC Code(s): H01L23/367, G06F1/20, H01L23/15, H01L23/427, H01L23/473, H01L23/498
CPC Code(s): H01L23/367
Abstract: embodiments disclosed herein include electronic packages. in an embodiment, the electronic package comprises a core with a first surface and a second surface opposite from the first surface, and where the core comprises glass. in an embodiment, a channel is disposed into the first surface of the core, and a lid is provided over the channel. in an embodiment, the lid seals the channel between a first end and a second end of the channel.
Inventor(s): Kyle Arrington of Gilbert AZ (US) for intel corporation, Bohan Shan of Chandler AZ (US) for intel corporation, Haobo Chen of Chandler AZ (US) for intel corporation, Ziyin Lin of Chandler AZ (US) for intel corporation, Hongxia Feng of Chandler AZ (US) for intel corporation, Yiqun Bai of Chandler AZ (US) for intel corporation, Dingying Xu of Chandler AZ (US) for intel corporation, Xiaoying Guo of Chandler AZ (US) for intel corporation, Bai Nie of Chandler AZ (US) for intel corporation, Srinivas Pietambaram of Chandler AZ (US) for intel corporation, Gang Duan of Chandler AZ (US) for intel corporation
IPC Code(s): H01L23/473, H01L23/15, H01L23/467, H01L23/538
CPC Code(s): H01L23/473
Abstract: methods, systems, apparatus, and articles of manufacture to cool integrated circuit packages having glass substrates are disclosed. an example glass core of an integrated circuit (ic) package disclosed herein includes a fluid inlet to receive a cooling fluid, a fluid outlet, and a channel to fluidly couple the fluid inlet to the fluid outlet, the cooling fluid to flow through the channel from the fluid inlet to the fluid outlet, the channel fluidly isolated from one or more vias extending between a first surface and a second surface of the glass core.
Inventor(s): Han Wui THEN of Portland OR (US) for intel corporation, Marko RADOSAVLJEVIC of Portland OR (US) for intel corporation, Heli Chetanbhai VORA of Hillsboro OR (US) for intel corporation, Samuel James BADER of Hillsboro OR (US) for intel corporation, Ahmad ZUBAIR of Hillsboro OR (US) for intel corporation, Thomas HOFF of Hillsboro OR (US) for intel corporation, Pratik KOIRALA of Portland OR (US) for intel corporation, Michael S. BEUMER of Portland OR (US) for intel corporation, Paul NORDEEN of Hillsboro OR (US) for intel corporation, Nityan NAIR of Portland OR (US) for intel corporation
IPC Code(s): H01L23/48, H01L23/528, H01L23/532, H01L23/66, H01L29/20, H01L29/40, H01L29/778, H01P3/00
CPC Code(s): H01L23/481
Abstract: gallium nitride (gan) devices with through-silicon vias for integrated circuit technology are described. in an example, an integrated circuit structure includes a layer including gallium and nitrogen, the layer including gallium and nitrogen above a silicon substrate. a backside structure is below the silicon substrate and opposite the layer including gallium and nitrogen, the backside structure including conductive features and dielectric structures. the integrated circuit structure also includes a plurality of through-silicon via power bars having a staggered arrangement, individual ones of the through-silicon via power bars extending through the layer including gallium and nitrogen and through the silicon substrate to a corresponding one of the conductive features of the backside structure, and individual ones of the through-silicon via power bars having a tapered portion coupled to an essentially vertical portion.
Inventor(s): Yi YANG of Gilbert AZ (US) for intel corporation, Andrew WENTZEL of Tempe AZ (US) for intel corporation, Marcel WALL of Phoenix AZ (US) for intel corporation, Suddhasattwa NAD of Chandler AZ (US) for intel corporation
IPC Code(s): H01L23/498, C25D3/38, C25D7/12, C25D17/00, H01L23/15
CPC Code(s): H01L23/49827
Abstract: in an embodiment, a package substrate is described. in an embodiment, the package substrate comprises a layer, where the layer is a dielectric material. in an embodiment, a via opening is provided through a thickness of the layer. in an embodiment, a conductive via is in the via opening, where the conductive via has a substantially uniform composition throughout a thickness of the conductive via. in an embodiment the conductive via directly contacts the layer.
Inventor(s): Kristof DARMAWIKARTA of Chandler AZ (US) for intel corporation, Benjamin DUONG of Phoenix AZ (US) for intel corporation, Darko GRUJICIC of Chandler AZ (US) for intel corporation, Shayan KAVIANI of Phoenix AZ (US) for intel corporation, Mahdi MOHAMMADIGHALENI of Phoenix AZ (US) for intel corporation, Suddhasattwa NAD of Chandler AZ (US) for intel corporation, Thomas L. SOUNART of Chandler AZ (US) for intel corporation, Marcel WALL of Phoenix AZ (US) for intel corporation, Ravindranath V. MAHAJAN of Chandler AZ (US) for intel corporation, Rahul N. MANEPALLI of Chandler AZ (US) for intel corporation
IPC Code(s): H01L23/498, H01L27/01
CPC Code(s): H01L23/49838
Abstract: embodiments disclosed herein include an electronic package. in an embodiment, the electronic package comprises a package substrate, where the package substrate comprises a plurality of stacked dielectric layers. in an embodiment, the electronic package further comprises an opening into the package substrate, where the opening passes through at least two of the plurality of dielectric layers. in an embodiment, a first pad is at the bottom of the opening, a capacitor is disposed in the opening, and a second pad is over the capacitor.
Inventor(s): Han Wui THEN of Portland OR (US) for intel corporation, Marko RADOSAVLJEVIC of Portland OR (US) for intel corporation, Samuel James BADER of Hillsboro OR (US) for intel corporation, Ahmad ZUBAIR of Hillsboro OR (US) for intel corporation, Pratik KOIRALA of Portland OR (US) for intel corporation, Michael S. BEUMER of Portland OR (US) for intel corporation, Heli Chetanbhai VORA of Hillsboro OR (US) for intel corporation, Ibrahim BAN of Beaverton OR (US) for intel corporation, Nityan NAIR of Portland OR (US) for intel corporation, Thomas HOFF of Hillsboro OR (US) for intel corporation
IPC Code(s): H01L23/522, H01L23/48
CPC Code(s): H01L23/5223
Abstract: structures having backside high voltage capacitors for front side gan-based devices are described. in an example, an integrated circuit structure includes a front side structure including a gan-based device layer, and one or more metallization layers above the gan-based device layer. a backside structure is below and coupled to the gan-based layer, the backside structure including metal layers and one or more alternating laterally-recessed metal insulator metal capacitors.
20240213154.INTERNAL NODE JUMPER FOR MEMORY BIT CELLS_simplified_abstract_(intel corporation)
Inventor(s): Smita SHRIDHARAN of Beaverton OR (US) for intel corporation, Zheng GUO of Portland OR (US) for intel corporation, Eric A. KARL of Portland OR (US) for intel corporation, George SHCHUPAK of Zviya (IL) for intel corporation, Tali KOSINOVSKY of Haifa (IL) for intel corporation
IPC Code(s): H01L23/528, H01L23/535, H01L27/092, H10B10/00
CPC Code(s): H01L23/528
Abstract: memory bit cells having internal node jumpers are described. in an example, an integrated circuit structure includes a memory bit cell on a substrate. the memory bit cell includes first and second gate lines parallel along a second direction of the substrate. the first and second gate lines have a first pitch along a first direction of the substrate, the first direction perpendicular to the second direction. first, second and third interconnect lines are over the first and second gate lines. the first, second and third interconnect lines are parallel along the second direction of the substrate. the first, second and third interconnect lines have a second pitch along the first direction, where the second pitch is less than the first pitch. one of the first, second and third interconnect lines is an internal node jumper for the memory bit cell.
Inventor(s): Kristof DARMAWIKARTA of Chandler AZ (US) for intel corporation, Srinivas V. PIETAMBARAM of Chandler AZ (US) for intel corporation, Gang DUAN of Chandler AZ (US) for intel corporation, Tarek A. IBRAHIM of Mesa AZ (US) for intel corporation, Aaron GARELICK of Chandler AZ (US) for intel corporation, Srikant NEKKANTY of Chandler AZ (US) for intel corporation, Ravindranath V. MAHAJAN of Chandler AZ (US) for intel corporation, Rahul N. MANEPALLI of Chandler AZ (US) for intel corporation
IPC Code(s): H01L23/532, H01L23/00, H01L23/15, H01L23/498, H01L23/522, H01L23/535, H01L23/64, H01L25/065
CPC Code(s): H01L23/53209
Abstract: embodiments disclosed herein include package substrates. in an embodiment, the package substrate comprises a core and buildup layers over the core. in an embodiment, a pad is provided on the buildup layers. in an embodiment, a liquid metal well is over the pad.
20240213163.INTERCONNECT DEVICE AND METHOD_simplified_abstract_(intel corporation)
Inventor(s): Jung Kyu Han of Chandler AZ (US) for intel corporation
IPC Code(s): H01L23/535, H01L23/00, H01L23/538, H01L23/544, H01L23/66, H01L25/065
CPC Code(s): H01L23/535
Abstract: an electronic device and associated methods are disclosed. in one example, the electronic device includes vertical connections with a layer including tin between the vertical connections and conductive traces. in selected examples, a layer including tin is used in conjunction with other interface layers. in selected examples, a layer including tin is used in all vertical connections.
Inventor(s): Minglu LIU of Chandler AZ (US) for intel corporation, Gang DUAN of Chandler AZ (US) for intel corporation, Liang HE of Chandler AZ (US) for intel corporation, Ziyin LIN of Chandler AZ (US) for intel corporation, Elizabeth NOFEN of Phoenix AZ (US) for intel corporation, Yiqun BAI of Chandler AZ (US) for intel corporation, Jonathan ATKINS of Phoenix AZ (US) for intel corporation, Jesus S. NIETO PESCADOR of Chandler AZ (US) for intel corporation, Srinivas V. PIETAMBARAM of Chandler AZ (US) for intel corporation, Kristof DARMAWIKARTA of Chandler AZ (US) for intel corporation
IPC Code(s): H01L23/538, H01L23/00, H01L23/522, H01L23/528
CPC Code(s): H01L23/5381
Abstract: embodiments disclosed herein include an electronic package. in an embodiment, the electronic package comprises a package substrate, and an opening in the package substrate. in an embodiment, a plurality of first pads are provided at a bottom of the opening, and a bridge die is in the opening. in an embodiment, the bridge die comprises a plurality of second pads that are coupled to the first pads by solder. in an embodiment, a non-conductive film (ncf) is around the solder between the first pads and the second pads.
20240213169.LOW DIE HEIGHT GLASS SUBSTRATE DEVICE AND METHOD_simplified_abstract_(intel corporation)
Inventor(s): Bohan Shan of Chandler AZ (US) for intel corporation, Haobo Chen of Chandler AZ (US) for intel corporation, Yiqun Bai of Chandler AZ (US) for intel corporation, Dingying Xu of Chandler AZ (US) for intel corporation, Srinivas Venkata Ramanuja Pietambaram of Chandler AZ (US) for intel corporation, Hongxia Feng of Chandler AZ (US) for intel corporation, Gang Duan of Chandler AZ (US) for intel corporation, Xiaoying Guo of Chandler AZ (US) for intel corporation, Ziyin Lin of Chandler AZ (US) for intel corporation, Bai Nie of Chandler AZ (US) for intel corporation, Kyle Jordan Arrington of Gilbert AZ (US) for intel corporation, Jeremy D. Ecton of Gilbert AZ (US) for intel corporation, Brandon C. Marin of Gilbert AZ (US) for intel corporation
IPC Code(s): H01L23/538, H01L21/48, H01L21/56, H01L23/15, H01L23/31, H01L23/498, H01L23/64, H10B80/00
CPC Code(s): H01L23/5389
Abstract: an electronic system includes a substrate and a top surface active component die. the substrate includes a glass core layer including a cavity formed through the glass core layer; a glass core layer active component die disposed in the cavity; a first buildup layer contacting a first surface of the glass core layer; a second buildup layer contacting a second surface of the glass core layer; and a mold layer contacting a surface of the first buildup layer. the mold layer includes a mold layer active component die disposed in the mold layer, and the first buildup layer includes electrically conductive interconnect providing electrical continuity between the glass core layer active component die and the mold layer active component die. the top surface active component die is attached to the top surface of the substrate and electrically connected to the mold layer active component die.
20240213170.GLASS SUBSTRATE DEVICE WITH EMBEDDED COMPONENTS_simplified_abstract_(intel corporation)
Inventor(s): Bohan Shan of Chandler AZ (US) for intel corporation, Haobo Chen of Chandler AZ (US) for intel corporation, Yiqun Bai of Chandler AZ (US) for intel corporation, Dingying Xu of Chandler AZ (US) for intel corporation, Srinivas Venkata Ramanuja Pietambaram of Chandler AZ (US) for intel corporation, Hongxia Feng of Chandler AZ (US) for intel corporation, Gang Duan of Chandler AZ (US) for intel corporation, Xiaoying Guo of Chandler AZ (US) for intel corporation, Ziyin Lin of Chandler AZ (US) for intel corporation, Bai Nie of Chandler AZ (US) for intel corporation, Kyle Jordan Arrington of Gilbert AZ (US) for intel corporation, Jeremy D. Ecton of Gilbert AZ (US) for intel corporation, Brandon C. Marin of Gilbert AZ (US) for intel corporation
IPC Code(s): H01L23/538, H01L23/498, H01L25/16, H01L25/18, H10B80/00
CPC Code(s): H01L23/5389
Abstract: an electronic system includes a substrate and a top surface active component die. the substrate includes a glass core layer having a glass core layer active component die disposed in a cavity and a discrete passive component disposed in another cavity; a mold layer including a mold layer active component die disposed in the mold layer; and a buildup layer contacting a top surface of the glass core layer and a bottom surface of the mold layer. the buildup layer includes electrically conductive interconnect connecting the glass core layer active component die, the discrete passive component, and the mold layer active component die. the top surface of the component die is electrically connected to the mold layer active component die.
Inventor(s): Tomita YOSHIHIRO of Tsukuba-shi (JP) for intel corporation, Eric J. LI of Chandler AZ (US) for intel corporation, Shawna M. LIFF of Scottsdale AZ (US) for intel corporation, Javier A. FALCON of Chandler AZ (US) for intel corporation, Joshua D. HEPPNER of Chandler AZ (US) for intel corporation
IPC Code(s): H01L23/538, H01L21/48, H01L21/56, H01L23/00, H01L23/13, H01L23/31, H01L23/48, H01L23/498, H01L23/552, H01L25/04, H01L25/065, H01L25/07, H01L25/075, H01L25/11, H01L25/16
CPC Code(s): H01L23/5389
Abstract: embodiments of the invention include molded modules and methods for forming molded modules. according to an embodiment the molded modules may be integrated into an electrical package. electrical packages according to embodiments of the invention may include a die with a redistribution layer formed on at least one surface. the molded module may be mounted to the die. according to an embodiment, the molded module may include a mold layer and a plurality of components encapsulated within the mold layer. terminals from each of the components may be substantially coplanar with a surface of the mold layer in order to allow the terminals to be electrically coupled to the redistribution layer on the die. additional embodiments of the invention may include one or more through mold vias formed in the mold layer to provide power delivery and/or one or more faraday cages around components.
Inventor(s): Liang He of Chandler AZ (US) for intel corporation, Yue Deng of Chandler AZ (US) for intel corporation, Gang Duan of Chandler AZ (US) for intel corporation, Jung Kyu Han of Chandler AZ (US) for intel corporation, Ali Lehaf of Chandler AZ (US) for intel corporation, Srinivas Pietambaram of Chandler AZ (US) for intel corporation
IPC Code(s): H01L23/00, H01L23/538
CPC Code(s): H01L24/13
Abstract: an electronic package comprises a first die having at least one first interconnect with solder over or under a first metal feature. a second die has at least one second interconnect to the first die, each second interconnect comprising a second metal feature comprising copper, solder over or under the second metal feature, and a layer between the solder and the second metal feature, wherein the layer comprises iron and has a different material than material of the first interconnect.
Inventor(s): MD Altaf Hossain of Portland OR (US) for intel corporation, Ankireddy Nalamalpu of Portland OR (US) for intel corporation, Dheeraj Subbareddy of Portland OR (US) for intel corporation
IPC Code(s): H01L23/00, G06F13/14, G06F13/38, G06F13/42, H01L25/065
CPC Code(s): H01L24/18
Abstract: an integrated circuit includes a package substrate that includes first and second electrical traces. the integrated circuit includes first, second, third, and fourth configurable dies, which are mounted on the package substrate. the first and second configurable dies are arranged in a first row. the third and fourth configurable dies are arranged in a second row, which is approximately parallel to the first row. the first and third configurable dies are arranged in a first column. the second and fourth configurable dies are arranged in a second column, which is approximately parallel to the first column. the first electrical trace couples the first and third configurable dies, and the second electrical trace couples the second and third configurable dies. the second electrical trace is oblique with respect to the first electrical trace. the oblique trace improves the latency of signals transmitted between dies and thereby increases the circuit operating speed.
Inventor(s): Adel A. ELSHERBINI of Tempe AZ (US) for intel corporation, Amr Elshazly of Hillsboro OR (US) for intel corporation, Arun CHANDRASEKHAR of Chandler AZ (US) for intel corporation, Shawna M. LIFF of Scottsdale AZ (US) for intel corporation, Johanna M. SWAN of Scottsdale AZ (US) for intel corporation
IPC Code(s): H01L25/065, H01L23/498, H01L25/00
CPC Code(s): H01L25/0652
Abstract: microelectronic assemblies, and related devices and methods, are disclosed herein. for example, in some embodiments, a microelectronic assembly may include a package substrate, a first die coupled to the package substrate with first interconnects, and a second die coupled to the first die with second interconnects, wherein the second die is coupled to the package substrate with third interconnects, a communication network is at least partially included in the first die and at least partially included in the second die, and the communication network includes a communication pathway between the first die and the second die.
20240213225.PACKAGE STACKING USING CHIP TO WAFER BONDING_simplified_abstract_(intel corporation)
Inventor(s): Georg SEIDEMANN of Landshut (DE) for intel corporation, Klaus REINGRUBER of Langquaid (DE) for intel corporation, Christian GEISSLER of Teugn (DE) for intel corporation, Sven ALBERS of Regensburg (DE) for intel corporation, Andreas WOLTER of Regensburg (DE) for intel corporation, Marc DITTES of Regensburg (DE) for intel corporation, Richard PATTEN of Langquaid (DE) for intel corporation
IPC Code(s): H01L25/065, H01L21/48, H01L21/56, H01L23/00, H01L23/31, H01L23/48, H01L23/498, H01L23/538, H01L25/00
CPC Code(s): H01L25/0657
Abstract: embodiments are generally directed to package stacking using chip to wafer bonding. an embodiment of a device includes a first stacked layer including one or more semiconductor dies, components or both, the first stacked layer further including a first dielectric layer, the first stacked layer being thinned to a first thickness; and a second stacked layer of one or more semiconductor dies, components, or both, the second stacked layer further including a second dielectric layer, the second stacked layer being fabricated on the first stacked layer.
Inventor(s): Suddhasattwa Nad of Chandler AZ (US) for intel corporation, Srinivas Pietambaram of Chandler AZ (US) for intel corporation, Brandon Marin of Gilbert AZ (US) for intel corporation, Jeremy Ecton of Gilbert AZ (US) for intel corporation, Gang Duan of Chandler AZ (US) for intel corporation
IPC Code(s): H01L25/18, H01L23/00, H01L25/00, H01L25/065
CPC Code(s): H01L25/18
Abstract: an apparatus is provided which comprises: an integrated circuit logic device, an integrated circuit power device conductively coupled with a first surface of the integrated circuit logic device, wherein the integrated circuit power device extends laterally beyond a side of the integrated circuit logic device, one or more vias adjacent the side of the integrated circuit logic device extending from contact with the integrated circuit power device to level with a second surface of the integrated circuit logic device opposite the first surface of the integrated circuit logic device, and conductive contacts on the second surface of the integrated circuit logic device. other embodiments are also disclosed and claimed.
20240213250.SELF-ALIGNED BACKBONE FOR FORKSHEET TRANSISTORS_simplified_abstract_(intel corporation)
Inventor(s): Shao Ming KOH of Tigard OR (US) for intel corporation, Sudipto NASKAR of Portland OR (US) for intel corporation, Leonard P. GULER of Hillsboro OR (US) for intel corporation, Patrick MORROW of Portland OR (US) for intel corporation, Richard E. SCHENKER of Portland OR (US) for intel corporation, Walid M. HAFEZ of Portland OR (US) for intel corporation, Charles H. WALLACE of Portland OR (US) for intel corporation, Mohit K. HARAN of Hillsboro OR (US) for intel corporation, Jeanne L. LUCE of Hillsboro OR (US) for intel corporation, Dan S. LAVRIC of Beaverton OR (US) for intel corporation, Jack T. KAVALIEROS of Portland OR (US) for intel corporation, Matthew PRINCE of Portland OR (US) for intel corporation, Lars LIEBMANN of Mechanicville NY (US) for intel corporation
IPC Code(s): H01L27/092, H01L29/06, H01L29/786
CPC Code(s): H01L27/0924
Abstract: embodiments disclosed herein include forksheet transistor transistors with self-aligned backbones. in an example, an integrated circuit structure includes a backbone including a lower backbone portion distinct from an upper backbone portion. a first vertical stack of nanowires is in lateral contact with a first side of the backbone. a second vertical stack of nanowires is in lateral contact with a second side of the backbone, the second side opposite the first side.
Inventor(s): Darko GRUJICIC of Chandler AZ (US) for intel corporation, Thomas L. SOUNART of Chandler AZ (US) for intel corporation, Benjamin DUONG of Phoenix AZ (US) for intel corporation, Kristof DARMAWIKARTA of Chandler AZ (US) for intel corporation, Shayan KAVIANI of Phoenix AZ (US) for intel corporation, Suddhasattwa NAD of Chandler AZ (US) for intel corporation, Mahdi MOHAMMADIGHALENI of Phoenix AZ (US) for intel corporation, Marcel WALL of Phoenix AZ (US) for intel corporation, Rengarajan SHANMUGAM of Tempe AZ (US) for intel corporation
IPC Code(s): H01G4/33
CPC Code(s): H01L28/40
Abstract: embodiments disclosed herein include a package core. in an embodiment, the package core comprises a core substrate that includes glass. in an embodiment, a cavity is provided into the core substrate. in an embodiment, a capacitor is lining sidewalls of the cavity, and the capacitor comprises a first layer, a dielectric layer over the first layer, and a second layer over the dielectric layer.
20240213324.ELONGATED CONTACT FOR SOURCE OR DRAIN REGION_simplified_abstract_(intel corporation)
Inventor(s): Tuhin Guha Neogi of Hillsboro OR (US) for intel corporation, Hwichan Jun of Portland OR (US) for intel corporation, Francis Goodwin of Hillsboro OR (US) for intel corporation
IPC Code(s): H01L29/10, H01L25/065, H01L29/06
CPC Code(s): H01L29/1041
Abstract: techniques are provided herein to form semiconductor devices that include an elongated contact having two different heights on a source or drain region. a semiconductor device includes a gate structure around or otherwise on a semiconductor region (or channel region) that extends from a source or drain region. an elongated conductive contact is formed over the source or drain region that stretches or otherwise extends laterally across the source/drain trench above an adjacent source or drain region without contacting the adjacent source or drain region. a conductive via may contact the portion of the conductive contact over the adjacent source or drain region. accordingly, the conductive contact may have a first thickness above the source or drain region and a second thickness above the adjacent source or drain region with the first thickness being greater than the second thickness.
Inventor(s): Vinith BEJUGAM of Chandler AZ (US) for intel corporation, Yonggang LI of Chandler AZ (US) for intel corporation, Srinivas V. PIETAMBARAM of Chandler AZ (US) for intel corporation, Chandrasekharan NAIR of Mesa AZ (US) for intel corporation, Whitney BRYKS of Tempe AZ (US) for intel corporation, Gene CORYELL of Maricopa AZ (US) for intel corporation
IPC Code(s): H01L29/16, H01L21/768, H01L23/00, H01L23/31, H01L23/48
CPC Code(s): H01L29/1606
Abstract: embodiments disclosed herein include a package substrate. in an embodiment, the package substrate comprises a core with a via opening through the core. in an embodiment, the via opening comprises sidewalls. in an embodiment, a composite layer is provided along the sidewalls, and the composite layer comprises carbon. in an embodiment, the package substrate further comprises a via within the via opening, where the via is electrically conductive.
Inventor(s): Han Wui THEN of Portland OR (US) for intel corporation, Sansaptak DASGUPTA of Milpitas CA (US) for intel corporation, Pratik KOIRALA of Portland OR (US) for intel corporation, Wesley HARRISON of Portland OR (US) for intel corporation, Marko RADOSAVLJEVIC of Portland OR (US) for intel corporation
IPC Code(s): H01L29/20, H01L29/40, H01L29/423, H01L29/66, H01L29/78
CPC Code(s): H01L29/2003
Abstract: gallium nitride (gan) layer on substrate carburization for integrated circuit technology is described. in an example, an integrated circuit structure includes a substrate including silicon. a layer comprising silicon and carbon is above the substrate. a layer comprising gallium and nitrogen is on the layer comprising silicon and carbon.
20240213947.EDGE COMBINING SUB-HARMONIC N-PATH FILTER_simplified_abstract_(intel corporation)
Inventor(s): Run Levinger of Tel Aviv (IL) for intel corporation, SOUMYA GUPTA of Corvallis OR (US) for intel corporation, SASHANK KRISHNAMURTHY of Hillsboro OR (US) for intel corporation, Ashoke Ravi of Portland OR (US) for intel corporation, Ofir Degani of Haifa (IL) for intel corporation
IPC Code(s): H03H7/01
CPC Code(s): H03H7/1758
Abstract: a filter includes a plurality of filtering paths. the plurality of filtering paths is driven by a corresponding plurality of local oscillator (lo) signals associated with an lo frequency. each of the lo signals has a phase of a plurality of phases. each filtering path of the plurality of filtering paths includes a plurality of signal generation branches. the plurality of signal generation branches is configured to receive a harmonic lo signal based on a fraction of the lo frequency, and generate an lo signal of the corresponding plurality of lo signals associated with the lo frequency using the harmonic lo signal.
20240213961.CLOCK ADJUSTMENT CIRCUIT WITH BIAS SCHEME_simplified_abstract_(intel corporation)
Inventor(s): Zeev Toroker of Haifa (IL) for intel corporation, Daljeet Kumar of New Delhi (IN) for intel corporation, Yevgeny Perelman of Haifa (IL) for intel corporation
IPC Code(s): H03K3/017, H03K5/05
CPC Code(s): H03K3/017
Abstract: some embodiments include apparatuses comprising a first node; a second node; a first transistor and a second transistor, the first and second transistors including a common gate coupled to the node and a common terminal coupled to the second node; first additional transistors coupled in parallel with each other between a terminal of the first transistor and a first supply node, the first additional transistors including gates; and second additional transistors coupled in parallel with each other between a terminal of the second transistor and a second supply node, the second additional transistors including gates.
20240213987.IP FREQUENCY ADAPTIVE SAME-CYCLE CLOCK GATING_simplified_abstract_(intel corporation)
Inventor(s): Jianwei Dai of Portland OR (US) for intel corporation, Jimin Zhang of Portland OR (US) for intel corporation
IPC Code(s): H03K19/17736, H03K19/17704, H03K19/20
CPC Code(s): H03K19/1774
Abstract: adaptive clock gating may provide improved power management of electronic devices. clock gating may include removing a clock signal to state elements when those state elements are not being used, and the adaptive clock gating may provide improved clock gating for higher-level clock gates operating at increased frequencies. in an example, the adaptive clock gating may enable clock gating for higher-level clock gates within ip blocks that may be otherwise prevented from using clock gating due to timing requirements. the adaptive clock gating may be used to reduce power consumed by the clock distribution of ip blocks, thereby providing improved power efficiency. an adaptive clock gating circuit may include an ip clock frequency control unit with an adaptive clock gating logic circuit. the adaptive clock gating logic circuit may be used to selectively enable or disable high-level clock gates for the target ip based on a selected clock frequency.
Inventor(s): Marc Jan Georges TIEBOUT of Finkenstein (AT) for intel corporation, Edwin THALLER of Faak am See (AT) for intel corporation, Kameran AZADET of San Ramon CA (US) for intel corporation
IPC Code(s): H03L7/091, H03L7/07, H03L7/099
CPC Code(s): H03L7/091
Abstract: a system and method for testing or determining a phase noise and/or jitter of a phase locked loop (pll). the system includes a first pll configured to generate a first clock signal based on a reference clock signal, a first buffer for providing the reference clock signal to the first pll, a mixer configured to mix the first clock signal with a second clock signal, an analog-to-digital converter (adc) configured to convert an output of the mixer to digital data, and a processing circuit configured to process the digital data to determine a phase noise or jitter of the first pll and generate an output indicative of the phase noise or jitter of the first pll. the system may include a second pll configured to generate the second clock signal based on the reference clock signal, and a second buffer for providing the reference clock signal to the second pll.
Inventor(s): Daniel GRUBER of St. Andrae (AT) for intel corporation, Michael KALCHER of Villach (AT) for intel corporation, Martin CLARA of Santa Clara CA (US) for intel corporation
IPC Code(s): H03M1/06
CPC Code(s): H03M1/0604
Abstract: a digital-to-analog converter (dac) and a method for correcting amplitude and/or skew error in a dac. the dac includes a main dac, cell error determination circuit, a correction dac, and a combiner. the main dac includes a plurality of dac cells. the cell error determination circuit is configured to determine an amplitude error and/or a skew error of each of the plurality of dac cells and generate error data of the dac based on the input data to the dac cells. the correction dac is configured to generate an error signal based on the error data. the combiner is configured to combine the error signal with an output of the main dac.
Inventor(s): Albert MOLINA of Novelda (ES) for intel corporation, Kameran AZADET of San Ramon CA (US) for intel corporation, Matteo CAMPONESCHI of Villach (AT) for intel corporation, Martin CLARA of Santa Clara CA (US) for intel corporation
IPC Code(s): H03M1/06
CPC Code(s): H03M1/0604
Abstract: provided is an apparatus for analog-to-digital conversion. the apparatus comprises a plurality of first analog-to-digital converter, adc, cores configured to receive an analog input signal and to generate respective first digital data based on the analog input signal. further, the apparatus comprises a second adc core configured to receive the analog input signal and to generate second digital data based on the analog input signal. in addition, the apparatus comprises a plurality of correction circuits each coupled to a respective one of the plurality of first adc cores, wherein the plurality of correction circuits is configured to receive the second digital data and to modify the respective first digital data based on the second digital data.
Inventor(s): Vamshi Krishna AAGIRU of Bangalore (IN) for intel corporation, Santhosh AP of Bangalore (IN) for intel corporation, Praveen Kashyap Ananta BHAT of Bangalore (IN) for intel corporation, Arjun C of Bangalore (IN) for intel corporation, Shailendra Singh CHAUHAN of Bangalore (IN) for intel corporation, Sajal Kumar DAS of Bangalore (IN) for intel corporation, Walid EL HAJJ of Antibes (FR) for intel corporation, Isha GARG of Bangalore (IN) for intel corporation, Sagar GUPTA of Ghaziabad (IN) for intel corporation, Mallari HANCHATE of Bangalore (IN) for intel corporation, Mythili HEGDE of Bangalore (IN) for intel corporation, Siva Prasad JANGILI GANGA of Jambagh (IN) for intel corporation, Satyajit Siddharay KAMAT of Bangalore (IN) for intel corporation, Noam KOGOS of Ramat Hasharo (IL) for intel corporation, Ronen KRONFELD of Shoham (IL) for intel corporation, Adiel LANGER of Petah Tiqwa (IL) for intel corporation, Gil MEYUHAS of Tel-Aviv (IL) for intel corporation, Padmesh MURUGAN LATHA of Bangalore (IN) for intel corporation, Vishram Shriram PANDIT of Bangalore (IN) for intel corporation, Abhijith PRABHA of Piravom (IN) for intel corporation, Manisha RAIGURU of Bangalore (IN) for intel corporation, Ehud RESHEF of Qiryat Tivon (IL) for intel corporation, Amir RUBIN of Kiryat Ono (IL) for intel corporation, Shubham Kumar SAHU of Balasore (IN) for intel corporation, Gurpreet SANDHU of Bangalore (IN) for intel corporation, Michael SHACHAR of Kfar Glikson (IL) for intel corporation, Harry SKINNER of Beaverton OR (US) for intel corporation, Madhukiran SRINIVASAREDDY of Bangalore (IN) for intel corporation, Gokul SUBRAMANIAM of Bangalore (IN) for intel corporation, Maruti TAMRAKAR of Chhattisgarh (IN) for intel corporation, Jayprakash THAKUR of Bangalore (IN) for intel corporation, Vijaya Prasad UMMELLA of Bangalore (IN) for intel corporation, Yagnesh Vinodrai WAGHELA of Bangalore (IN) for intel corporation
IPC Code(s): H04B1/3827, H04W52/36
CPC Code(s): H04B1/3838
Abstract: various principles and methods are described herein to improve wireless communication in a user computing device. certain aspects of the disclosure describe management of wireless transmissions relative to various regulations related to a specific absorption rate. other aspects of the disclosure relate to detection of user proximity to a transmitting antenna. other aspects relate to alternative strategies to improve wireless communication, such as selection of alternate antennas or baseband modems, or changes in device orientation.
Inventor(s): Alexei DAVYDOV of Santa Clara CA (US) for intel corporation, Avik SENGUPTA of San Jose CA (US) for intel corporation, Bishwarup MONDAL of San Ramon CA (US) for intel corporation, Guotong WANG of Santa Clara CA (US) for intel corporation
IPC Code(s): H04L5/00, H04W72/232
CPC Code(s): H04L5/005
Abstract: systems, apparatuses, methods, and computer-readable media are provided for channel state information (csi)-reference signal (rs) triggering for multiple user equipments (ues) using a single downlink control information (dci). in some embodiments, a new radio network temporary identifier (rnti) may be used to indicate triggering of csi-rs transmission for multiple ues. additionally, or alternatively, a new dci format may be used that supports csi-rs triggering for multiple ues. the techniques described herein may provide reduced dci overhead compared with prior techniques. other embodiments may be described and claimed.
Inventor(s): Guotong Wang of Beijing (CN) for intel corporation, Alexei Davydov of Nizhny Novgorod (RU) for intel corporation
IPC Code(s): H04L5/00, H04W72/1263, H04W72/232
CPC Code(s): H04L5/0053
Abstract: systems, apparatuses, methods, and computer-readable media are provided to transmit multiple channel state information (csi)-reference signal (rs) resources in different slots for non-codebook based physical uplink shared channel (pusch) transmission in multi-transmission-reception point (trp) operation. other embodiments may be described and claimed.
Inventor(s): Daniel GRUBER of St. Andrae (AT) for intel corporation, Edwin THALLER of Faak am See (AT) for intel corporation, Michael KALCHER of Villach (AT) for intel corporation
IPC Code(s): H04L7/033, G06F1/10, G06F1/12, H03L7/081
CPC Code(s): H04L7/0337
Abstract: a multi-device system and a method for phase alignment of multiple devices in a multi-device system. the system includes a plurality of devices, a plurality of clock dividers, and a delay circuit. the plurality of devices are configured to operate based on a first clock signal. the clock dividers are configured to generate a second clock signal from the first clock signal and provide the second clock signal to the devices. the delay circuit is configured to incur a specific delay to the second clock signal provided to the devices such that a phase of the second clock signal provided to the devices is spread over time. each of the clock dividers may be reset based on a reference clock signal provided to each clock divider, and the delay circuit may incur the specific delay on the reference clock signal provided to each clock divider.
Inventor(s): Zhiqiang LI of Beijing (CN) for intel corporation, Daniel MIDDLETON of Orono MN (US) for intel corporation, Dan HE of Shanghai (CN) for intel corporation, Yiqi CHEN of Shanghai (CN) for intel corporation
IPC Code(s): H04L9/08
CPC Code(s): H04L9/0825
Abstract: an apparatus and method of protect secret input data, secret processing, and secret output data by receiving a signed private enclave from a secret processing owner; receiving a signed manager enclave from a trusted third party (ttp); deploying the signed manager enclave; receiving a protected code loader (pcl) key encrypted with an encryption public key of the signed manager enclave from the secret processing owner; deploying the signed private enclave; running secret processing in the signed private enclave with secret input data to generate secret output data; and encrypting the secret output data in the signed private enclave using an ephemeral key, encrypting the ephemeral key in the signed private enclave using an encryption public key of the signed manager enclave, and sending the encrypted secret output data and the encrypted ephemeral key to the signed manager enclave.
Inventor(s): Albert MOLINA of Novelda (ES) for intel corporation, Wayne BALLANTYNE of Chandler AZ (US) for intel corporation, Kannan RAJAMANI of Basking Ridge NJ (US) for intel corporation, Benjamin JANN of Portland OR (US) for intel corporation, Zoran ZIVKOVIC of Hertogenbosch (NL) for intel corporation, Kameran AZADET of San Ramon CA (US) for intel corporation
IPC Code(s): H04L25/03
CPC Code(s): H04L25/03949
Abstract: an apparatus for controlling an equalizer is provided. the apparatus comprises interface circuitry configured to receive at least one of an input signal and an output signal of the equalizer. the apparatus further comprises processing circuitry configured to determine at least one signal metric based on the at least one of the input signal and the output signal of the equalizer, select an operating mode of the equalizer from a plurality of different operating modes based on the determined signal metric, and control the equalizer to operate in the selected operating mode.
Inventor(s): Dawei Ying of Hillsboro OR (US) for intel corporation, Leifeng Ruan of Beijing (CN) for intel corporation, Jaemin Han of Portland OR (US) for intel corporation, Qian Li of Beaverton OR (US) for intel corporation
IPC Code(s): H04L41/0894
CPC Code(s): H04L41/0894
Abstract: the present invention relates to an apparatus comprising: memory to store policy statement information for a plurality of radio access network (ran) automation applications (rapps); and processing circuitry, coupled with the memory, to: retrieve the policy statement information from the memory, wherein the policy statement information includes respective policy scope identifiers for respective rapps in the plurality of rapps; identify a conflict associated with common or overlapping policy scope identifiers between two or more rapps from the plurality of rapps; modify one or more a1 policies associated with an a1 interface connecting a non-real-time (non-rt) ran intelligence controller (ric) and a near-real-time (near-rt) ric to resolve the conflict; and notify the two or more rapps of the modification of the one or more a1 policies.
20240214279.MULTI-NODE SERVICE RESILIENCY_simplified_abstract_(intel corporation)
Inventor(s): Matthew J. ADILETTA of Bolton MA (US) for intel corporation, Zane BALL of Portland OR (US) for intel corporation, Susanne M. BALLE of Hudson NH (US) for intel corporation, Patrick CONNOR of Beaverton OR (US) for intel corporation
IPC Code(s): H04L41/5019, H04L41/16, H04L43/0823
CPC Code(s): H04L41/5019
Abstract: examples described herein relate to determining whether to process or not process data based on a reliability metric. for example, based on receiving a response to a request to a first microservice, with the reliability metric, from one or more servers, a decision can be made of whether to process, by a second microservice, a result associated with the response based on the reliability metric. in some examples, the reliability metric comprises an indicator of memory health and computational accuracy.
Inventor(s): Zongrui Ding of Portland OR (US) for intel corporation, Qian Li of Beaverton OR (US) for intel corporation, Sangeetha L. Bangolae of Portland OR (US) for intel corporation, Youn Hyoung Heo of Sunnyvale CA (US) for intel corporation, Abhijeet Ashok Kolekar of Hillsboro OR (US) for intel corporation, Ching-YU Liao of Hillsboro OR (US) for intel corporation, Thomas Luetzenkirchen of Taufkirchen (DE) for intel corporation, Sudeep K. Palat of Cheltenham (GB) for intel corporation, Alexandre Saso Stojanovski of Paris (FR) for intel corporation, Xiaopeng Tong of Beijing (CN) for intel corporation
IPC Code(s): H04L41/5054, H04L45/00
CPC Code(s): H04L41/5054
Abstract: an apparatus and system for traffic steering for service function chaining (sfc) are described. different protocol stacks may be used to enable sfc for the user plane. the protocol stacks include: separate sfc service layer and transport protocols in which transport uses identifiers of different enhanced user plane functions (eupfs) and communication (comm) service functions (sfs), transport protocols that are integrated with sfc-related information in which a general packet radio service tunneling protocol-user (gtp-u) header or a segment routing header (srh) has type-length-value (tlv) fields contains the sfc-related information, or an sfc inherent segment routing (sr) protocol stack in which first sfc-related information is carried as a locator: function field in segment routing header (srh) and second sfc-related information is contained in a type-length-value (tlv) field of the srh, the first sfc-related information comprising a comm sf and identification of sfs reachable from the comm sf.
Inventor(s): Ned M. Smith of Beaverton OR (US) for intel corporation, Rajesh Poornachandran of Portland OR (US) for intel corporation, Sunil K. Cheruvu of Tempe AZ (US) for intel corporation
IPC Code(s): H04L9/40
CPC Code(s): H04L63/126
Abstract: the technology described herein includes receiving a first reference integrity manifest (rim) and a first proto-rim from a first endorser, the first endorser asserting authority, by the first rim and the first proto-rim, to supply first attestation reference values for a computing device; storing the first proto-rim in a rim transparency database; notarizing the first proto-rim; and providing the first rim and the notarized first proto-rim to a verifier of the computing device.
Inventor(s): Chen Wang of San Jose CA (US) for intel corporation, Ximin Zhang of San Jose CA (US) for intel corporation, Huan Dou of Beijing (CN) for intel corporation, Yi-Jen Chiu of San Jose CA (US) for intel corporation, Sang-Hee Lee of San Jose CA (US) for intel corporation
IPC Code(s): H04N19/44, G06F18/25, G06N3/08, G06T3/4007, G06T3/4053, G06T9/00, G06V10/82, H04N19/132, H04N19/159, H04N19/176, H04N19/184, H04N19/30
CPC Code(s): H04N19/44
Abstract: techniques related to accelerated video enhancement using deep learning selectively applied based on video codec information are discussed. such techniques include applying a deep learning video enhancement network selectively to decoded non-skip blocks that are in low quantization parameter frames, bypassing the deep learning network for decoded skip blocks in low quantization parameter frames, and applying non-deep learning video enhancement to high quantization parameter frames.
20240214597.DETECTION OF VIDEO TAMPERING_simplified_abstract_(intel corporation)
Inventor(s): Noam Levy of Karmiel (IL) for intel corporation, Guy Ben-Artzi of Zichron Yaacov (IL) for intel corporation
IPC Code(s): H04N19/467, H04L9/06, H04L9/32, H04N19/176
CPC Code(s): H04N19/467
Abstract: techniques are provided for generation of secure video and tamper detection of the secure video. a methodology implementing the techniques according to an embodiment includes selecting a subset of macroblocks from a video frame to be transmitted and calculating a low frequency metric on each of the selected macroblocks. the method also includes performing a hash calculation on the low frequency metrics to generate a frame signature, encrypting the frame signature (using a private key) to generate an encrypted watermark, and modifying pixels of each of the selected macroblocks to generate the secured video frame, the modifications based on bits of the encrypted watermark that are associated with the selected macroblock. the method further includes authenticating a received video frame by comparing a calculated frame signature to an authenticated frame signature, the authenticated frame signature decrypted (using a public key) from an extracted watermark of the received video frame.
Inventor(s): David Israel Gonzalez-Aguirre of Hillsboro OR (US) for intel corporation
IPC Code(s): H04N23/84, G06T3/40, H04N13/128, H04N13/239
CPC Code(s): H04N23/84
Abstract: example systems, apparatus, articles of manufacture, and methods are disclosed to implement and utilize epipolar scan line neural processor arrays for four-dimensional event detection and identification. an example apparatus disclosed herein is to generate, based on left input image data and right input image data, left epipolar image data and right epipolar image data, the left epipolar image data including a plurality of left epipolar scan lines, the right epipolar image data including a plurality of right epipolar scan lines. the example apparatus is also to process, with respective neural processors, respective pairs of the left epipolar scan lines and the right epipolar scan lines to detect events represented in the left input image data and the right input image data, and output data packets representative of the detected events.
Inventor(s): Nikhil Satyarthi of Yelahanka (IN) for intel corporation, Rajakumar Hegde of Karnataka (IN) for intel corporation, Aryabhata Deshpande of Bommanahalli (IN) for intel corporation, Ashok Kunjidhapatham of Devarachikkanahalli (IN) for intel corporation, Sanjeev Ramachandran of Karnataka (IN) for intel corporation, Dinesh Kumar Prakasam of Madurai (IN) for intel corporation, Baranidhar Ramanathan of Kasavanahalli (IN) for intel corporation
IPC Code(s): H04Q11/00, H04L41/0816, H04L41/22
CPC Code(s): H04Q11/0066
Abstract: an orchestration adapter of an optical network is herein described. the orchestration adapter comprises a processor and a non-transitory computer-readable medium storing processor-executable instructions that, when executed, cause the processor to: store a mapping of a correspondence between logical-view passbands and physical-view passbands, each of the physical-view passbands comprising one or more partition(s), each corresponding to a particular logical-view passband; receive a logical-view operation request from an orchestrator of a network element, the logical-view operation request identifying an operation and a first logical-view passband, the operation being executable by a control block of the network element; and send a physical-view operation request to the control block, the physical-view operation request comprising instructions to cause the control block to execute the operation, the instructions identifying the operation and a first physical-view passband, a first partition of the first physical-view passband corresponding to the first logical-view passband.
Inventor(s): Rafael Rosales of Bavaria (DE) for intel corporation, Ignacio Alvarez of Portland OR (US) for intel corporation, Willem Beltman of West Linn OR (US) for intel corporation
IPC Code(s): H04S7/00, G06F3/16
CPC Code(s): H04S7/303
Abstract: an apparatus, including: an interface operable to receive real-time information related to one or more actors in a real environment; and processing circuitry operable to: generate a digital twin of the real environment, wherein the digital twin is a virtual representation of the real environment; spawn a model that mirrors the one or more actors based on the real-time information; and generate a spatial sound signal based on the digital twin for transmission to an ego actor of the one or more actors in the real environment, wherein the generation of the spatial sound signal comprises generating the spatial sound signal to be individualized from an auditory perspective of the ego actor in the real environment to originate from a source actor of the one or more actors.
Inventor(s): Vesh Raj SHARMA BANJADE of Portland OR (US) for intel corporation, Kathiravetpillai SIVANESAN of Portland OR (US) for intel corporation, Satish C. JHA of Portland OR (US) for intel corporation, Leonardo GOMES BALTAR of Munich (DE) for intel corporation
IPC Code(s): H04W4/40, H04W4/029
CPC Code(s): H04W4/40
Abstract: the present disclosure is related to intelligent transport systems (its), and in particular, to vulnerable road user (vru) basic services (vbs) of a vru its station (its-s). implementations of how the vbs is arranged within the facilities layer of an its-s, different conditions for vru awareness message (vam) dissemination, and format and coding rules of the vam generation.
Inventor(s): Yizhi Yao of Chandler AZ (US) for intel corporation, Joey Chou of Scottsdale AZ (US) for intel corporation
IPC Code(s): H04W28/02, H04W28/24
CPC Code(s): H04W28/0268
Abstract: a device to host a service producer in a 5g system (or 5g system architecture), a method to be performed at the device, and a non-transitory storage device storing instructions to be executed at the device. the method includes: decoding a request from a service consumer to manage one or more 5g quality of service (qos) indicators (5qis), each 5qi including a 5qi value and corresponding 5qi characteristics; configuring one or more network functions (nfs) of the 5gs with the 5qis based on the request; and encoding for transmission to the service consumer a message including a result of managing the one or more 5qis.
Inventor(s): Hua Li of Arlington VA (US) for intel corporation, Meng Zhang of Beijing (CN) for intel corporation, Andrey Chervyakov of Nizhny Novgorod (RU) for intel corporation, Rui Huang of Beijing, 11 (CN) for intel corporation, Ilya Bolotin of Nizhny-Novgorod (RU) for intel corporation
IPC Code(s): H04W36/00, H04B17/318
CPC Code(s): H04W36/0085
Abstract: an apparatus and system for a receive (rx) beam assumption, and inter-cell radio beam measurements and resource management (rrm) requirements are described. in response to a determination whether or not a frequency range2 (fr2) signal from a neighbor cell is to be measured inside a synchronization system (ss) zphysical broadcast channel (pbch) block measurement timing configuration (smtc) window, a first rx beam from the neighbor cell for a layer 1 reference signal received power (l1-rsrp) measurement of the fr2 signal and a second rx beam for a layer 3 rsrp (l3-rsrp) measurement of the fr2 signal are selected. a l1-rsrp of the fr2 signal for the first rx beam and l3-rsrp of the fr2 signal for the second rx beam are measured and feedback provided to a serving cell.
20240214942.POWER SCALING FOR UPLINK FULL POWER TRANSMISSION_simplified_abstract_(intel corporation)
Inventor(s): Guotong Wang of Beijing (CN) for intel corporation, Alexei Davydov of Nizhny Novgorod (RU) for intel corporation
IPC Code(s): H04W52/14, H04W52/36
CPC Code(s): H04W52/146
Abstract: a computer-readable storage medium stores instructions to configure a ue for power scaling in uplink data transmissions in a 5g nr and beyond wireless network, and to cause the ue to perform operations including decoding rrc signaling received from a base station. the rrc signaling includes a power scaling factor. the power scaling factor indicates a transmission mode for uplink full power transmission. a linear output power value is determined for a maximum output power associated with the ue. the linear output power value is scaled using the power scaling factor to generate a scaled linear output power value. a pusch power control output is determined based on the scaled linear output power value. the operations further include causing the uplink full power transmission of uplink data using the pusch. the uplink full power transmission has transmit power based on the pusch power control output.
20240215018.SYSTEMS AND METHODS OF POWER HEADROOM REPORTING_simplified_abstract_(intel corporation)
Inventor(s): Yi Wang of Beijing (CN) for intel corporation, Toufiqul Islam of Santa Clara CA (US) for intel corporation, Sergey Panteleev of Maynooth (IE) for intel corporation, Debdeep Chatterjee of San Jose CA (US) for intel corporation, Salvatore Talarico of Los Gatos CA (US) for intel corporation, Yingyang Li of Beijing (CN) for intel corporation
IPC Code(s): H04W72/1268, H04B7/06, H04L1/1812, H04W72/21, H04W72/566
CPC Code(s): H04W72/1268
Abstract: an apparatus and system of supporting simultaneous physical uplink control channel (pucch) and physical uplink shared channel (pusch) transmission are described. a user equipment (ue) that supports service types with different priority levels is configured by a 5th generation nodeb (gnb) to multiplex transmissions with different priorities on different serving cells in different bands. the ue multiplexes and prioritizes high priority (hp) and low priority (lp) uplink transmissions with and without simultaneous pucch and pusch transmissions based on repetition and scheduling request (sr).
Inventor(s): Sergey Sosnin of Santa Clara CA (US) for intel corporation, Gang Xiong of Portland OR (US) for intel corporation, Avik Sengupta of San Jose CA (US) for intel corporation, Alexei Davydov of Santa Clara CA (US) for intel corporation, Jie Zhu of San Jose CA (US) for intel corporation, Gregory Ermolaev of Santa Clara CA (US) for intel corporation
IPC Code(s): H04W72/1268, H04L1/00, H04L27/26, H04W72/044, H04W72/0446, H04W72/0453
CPC Code(s): H04W72/1268
Abstract: among other things, some embodiments of the present disclosure are directed to coverage enhancement techniques for the physical uplink control channel (pucch). specifically, the pucch may be transmitted from two or more antenna ports of a user equipment (ue) based on configuration information received from a base station. other embodiments may be disclosed and/or claimed.
Inventor(s): Onur OZKAN of Scottsdale AZ (US) for intel corporation, Jacob VEHONSKY of Gilbert AZ (US) for intel corporation, Vinith BEJUGAM of Chandler AZ (US) for intel corporation, Nicholas S. HAEHN of Scottsdale AZ (US) for intel corporation, Andrea NICOLAS FLORES of Chandler AZ (US) for intel corporation, Mao-Feng TSENG of Tempe AZ (US) for intel corporation
IPC Code(s): H05K1/11, H05K1/03, H05K1/18
CPC Code(s): H05K1/112
Abstract: embodiments disclosed herein include a package core. in an embodiment, the package core comprises a substrate with a first surface and a second surface opposite from the first surface. in an embodiment, the substrate comprise glass. in an embodiment, a via is provided through the substrate, where the via is electrically conductive. in an embodiment, a recess is formed into the first surface of the substrate, and a trace is embedded in the recess. in an embodiment, the trace is electrically conductive.
Inventor(s): Abhishek Anil SHARMA of Portland OR (US) for intel corporation, Tahir GHANI of Portland OR (US) for intel corporation, Sagar SUTHRAM of Portland OR (US) for intel corporation, Anand S. MURTHY of Portland OR (US) for intel corporation, Pushkar RANADE of San Jose CA (US) for intel corporation, Wilfred GOMES of Portland OR (US) for intel corporation
IPC Code(s): H10B12/00
CPC Code(s): H10B12/315
Abstract: structures having backside power delivery and signal routing for front side dram are described. in an example, an integrated circuit structure includes a front side structure including a dynamic random access memory (dram) layer having one or more capacitors over one or more transistors, and a plurality of metallization layers above the dram layer. a backside structure is below and coupled to the transistors of the dram layer, the backside structure including metal lines for power delivery and signal routing to the one or more transistors of the dram layer.
Inventor(s): Abhishek Anil SHARMA of Portland OR (US) for intel corporation, Tahir GHANI of Portland OR (US) for intel corporation, Anand S. MURTHY of Portland OR (US) for intel corporation, Wilfred GOMES of Portland OR (US) for intel corporation, Pushkar RANADE of San Jose CA (US) for intel corporation, Sagar SUTHRAM of Portland OR (US) for intel corporation
IPC Code(s): H10B53/20, H01L23/522, H01L23/528, H10B53/10, H10B61/00
CPC Code(s): H10B53/20
Abstract: structures having backside capacitors are described. in an example, an integrated circuit structure includes a front side structure including a device layer having a plurality of select transistors, a plurality of metallization layers above the plurality of select transistors, and a plurality of vias below and coupled to the plurality of select transistors. a backside structure is below the plurality of vias of the device layer. the backside structure includes a memory layer coupled to the plurality of select transistors by the plurality of vias.
20240215269.GLASS SUBSTRATE DEVICE WITH THROUGH GLASS CAVITY_simplified_abstract_(intel corporation)
Inventor(s): Bohan Shan of Chandler AZ (US) for intel corporation, Haobo Chen of Chandler AZ (US) for intel corporation, Yiqun Bai of Chandler AZ (US) for intel corporation, Dingying Xu of Chandler AZ (US) for intel corporation, Srinivas Venkata Ramanuja Pietambaram of Chandler AZ (US) for intel corporation, Hongxia Feng of Chandler AZ (US) for intel corporation, Gang Duan of Chandler AZ (US) for intel corporation, Xiaoying Guo of Chandler AZ (US) for intel corporation, Ziyin Lin of Chandler AZ (US) for intel corporation, Bai Nie of Chandler AZ (US) for intel corporation, Kyle Jordan Arrington of Gilbert AZ (US) for intel corporation
IPC Code(s): H10B80/00, H01L23/00, H01L23/498, H01L23/538, H01L25/16, H01L25/18
CPC Code(s): H10B80/00
Abstract: an electronic system includes a substrate that includes a glass core layer including a cavity formed through the glass core layer; at least one active component die disposed in the cavity; a first buildup layer contacting a first surface of the glass core layer and a first surface of the at least one active component die, wherein the first buildup layer includes electrically conductive interconnect contacting the at least one active component die and extending to a first surface of the substrate; a second buildup layer contacting a second surface of the glass core layer and a second surface of the at least one active component die; and one or more solder bumps on a second surface of the substrate and contacting the second surface of the at least one active component die.
- Intel Corporation
- G01C21/34
- G01C21/36
- CPC G01C21/3461
- Intel corporation
- G01R31/28
- H01L21/66
- CPC G01R31/2879
- G01R31/3177
- G06F30/333
- CPC G01R31/3177
- G01S7/4865
- G01S17/14
- CPC G01S7/4865
- G02B6/42
- G02B1/04
- G02B3/00
- CPC G02B6/4206
- G03F7/00
- G03F7/038
- G03F7/16
- G03F7/20
- G03F7/40
- CPC G03F7/0032
- G03F7/32
- CPC G03F7/40
- G06F1/16
- B32B5/02
- B32B5/26
- C23C14/20
- C23C14/35
- C23C16/06
- CPC G06F1/1615
- G06F1/3234
- G06F1/3228
- CPC G06F1/3275
- G06F9/30
- G06F7/483
- G06F7/485
- G06F7/487
- G06F7/53
- G06F7/544
- G06F17/16
- CPC G06F9/30014
- G06F9/38
- CPC G06F9/30029
- G06F11/34
- G06F12/02
- CPC G06F9/30047
- CPC G06F9/30145
- G06F9/54
- G06F11/30
- CPC G06F9/3885
- G06F9/455
- CPC G06F9/45558
- G06F9/50
- H04L45/745
- H04L61/103
- H04L67/1004
- H04L67/1097
- H04L67/51
- H04L67/566
- H04W8/22
- CPC G06F9/5005
- G06F11/07
- CPC G06F11/0772
- G06F11/10
- G11C29/02
- CPC G06F11/106
- CPC G06F12/0246
- G06F12/0815
- CPC G06F12/0815
- G06F12/0837
- G06F12/0811
- CPC G06F12/0837
- G06F12/0891
- G06F12/1009
- CPC G06F12/0891
- G06F21/10
- CPC G06F21/101
- G06F21/45
- CPC G06F21/45
- G06N3/045
- CPC G06N3/045
- G06N5/022
- CPC G06N5/022
- G06Q50/26
- G06F21/62
- G08G1/01
- CPC G06Q50/265
- G06T5/00
- CPC G06T5/00
- G06T7/73
- G06T7/11
- CPC G06T7/73
- G06T15/04
- A63F13/52
- A63F13/95
- CPC G06T15/04
- H01L21/28
- B24B37/04
- H01L21/8238
- H01L27/092
- H01L29/06
- H01L29/417
- H01L29/423
- H01L29/66
- H01L29/775
- CPC H01L21/28123
- H01L21/683
- B25J15/06
- CPC H01L21/6838
- CPC H01L21/823878
- H01L23/367
- G06F1/20
- H01L23/15
- H01L23/427
- H01L23/473
- H01L23/498
- CPC H01L23/367
- H01L23/467
- H01L23/538
- CPC H01L23/473
- H01L23/48
- H01L23/528
- H01L23/532
- H01L23/66
- H01L29/20
- H01L29/40
- H01L29/778
- H01P3/00
- CPC H01L23/481
- C25D3/38
- C25D7/12
- C25D17/00
- CPC H01L23/49827
- H01L27/01
- CPC H01L23/49838
- H01L23/522
- CPC H01L23/5223
- H01L23/535
- H10B10/00
- CPC H01L23/528
- H01L23/00
- H01L23/64
- H01L25/065
- CPC H01L23/53209
- H01L23/544
- CPC H01L23/535
- CPC H01L23/5381
- H01L21/48
- H01L21/56
- H01L23/31
- H10B80/00
- CPC H01L23/5389
- H01L25/16
- H01L25/18
- H01L23/13
- H01L23/552
- H01L25/04
- H01L25/07
- H01L25/075
- H01L25/11
- CPC H01L24/13
- G06F13/14
- G06F13/38
- G06F13/42
- CPC H01L24/18
- H01L25/00
- CPC H01L25/0652
- CPC H01L25/0657
- CPC H01L25/18
- H01L29/786
- CPC H01L27/0924
- H01G4/33
- CPC H01L28/40
- H01L29/10
- CPC H01L29/1041
- H01L29/16
- H01L21/768
- CPC H01L29/1606
- H01L29/78
- CPC H01L29/2003
- H03H7/01
- CPC H03H7/1758
- H03K3/017
- H03K5/05
- CPC H03K3/017
- H03K19/17736
- H03K19/17704
- H03K19/20
- CPC H03K19/1774
- H03L7/091
- H03L7/07
- H03L7/099
- CPC H03L7/091
- H03M1/06
- CPC H03M1/0604
- H04B1/3827
- H04W52/36
- CPC H04B1/3838
- H04L5/00
- H04W72/232
- CPC H04L5/005
- H04W72/1263
- CPC H04L5/0053
- H04L7/033
- G06F1/10
- G06F1/12
- H03L7/081
- CPC H04L7/0337
- H04L9/08
- CPC H04L9/0825
- H04L25/03
- CPC H04L25/03949
- H04L41/0894
- CPC H04L41/0894
- H04L41/5019
- H04L41/16
- H04L43/0823
- CPC H04L41/5019
- H04L41/5054
- H04L45/00
- CPC H04L41/5054
- H04L9/40
- CPC H04L63/126
- H04N19/44
- G06F18/25
- G06N3/08
- G06T3/4007
- G06T3/4053
- G06T9/00
- G06V10/82
- H04N19/132
- H04N19/159
- H04N19/176
- H04N19/184
- H04N19/30
- CPC H04N19/44
- H04N19/467
- H04L9/06
- H04L9/32
- CPC H04N19/467
- H04N23/84
- G06T3/40
- H04N13/128
- H04N13/239
- CPC H04N23/84
- H04Q11/00
- H04L41/0816
- H04L41/22
- CPC H04Q11/0066
- H04S7/00
- G06F3/16
- CPC H04S7/303
- H04W4/40
- H04W4/029
- CPC H04W4/40
- H04W28/02
- H04W28/24
- CPC H04W28/0268
- H04W36/00
- H04B17/318
- CPC H04W36/0085
- H04W52/14
- CPC H04W52/146
- H04W72/1268
- H04B7/06
- H04L1/1812
- H04W72/21
- H04W72/566
- CPC H04W72/1268
- H04L1/00
- H04L27/26
- H04W72/044
- H04W72/0446
- H04W72/0453
- H05K1/11
- H05K1/03
- H05K1/18
- CPC H05K1/112
- H10B12/00
- CPC H10B12/315
- H10B53/20
- H10B53/10
- H10B61/00
- CPC H10B53/20
- CPC H10B80/00
