Intel Corporation patent applications on June 13th, 2024
Patent Applications by Intel Corporation on June 13th, 2024
Intel Corporation: 43 patent applications
Intel Corporation has applied for patents in the areas of H04W52/36 (4), H01L23/00 (4), G06F21/60 (4), H04L5/00 (3), H01L21/56 (3) H04W52/367 (3), G01S7/4817 (1), H04L45/74 (1), H01L27/0886 (1), H01L29/0673 (1)
With keywords such as: device, data, network, based, structure, memory, processor, information, power, and compute in patent application abstracts.
Patent Applications by Intel Corporation
20240192332.LIGHT DETECTION AND RANGING SYSTEMS_simplified_abstract_(intel corporation)
Inventor(s): Liron AIN-KEDEM of Kiryat Tivon (IL) for intel corporation, Gilad RAHAMIM of Ramat Gan (IL) for intel corporation, Ahuva KROIZER of Jerusalem (IL) for intel corporation, Avi MEDLINSKY of Ramat Yishay (IL) for intel corporation
IPC Code(s): G01S7/481, G01R19/00, G01S7/497, G01S17/931
CPC Code(s): G01S7/4817
Abstract: a light detection and ranging system is provided. the light detection and ranging system includes a lidar scanning mirror; a processor configured to control the lidar scanning mirror; a first position sensor configured to determine a first position and a second position sensor configured to detect a second position of the lidar scanning mirror. the processor is configured to determine whether an eye-safety criterion is met based on the first position and the second position, and control light output of the lidar system based on whether the eye-safety criterion is met.
Inventor(s): Changhua Liu of Chandler AZ (US) for intel corporation, Robert A. May of Chandler AZ (US) for intel corporation, Bai Nie of Chandler AZ (US) for intel corporation
IPC Code(s): G02B6/42
CPC Code(s): G02B6/4214
Abstract: an integrated circuit (ic) package substrate comprises an upper surface, a lower surface opposite the upper surface, and an outer side surface extending between the upper surface and the lower surface. at least one optical path is in a plane of the ic package substrate, and at least one vertical optical coupler at an upper or lower surface of the ic package substrate is optically coupled to the optical path.
Inventor(s): Chuen Ming Tan of Bayan Lepas (MY) for intel corporation, Venkataramani Gopalakrishnan of Folsom CA (US) for intel corporation, Aneesh Tuljapurkar of Bangalore (IN) for intel corporation, Vishwanath Somayaji of Bangalore (IN) for intel corporation, Tabassum Yasmin of Bangalore (IN) for intel corporation
IPC Code(s): G06F1/3225, G06F1/3287
CPC Code(s): G06F1/3225
Abstract: embodiments herein relate to a circuit which allows the re-use of an existing power supply units having main power rails and an auxiliary power rail, while supporting large memory configurations in a sleep state to avoid data loss. a processor determines whether a power requirement of memory modules in a computing device exceeds an available power of the auxiliary power rail. if this is the case, the processor asserts an override signal which is used by a logic circuit to force the power supply to remain on in the sleep state. a set of switches disconnect the main rails from other components which can be turned off in the sleep state. a select circuit selects one of the main rails to power the memory modules.
Inventor(s): Elad Sunray of Haifa (IL) for intel corporation, Dmitry Rudoy of Haifa (IL) for intel corporation, Noam Levy of Karmiel (IL) for intel corporation
IPC Code(s): G06F3/01, G06T3/60, G06T7/73, G06T7/80
CPC Code(s): G06F3/013
Abstract: systems and methods for real-time, efficient, monocular gaze position determination that can be performed in real-time on a consumer-grade laptop. gaze tracking can be used for human-computer interactions, such as window selection, user attention on screen information, gaming, augmented reality, and virtual reality. gaze position estimation from a monocular camera involves estimating the line-of-sight of a user and intersecting the line-of-sight with a two-dimensional (2d) screen. the system uses a neural network to determine gaze position within about four degrees of accuracy while maintaining very low computational complexity. the system can be used to determine gaze position across multiple screens, determining which screen a user is viewing as well as a gaze target area on the screen. there are many different scenarios in which a gaze position estimation system can be used, including different head poses, different facial expressions, different cameras, different screens, and various illumination scenarios.
Inventor(s): Robert VALENTINE of Kiryat Tivon (IL) for intel corporation, Mark J. CHARNEY of Lexington MA (US) for intel corporation, Elmoustapha OULD-AHMED-VALL of Chandler AZ (US) for intel corporation, Dan BAUM of Haifa (IL) for intel corporation, Zeev SPERBER of Zichron Yackov (IL) for intel corporation, Jesus CORBAL of King City OR (US) for intel corporation, Bret L. TOLL of Hillsboro OR (US) for intel corporation, Raanan SADE of Kibutz Sarid (IL) for intel corporation, Igor YANOVER of Yokneam Illit (IL) for intel corporation, Yuri GEBIL of Nahariya (IL) for intel corporation, Rinat RAPPOPORT of Haifa (IL) for intel corporation, Stanislav SHWARTSMAN of Haifa (IL) for intel corporation, Menachem ADELMAN of Haifa (IL) for intel corporation, Simon RUBANOVICH of Haifa (IL) for intel corporation
IPC Code(s): G06F9/30, G06F7/485, G06F7/487, G06F7/76, G06F9/38, G06F17/16
CPC Code(s): G06F9/30036
Abstract: embodiments detailed herein relate to matrix (tile) operations. for example, decode circuitry to decode an instruction having fields for an opcode and a memory address; and execution circuitry to execute the decoded instruction to set a tile configuration for the processor to utilize tiles in matrix operations based on a description retrieved from the memory address, wherein a tile a set of 2-dimensional registers are discussed.
20240192981.EXITLESS GUEST TO HOST NOTIFICATION_simplified_abstract_(intel corporation)
Inventor(s): Wei WANG of Shanghai (CN) for intel corporation, Kun TIAN of Shanghai (CN) for intel corporation, Gilbert NEIGER of Portland OR (US) for intel corporation, Rajesh SANKARAN of Portland OR (US) for intel corporation, Asit MALLICK of Saratoga CA (US) for intel corporation, Jr-Shian TSAI of Portland OR (US) for intel corporation, Jacob Jun PAN of Portland OR (US) for intel corporation, Mesut ERGIN of Portland OR (US) for intel corporation
IPC Code(s): G06F9/455, G06F9/30
CPC Code(s): G06F9/45558
Abstract: embodiments of exitless guest to host (g2h) notification are described. in some embodiments, g2h is provided via an instruction. an exemplary processor includes decoder circuitry to decode a single instruction, the single instruction to include a field for an opcode; and execution processing resources to execute the decoded single instruction according to the at least the opcode to cause an exitless guest to host notification from a virtual processor to a physical or virtual processor.
Inventor(s): Vaibhav SHANKAR of Seattle WA (US) for intel corporation, Amir Ali RADJAI of Portland OR (US) for intel corporation, Jaishankar RAJENDRAN of Bangalore (IN) for intel corporation, Evrim BINBOGA of Pleasanton CA (US) for intel corporation, Prashant KODALI of Portland OR (US) for intel corporation
IPC Code(s): G06F12/02, G11C29/54
CPC Code(s): G06F12/023
Abstract: examples include techniques associated with allocating memory capacity of a memory partitioned to include a first region arranged to include in-line or in-band error correction control (ibecc) memory and a second region arranged to include non-ibecc memory. the first and second regions can be re-sized based on usage of either region reaching a threshold.
Inventor(s): Michelle M. WIGTON of Timnath CO (US) for intel corporation, Kambiz R. MUNSHI of Westford MA (US) for intel corporation, Zhongyao Linda GU of Acton MA (US) for intel corporation, Mohammad M. RASHID of San Jose CA (US) for intel corporation, Victor LAU of Marlborough MA (US) for intel corporation, Jing LING of Milpitas CA (US) for intel corporation
IPC Code(s): G06F13/16, H10B12/00
CPC Code(s): G06F13/1689
Abstract: memory power consumption is reduced without increasing latency of memory read access. when inactive, power consumption is reduced in a phy in a memory controller by disabling receiver bias circuitry and a clock network in the phy. the memory controller sends two command-based signals to the phy to enable the phy to enable the receiver bias circuitry and the clock network in the phy to transition the memory from a low power state to an active power state prior to or at the time of receiving command from the memory controller. a first command-based signal is an early command indication signal that is sent before any command. the second command-based signal is a read indication signal that is sent synchronous with every read command. upon receiving these signals, the phy enables the clock network and receiver bias circuitry.
Inventor(s): SIDDHARTHA CHHABRA of Portland OR (US) for intel corporation
IPC Code(s): G06F21/54, G06F11/10, G06F21/60
CPC Code(s): G06F21/54
Abstract: techniques for dynamically configurable scalable memory integrity and enhanced reliability, availability, and serviceability (smiras) are described. a smiras based system may be enabled to use an integrity-based metadata organization, a replay protection-based metadata organization, or a combination of both metadata organizations.
Inventor(s): ARDHI WIRATAMA BASKARA YUDHA of Orlando FL (US) for intel corporation, RESHMA LAL of Portland OR (US) for intel corporation
IPC Code(s): G06F21/60, H04L9/08
CPC Code(s): G06F21/602
Abstract: an apparatus comprises a local computer readable memory, a compute processor comprising one or more processing resources to execute a compute process, and a cryptographic processor to prefetch encrypted compute data for the compute processor and decrypt the compute data prior to making the compute data accessible to the compute processor.
Inventor(s): Francesc Guim Bernat of Barcelona (ES) for intel corporation, Marcos Carranza of Portland OR (US) for intel corporation, Kshitij Doshi of Tempe AZ (US) for intel corporation, Ned Smith of Beaverton OR (US) for intel corporation, Karthik Kumar of Chandler AZ (US) for intel corporation
IPC Code(s): G06F21/60
CPC Code(s): G06F21/604
Abstract: techniques and mechanisms to allocate functionality of a chiplet for access by one or more processor cores which are coupled to remote processor via a network switch. in an embodiment, a composite chip communicates with the switch via a compute express link (cxl) link. the switch receives capability information which identifies both a chiplet of the composite chip, and a functionality which is available from a resource of that chiplet. based on the capability information, the switch provides an inventory of chiplet resources. in response to an allocation request, the switch accesses the inventory to identify whether a suitable chiplet resource is available. based on the access, the switch configures a chip to enable an allocation of a chiplet resource. in another embodiment, the chiplet resource is allocated at a sub-processor level of granularity, and disables access to the chiplet resource by one or more local processor cores.
Inventor(s): Anne MATSUURA of Portland OR (US) for intel corporation, Pradnya Laxman KHALATE of Cornelius OR (US) for intel corporation, Shavindra PREMARATNE of Portland OR (US) for intel corporation, Sahar DARAEIZADEH of Redmond WA (US) for intel corporation, Albert SCHMITZ of Beaverton OR (US) for intel corporation, Xin-Chuan WU of Santa Clara CA (US) for intel corporation, Todor MLADENOV of Portland OR (US) for intel corporation, Brandon BARNETT of Beaverton OR (US) for intel corporation
IPC Code(s): G06N10/20
CPC Code(s): G06N10/20
Abstract: apparatus and method for compiling and executing hybrid classical-quantum programs. for example, one embodiment of an apparatus comprises: a host processor to perform a partial compilation on hybrid quantum-classical source code to generate one or more sequential blocks of quantum operations; a quantum compiler accelerator to receive compilation work offloaded by the host processor including the one or more sequential blocks of quantum operations, the quantum compiler to perform optimization operations to optimize runtime execution of one or more of the quantum operations in view if a quantum accelerator architecture to generate optimized quantum operations; and a quantum execution accelerator having the quantum accelerator architecture to execute the optimized quantum operations to manipulate a state of one or more qubits, to measure a state of the one or more qubits, and to provide measurement data indicating the state to the host processor.
Inventor(s): Francesc Guim Bernat of Barcelona (ES) for intel corporation, Karthik Kumar of Chandler AZ (US) for intel corporation, Akhilesh S. Thyagaturu of Tampa FL (US) for intel corporation, Thijs Metsch of Bruehl (DE) for intel corporation, Adrian Hoban of Cratloe (IE) for intel corporation
IPC Code(s): G06Q30/018, G06F9/50
CPC Code(s): G06Q30/018
Abstract: systems, apparatus, articles of manufacture, and methods are disclosed. an example apparatus includes programmable circuitry to at least: obtain a first response associated with an estimate of emissions to be produced by execution of a workload on first hardware; obtain a second response associated with an estimate of emissions to be produced by execution of the workload on second hardware; and assign one of the first or the second hardware to execute the workload based on the first response and the second response, the assigned one of the first or the second hardware to at least one of utilize more time or more memory to execute the workload than the other of the first or the second hardware.
Inventor(s): Zhenyu Z WANG of Shanghai (CN) for intel corporation, Xinda ZHAO of Shanghai (CN) for intel corporation, Owen ZHANG of Shanghai (CN) for intel corporation
IPC Code(s): G06T1/20, G06F9/50
CPC Code(s): G06T1/20
Abstract: apparatus and method for migrating a container including graphics processor state. one embodiment of an apparatus comprises: a first graphics processor coupled to a first system memory; execution circuitry of the graphics processor to execute graphics operations of processes grouped into a plurality of containers, the execution circuitry to be shared by the plurality of containers; and a first container migration engine to migrate a first container of the plurality of containers to a second graphics processor coupled to a second system memory, the first container migration engine to freeze operation of the first container at a specified execution point defined by a first container state including process-visible state data and driver-visible state data, the first container migration engine to transmit the first container state to a second container migration engine associated with the second graphics processor and second system memory, the second container migration engine to restore the first container to the specified execution point using the process-visible state data and the driver-visible state data.
20240193981.HUMAN POSTURE DETECTION_simplified_abstract_(intel corporation)
Inventor(s): David Pearce of El Dorado Hills CA (US) for intel corporation, David Stanhill of Hoshaya (IL) for intel corporation
IPC Code(s): G06V40/10, G06V10/82, G06V40/60
CPC Code(s): G06V40/103
Abstract: a user computing device includes a camera sensor and a depth sensor. image data generated by the camera captures an image of a user of the user computing device and is provided as an input to a first machine learning model trained to determine a feature set associated with posture of the user from the image data. depth data generated by the depth sensor contemporaneously with generation of the image data is provided as input to a second machine learning model along with the first feature set to generate a second feature set as an output of the second machine learning model based on the depth data and the first feature set. the posture of the user is determined from the second feature set to provide feedback to the user.
Inventor(s): Sumod CHERUKKATE of Bangalore (IN) for intel corporation, Willem BELTMAN of West Linn OR (US) for intel corporation, Mallari HANCHATE of Bangalore (IN) for intel corporation, Srikanth POTLURI of Folsom CA (US) for intel corporation, Sangeeta MANEPALLI of Chandler AZ (US) for intel corporation, Abhishek SRIVASTAV of Bangalore (IN) for intel corporation
IPC Code(s): G10L21/0364, G06F3/01, G06T7/50, G06V40/16, H04R1/32
CPC Code(s): G10L21/0364
Abstract: this disclosure describes systems, methods, and devices related to user tracking. a device may identify metadata comprising depth sensing information and camera information received from an in-room device located at a first location having a first camera. the device may perform face recognition on one or more in-room users. the device may calculate a distance of a first in-room user based on the metadata and a first number of pixels across the face of the first in-room user. the device may calculate a distance between the first in-room user and a second in-room user based on the metadata and the first number of pixels across the face of the first in-room user and a number of pixels across the face of the second in-room user.
Inventor(s): Eungnak Han of Portland OR (US) for intel corporation, Florian Gstrein of Portland OR (US) for intel corporation, Gurpreet Singh of Portland OR (US) for intel corporation
IPC Code(s): H01L21/027, H01L21/033, H01L21/8234, H01L23/528, H01L23/532, H01L27/088
CPC Code(s): H01L21/0274
Abstract: a cross-linkable diblock copolymer can facilitate multi-pitch patterning for forming an ic device. the ic device may include a metal layer with different pitches. the metal layer may include a first region having a first pitch and a second region having a second pitch that is greater than the first pitch. the cross-linkable diblock copolymer may be deposited over the metal layer. the portion of the diblock copolymer over the second region may be exposed to light (e.g., uv), which causes cross-linking of functional groups in the diblock copolymer. the cross-linking may form a structure that includes an amorphous phase of the diblock copolymer. the structure may be over and aligned with the second region of the metal layer. after the structure is formed, the diblock copolymer over the first region may self-assemble and form lamellar structures that are aligned with metal lines and insulative structures in the first region.
Inventor(s): Valluri R. RAO of Saratoga CA (US) for intel corporation, Patrick MORROW of Portland OR (US) for intel corporation, Rishabh MEHANDRU of Portland OR (US) for intel corporation, Doug INGERLY of Portland OR (US) for intel corporation, Kimin JUN of Portland OR (US) for intel corporation, Kevin O'BRIEN of Portland OR (US) for intel corporation, Paul FISCHER of Portland OR (US) for intel corporation, Szuya S. LIAO of Portland OR (US) for intel corporation, Bruce BLOCK of Portland OR (US) for intel corporation
IPC Code(s): H01L21/822, G01R1/073, H01L21/306, H01L21/66, H01L21/683, H01L21/8238, H01L23/00, H01L23/528, H01L23/532, H01L25/065, H01L27/092, H01L27/12, H01L29/04, H01L29/06, H01L29/08, H01L29/16, H01L29/20, H01L29/66
CPC Code(s): H01L21/8221
Abstract: integrated circuit cell architectures including both front-side and back-side structures. one or more of back-side implant, semiconductor deposition, dielectric deposition, metallization, film patterning, and wafer-level layer transfer is integrated with front-side processing. such double-side processing may entail revealing a back side of structures fabricated from the front-side of a substrate. host-donor substrate assemblies may be built-up to support and protect front-side structures during back-side processing. front-side devices, such as fets, may be modified and/or interconnected during back-side processing. electrical test may be performed from front and back sides of a workpiece. back-side devices, such as fets, may be integrated with front-side devices to expand device functionality, improve performance, or increase device density.
Inventor(s): Kristof Darmawikarta of Chandler AZ (US) for intel corporation, Steve S. Cho of Chandler AZ (US) for intel corporation, Hiroki Tanaka of Gilbert AZ (US) for intel corporation, Haobo Chen of Chandler AZ (US) for intel corporation, Gang Duan of Chandler AZ (US) for intel corporation, Brandon Christian Marin of Gilbert AZ (US) for intel corporation, Suddhasattwa Nad of Chandler AZ (US) for intel corporation, Srinivas V. Pietambaram of Chandler AZ (US) for intel corporation
IPC Code(s): H01L23/15, C23C18/16, C23C18/18, C23C18/48, H01L21/48, H01L23/00, H01L23/498, H01L25/065
CPC Code(s): H01L23/15
Abstract: apparatus and methods for electroless surface finishing on glass. a planarization process is performed on buildup dielectric and/or solder resist to create a flatter, more planar, upper surface for a substrate having a glass layer. planarity is characterized by having surface variations of less than about 5 microns, as measured by recesses and/or protrusions. the planar surface enables finishing the substrate surface with an electroless nipdau process.
Inventor(s): Lizabeth KESER of Munich (DE) for intel corporation, Bernd WAIDHAS of Pettendorf (DE) for intel corporation, Thomas ORT of Veitsbronn (DE) for intel corporation, Thomas WAGNER of Regelsbach (DE) for intel corporation
IPC Code(s): H01L23/31, H01L21/56, H01L23/00, H01L23/522
CPC Code(s): H01L23/3114
Abstract: a semiconductor device and method of including peripheral devices into a package is disclosed. in one example, a peripheral device includes a passive device such as a capacitor or an inductor. examples are shown that include a peripheral device that is substantially the same thickness as a die or a die assembly. examples are further shown that use this configuration in a fan out process to form semiconductor devices.
Inventor(s): Gang Duan of Chandler AZ (US) for intel corporation, Rahul Manepalli of Chandler AZ (US) for intel corporation, Srinivas Pietambaram of Chandler AZ (US) for intel corporation, Brandon Marin of Gilbert AZ (US) for intel corporation, Suddhasattwa Nad of Chandler AZ (US) for intel corporation, Jeremy Ecton of Gilbert AZ (US) for intel corporation
IPC Code(s): H01L23/538, H01L21/48, H01L21/56, H01L21/683, H01L23/31
CPC Code(s): H01L23/5381
Abstract: an integrated circuit (ic) package comprises a first ic die having first metallization features, a second ic die having second metallization features, and a third ic die having third metallization features. a glass layer is between the third ic die and both of the first ic die and the second ic die. a plurality of first through vias extend through the glass layer, coupling the third metallization features with first ones of the first metallization features and with first ones of the second metallization features. a plurality of second through vias extend through the glass layer. a dielectric material is around the third die and a package metallization is within the dielectric material. the package metallization is coupled to at least one of the first, second, or third ic die, and terminating at a plurality of package interconnect interfaces.
Inventor(s): Suddhasattwa Nad of Chandler AZ (US) for intel corporation, Brandon Marin of Gilbert AZ (US) for intel corporation, Jeremy Ecton of Gilbert AZ (US) for intel corporation, Gang Duan of Chandler AZ (US) for intel corporation, Srinivas Pietambaram of Chandler AZ (US) for intel corporation
IPC Code(s): H01L25/16, G02B6/42, H01L21/56, H01L23/00, H01L23/433
CPC Code(s): H01L25/167
Abstract: apparatuses, systems, assemblies, and techniques related to integrating photonics integrated circuit devices and electronic integrated circuit devices into an assembly or module are described. an integrated module includes a photonics integrated circuit device within an opening of a glass core substrate and an electronic integrated circuit device direct bonded to the photonics integrated circuit device. an optical waveguide is within or on the glass core substrate and has a terminal end edge coupled to the photonics integrated circuit device within the opening.
20240194672.MULTI-PITCH PATTERNING THROUGH ONE-STEP FLOW_simplified_abstract_(intel corporation)
Inventor(s): Bharath Bangalore Rajeeva of Hillsboro OR (US) for intel corporation, Manish Chandhok of Beaverton OR (US) for intel corporation, Gurpreet Singh of Portland OR (US) for intel corporation, Kevin Huggins of Beaverton OR (US) for intel corporation, Eungnak Han of Portland OR (US) for intel corporation, Florian Gstrein of Portland OR (US) for intel corporation, Marko Radosavljevic of Portland OR (US) for intel corporation
IPC Code(s): H01L27/088, H01L21/02, H01L21/027, H01L23/522, H01L29/10, H01L29/423
CPC Code(s): H01L27/088
Abstract: an ic device may include a first conductive structure in a first section and a second conductive structure in a second section. the second conductive structure is in parallel with the first conductive structure in a first direction. a dimension of the second conductive structure in a second direction perpendicular to the first direction is greater than a dimension of the first conductive structure in the second direction. the first conductive structure may be coupled to a channel region of a transistor. the second conductive structure may be coupled to a channel region of another transistor. a first structure comprising a first dielectric material may be over the first conductive structure. a second structure comprising a second dielectric material may be over the second section. a third structure comprising the first dielectric material may be over the second conductive structure and be at least partially surrounded by the second structure.
Inventor(s): Hwichan Jun of Portland OR (US) for intel corporation, Guillaume Bouche of Hillsboro OR (US) for intel corporation
IPC Code(s): H01L27/088, H01L29/06, H01L29/08, H01L29/423, H01L29/78
CPC Code(s): H01L27/0886
Abstract: techniques to form semiconductor devices that include both finfet and gate-all-around (gaa) devices on same substrate. the finfet and gaa devices may have different gate oxide thicknesses and/or shallow trench isolation (sti) thicknesses, along with coplanar channel regions. in an example, a first semiconductor device includes a finfet structure with a first gate structure around or otherwise on a semiconductor fin while a second semiconductor device includes a gaa structure with a second gate structure around or otherwise on a plurality of semiconductor bodies (e.g., nanoribbons). the first gate structure includes a first gate dielectric and a first gate electrode (e.g., conductive material such as workfunction material and/or gate fill metal) and the second gate structure includes a second gate dielectric and a second gate electrode. the first gate dielectric includes a first gate oxide layer that is thicker than a second gate oxide layer of the second gate dielectric.
Inventor(s): Matthew J. Prince of Portland OR (US) for intel corporation, Amitesh Shrivastava of Chandler AZ (US) for intel corporation, Walid M. Hafez of Portland OR (US) for intel corporation, Anurag A. Jain of Portland OR (US) for intel corporation, Gary Ding of Portland OR (US) for intel corporation, Sharath Hegde of Portland OR (US) for intel corporation, Caitlin M. Kilroy of Hillsboro OR (US) for intel corporation, Inki Kim of Portland OR (US) for intel corporation
IPC Code(s): H01L29/06, H01L21/033, H01L29/08, H01L29/66
CPC Code(s): H01L29/0673
Abstract: techniques are provided herein to use a chemical mechanical polishing (cmp) process to polish carbon hard mask (chm) for a variety of useful semiconductor fabrication applications. in one example, a cmp process that uses a silica-based slurry is used to polish chm formed over gate trenches of different widths, such that the chm can recess to substantially the same height within the gate trenches of different widths. in another example, chm may be deposited over groups of fins or a backbone structure and polished using a cmp process with a silica-based slurry to ensure a planar top surface of chm over the groups of fins or backbone structure.
Inventor(s): Walid EL HAJJ of Antibes (FR) for intel corporation, John ROMAN of Hillsboro OR (US) for intel corporation, Nawfal ASRIH of Mandelieu-la-Napoule (FR) for intel corporation
IPC Code(s): H01Q1/24, G01R29/08
CPC Code(s): H01Q1/245
Abstract: methods of arranging and designing antennas to optimize electromagnetic field distributions in the near-field region of an antenna to optimize parameters such as electric field (e-field), magnetic field (h-field), specific absorption rate (sar), power density (pd), etc. while ensuring specific performance of the antenna in the far-field region in terms of gain, efficiency, radiation pattern, etc.
Inventor(s): Seunghee Han of San Jose CA (US) for intel corporation, Yingyang Li of Beijing (CN) for intel corporation, Yi Wang of Beijing (CN) for intel corporation
IPC Code(s): H04L5/00, H04W72/232
CPC Code(s): H04L5/0035
Abstract: an apparatus and system are described to support secondary cell (scell) dormancy switching when cross-carrier scheduling (ccs) from scell to primary cell (pcell) transmission is supported are described. a physical downlink control channel (pdcch) transmission on the sscell has a downlink control information format (dci) format 0_1 or 1_1 containing a scell dormancy indication field and a cif are used to indicate ccs and scell dormancy switching to deactivate the scell. the cif value is either 0 or indicates the pcell and may depend on whether physical downlink shared channel (pdsch) transmission is scheduled. the dci triggers bandwidth part (bwp) switching for the pcell to indicate to the ue to switch to monitoring ue-specific search space sets on the pcell instead of on the scell.
20240195605.TECHNOLOGIES FOR DYNAMIC ACCELERATOR SELECTION_simplified_abstract_(intel corporation)
Inventor(s): Francesc Guim Bernat of Barcelona (ES) for intel corporation
IPC Code(s): H04L9/08, B25J15/00, G06F1/18, G06F1/20, G06F3/06, G06F9/28, G06F9/44, G06F9/4401, G06F9/445, G06F9/448, G06F9/48, G06F9/50, G06F11/34, G06F12/02, G06F12/06, G06F12/0802, G06F12/1045, G06F12/14, G06F13/16, G06F13/40, G06F13/42, G06F15/16, G06F15/173, G06F15/78, G06F16/11, G06F16/22, G06F16/23, G06F16/2453, G06F16/2455, G06F16/248, G06F16/25, G06F16/901, G06F21/10, G06F30/34, G06N3/063, G06Q10/0631, G06Q30/0283, G11C8/12, G11C29/02, G11C29/36, G11C29/38, G11C29/44, H04L9/40, H04L41/0213, H04L41/0668, H04L41/0677, H04L41/0893, H04L41/0896, H04L41/14, H04L41/5019, H04L41/5025, H04L45/28, H04L45/7453, H04L47/11, H04L47/125, H04L49/00, H04L49/351, H04L49/40, H04L49/9005, H04L67/1001, H04L67/1008, H04L69/12, H04L69/22, H04L69/32, H04L69/321, H05K7/14, H05K7/18, H05K7/20
CPC Code(s): H04L9/0819
Abstract: technologies for dynamic accelerator selection include a compute sled. the compute sled includes a network interface controller to communicate with a remote accelerator of an accelerator sled over a network, where the network interface controller includes a local accelerator and a compute engine. the compute engine is to obtain network telemetry data indicative of a level of bandwidth saturation of the network. the compute engine is also to determine whether to accelerate a function managed by the compute sled. the compute engine is further to determine, in response to a determination to accelerate the function, whether to offload the function to the remote accelerator of the accelerator sled based on the telemetry data. also the compute engine is to assign, in response a determination not to offload the function to the remote accelerator, the function to the local accelerator of the network interface controller.
Inventor(s): Kshitij Doshi of Tempe AZ (US) for intel corporation, Ned M. Smith of Beaverton OR (US) for intel corporation, Rajesh Poornachandran of Portland OR (US) for intel corporation, Sunil K. Cheruvu of Tempe AZ (US) for intel corporation, David W. Palmer of Beaverton OR (US) for intel corporation
IPC Code(s): H04L9/32, H04L9/08
CPC Code(s): H04L9/3247
Abstract: the technology described herein includes a plurality of intellectual property (ip) blocks; and a host ip block, the host ip block including a primary root of trust (rot) ip block (prib) coupled to the plurality of ip blocks, to receive a request from a computing system to establish a secure communications session with a selected one of a plurality of intellectual property (ip) blocks, authenticate and attest the computing system, sign evidence of the prib with a prib key, send the signed evidence of the prib to the computing system, and establish the secure communications session between the computing system and the selected ip block if the prib is trusted by the computing system based at least in part on the signed evidence of the prib.
Inventor(s): Iosif GASPARAKIS of Hillsboro OR (US) for intel corporation, Malini K. BHANDARU of San Jose CA (US) for intel corporation, Ranganath SUNKU of Beaverton OR (US) for intel corporation
IPC Code(s): H04L41/5003, G06F9/455, G06F12/084, G06F12/0864, H04L43/08, H04L47/70, H04L67/568
CPC Code(s): H04L41/5003
Abstract: technologies for managing cache quality of service (qos) include a compute node that includes a network interface controller (nic) configured to identify a total amount of available shared cache ways of a last level cache (llc) of the compute node and identify a destination address for each of a plurality of virtual machines (vms) managed by the compute node. the nic is further configured to calculate a recommended amount of cache ways for each workload type associated with vms based on network traffic to be received by the nic and processed by each of the vms, wherein the recommended amount of cache ways includes a recommended amount of hardware i/o llc cache ways and a recommended amount of isolated llc cache ways usable to update a cache qos register that includes the recommended amount of cache ways for each workload type. other embodiments are described herein.
20240195740.RECEIVER-BASED PRECISION CONGESTION CONTROL_simplified_abstract_(intel corporation)
Inventor(s): Rong Pan of Saratoga CA (US) for intel corporation, Pedro Yebenes Segura of San Jose CA (US) for intel corporation, Roberto Penaranda Cebrian of Santa Clara CA (US) for intel corporation, Robert Southworth of Chatsworth CA (US) for intel corporation, Malek Musleh of Portland OR (US) for intel corporation, Jeongkeun Lee of Los Altos CA (US) for intel corporation, Changhoon Kim of Palo Alto CA (US) for intel corporation
IPC Code(s): H04L45/74, G06F15/173, H04L45/00, H04L47/12
CPC Code(s): H04L45/74
Abstract: examples described herein relate to a network agent, when operational, to: receive a packet, determine transmit rate-related information for a sender network device based at least on operational and telemetry information accumulated in the received packet, and transmit the transmit rate-related information to the sender network device. in some examples, the network agent includes a network device coupled to a server, a server, or a network device. in some examples, the operational and telemetry information comprises: telemetry information generated by at least one network device in a path from the sender network device to the network agent.
20240195749.PATH SELECTION FOR PACKET TRANSMISSION_simplified_abstract_(intel corporation)
Inventor(s): Anurag AGRAWAL of Santa Clara CA (US) for intel corporation, John Andrew FINGERHUT of Cary NC (US) for intel corporation, Xiaoyan DING of Lantau Island (HK) for intel corporation, Song ZHANG of Beijing (CN) for intel corporation
IPC Code(s): H04L47/628, H04L45/24, H04L49/00
CPC Code(s): H04L47/628
Abstract: examples described herein relate to a network interface device comprising a multi-stage programmable packet processing pipeline circuitry to determine a path to transmit a packet based on relative network traffic transmitted via multiple paths. in some examples, determine a path to transmit a packet is based on deficit round robin (drr). in some examples, the programmable packet processing pipeline circuitry includes: a first stage to manage two or more paths, wherein a path of the two or more paths of the first stage is associated with two or more child nodes, a second stage to manage two or more paths, wherein a path of the two or more paths of the second stage is associated with two or more child nodes, and at least one child node is associated with the determined path.
20240195789.CRYPTOGRAPHIC DATA PROCESSING USING A DMA ENGINE_simplified_abstract_(intel corporation)
Inventor(s): Kshitij Arun Doshi of Tempe AZ (US) for intel corporation, Uzair Qureshi of Chandler AZ (US) for intel corporation, Lokpraveen Mosur of Gilbert AZ (US) for intel corporation, Patrick Fleming of Portlaoise (IE) for intel corporation, Stephen Doyle of Ennis CE (IE) for intel corporation, Brian Andrew Keating of Limerick (IE) for intel corporation, Ned M. Smith of Beaverton OR (US) for intel corporation
IPC Code(s): H04L9/40, G06F13/28, G06F21/60
CPC Code(s): H04L63/0435
Abstract: a computing device includes a direct memory access (dma) engine coupled to a memory, a network interface, and processing circuitry. the processing circuitry is to perform a secure exchange with a second computing device to negotiate a shared encryption key, based on a request for data received via the network interface from the second computing device. the dma engine is to retrieve the data from a storage location based on an encryption command. the encryption command indicates the storage location. the dma engine is to encrypt the data based on the shared encryption key to generate encrypted data, and store the encrypted data in the memory.
Inventor(s): Dario Sabella of Gassino (IT) for intel corporation, Samar Shailendra of Bangalore (IN) for intel corporation, Miltiadis Filippou of München (DE) for intel corporation
IPC Code(s): H04L67/289, H04L67/51
CPC Code(s): H04L67/289
Abstract: various approaches are provided for enabling edge dual deployment (edd). edd includes multi-access edge computing (mec) dual deployments (mdd) initialization performed as a preliminary step before the actual registration, as a mechanism to allow the two platforms (ees and mec platform) to communicate directly. mdd establishment is a dual registration mechanism of the edge application in the edd environment. mdd update and closing are analogous registration update and de-registration processes, with both sub-cases.
Inventor(s): Dawei YING of Portland OR (US) for intel corporation, Leifeng RUAN of Beijing (CN) for intel corporation, Zongrui DING of Portland OR (US) for intel corporation, Qian LI of Portland OR (US) for intel corporation, Jaemin HAN of Portland OR (US) for intel corporation, Geng WU of Portland OR (US) for intel corporation
IPC Code(s): H04W4/60, H04W8/18
CPC Code(s): H04W4/60
Abstract: this disclosure describes systems, methods, and devices related to data functions. a device may identify a first request received from a data consumer non-rt ric application (rapp), wherein the first request is received over an r1 termination interface. the device may cause to send a first response to the data consumer rapp in response to the first request. the device may identify a data producer rapp by checking a data catalog in order to satisfy the first request. the device may cause to send a notification frame to the data consumer rapp over the r1 termination interface indicating that data will be delivered to the data consumer rapp.
Inventor(s): Joey Chou of Santa Clara CA (US) for intel corporation, Yizhi Yao of Chandler AZ (US) for intel corporation
IPC Code(s): H04W24/04, H04L61/5046, H04W8/26, H04W24/10, H04W84/18
CPC Code(s): H04W24/04
Abstract: methods, systems, and storage media are described for physical-layer cell identifier (pci) configuration and mobility robustness optimization (mro). in particular, some embodiments may be directed to fifth-generation self-organizing network (5g son) solutions such as the management of distributed physical-layer cell identifier (pci) configuration, centralized pci configuration, and mro. other embodiments may be described and/or claimed.
20240196239.UPLINK IMPACT ON PUCCH SCELL ACTIVATION DELAY_simplified_abstract_(intel corporation)
Inventor(s): Hua Li of Arlington VA (US) for intel corporation, Meng Zhang of Beijing (CN) for intel corporation, Andrey Chervyakov of Nizhny Novgorod (RU) for intel corporation, Rui Huang of Beijing, 11 (CN) for intel corporation, IIYA Bolotin of Nizhny-Novgorod (RU) for intel corporation
IPC Code(s): H04W24/08, H04W24/10
CPC Code(s): H04W24/08
Abstract: a computer-readable storage medium stores instructions to configure a ue for scell activation in a 5g nr network, and to cause the ue to perform operations including decoding a first mac ce received from a base station on a pdsch. the first mac ce includes a pucch scell activation command. a second mac ce is decoded, which includes pl-rs configuration information. dl activation process is performed within a pre-configured activation time starting at a first slot of the first mac ce reception. the availability of a pl-rs is determined based on the pl-rs configuration information. cslrs measurements are performed in response to the pucch scell activation command. the cslrs measurements include a path loss calculation performed within an extended time period starting after the dl activation process and having a duration based on the availability of the pl-rs.
20240196341.POWER SPECTRAL DENSITY LIMIT FOR 6 GHZ_simplified_abstract_(intel corporation)
Inventor(s): Laurent Cariou of Milizac (FR) for intel corporation, Ido Ouzieli of Tel Aviv (IL) for intel corporation, Carlos Cordeiro of Portland OR (US) for intel corporation, Hassan Yaghoobi of San Jose CA (US) for intel corporation, Thomas J. Kenney of Portland OR (US) for intel corporation
IPC Code(s): H04W52/34, H04W52/32, H04W52/36, H04W52/52
CPC Code(s): H04W52/346
Abstract: this disclosure describes systems, methods, and devices related to power spectral density (psd) limit. a device may generate a frame comprising one or more elements to be sent to a first station device, wherein the frame is to be sent using a 6 ghz band. the device may include in the frame, information associated with a psd limit on a per bandwidth size basis of the 6 ghz band. the device may cause to send the frame to the first station device.
Inventor(s): Sajal Kumar DAS of Bangalore (IN) for intel corporation, Madhukiran SRINIVASAREDDY of Bangalore (IN) for intel corporation, Jayprakash THAKUR of Bangalore (IN) for intel corporation, Maruti TAMRAKAR of Chhattisgarh (IN) for intel corporation, Mallari HANCHATE of Bangalore (IN) for intel corporation, Vamshi Krishna AAGIRU of Bangalore (IN) for intel corporation, Abhijith PRABHA of Piravom (IN) for intel corporation, Sagar GUPTA of Pradesh (IN) for intel corporation, Mythili HEGDE of Bangalore (IN) for intel corporation
IPC Code(s): H04W52/36, H04L1/00, H04W52/28
CPC Code(s): H04W52/367
Abstract: a mobile radio terminal device may include a processor configured to receive information that one or more antennas of the mobile radio terminal device are in proximity of a human body part of a user of the mobile radio terminal device, modify a transmission configuration of the mobile radio terminal device based on the received information, and generate a message representing the changed transmission configuration.
Inventor(s): Vamshi Krishna AAGIRU of Bangalore (IN) for intel corporation, Nithesha ANANDA of Surathkal (IN) for intel corporation, Santhosh AP of Bangalore (IN) for intel corporation, Abir CHATTERJEE of Khandaghosh (IN) for intel corporation, Sajal Kumar DAS of Bangalore (IN) for intel corporation, Walid EL HAJJ of Antibes (FR) for intel corporation, Noam KOGOS of Ramat Hasharon (IL) for intel corporation, Adiel LANGER of Petah Tiqwa (IL) for intel corporation, Gil MEYUHAS of Tel-Aviv (IL) for intel corporation, Amir RUBIN of Kiryat Ono (IL) for intel corporation, Michael SHACHAR of Kfar Glikson (IL) for intel corporation, Nidhi P. SHETTY of Bangalore (IN) for intel corporation, Madhukiran SRINIVASAREDDY of Bangalore (IN) for intel corporation, Ricardo VELASCO of San Jose CA (US) for intel corporation
IPC Code(s): H04W52/36, H04W52/22, H04W76/28
CPC Code(s): H04W52/367
Abstract: devices with radiating antennas are subject to various regulations designed to limit the absorption of radiofrequency energy in a human body part in close proximity to a radiating antenna. various conventional strategies are available for management of transmissions to comply with these regulations; however, each of these conventional strategies has drawbacks, such as a negative effect on the wireless link. various strategies are disclosed herein to comply with the requisite regulations while maintaining the wireless link. in addition, strategies are presented to select wireless link rates, taking into account limitations that may be in place to satisfy the necessary regulations.
Inventor(s): Gil MEYUHAS of Tel Aviv (IL) for intel corporation, Noam KOGOS of Ramat Hasharon (IL) for intel corporation, Adiel LANGER of Petah Tiqwa (IL) for intel corporation
IPC Code(s): H04W52/36, H04W52/28
CPC Code(s): H04W52/367
Abstract: methods and apparatus are provided to control a body proximity sensing operation. an apparatus for a wireless communication device, the apparatus may include an interface to a radio frequency (rf) transceiver, and processing circuitry configured to: monitor one or more transmit power limitation parameters used to limit transmit power of transmissions of rf communication signals, and cause, based on a first transmit power limit including a monitored transmit power limitation parameter and a second transmit power limit, the rf transceiver to perform a body proximity sensing operation.
Inventor(s): Fatemeh Hamidi-Sepehr of San Jose CA (US) for intel corporation, Murali Narasimha of Lake Wswego OR (US) for intel corporation, Yujian Zhang of Beijing (CN) for intel corporation, Mustafa Emara of Munich (DE) for intel corporation, Qian Li of Beaverton OR (US) for intel corporation
IPC Code(s): H04W72/0446, H04L5/00, H04W72/21
CPC Code(s): H04W72/0446
Abstract: a non-transitory computer-readable storage medium stores instructions for execution by one or more processors of user equipment (ue). the instructions cause the ue to encode a scheduling request (sr) for transmission to a base station during one of a plurality of sr occasions. the sr includes an indication based on a size of an uplink (ul) data packet. control information received from the base station in response to the sr is decoded. the control information includes a scheduling grant based on the size of the ul data packet. the ul data packet is encoded for transmission using the scheduling grant. the ul data packet is encoded for transmission using the scheduling grant.
20240196413.BWP-BASED OPERATIONS FOR REDCAP USER EQUIPMENTS_simplified_abstract_(intel corporation)
Inventor(s): Debdeep Chatterjee of San Jose CA (US) for intel corporation, Gang Xiong of Beaverton OR (US) for intel corporation, Toufiqul Islam of Santa Clara CA (US) for intel corporation, Yingyang Li of Beijing (CN) for intel corporation
IPC Code(s): H04W72/232, H04L5/00, H04W74/0833
CPC Code(s): H04W72/232
Abstract: a computer-readable storage medium stores instructions to configure a ue for reduced capability (redcap) operation in a 5g nr network, and to cause the ue to perform operations. the operations include decoding a master information block (mib) to determine a control resource set (coreset) and a common search space (css): decoding a system information block (sib) in a physical downlink shared channel (pdsch) scheduled by a downlink control information (dci) format, the dci format received based on the coreset and the css: determining an additional coreset within a separate initial de bwp using the sib: and performing reception of a physical downlink control channel (pdcch) in a pdcch type1 common search space (css) set or a pdsch associated with random access (ra) procedure in the separate initial de bwp.
- Intel Corporation
- G01S7/481
- G01R19/00
- G01S7/497
- G01S17/931
- CPC G01S7/4817
- Intel corporation
- G02B6/42
- CPC G02B6/4214
- G06F1/3225
- G06F1/3287
- CPC G06F1/3225
- G06F3/01
- G06T3/60
- G06T7/73
- G06T7/80
- CPC G06F3/013
- G06F9/30
- G06F7/485
- G06F7/487
- G06F7/76
- G06F9/38
- G06F17/16
- CPC G06F9/30036
- G06F9/455
- CPC G06F9/45558
- G06F12/02
- G11C29/54
- CPC G06F12/023
- G06F13/16
- H10B12/00
- CPC G06F13/1689
- G06F21/54
- G06F11/10
- G06F21/60
- CPC G06F21/54
- H04L9/08
- CPC G06F21/602
- CPC G06F21/604
- G06N10/20
- CPC G06N10/20
- G06Q30/018
- G06F9/50
- CPC G06Q30/018
- G06T1/20
- CPC G06T1/20
- G06V40/10
- G06V10/82
- G06V40/60
- CPC G06V40/103
- G10L21/0364
- G06T7/50
- G06V40/16
- H04R1/32
- CPC G10L21/0364
- H01L21/027
- H01L21/033
- H01L21/8234
- H01L23/528
- H01L23/532
- H01L27/088
- CPC H01L21/0274
- H01L21/822
- G01R1/073
- H01L21/306
- H01L21/66
- H01L21/683
- H01L21/8238
- H01L23/00
- H01L25/065
- H01L27/092
- H01L27/12
- H01L29/04
- H01L29/06
- H01L29/08
- H01L29/16
- H01L29/20
- H01L29/66
- CPC H01L21/8221
- H01L23/15
- C23C18/16
- C23C18/18
- C23C18/48
- H01L21/48
- H01L23/498
- CPC H01L23/15
- H01L23/31
- H01L21/56
- H01L23/522
- CPC H01L23/3114
- H01L23/538
- CPC H01L23/5381
- H01L25/16
- H01L23/433
- CPC H01L25/167
- H01L21/02
- H01L29/10
- H01L29/423
- CPC H01L27/088
- H01L29/78
- CPC H01L27/0886
- CPC H01L29/0673
- H01Q1/24
- G01R29/08
- CPC H01Q1/245
- H04L5/00
- H04W72/232
- CPC H04L5/0035
- B25J15/00
- G06F1/18
- G06F1/20
- G06F3/06
- G06F9/28
- G06F9/44
- G06F9/4401
- G06F9/445
- G06F9/448
- G06F9/48
- G06F11/34
- G06F12/06
- G06F12/0802
- G06F12/1045
- G06F12/14
- G06F13/40
- G06F13/42
- G06F15/16
- G06F15/173
- G06F15/78
- G06F16/11
- G06F16/22
- G06F16/23
- G06F16/2453
- G06F16/2455
- G06F16/248
- G06F16/25
- G06F16/901
- G06F21/10
- G06F30/34
- G06N3/063
- G06Q10/0631
- G06Q30/0283
- G11C8/12
- G11C29/02
- G11C29/36
- G11C29/38
- G11C29/44
- H04L9/40
- H04L41/0213
- H04L41/0668
- H04L41/0677
- H04L41/0893
- H04L41/0896
- H04L41/14
- H04L41/5019
- H04L41/5025
- H04L45/28
- H04L45/7453
- H04L47/11
- H04L47/125
- H04L49/00
- H04L49/351
- H04L49/40
- H04L49/9005
- H04L67/1001
- H04L67/1008
- H04L69/12
- H04L69/22
- H04L69/32
- H04L69/321
- H05K7/14
- H05K7/18
- H05K7/20
- CPC H04L9/0819
- H04L9/32
- CPC H04L9/3247
- H04L41/5003
- G06F12/084
- G06F12/0864
- H04L43/08
- H04L47/70
- H04L67/568
- CPC H04L41/5003
- H04L45/74
- H04L45/00
- H04L47/12
- CPC H04L45/74
- H04L47/628
- H04L45/24
- CPC H04L47/628
- G06F13/28
- CPC H04L63/0435
- H04L67/289
- H04L67/51
- CPC H04L67/289
- H04W4/60
- H04W8/18
- CPC H04W4/60
- H04W24/04
- H04L61/5046
- H04W8/26
- H04W24/10
- H04W84/18
- CPC H04W24/04
- H04W24/08
- CPC H04W24/08
- H04W52/34
- H04W52/32
- H04W52/36
- H04W52/52
- CPC H04W52/346
- H04L1/00
- H04W52/28
- CPC H04W52/367
- H04W52/22
- H04W76/28
- H04W72/0446
- H04W72/21
- CPC H04W72/0446
- H04W74/0833
- CPC H04W72/232
