Intel Corporation patent applications on July 4th, 2024
Patent Applications by Intel Corporation on July 4th, 2024
Intel Corporation: 152 patent applications
Intel Corporation has applied for patents in the areas of H01L23/00 (21), H01L23/498 (20), H01L21/48 (17), H01L29/66 (16), H01L29/06 (15) H01L25/18 (4), H01L23/49894 (3), H01L29/7606 (3), H04W72/1268 (3), G02B6/4214 (3)
With keywords such as: layer, device, substrate, die, memory, material, circuit, glass, semiconductor, and structure in patent application abstracts.
Patent Applications by Intel Corporation
20240217103. TRAJECTORY PLANNING SYSTEMS AND METHODS_simplified_abstract_(intel corporation)
Inventor(s): David Gomez Gutierrez of Tlaquepaque (MX) for intel corporation, Leobardo Campos Macias of Guadalajara (MX) for intel corporation, Christopher Cruz Ancona of Coyoacan (MX) for intel corporation, Rafael De La Guardia Gonzalez of Teuchitlan (MX) for intel corporation, Javier Felip Leon of Hillsboro OR (US) for intel corporation
IPC Code(s): B25J9/16
CPC Code(s): B25J9/1666
Abstract: techniques are disclosed for a trajectory planning of robots, such as collaborative robots (cobots). a controller of a robot may include a path planner, a trajectory generator, and a trajectory controller. the path planner may determine a plurality of waypoints defining a path between an initial pose of the robot and a goal pose of the robot. the trajectory generator may determine a trajectory between the initial pose and the goal pose based on the waypoints and one or more trajectory criterion. the trajectory controller may generate a control signal to control the robot based on the determined trajectory.
Inventor(s): Long Thanh NGUYEN of Ho Chi Minh City (VN) for intel corporation, Tin DO of Ho Chi Minh City (VN) for intel corporation, Le Hoai Bao NGUYEN of Dong Nai (VN) for intel corporation, Phu Tuc NGUYEN of Ho Chi Minh City (VN) for intel corporation, Hung Quy SOI of Ho Chi Minh City (VN) for intel corporation
IPC Code(s): B25J15/06, B25J9/16, B25J11/00, H05K3/36
CPC Code(s): B25J15/0683
Abstract: this disclosure describes enhanced substrate transfer arm (sta) and pedestal designs related to a thermal compression bonding process. the designs include multiple row patterns of the sta and the pedestal used to: pick up a first substrate row from a first row of a tray; place the first substrate row onto a first row of a bond stage corresponding to the first row of the tray; pick up a second substrate row from the tray; place, using the suction cups, the second substrate row onto a remaining empty row of the bond stage; pick up the first substrate row after thermal bonding from the bond stage; place the first substrate row after thermal bonding onto the tray; when all substrates from the tray have been thermally bonded, pick up a last substrate row after thermal bonding from the bond stage; and place the last substrate row onto the tray.
Inventor(s): Kristof DARMAWIKARTA of Chandler AZ (US) for intel corporation, Tarek A. IBRAHIM of Mesa AZ (US) for intel corporation, Srinivas V. PIETAMBARAM of Chandler AZ (US) for intel corporation, Dilan SENEVIRATNE of Chandler AZ (US) for intel corporation, Jieying KONG of Chandler AZ (US) for intel corporation, Thomas HEATON of Gilbert AZ (US) for intel corporation, Whitney BRYKS of Tempe AZ (US) for intel corporation, Vinith BEJUGAM of Chandler AZ (US) for intel corporation, Junxin WANG of Gilbert AZ (US) for intel corporation, Gang DUAN of Chandler AZ (US) for intel corporation
IPC Code(s): B32B17/10, B32B7/12, B32B17/02, B65D85/48
CPC Code(s): B32B17/10642
Abstract: embodiments disclosed herein include package substrates with glass stiffeners. in an embodiment, the package substrate comprises a first layer, where the first layer comprises glass. in an embodiment, the package substrate comprises a second layer over the first layer, where the second layer is a buildup film. in an embodiment, the package substrate further comprises an electrically conductive interconnect structure through the first layer and the second layer.
Inventor(s): Oliver Patterson of San Jose CA (US) for intel corporation, Kale Beckwitt of Portland OR (US) for intel corporation
IPC Code(s): G01N23/18, H01L21/67
CPC Code(s): G01N23/18
Abstract: systems, apparatus, articles of manufacture, and methods to inspect wafer manufacture are disclosed. an example apparatus includes processor circuitry to at least one of instantiate operations corresponding to the machine readable instructions or execute machine readable instructions to predict a structure of a semiconductor wafer that is to result from a second wafer manufacturing operation based on a first image of the semiconductor wafer obtained after a first wafer manufacturing operation, the second wafer manufacturing operation to be performed subsequent to the first wafer manufacturing operation, and determine whether an actual defect developed in the semiconductor wafer between completion of the first wafer manufacturing operation and completion of the second wafer manufacturing operation based on the predicted structure of the semiconductor wafer and a second image representative of the semiconductor wafer after completion of the second wafer manufacturing operation.
Inventor(s): Prasoon JOSHI of Hillsboro OR (US) for intel corporation, Joseph BASILE of Beaverton OR (US) for intel corporation, Eric BRUMMER of Orangevale CA (US) for intel corporation, Evan FLEDELL of Portland OR (US) for intel corporation, Joshua FREIER of Portland OR (US) for intel corporation, Brett GROSSMAN of Forest Grove OR (US) for intel corporation, Jennifer HUENING of Hillsboro OR (US) for intel corporation, Matthew KIRSCH of Hillsboro OR (US) for intel corporation, James NEEB of Gilbert AZ (US) for intel corporation, Robert NESTING of Forest Grove OR (US) for intel corporation, Charles PETERSON of Hillsboro OR (US) for intel corporation, Ashraf REZAIE of Portland OR (US) for intel corporation, Ling Hong TAN of Simpang Ampat (MY) for intel corporation, Xianghong TONG of Hillsboro OR (US) for intel corporation, Vladimir VLASYUK of Folsom CA (US) for intel corporation
IPC Code(s): G01R31/28, G01R1/07
CPC Code(s): G01R31/2834
Abstract: the disclosure is directed to a device interface, system and method for connecting a tester interface unit (tiu) to an automated test equipment that enable data rates of over 1.0 gbps over scalable high speed cables. the device interface includes at least one flange assembly connecting an electron beam probe (ebp) in a vacuum-controlled environment to an ambient environment, the flange assembly including a vacuum-controlled passthrough environment coupled to the ebp, a plurality of cables coupled to a plurality of connectors within the vacuum-controlled passthrough environment to provide power, control and signal connections to the ambient environment, the plurality cables including plurality of hermetically-sealed printed circuit boards (pcbs) carrying digital high speed signals from the tiu, a plurality of power cables supporting a plurality of power requirements, and a plurality of ate communication control cables to direct the tiu.
Inventor(s): Rakesh KANDULA of Bangalore (IN) for intel corporation, Edward BRAZIL of Naas (IE) for intel corporation, Amir ZALTZMAN of Udim (IL) for intel corporation, Alon PERETZ of Haifa (IL) for intel corporation, Alexander SEREBRYANIK of Kiryat Ata (IL) for intel corporation, Chai ZIV of Even Shemuel (IL) for intel corporation, Nir BARUCH of Tel Aviv (IL) for intel corporation, Gilad SHAYEVITZ of Olesh (IL) for intel corporation
IPC Code(s): G01R31/317
CPC Code(s): G01R31/31705
Abstract: examples include techniques for debug, survivability, and infield testing of a system-on-a-chip (soc) or system-on-a-package (sop) that can be configured as a processor. the techniques include using an agent coupled with a network-on-chip (noc) fabric to launch transaction over the noc fabric to test or debug agents, devices, or devices coupled to the soc or sop and/or interconnected to the noc fabric.
20240219629. PHOTONIC INTEGRATED CIRCUITS WITH GLASS CORES_simplified_abstract_(intel corporation)
Inventor(s): Changhua Liu of Chandler AZ (US) for intel corporation, Robert May of Chandler AZ (US) for intel corporation, Bai Nie of Chandler AZ (US) for intel corporation
IPC Code(s): G02B6/12, G02B6/13, H01L23/538, H01L25/00, H01L25/18
CPC Code(s): G02B6/12004
Abstract: methods, apparatus, systems, and articles of manufacture are disclosed utilizing photonic integrated circuits with glass cores. an example apparatus comprises a primary package substrate including a glass core and first contacts along an outer surface of the primary package substrate, a photonic integrated circuit (pic) within the primary package substrate adjacent a surface of the glass core, and a secondary package substrate supporting a semiconductor die on a first side of the secondary package substrate, the secondary package substrate including second contacts on a second side of the secondary package substrate, the first contacts electrically coupled to the second contacts.
Inventor(s): Umesh Prasad of Chandler AZ (US) for intel corporation, Suddhasattwa Nad of Chandler AZ (US) for intel corporation, Benjamin T. Duong of Phoenix AZ (US) for intel corporation, Yi Yang of Gilbert AZ (US) for intel corporation
IPC Code(s): G02B6/122, G02B1/02, G02B3/00
CPC Code(s): G02B6/122
Abstract: technologies for integrated graded index (grin) lenses for photonic circuits is disclosed. in one illustrative embodiment, a glass substrate has a cavity in which a grin lens is disposed. in other embodiments, the grin lens may be on a surface of the glass substrate. the grin lens focuses and collimates light to a free-space beam from a waveguide defined in the glass substrate. another component such as a photonic integrated circuit (pic) die may also have a grin lens and focus the free-space beam into a waveguide in the pic die. the use of grin lenses allows for passive coupling to waveguides without further active alignment that minimizes signal transmission losses.
Inventor(s): Suddhasattwa Nad of Chandler AZ (US) for intel corporation, Brandon Marin of Gilbert AZ (US) for intel corporation, Jeremy Ecton of Gilbert AZ (US) for intel corporation, Gang Duan of Chandler AZ (US) for intel corporation, Srinivas Pietambaram of Chandler AZ (US) for intel corporation
IPC Code(s): G02B6/122, G02B6/138
CPC Code(s): G02B6/1221
Abstract: an integrated circuit (ic) module includes a photonic ic, an electrical ic, and a switchable waveguide device that, using a signal from the electrical ic, controls optical signals to or from the photonic ic. the switchable waveguide device may be formed by coupling metallization structures on both sides of, and either level with or below, a nonlinear optical material. the metallization structures may be in the photonic or electrical ic. the nonlinear optical material may be above the electrical ic in the photonic ic or on a glass substrate. the photonic and electrical ics may be hybrid bonded or soldered together. the ic module may be coupled to a system substrate.
Inventor(s): Suddhasattwa Nad of Chandler AZ (US) for intel corporation, Benjamin Duong of Phoenix AZ (US) for intel corporation, Hiroki Tanaka of Gilbert AZ (US) for intel corporation, Brandon Marin of Gilbert AZ (US) for intel corporation, Jeremy Ecton of Gilbert AZ (US) for intel corporation, Gang Duan of Chandler AZ (US) for intel corporation, Srinivas Pietambaram of Chandler AZ (US) for intel corporation, Hari Mahalingam of San Jose CA (US) for intel corporation
IPC Code(s): G02B6/35, G02B6/42, H01L23/498
CPC Code(s): G02B6/35
Abstract: an integrated circuit (ic) module includes a photonic ic, an electrical ic, and a switchable waveguide device that, using a signal from the electrical ic, controls optical signals to or from the photonic ic. the switchable waveguide device may be formed by coupling metallization structures on both sides of, and either level with or below, a nonlinear optical material. the metallization structures may be in the photonic or electrical ic. the nonlinear optical material may be above the electrical ic in the photonic ic or on a glass substrate. the photonic and electrical ics may be hybrid bonded or soldered together. the ic module may be coupled to a system substrate.
Inventor(s): Suddhasattwa Nad of Chandler AZ (US) for intel corporation, Brandon Marin of Gilbert AZ (US) for intel corporation, Jeremy Ecton of Gilbert AZ (US) for intel corporation, Gang Duan of Chandler AZ (US) for intel corporation, Srinivas Pietambaram of Chandler AZ (US) for intel corporation
IPC Code(s): G02B6/35
CPC Code(s): G02B6/356
Abstract: an integrated circuit (ic) module includes a photonic ic, an electrical ic, and a switchable waveguide device that, using a signal from the electrical ic, controls optical signals to or from the photonic ic. the switchable waveguide device may be formed by coupling metallization structures on both sides of, and either level with or below, a nonlinear optical material. the metallization structures may be in the photonic or electrical ic. the nonlinear optical material may be above the electrical ic in the photonic ic or on a glass substrate. the photonic and electrical ics may be hybrid bonded or soldered together. the ic module may be coupled to a system substrate.
20240219653. PHOTONIC ALIGNMENT DEVICE AND METHOD_simplified_abstract_(intel corporation)
Inventor(s): Yonggang Li of Chandler (AZ) for intel corporation, Bai Nie of Chandler (AZ) for intel corporation
IPC Code(s): G02B6/42
CPC Code(s): G02B6/4212
Abstract: an electronic device and associated methods are disclosed. in one example, the electronic device includes a photonic die and at least one optical fiber. devices and methods are shown that include an optical coupler and one or more correction regions to align a beam between the photonic die and the optical fiber.
20240219654. OPTICAL SEMICONDUCTOR PACKAGE AND METHOD_simplified_abstract_(intel corporation)
Inventor(s): Ziyin Lin of Chandler AZ (US) for intel corporation, Yiqun Bai of Chandler AZ (US) for intel corporation, Bohan Shan of Chandler AZ (US) for intel corporation, Kyle Jordan Arrington of Gilbert AZ (US) for intel corporation, Haobo Chen of Chandler AZ (US) for intel corporation, Dingying Xu of Chandler AZ (US) for intel corporation, Robert Alan May of Chandler AZ (US) for intel corporation, Gang Duan of Chandler AZ (US) for intel corporation, Bai Nie of Chandler AZ (US) for intel corporation, Srinivas Venkata Ramanuja Pietambaram of Chandler AZ (US) for intel corporation
IPC Code(s): G02B6/42, H01L25/16
CPC Code(s): G02B6/4214
Abstract: a semiconductor device and associated methods are disclosed. in one example, the electronic device includes a photonic die and a glass substrate. in selected examples, the semiconductor device includes one or more turning mirrors to direct an optical signal between the photonic die and the glass substrate. configurations of turning mirrors are provided to improve signal integrity and manufacturability.
20240219655. OPTICAL SEMICONDUCTOR PACKAGE AND METHOD_simplified_abstract_(intel corporation)
Inventor(s): Haobo Chen of Chandler AZ (US) for intel corporation, Bohan Shan of Chandler AZ (US) for intel corporation, Bai Nie of Chandler AZ (US) for intel corporation, Brandon C. Marin of Gilbert AZ (US) for intel corporation, Dingying Xu of Chandler AZ (US) for intel corporation, Gang Duan of Chandler AZ (US) for intel corporation, Hongxia Feng of Chandler AZ (US) for intel corporation, Jeremy D. Ecton of Gilbert AZ (US) for intel corporation, Kristof Darmawikarta of Chandler AZ (US) for intel corporation, Kyle Jordan Arrington of Gilbert AZ (US) for intel corporation, Srinivas Venkata Ramanuja Pietambaram of Chandler AZ (US) for intel corporation, Xiaoying Guo of Chandler AZ (US) for intel corporation, Yiqun Bai of Chandler AZ (US) for intel corporation, Ziyin Lin of Chandler AZ (US) for intel corporation
IPC Code(s): G02B6/42, H01L21/48
CPC Code(s): G02B6/4214
Abstract: a semiconductor device and associated methods are disclosed. in one example, the electronic device includes a photonic die and a glass substrate. in selected examples, the semiconductor device includes one or more turning mirrors to direct an optical signal between the photonic die and the glass substrate. configurations of turning mirrors are provided to improve signal integrity and manufacturability.
20240219656. OPTICAL SEMICONDUCTOR PACKAGE AND METHOD_simplified_abstract_(intel corporation)
Inventor(s): Ziyin Lin of Chandler AZ (US) for intel corporation, Yiqun Bai of Chandler AZ (US) for intel corporation, Bohan Shan of Chandler AZ (US) for intel corporation, Kyle Jordan Arrington of Gilbert AZ (US) for intel corporation, Haobo Chen of Chandler AZ (US) for intel corporation, Dingying Xu of Chandler AZ (US) for intel corporation, Robert Alan May of Chandler AZ (US) for intel corporation, Gang Duan of Chandler AZ (US) for intel corporation, Bai Nie of Chandler AZ (US) for intel corporation, Srinivas Venkata Ramanuja Pietambaram of Chandler AZ (US) for intel corporation
IPC Code(s): G02B6/42, H01L23/15, H01L25/16
CPC Code(s): G02B6/4214
Abstract: a semiconductor device and associated methods are disclosed. in one example, the electronic device includes a photonic die and a glass substrate. in selected examples, the semiconductor device includes one or more turning mirrors to direct an optical signal between the photonic die and the glass substrate. configurations of turning mirrors are provided to improve signal integrity and manufacturability.
20240219659. OPTICAL SEMICONDUCTOR PACKAGE AND METHOD_simplified_abstract_(intel corporation)
Inventor(s): Ziyin Lin of Chandler AZ (US) for intel corporation, Yiqun Bai of Chandler AZ (US) for intel corporation, Bohan Shan of Chandler AZ (US) for intel corporation, Kyle Jordan Arrington of Gilbert AZ (US) for intel corporation, Haobo Chen of Chandler AZ (US) for intel corporation, Dingying Xu of Chandler AZ (US) for intel corporation, Robert Alan May of Chandler AZ (US) for intel corporation, Gang Duan of Chandler AZ (US) for intel corporation, Bai Nie of Chandler AZ (US) for intel corporation, Srinivas Venkata Ramanuja Pietambaram of Chandler AZ (US) for intel corporation
IPC Code(s): G02B6/42, G02B5/10
CPC Code(s): G02B6/4246
Abstract: a semiconductor device and associated methods are disclosed. in one example, the electronic device includes a photonic die and a glass substrate. in selected examples, the semiconductor device includes one or more turning mirrors to direct an optical signal between the photonic die and the glass substrate. configurations of turning mirrors are provided to improve signal integrity and manufacturability.
20240219660. OPTICAL SEMICONDUCTOR PACKAGE AND METHOD_simplified_abstract_(intel corporation)
Inventor(s): Bohan Shan of Chandler AZ (US) for intel corporation, Hongxia Feng of Chandler AZ (US) for intel corporation, Haobo Chen of Chandler AZ (US) for intel corporation, Yiqun Bai of Chandler AZ (US) for intel corporation, Dingying Xu of Chandler AZ (US) for intel corporation, Eric J.M. Moret of Beaverton OR (US) for intel corporation, Robert Alan May of Chandler AZ (US) for intel corporation, Srinivas Venkata Ramanuja Pietambaram of Chandler AZ (US) for intel corporation, Tarek A. Ibrahim of Mesa AZ (US) for intel corporation, Gang Duan of Chandler AZ (US) for intel corporation, Xiaoying Guo of Chandler AZ (US) for intel corporation, Ziyin Lin of Chandler AZ (US) for intel corporation, Bai Nie of Chandler AZ (US) for intel corporation, Kyle Jordan Arrington of Gilbert AZ (US) for intel corporation, Bin Mu of Tempe AZ (US) for intel corporation
IPC Code(s): G02B6/42, G02B5/10
CPC Code(s): G02B6/4246
Abstract: a semiconductor device and associated methods are disclosed. in one example, the electronic device includes a photonic die and a glass substrate. in selected examples, the semiconductor device includes one or more turning mirrors to direct an optical signal between the photonic die and the glass substrate. configurations of turning mirrors are provided to improve signal integrity and manufacturability.
Inventor(s): Santosh Tripathi of Portland OR (US) for intel corporation, Tuyen Tran of Portland OR (US) for intel corporation
IPC Code(s): G05B19/418, G01R1/073, H01L21/768
CPC Code(s): G05B19/41875
Abstract: methods, apparatus, systems, and articles of manufacture to detect defects during semiconductor chip fabrication and/or to debug semiconductor chips after fabrication are disclosed. an example apparatus includes a substrate, integrated circuitry on a first side of the substrate, and an array of pins extending through the substrate. the pins include first ends on the first side of the substrate and second ends protruding beyond a second side of the substrate opposite the first side.
20240220129. NAND AGING PROTECTION SCHEME_simplified_abstract_(intel corporation)
Inventor(s): Sriram Balasubrahmanyam of Folsom CA (US) for intel corporation, Jong Tai Park of Pleasanton CA (US) for intel corporation, Tri Tran of Elk Grove CA (US) for intel corporation, Arti Sharma of Santa Clara CA (US) for intel corporation, Ashish Shukla of San Jose CA (US) for intel corporation
IPC Code(s): G06F3/06
CPC Code(s): G06F3/0616
Abstract: systems, apparatuses, and methods may provide for technology for an aging protection scheme for memory structures. for example, such technology determines a completion of a burst cycle operation. such technology alternates between a first park status applied to even node devices and a second park status applied to odd node devices in response to the determined completion of the burst cycle operation.
20240220248. RESTRICTING VECTOR LENGTH IN A PROCESSOR_simplified_abstract_(intel corporation)
Inventor(s): Vivekananthan SANJEEPAN of Portland OR (US) for intel corporation, Gilbert NEIGER of Portland OR (US) for intel corporation, Michael ESPIG of Newberg OR (US) for intel corporation
IPC Code(s): G06F9/30
CPC Code(s): G06F9/30036
Abstract: techniques to restrict vector length in a processor are described. a method of an aspect that may be performed by a processor includes executing first instances of vector instructions having respective opcode values regardless of whether they specify wider vectors of a wider vector width or narrower vectors of a narrower vector width, when a control value is a first value. the method also includes executing second instances of vector instructions having the respective opcode values when they specify narrower vectors of the narrower vector width, but do not specify wider vectors of the wider vector width, when the control value is a second different value. the method also includes preventing execution of third instances of vector instructions having the respective opcode values when they specify wider vectors of the wider vector width, when the control value is the second value. other methods, processors, and systems are disclosed.
20240220249. FLEXIBLE VECTORIZED PROCESSING ARCHITECTURE_simplified_abstract_(intel corporation)
Inventor(s): Jian-Guo Chen of Basking Ridge NJ (US) for intel corporation, David Dougherty of Allentown PA (US) for intel corporation, Madihally Narasimha of Saratoga CA (US) for intel corporation, Joseph Othmer of Ocean NJ (US) for intel corporation, Hong Wan of Allentown PA (US) for intel corporation, Joseph Williams of Holmdel NJ (US) for intel corporation, Zoran Zivkovic of Hertogenbosch (NL) for intel corporation
IPC Code(s): G06F9/30, G06F30/343
CPC Code(s): G06F9/30036
Abstract: techniques are disclosed for the implementation of a programmable processing array architecture that realizes vectorized processing operations for a variety of applications. such vectorized processing operations may include digital front end (dfe) processing operations, which include finite impulse response (fir) filter processing operations. the programmable processing array architecture provides a front-end interconnection network that generates specific data sliding time window patterns in accordance with the particular dfe processing operation to be executed. the architecture enables the processed data generated in accordance with these sliding time window patterns to be fed to a set of multipliers and adders to generate output data. the architecture supports a wide range of processing operations to be performed via a single programmable processing array platform by leveraging the programmable nature of the array and the use of instruction sets.
Inventor(s): Mathew Lowes of Austin TX (US) for intel corporation, Martin J. Licht of Round Rock TX (US) for intel corporation, Jonathan D. Combs of Austin TX (US) for intel corporation
IPC Code(s): G06F9/30, G06F12/0875
CPC Code(s): G06F9/30047
Abstract: techniques for implementing a variable width unaligned fetch for instructions are described. in certain examples, a hardware processor core includes fetch circuitry to perform a single fetch operation to fetch from a paged memory: (i) a multiple cache line width of instruction data, between a minimum width that is greater than one cache line and a maximum width that is a plurality of cache lines, when the multiple cache line width of the instruction data does not include a page boundary of the paged memory, and (ii) less than or equal to one cache line width of the instruction data when the multiple cache line width of the instruction data does include the page boundary of the paged memory; decoder circuitry to decode a single instruction, comprising an opcode, from the instruction data into a decoded instruction; and execution circuitry to execute the decoded instruction according to the opcode.
20240220254. DATA MULTICAST IN COMPUTE CORE CLUSTERS_simplified_abstract_(intel corporation)
Inventor(s): Chunhui Mei of San Diego CA (US) for intel corporation, Yongsheng Liu of San Diego CA (US) for intel corporation, John A. Wiegert of Aloha OR (US) for intel corporation, Vasanth Ranganathan of El Dorado Hills CA (US) for intel corporation, Ben J. Ashbaugh of Folsom CA (US) for intel corporation, Fangwen Fu of Folsom CA (US) for intel corporation, Hong Jiang of Los Altos CA (US) for intel corporation, Guei-Yuan Lueh of San Jose CA (US) for intel corporation, James Valerio of North Plains OR (US) for intel corporation, Alan M. Curtis of El Dorado Hills CA (US) for intel corporation, Maxim Kazakov of San Diego CA (US) for intel corporation
IPC Code(s): G06F9/30, G06F9/38, G06F9/50, G06F9/54
CPC Code(s): G06F9/30087
Abstract: data multicast in compute core clusters is described. an example of an apparatus includes one or more processors including at least a first processor, the first processor including one or more clusters of cores and a memory, wherein each cluster of cores includes multiple cores, each core including one or more processing resources, shared memory, and broadcast circuitry; and wherein a first core in a first cluster of cores is to request a data element, determine whether any additional cores in the first cluster require the data element, and, upon determining that one or more additional cores in the first cluster require the data element, broadcast the data element to the one or more additional cores via interconnects between the broadcast circuitry of the cores of the first core cluster.
Inventor(s): Vedvyas Shanbhogue of Austin TX (US) for intel corporation, Ravi L. Sahita of Portland OR (US) for intel corporation, Vincent Scarlata of Beaverton OR (US) for intel corporation, Barry E. Huntley of Hillsboro OR (US) for intel corporation
IPC Code(s): G06F9/4401, G06F9/455, G06F12/1009, G06F21/78, H04L9/30, H04L9/32
CPC Code(s): G06F9/4403
Abstract: a processor includes a range register to store information that identifies a reserved range of memory associated with a secure arbitration mode (seam) and a core coupled to the range register. the core includes security logic to unlock the range register on a logical processor, of the processor core, that is to initiate the seam. the logical processor is to, via execution of the security logic, store, in the reserved range, a seam module and a manifest associated with the seam module, wherein the seam module supports execution of one or more trust domains; initialize a seam virtual machine control structure (vmcs) within the reserved range of the memory that is to control state transitions between a virtual machine monitor (vmm) and the seam module; and authenticate the seam module using a manifest signature of the manifest.
Inventor(s): Atsuo Kuwahara of Camas WA (US) for intel corporation, Prasanna Desai of Elfin Forest CA (US) for intel corporation, Kannan Raja of Beaverton OR (US) for intel corporation
IPC Code(s): G06F9/4401, G06F1/3231, H04W52/02
CPC Code(s): G06F9/4418
Abstract: for example, a display device may be configured to detect a proximity event based on bluetooth (bt) signals communicated between a bt radio of the display device and a peripheral bt device. for example, the proximity event may indicate proximity of the peripheral bt device to the display device. for example, the display device may be configured to, based on the proximity event, send a proximity-based trigger signal to a computing device via a communication link between the display device and the computing device. for example, the proximity-based trigger signal may be configured to trigger a proximity-based change of an operational state of the computing device.
Inventor(s): Rakesh Kandula of Doddakannelli (IN) for intel corporation, Shlomo Avni of Ein Hamifratz (IL) for intel corporation, Fei Su of Ann Arbor MI (US) for intel corporation
IPC Code(s): G06F9/48, G06F11/263
CPC Code(s): G06F9/4812
Abstract: methods and apparatus relating to intelligent sensors for high quality silicon life cycle management as well as efficient infield structural and/or functional testing are described. in an embodiment, one or more registers store configuration data. a sensor having sensor event detection logic circuitry detects an event based at least in part on one or more sensor signals and the stored configuration data. the sensor event detection logic circuitry generates a signal to cause interrupt generator logic circuitry of the sensor to generate an interrupt. other embodiments are also disclosed and claimed.
Inventor(s): Gregory Henry of Hillsboro OR (US) for intel corporation, Kermin E. Chofleming of Hudson MA (US) for intel corporation, Simon C. Steely, JR. of Hudson NH (US) for intel corporation
IPC Code(s): G06F9/50, G06F5/01, G06F7/487
CPC Code(s): G06F9/5027
Abstract: systems, methods, and apparatuses relating to floating-point support circuitry to implement floating-point operations on a two-dimensional grid of fixed-point processing elements are described. in one example, a hardware processor includes a two-dimensional grid of fixed-point processing elements; floating-point support circuitry coupled to the two-dimensional grid of fixed-point processing elements; storage for a first, a second, and a destination two-dimensional floating-point matrices coupled to the floating-point support circuitry; and controller circuitry to cause the two-dimensional grid of fixed-point processing elements and the floating-point support circuitry to: determine, by the floating-point support circuitry, an extreme exponent for each row of the first two-dimensional floating-point matrix and for each column of the second two-dimensional floating-point matrix, generate, by the floating-point support circuitry, a first fixed-point matrix from the first two-dimensional floating-point matrix and a second fixed-point matrix from the second two-dimensional floating-point matrix, generate, by the two-dimensional grid of fixed-point processing elements, corresponding fixed-point results by a multiplication of fixed-point elements of the first fixed-point matrix by corresponding fixed-point elements of the second fixed-point matrix, scale, by the floating-point support circuitry, the corresponding fixed-point results according to the extreme exponents to generate scaled fixed-point results, generate, by the floating-point support circuitry, a resultant floating-point matrix from the scaled fixed-point results, and store the resultant floating-point matrix into the destination two-dimensional floating-point matrix.
Inventor(s): Chunhui Mei of San Diego CA (US) for intel corporation, Yongsheng Liu of San Diego CA (US) for intel corporation, John A. Wiegert of Aloha OR (US) for intel corporation, Vasanth Ranganathan of El Dorado Hills CA (US) for intel corporation, Ben J. Ashbaugh of Folsom CA (US) for intel corporation, Fangwen Fu of Folsom CA (US) for intel corporation, Hong Jiang of Los Altos CA (US) for intel corporation, Guei-Yuan Lueh of San Jose CA (US) for intel corporation, James Valerio of North Plains OR (US) for intel corporation, Alan M. Curtis of El Dorado Hills CA (US) for intel corporation, Maxim Kazakov of San Diego CA (US) for intel corporation
IPC Code(s): G06F9/52, G06F9/38, G06F9/50
CPC Code(s): G06F9/522
Abstract: synchronization for data multicast in compute core clusters is described. an example of an apparatus includes one or more processors including at least a graphics processing unit (gpu), the gpu including one or more clusters of cores and a memory, wherein each cluster of cores includes a plurality of cores, each core including one or more processing resources, shared local memory, and gateway circuitry, wherein the gpu is to initiate broadcast of a data element from a producer core to one or more consumer cores, and synchronize the broadcast of the data element utilizing the gateway circuitry of the producer core and the one or more consumer cores, and wherein synchronizing the broadcast of the data element includes establishing a multi-core barrier for broadcast of the data element.
Inventor(s): David M. Durham of Beaverton OR (US) for intel corporation, Sergej Deutsch of Hillsboro OR (US) for intel corporation, Karanvir Grewal of Hillsboro OR (US) for intel corporation
IPC Code(s): G06F11/10, H04L9/08
CPC Code(s): G06F11/1044
Abstract: the technology disclosed herein includes a memory to store a plurality of pages, a page of the plurality of pages configured as one of a trusted execution environment (tee) configuration and a non-tee configuration, and a memory controller to attempt to access the page using a memory address and the tee configuration and generate a first error correcting code (ecc); and when data for the first ecc is at least one of correct and correctable by ecc for the attempt to access the page using the tee configuration, attempt to access the page using the memory address and the non-tee configuration and generate a second ecc, and when data the second ecc is at least one of correct and correctable by ecc for the attempt to access the page using the non-tee configuration, store the memory address as an unknown cacheline address.
Inventor(s): Baruch Chaikin of Haifa (IL) for intel corporation, Ahmad Yasin of Haifa (IL) for intel corporation
IPC Code(s): G06F11/34, G06F9/455, G06F9/50
CPC Code(s): G06F11/3466
Abstract: techniques for flexible virtualization of performance monitoring are described. in an embodiment, an apparatus includes a plurality of performance monitoring hardware resources and an instruction decoder to decode a first instruction to access a first performance monitoring hardware resource of the plurality of performance monitoring hardware resources. in response to the first instruction being received by a virtual machine, the apparatus is to determine whether the first performance monitoring hardware resource is allocated to the virtual machine based on an allocation model to allow any set of the performance monitoring hardware resources to be allocated to the virtual machine, execute the first instruction within the virtual machine in response to a determination that the first performance monitoring hardware resource is allocated to the virtual machine, and raise an exception within the virtual machine in response to a determination that the first performance monitoring hardware resource is not allocated to the virtual machine.
Inventor(s): Nadav Bonen of Ofer Z (IL) for intel corporation, Israel Diamand of Aderet M (IL) for intel corporation, Julius Mandelblat of Haifa (IL) for intel corporation, Asaf Rubinstein of Kefar (IL) for intel corporation, Igor Brainman of Kfar Saba M (IL) for intel corporation
IPC Code(s): G06F12/0802
CPC Code(s): G06F12/0802
Abstract: methods and apparatus relating to dynamic allocation schemes applied to a memory side cache for bandwidth and/or performance optimization are described. in an embodiment, a memory side cache stores a portion of data to be stored in a main memory. logic circuitry determines whether to allocate a portion of the memory side cache for use by a device. the remaining portion of the memory side cache is to be used by a processor. the allocated portion of the memory side cache is reallocated for use by the processor in response to a determination that the allocated portion of the memory side cache is no longer to be used by the device. other embodiments are also disclosed and claimed.
20240220410. Leveraging System Cache for Performance Cores_simplified_abstract_(intel corporation)
Inventor(s): Ayan Mandal of Bangaluru (IN) for intel corporation, Prasanna Pandit of Bengaluru (IN) for intel corporation, Neetu Jindal of Kurukshetra (IN) for intel corporation, Israel Diamand of Aderet M (IL) for intel corporation, Asaf Rubinstein of Kefar (IL) for intel corporation, Leon Polishuk of Haifa (IL) for intel corporation, Oz Shitrit of Tel Aviv (IL) for intel corporation
IPC Code(s): G06F12/0806
CPC Code(s): G06F12/0806
Abstract: methods and apparatus relating to leveraging system cache for performance cores are described. in an embodiment, a system cache stores one or more cachelines that are to be evicted from a processor cache. logic circuitry determines whether to store the one or more cachelines in the system cache based at least in part on comparison of a threshold value with a hit rate associated with the one or more cachelines. other embodiments are also disclosed and claimed.
Inventor(s): Chunhui Mei of San Diego CA (US) for intel corporation, Doddaballapur Jayasimha of Saratoga CA (US) for intel corporation, Aravindh V. Anantaraman of Folsom CA (US) for intel corporation, Yongsheng Liu of San Diego CA (US) for intel corporation, Hong Jiang of Los Altos CA (US) for intel corporation
IPC Code(s): G06F12/121, G06F12/0895
CPC Code(s): G06F12/121
Abstract: locally biased cache replacement for a clustered cache architecture is described. an example of an apparatus includes clusters of cores; a clustered cache including multiple cache partitions for the clusters of cores, each cache partition including multiple cachelines; and a computer memory including memory partitions, each of the cache partitions being associated with a respective local memory partition, wherein each cacheline of the cache partitions includes a cacheline tag, each cacheline tag including a local tag to indicate whether data stored in the cacheline is local data stored in the local memory partition or remote data stored in a remote memory partition, and a used tag to indicate whether data stored in the cacheline is recently accessed; and wherein the clustered cache includes circuitry to select cachelines for cache replacement in a cache partition based on values of the tags of the cachelines.
Inventor(s): Michael LeMay of Hillsboro OR (US) for intel corporation, David M. Durham of Beaverton OR (US) for intel corporation, Salmin Sultana of Hillsboro OR (US) for intel corporation, Andrew V. Anderson of Hillsboro OR (US) for intel corporation, Hans Goran Liljestrand of Helsinki (FI) for intel corporation
IPC Code(s): G06F12/14, H04L9/08
CPC Code(s): G06F12/1408
Abstract: techniques disclosed include selecting a first key identifier (id) for a first compartment of a compartmentalized process of a computing system, the first compartment including first private data; assigning a first extended page table (ept) having at least one memory address including the first key id; encrypting the first private data with a first key associated with the first key id; and storing the encrypted first private data in a memory starting at the at least one memory address of the first ept.
Inventor(s): Kannan Rajamani of Basking Ridge NJ (US) for intel corporation, Kameran Azadet of San Ramon CA (US) for intel corporation, Kevin Kinney of Coopersburg PA (US) for intel corporation, Thomas Smith of Colmar PA (US) for intel corporation, Zoran Zivkovic of Hertogenbosch (NL) for intel corporation
IPC Code(s): G06F15/80, G06F9/50, G06F9/54
CPC Code(s): G06F15/80
Abstract: techniques are disclosed for the use of a hybrid architecture that combines a programmable processing array and a hardware accelerator. the hybrid architecture functions to maintain synchronization between data samples to be transmitted, feedback data samples measured from an observed previous transmission of data samples, and output data samples that comprise the data samples from previous data transmissions, which may include data samples prior to or after the application of dpd terms. the architecture enables synchronization amongst several transmission channels, and provides for high flexibility with respect to timing flows and the movement and processing of data blocks.
Inventor(s): Deepak Samuel Kirubakaran of Hillsboro OR (US) for intel corporation, Rajshree Chabukswar of Sunnyvale CA (US) for intel corporation, Zhongsheng Wang of Camas WA (US) for intel corporation, Russell Fenger of Beaverton OR (US) for intel corporation, Asit Kumar Verma of Bangalore (IN) for intel corporation, DK Deepika of Secunderabad (IN) for intel corporation, Yevgeni Sabin of Haifa (IL) for intel corporation, Daniel J. Rogers of Folsom CA (US) for intel corporation, Cameron T. Rieck of Portland OR (US) for intel corporation
IPC Code(s): G06F15/80, G06F9/48
CPC Code(s): G06F15/80
Abstract: techniques for implementing dynamic simultaneous multi-threading (smt) scheduling on a hybrid processor platforms are described. in certain examples, a hardware processor includes a first plurality of physical processor cores of a first type to implement a plurality of logical processor cores of the first type; a second plurality of physical processor cores of a second type, wherein each core of the second type is to implement a plurality of logical processor cores of the second type; and circuitry to: determine if a set of threads of a foreground application is to use more than a lower threshold (e.g., a threshold number (e.g., one) of logical processor cores) and less than or equal to an upper threshold (e.g., a total number of the first plurality of physical processor cores of the first type and the second plurality of physical processor cores of the second type), and disable a second logical core of a physical processor core of the second type, and not disable a first logical core of the physical processor core of the second type, in response to a determination that the set of threads of the foreground application is to use more than the lower threshold number of logical processor cores and less than or equal to the upper threshold (e.g., the total number of the first plurality of physical processor cores of the first type and the second plurality of physical processor cores of the second type).
Inventor(s): Chunhui Mei of San Diego CA (US) for intel corporation, Jiasheng Chen of El Dorado Hills CA (US) for intel corporation, Ben J. Ashbaugh of Folsom CA (US) for intel corporation, Fangwen Fu of Folsom CA (US) for intel corporation, Hong Jiang of Los Altos CA (US) for intel corporation, Guei-Yuan Lueh of San Jose CA (US) for intel corporation, Rama S.B. Harihara of Santa Clara CA (US) for intel corporation, Maxim Kazakov of San Diego CA (US) for intel corporation
IPC Code(s): G06F15/80, G06F13/16
CPC Code(s): G06F15/8046
Abstract: a scalable and configurable clustered systolic array is described. an example of apparatus includes a cluster including multiple cores; and a cache memory coupled with the cluster, wherein each core includes multiple processing resources, a memory coupled with the plurality of processing resources, a systolic array coupled with the memory, and one or more interconnects with one or more other cores of the plurality of cores; and wherein the systolic arrays of the cores are configurable by the apparatus to form a logically combined systolic array for processing of an operation by a cooperative group of threads running on one or more of the plurality of cores in the cluster.
Inventor(s): Barry E. Huntley of Hillsboro OR (US) for intel corporation
IPC Code(s): G06F21/57
CPC Code(s): G06F21/57
Abstract: techniques for implementing instructions for a trust domain implemented by a processor are described. in certain examples, a hardware processor core, that implements a trust domain manager to manage one or more hardware isolated virtual machines as a respective trust domain with a region of protected memory, includes a debug register; a control register; decoder circuitry to decode a first single instruction into a first decoded instruction, the first single instruction having a field to indicate a data structure to store a control state of a trust domain and a debug state of the trust domain, and an opcode to indicate execution circuitry is to load the control state of the trust domain from the data structure into the control register and load the debug state of the trust domain from the data structure into the debug register; and the execution circuitry to execute the first decoded instruction according to the opcode.
Inventor(s): Utkarsh Y. Kakaiya of El Dorado Hills CA (US) for intel corporation, Eric Geisler of Hillsboro OR (US) for intel corporation, Rupin H. Vakharwala of Hillsboro OR (US) for intel corporation, Michael Prinke of Aloha OR (US) for intel corporation, David Koufaty of Portland OR (US) for intel corporation
IPC Code(s): G06F21/57
CPC Code(s): G06F21/57
Abstract: circuitry and methods for implementing address translation extensions for confidential computing hosts are described. in certain examples, a system includes a hardware processor core to implement a trust domain manager to manage one or more hardware isolated virtual machines as a respective trust domain with a region of protected memory; an input/output device coupled to the hardware processor core; and input/output memory management unit (iommu) circuitry comprising trusted direct memory access translation data and coupled between the hardware processor core and the input/output device, wherein the iommu circuitry is to, for a request from the input/output device for a direct memory access of a protected memory of a trust domain: in response to a field in the request being set to indicate the input/output device is in a trusted computing base of the trust domain and an entry in the trusted direct memory access translation data being set into an active state by the trust domain manager, allow the direct memory access by the input/output device.
20240220626. SECURE BOOT USING PARALLELIZATION_simplified_abstract_(intel corporation)
Inventor(s): Girisha Dengi of Bengaluru (IN) for intel corporation, Karthika Murthy of Bangalore (IN) for intel corporation, Santosh Male of Hyderabad (IN) for intel corporation
IPC Code(s): G06F21/57
CPC Code(s): G06F21/575
Abstract: an apparatus includes a basic input/output system (bios) comprising a boot read-only memory (boot-rom) to load a first stage boot loader (fsbl) into a random access memory (ram), a processor comprising at least a first processing core and a second processing core, the processor to initialize, in the first processing core, a first set of system drivers, activate, the second processing core, and load, in the second processing core, a second stage boot loader and one or more operating system images into a main system memory.
Inventor(s): Prateek Sahu of Austin TX (US) for intel corporation, Reshma Lal of Portland OR (US) for intel corporation
IPC Code(s): G06F21/60, G06F21/57, G06F21/85
CPC Code(s): G06F21/602
Abstract: an apparatus comprises a compute complex comprising one or more processing resources to execute a software process, a hardware processor to initiate an authentication request to at least one adjunct processing hardware device communicatively coupled to the compute complex, establish a session key with the at least one adjunct processing hardware device, negotiate, with a hypervisor, a virtual function allocation for at least one virtual adjunct processing device to be implemented by the at least one adjunct processing hardware device to define a configuration in a trusted page table, verify the configuration with the at least one adjunct processing hardware device using the session key, and lock the configuration in the trusted table.
Inventor(s): Daniël Kuijsters of Schijndel (NL) for intel corporation, Christoph Dobraunig of St. Veit an der Glan (AT) for intel corporation, Santosh Ghosh of Hillsboro OR (US) for intel corporation
IPC Code(s): G06F21/60, G06F21/54, G06F21/55
CPC Code(s): G06F21/602
Abstract: in one example an apparatus comprises a first input node to receive a first input bit, an encryption circuit to split the first input bit into a first share and a second share, and perform an encryption function on the first input share and the second input share to generate a first output share and a second output share, an error tag generator circuit to calculate a first error tag from the first input share and the second input share, and calculate a second error tag from the first output share and the second output share, an error detection circuit to generate an error signal when the first error tag does not match the second error tag.
Inventor(s): Luis Sergio Kida of Beaverton OR (US) for intel corporation, Reshma Lal of Portland OR (US) for intel corporation
IPC Code(s): G06F21/71, H04W12/71
CPC Code(s): G06F21/71
Abstract: an apparatus comprises a compute complex comprising one or more processing resources to execute a software process identified by a software identifier (swid), at least one hardware module, a communication fabric to provide a communication pathway between the compute complex, the at least one hardware module, and at least one memory device, and at least one memory management unit to provide access control to the memory device based at least in part on the software identifier.
Inventor(s): Michael Goldsmith of Lake Oswego OR (US) for intel corporation, Prashant Majhi of San Jose CA (US) for intel corporation, Per Sverdrup of Redwood City CA (US) for intel corporation, Chung-Ching Peng of Taipei (TW) for intel corporation
IPC Code(s): G06F30/392
CPC Code(s): G06F30/392
Abstract: methods, apparatus, systems, and articles of manufacture are disclosed including at least one memory; machine-readable instructions; and processor circuitry to at least one of execute or instantiate the machine-readable instructions to: obtain a register-transfer level design defining operations of electrical circuits in first and second dice of a multi-die semiconductor package, the second die to be stacked on the first die in the multi-die semiconductor package; and select placement of a cell for a physical layout for the multi-die semiconductor package based on the register-transfer level design, the cell including a via to electrically interconnect the first die to the second die.
Inventor(s): Sunita S. Thulasi of Portland OR (US) for intel corporation, Prashanth Kumar Siddhamshetty of Portland OR (US) for intel corporation, Minjung Kim of Portland OR (US) for intel corporation, Mark Horsch of Missouri City TX (US) for intel corporation, A S M Jonayat of North Plains OR (US) for intel corporation, Anish Shenoy of Mountain View CA (US) for intel corporation, Cheng-Tsung Lee of Beaverton OR (US) for intel corporation, Silvia Liong of Portland OR (US) for intel corporation, Dorian Alden of Portland OR (US) for intel corporation, Vipin Agrawal of Beaverton OR (US) for intel corporation, Anjan Raghunathan of Portland OR (US) for intel corporation, Rusty Wayne Conner of Portland OR (US) for intel corporation
IPC Code(s): G06F30/398, H01L23/498
CPC Code(s): G06F30/398
Abstract: methods, apparatus, systems, and articles of manufacture are disclosed to adjust vias in integrated circuits (ics) based on machine learning (ml). an example apparatus computes a dimension by which to extend a via based on at least one of a first metal wire in a first layer of the ic above the via, a via-to-via patterning constraint, or a via-to-metal shorting constraint for a second layer of the ic below the via. the example apparatus also computes a shifted position of the via based on at least one of (a) the dimension or (b) a width and a position of a second metal wire below the via, the width and the position predicted by an ml model. additionally, the example apparatus adjusts a configuration file corresponding to the ic based on at least one of the dimension or the shifted position of the via.
20240220785. Schedule-Aware Tensor Distribution Module_simplified_abstract_(intel corporation)
Inventor(s): Gautham Chinya of Sunnyvale CA (US) for intel corporation, Huichu Liu of Santa Clara CA (US) for intel corporation, Arnab Raha of San Jose CA (US) for intel corporation, Debabrata Mohapatra of San Jose CA (US) for intel corporation, Cormac Brick of San Francisco CA (US) for intel corporation, Lance Hacking of Spanish Fork UT (US) for intel corporation
IPC Code(s): G06N3/063, G06F9/38, G06F9/448, G06F9/50, G06N5/04
CPC Code(s): G06N3/063
Abstract: methods and systems include a neural network system that includes a neural network accelerator comprising. the neural network accelerator includes multiple processing engines coupled together to perform arithmetic operations in support of an inference performed using the deep neural network system. the neural network accelerator also includes a schedule-aware tensor data distribution circuitry or software that is configured to load tensor data into the multiple processing engines in a load phase, extract output data from the multiple processing engines in an extraction phase, reorganize the extracted output data, and store the reorganized extracted output data to memory.
20240221277. LEARNING NEURAL REFLECTANCE SHADERS FROM IMAGES_simplified_abstract_(intel corporation)
Inventor(s): Benjamin Ummenhofer of Unterhaching (DE) for intel corporation, Shenlong Wang of Santa Clara CA (US) for intel corporation, Sanskar Agrawal of Santa Clara CA (US) for intel corporation, Yixing Lao of Santa Clara CA (US) for intel corporation, Kai Zhang of Santa Clara CA (US) for intel corporation, Stephan Richter of Neubiberg (DE) for intel corporation, Vladlen Koltun of Santa Clara CA (US) for intel corporation
IPC Code(s): G06T15/00, G06N3/045, G06T15/04, G06T15/50, G06T17/20
CPC Code(s): G06T15/005
Abstract: described herein are techniques for learning neural reflectance shaders from images. a set of one or more machine learning models can be trained to optimize an illumination latent code and a set of reflectance latent codes for an object within a set of input images. a shader can then be generated based on a machine learning model of the one or more machine learning models. the shader is configured to sample the illumination latent code and the set of reflectance latent codes for the object. a 3d representation of the object can be rendered using the generated shader.
20240221295. FRAGMENT COMPRESSION FOR COARSE PIXEL SHADING_simplified_abstract_(intel corporation)
Inventor(s): Prasoonkumar Surti of Folsom CA (US) for intel corporation, Abhishek R. Appu of El Dorado Hills CA (US) for intel corporation, Subhajit Dasgupta of Bangalore (IN) for intel corporation, Srivallaba Mysore of Folsom CA (US) for intel corporation, Michael J. Norris of Folsom CA (US) for intel corporation, Vasanth Ranganathan of El Dorado Hills CA (US) for intel corporation, Joydeep Ray of Folsom CA (US) for intel corporation
IPC Code(s): G06T15/80, G06T1/20, G06T1/60, G06T15/00
CPC Code(s): G06T15/80
Abstract: one embodiment provides for a graphics processing unit comprising a processing cluster to perform multi-rate shading via coarse pixel shading and output shaded coarse pixels for processing by a post-shader pixel processing pipeline.
Inventor(s): Jaison FERNANDEZ of Bangalore (IN) for intel corporation, Sumod CHERUKKATE of Bangalore (IN) for intel corporation, Tarakesava Reddy KOKI of Hyderabad (IN) for intel corporation, Adam KUPRYJANOW of Gdansk (PL) for intel corporation, Srikanth POTLURI of Folsom CA (US) for intel corporation
IPC Code(s): G10K11/178, H04R1/10
CPC Code(s): G10K11/17823
Abstract: this disclosure describes systems, methods, and devices related to noise suppression processing. a device may establish a connection to a connected device. the device may calculate a first snr of a first sample of a first audio stream from the connected device. the device may calculate a second snr of a second sample of a second audio stream from a first device. the device may compare a difference of the first snr and the second snr to a delta snr threshold. the device may detect ambient noise level conditions and the delta snr threshold is based on the ambient noise level conditions. the device may determine whether to apply system-level preprocessing based on the comparison.
20240221756. END-TO-END NEUROMORPHIC ACOUSTIC PROCESSING_simplified_abstract_(intel corporation)
Inventor(s): Kuba Tomasz Lopatka of Gdansk (PL) for intel corporation, Katarzyna J. Kaszuba-Miotke of Gdynia (PL) for intel corporation, Karol Jan Polec of Gdansk (PL) for intel corporation
IPC Code(s): G10L15/34, G06N3/063, G10L15/16, G10L15/28
CPC Code(s): G10L15/34
Abstract: a neuromorphic processing device includes a spike generator including hardware to generate a set of input spikes based on acoustic signal data generated by a microphone of a computing device. the neuromorphic processing device further includes a neuromorphic compute block to implement a spiking neural network (snn), receive the set of input spikes as an input to the snn, and generate a set of output spikes from the snn based on the input. a result for an acoustic recognition task may be determined based on the set of output spikes.
Inventor(s): Abhishek Anil SHARMA of Portland OR (US) for intel corporation, Wilfred GOMES of Portland OR (US) for intel corporation, Tahir GHANI of Portland OR (US) for intel corporation, Anand S. MURTHY of Portland OR (US) for intel corporation
IPC Code(s): G11C11/409, H01L23/522, H01L23/528
CPC Code(s): G11C11/409
Abstract: structures having two-transistor gain cell are described. in an example, an integrated circuit structure includes a frontend device layer including a read transistor. a backend device layer is above the frontend device layer, the backend device layer including a write transistor. an intervening interconnect layer is between the backend device layer and the frontend device layer, the intervening interconnect layer coupling the write transistor of the backend device layer to the read transistor of the front-end device layer.
Inventor(s): Thomas Sounart of Chandler AZ (US) for intel corporation, Henning Braunisch of Phoenix AZ (US) for intel corporation, Aleksandar Aleksov of Chandler AZ (US) for intel corporation, Kristof Darmawikarta of Chandler AZ (US) for intel corporation, Numair Ahmed of Chandler AZ (US) for intel corporation, Darko Grujicic of Chandler AZ (US) for intel corporation, Suddhasattwa Nad of Chandler AZ (US) for intel corporation, Benjamin Duong of Phoenix AZ (US) for intel corporation, Marcel Wall of Phoenix AZ (US) for intel corporation, Shayan Kaviani of Phoenix AZ (US) for intel corporation
IPC Code(s): H01G4/01, H01G4/30, H01G4/33, H01L21/48, H01L23/538
CPC Code(s): H01G4/01
Abstract: substrate package-integrated oxide capacitors and related methods are disclosed herein. an example apparatus including a first layer and a thin film capacitor including a second layer on the first layer, the second layer defining a plurality of openings and a third layer disposed on the first layer and in the plurality of openings, the second layer and the third layer corresponding to electrodes of a capacitor and a fourth layer disposed between the first layer and the second layer, the third layer including an oxidized material, the third layer forming a dielectric of the capacitor.
Inventor(s): Suddhasattwa Nad of Chandler AZ (US) for intel corporation, Kristof Darmawikarta of Chandler AZ (US) for intel corporation, Benjamin Duong of Phoenix AZ (US) for intel corporation, Gang Duan of Chandler AZ (US) for intel corporation, Srinivas Pietambaram of Chandler AZ (US) for intel corporation, Brandon Marin of Gilbert AZ (US) for intel corporation, Jeremy Ecton of Gilbert AZ (US) for intel corporation, Jason Steill of Phoenix AZ (US) for intel corporation, Thomas Sounart of Chandler AZ (US) for intel corporation, Darko Grujicic of Chandler AZ (US) for intel corporation
IPC Code(s): H01G4/33, H01G4/012, H01G4/252, H01L21/48, H01L23/498, H01L25/16
CPC Code(s): H01G4/33
Abstract: apparatuses, capacitor structures, assemblies, and techniques related to package substrate embedded capacitors are described. a capacitor architecture includes a multi-layer capacitor structure at least partially within an opening extending through an insulative material layer of a package substrate or on a package substrate. the multi-layer capacitor structure includes at least two capacitor dielectric layers interleaved with a plurality of conductive layers such that the capacitor dielectric layers are at least partially within the opening and one of the conductive layers are on a sidewall of the opening.
20240222073. ION BEAM LITHOGRAPHY AND NANOENGINEERING_simplified_abstract_(intel corporation)
Inventor(s): Shida Tan of Saratoga CA (US) for intel corporation, Uygar Avci of Portland (CA) for intel corporation, Brandon Holybee of Portland OR (US) for intel corporation, Kirby Maxey of Hillsboro OR (US) for intel corporation, Kevin O'Brien of Portland OR (US) for intel corporation, Mahmut Sami Kavrik of Eugene OR (US) for intel corporation
IPC Code(s): H01J37/317, H01L21/027, H01L21/033, H01L21/311, H01L21/3213
CPC Code(s): H01J37/3174
Abstract: this disclosure describes systems, apparatus, methods, and devices related to ion beams fabrication. a device may overlay a wafer assembly of one or more layers with a top layer comprised of a material having 2d material characteristics. the device may be fabricated by applying an ion beam targeted to at least one of one or more regions of the top layer or a resist layer placed on top of the top layer, wherein the ion beam is tuned using a predetermined energy range or a dosing level of ions to modify material characteristics of the resist layer or to perform milling of the top layer or other layers of the one or more layers of the wafer assembly.
Inventor(s): Ala OMER of Phoenix AZ (US) for intel corporation, Peumie ABEYRATNE KURAGAMA of Chandler AZ (US) for intel corporation, Jieying KONG of Chandler AZ (US) for intel corporation, Wendy LIN of Chandler AZ (US) for intel corporation, Ao WANG of Chandler AZ (US) for intel corporation
IPC Code(s): H01J37/32, H01L21/3105
CPC Code(s): H01J37/32715
Abstract: this disclosure describes designs and methods for via cleaning, peeling protective film, and providing mild surface roughening and cleaning of a computer chip. a system may include a first electrode configured to generate plasma associated with cleaning vias by etching a residual material associated with smearing; an electrostatic stage configured to generate an electrostatic force associated with peeling the dielectric protective film from the semiconductor; and a stage on which the semiconductor is positioned while the electrostatic stage peels the dielectric protective film from the semiconductor, wherein the plasma is further associated with roughening a surface of the semiconductor after peeling the dielectric protective film from the semiconductor.
Inventor(s): Carl H. Naylor of Portland OR (US) for intel corporation, Kirby Maxey of Hillsboro OR (US) for intel corporation, Kevin OBrien of Portland OR (US) for intel corporation, Chelsey Dorow of Portland OR (US) for intel corporation, Sudarat Lee of Hillsboro OR (US) for intel corporation, Ashish Verma Penumatcha of Beaverton OR (US) for intel corporation, Uygar Avci of Portland OR (US) for intel corporation, Matthew Metz of Portland OR (US) for intel corporation, Scott B. Clendenning of Portland OR (US) for intel corporation, Mahmut Sami Kavrik of Eugene OR (US) for intel corporation, Chia-Ching Lin of Portland OR (US) for intel corporation, Ande Kitamura of Portland OR (US) for intel corporation
IPC Code(s): H01L21/02, H01L21/04, H01L23/31
CPC Code(s): H01L21/02568
Abstract: integrated circuit (ic) structures comprising transistors with metal chalcogenide channel material synthesized on a workpiece comprising a group iv crystal. prior to synthesis of the metal chalcogenide material, a passivation material is formed over the group iv crystal to limit exposure of the substrate to the growth precursor gas(es) and thereby reduce a quantity of chalcogen species subsequently degassed from the workpiece. the passivation material may be applied to the front side, back side, and/or edge of a workpiece. the passivation material may be sacrificial or retained as a permanent feature of an ic structure. the passivation material may be advantageously amorphous and/or a compound comprising at least one of a metal or nitrogen that is good diffusion barrier and thermally stable at the metal chalcogenide synthesis temperatures.
Inventor(s): Eungnak Han of Portland OR (US) for intel corporation, James Blackwell of Portland OR (US) for intel corporation, Gurpreet Singh of Portland OR (US) for intel corporation, Florian Gstrein of Portland OR (US) for intel corporation
IPC Code(s): H01L21/027, H01L21/02
CPC Code(s): H01L21/0274
Abstract: in-situ formation of a block copolymer through deprotection can provide patterns with flexible pitches. a layer of a protected polymer including a protecting group is formed. one or more portions of the layer may be exposed to light. the exposed portion(s) may be baked after the light exposure. the protecting group is removed after the light exposure or bake so that the protected polymer becomes a deprotected polymer in the exposure portion(s). the deprotected polymer is bonded with the protected polymer in the unexposed portion(s) of the layer but has a different solubility from the protected polymer so that phases of the block copolymer are separated. the phase separation can provide a periodic pattern with various pitches. the solution and roughness of the pattern can be enhanced by using cars formed with a protected, cross-linked polymer that includes a protective group and a function group with a ratio of 50:50.
20240222126. FABRICATION OF NOVEL DEVICES USING ION BEAMS_simplified_abstract_(intel corporation)
Inventor(s): Mahmut Sami Kavrik of Eugene OR (US) for intel corporation, Uygar Avci of Portland (CA) for intel corporation, Brandon Holybee of Portland OR (US) for intel corporation, Jennifer Lux of Hillsboro OR (US) for intel corporation, Kevin O'Brien of Portland OR (US) for intel corporation, Shida Tan of Saratoga CA (US) for intel corporation
IPC Code(s): H01L21/266, H01L21/265
CPC Code(s): H01L21/266
Abstract: this disclosure describes systems, apparatus, methods, and devices related to fabrication using ion beams. the device may apply an ion beam targeted to at least one of one or more regions of a top layer, a metal layer placed on top of the top layer, or one or more ion stoppers placed on top of the top layer, wherein the ion beam is tuned using a predetermined energy range or a dosing level of ions to modify the material characteristics of the 2d material at the one or more regions of the top layer. the device may create a bond between the one or more 2d and metal layers to the one or more regions of the top layer where the material characteristics of the 2d material have been modified due to the impinging ion beam.
Inventor(s): Shaojiang CHEN of Chandler AZ (US) for intel corporation, Jeremy D. ECTON of Gilbert AZ (US) for intel corporation, Oladeji FADAYOMI of Maricopa AZ (US) for intel corporation, Hsin-Wei WANG of Chandler AZ (US) for intel corporation, Changhua LIU of Chandler AZ (US) for intel corporation, Bin MU of Tempe AZ (US) for intel corporation, Hongxia FENG of Chandler AZ (US) for intel corporation, Brandon C. MARIN of Gilbert AZ (US) for intel corporation, Srinivas V. PIETAMBARAM of Chandler AZ (US) for intel corporation
IPC Code(s): H01L21/306, H01L21/321, H01L21/48, H01L21/768
CPC Code(s): H01L21/30604
Abstract: embodiments disclosed herein include electronic packages and methods of forming electronic packages. in an embodiment, an electronic package comprises a core, where the core comprises glass. in an embodiment, a through glass via (tgv) is provided through a thickness of the core. in an embodiment, the tgv comprises a top surface that is non-planar and includes a symmetric ridge on the non-planar top surface.
20240222136. ELECTRICAL LAYER WITH ROUGHENED SURFACES_simplified_abstract_(intel corporation)
Inventor(s): Bohan Shan of Chandler AZ (US) for intel corporation, Haobo Chen of Chandler AZ (US) for intel corporation, Srinivas Venkata Ramanuja Pietambaram of Chandler AZ (US) for intel corporation, Hongxia Feng of Chandler AZ (US) for intel corporation, Gang Duan of Chandler AZ (US) for intel corporation, Xiaoying Guo of Chandler AZ (US) for intel corporation, Ashay A. Dani of Chandler AZ (US) for intel corporation, Yiqun Bai of Chandler AZ (US) for intel corporation, Dingying Xu of Chandler AZ (US) for intel corporation, Bai Nie of Chandler AZ (US) for intel corporation, Kyle Jordan Arrington of Gilbert AZ (US) for intel corporation, Wei Wei of Chandler AZ (US) for intel corporation, Ziyin Lin of Chandler AZ (US) for intel corporation
IPC Code(s): H01L21/321, H01L21/3065, H01L21/311, H01L21/768
CPC Code(s): H01L21/3212
Abstract: mechanical or chemical processes can form roughened surfaces which can be used for coupling layers of electrical systems such as when forming dies, substrates, computer chips or the like that, when subjected to high stress, are robust enough to remain coupled together.
Inventor(s): Shaojiang CHEN of Chandler AZ (US) for intel corporation, Jeremy D. ECTON of Gilbert AZ (US) for intel corporation, Oladeji FADAYOMI of Maricopa AZ (US) for intel corporation, Srinivas V. PIETAMBARAM of Chandler AZ (US) for intel corporation, Matthew L. TINGEY of Mesa AZ (US) for intel corporation
IPC Code(s): H01L21/3213, H01L21/768, H01L23/15, H01L23/498
CPC Code(s): H01L21/3213
Abstract: embodiments disclosed herein include electronic packages and methods of forming electronic packages. in an embodiment, the electronic package comprises a core, where the core comprises glass. in an embodiment, a through glass via (tgv) is provided through a thickness of the core, where a top surface of the tgv is not coplanar with a top surface of the core. in an embodiment, the electronic package further comprises a ridge on the top surface of the tgv, where the ridge is symmetric about a centerline of the tgv.
Inventor(s): Suddhasattwa Nad of Chandler AZ (US) for intel corporation, Brandon Marin of Gilbert AZ (US) for intel corporation, Gang Duan of Chandler AZ (US) for intel corporation, Jeremy Ecton of Gilbert AZ (US) for intel corporation, Srinivas Pietambaram of Chandler AZ (US) for intel corporation
IPC Code(s): H01L21/48, H01L23/00, H01L23/495, H01L25/065
CPC Code(s): H01L21/4842
Abstract: microelectronic integrated circuit package structures include a solder joint structure having a first portion on a die and a second portion on a substrate. the first portion comprises a first metal. an inner portion of the second portion comprises a second metal, and an outer portion of the second portion comprises an intermetallic compound (imc) of the first and second metals.
20240222178. ENHANCED ELECTROSTATIC WAFER CHUCK DESIGNS_simplified_abstract_(intel corporation)
Inventor(s): Robert CHRONEOS, JR. of Chandler AZ (US) for intel corporation
IPC Code(s): H01L21/683, H01L21/67, H01L21/687
CPC Code(s): H01L21/6833
Abstract: this disclosure describes electrostatic wafer chuck designs for holding and heating semiconductor wafers. an electrostatic wafer chuck may include a metal base; a temperature sensor; and a multi-layer ceramic plate including: a bonding layer; a heater; a first dielectric positioned between the heater and the bonding layer; an electrode to electrostatically hold a semiconductor wafer; a second dielectric positioned between the heater and the electrode; a heat spreader to uniformly distribute heat from the heater to the semiconductor wafer; and a third dielectric positioned between the electrode and the semiconductor wafer; and a temperature sensor may extend through the metal base and at least partially through the multi-layer ceramic plate.
Inventor(s): Amey Anant Apte of Chandler AZ (US) for intel corporation, Mukul Renavikar of North Plains AZ (US) for intel corporation
IPC Code(s): H01L21/683, C09J7/24, C09J7/29, C09J7/38, C09J11/04, H01L23/60
CPC Code(s): H01L21/6836
Abstract: the disclosure is directed to a silicon bridge die package, a dicing-die attach film structure and a method for silicon processing including a silicon bridge die package including at least two silicon die incorporating a plurality of integrated circuits, an embedded multi-die interconnect bridge coupled to the at least two silicon die, a dicing-die attach film (ddaf) structure coupled to a silicon wafer, an electro-static discharge (esd) preventative within the ddaf structure to prevent static charge within the ddaf structure, and an auxetic material disposed within the ddaf structure configured to prevent dicing errors. a method for preparing a silicon die for singulation includes applying an auxetic material with an esd preventative additive to an organic resin to form a ddaf, combining the ddaf with an acrylic adhesive and a polyolefin base film, and mounting the ddaf to the silicon die.
Inventor(s): Bohan Shan of Chandler AZ (US) for intel corporation, Haobo Chen of Chandler AZ (US) for intel corporation, Bai Nie of Chandler AZ (US) for intel corporation, Srinivas Venkata Ramanuja Pietambaram of Chandler AZ (US) for intel corporation, Gang Duan of Chandler AZ (US) for intel corporation, Kyle Jordan Arrington of Gilbert AZ (US) for intel corporation, Ziyin Lin of Chandler AZ (US) for intel corporation, Hongxia Feng of Chandler AZ (US) for intel corporation, Yiqun Bai of Chandler AZ (US) for intel corporation, Xiaoying Guo of Chandler AZ (US) for intel corporation, Dingying Xu of Chandler AZ (US) for intel corporation, Kristof Darmawikarta of Chandler AZ (US) for intel corporation
IPC Code(s): H01L23/15, H01L21/48, H01L23/498
CPC Code(s): H01L23/15
Abstract: an integrated circuit device substrate includes a first glass layer, a second glass layer, and a dielectric interface layer between the first glass layer and the second glass layer. a plurality of conductive pillars extend through the first glass layer, the dielectric layer and the second glass layer, wherein the conductive pillars taper from a first diameter in the dielectric layer to a second diameter in the first glass layer and the second glass layer, and wherein the first diameter is greater than the second diameter.
Inventor(s): Peumie Abeyratne Kuragama of Chandler AZ (US) for intel corporation, Dilan Seneviratne of Phoenix AZ (US) for intel corporation, Whitney Bryks of Tempe AZ (US) for intel corporation
IPC Code(s): H01L23/16, H01L23/00, H01L23/15, H01L23/538
CPC Code(s): H01L23/16
Abstract: ic device packages including a low-cte polymer dielectric build-up material comprising a filler having a negative cte. low cte build-up materials may have a cte less than 10 ppm/k below the glass transition temperature (t) of the polymer resin containing the filler. with a negative cte filler, polymer resin expansion during thermal cycles (e.g., resin cure) may be at least partially countered through negative thermal expansion of the filler.
Inventor(s): Zhixin XIE of Chandler AZ (US) for intel corporation, Jung Kyu HAN of Chandler AZ (US) for intel corporation, Gang DUAN of Chandler AZ (US) for intel corporation
IPC Code(s): H01L23/31, G02B6/42, H01L21/56, H01L23/00, H01L23/29, H01L25/065, H01L25/10
CPC Code(s): H01L23/3135
Abstract: embodiments disclosed herein include electronic packages. in an embodiment, the electronic package comprises a package substrate with a die coupled to the package substrate by a plurality of interconnects. in an embodiment, a first layer is on the package substrate surrounding the die, and a second layer is over and around the die. in an embodiment, the second layer underfills the plurality of interconnects, and the second layer has a different material composition than the first layer.
Inventor(s): Gang Duan of Chandler AZ (US) for intel corporation, Srinivas Pietambaram of Chandler AZ (US) for intel corporation, Brandon Marin of Gilbert AZ (US) for intel corporation, Suddhasattwa Nad of Chandler AZ (US) for intel corporation, Jeremy Ecton of Gilbert AZ (US) for intel corporation, Yang Wu of Chandler AZ (US) for intel corporation, Minglu Liu of Chandler AZ (US) for intel corporation, Yosuke Kanaoka of Chandler AZ (US) for intel corporation
IPC Code(s): H01L23/367, H01L21/56, H01L23/00, H01L23/31, H01L23/42, H01L23/48, H01L23/538, H01L25/18
CPC Code(s): H01L23/367
Abstract: microelectronic integrated circuit package structures include a first die and a second die both coupled to a bridge structure at an interface. a first thermally conductive mold material is on a first side of the interface and surrounds the first die and the second die. a second mold material is on a second, opposing side of the interface and surrounds the bridge structure.
Inventor(s): Abhishek Anil SHARMA of Portland OR (US) for intel corporation, Han Wui THEN of Portland OR (US) for intel corporation, Wilfred GOMES of Portland OR (US) for intel corporation, Anand S. MURTHY of Portland OR (US) for intel corporation, Tahir GHANI of Portland OR (US) for intel corporation, Sagar SUTHRAM of Portland OR (US) for intel corporation, Pushkar RANADE of San Jose CA (US) for intel corporation
IPC Code(s): H01L23/48, H01L21/02, H01L23/00, H01L23/498, H01L23/522, H01L25/065, H01L27/088
CPC Code(s): H01L23/481
Abstract: embodiments described herein may be related to apparatuses, processes, systems, and/or techniques for semiconductor packages that use devices within an sic layer coupled with devices within a gan layer proximate to the sic to convert a high voltage source to the package, e.g. greater than 1 kv, to 1-1.8 v used by components within the package. the devices may be transistors. the voltage conversion will allow increased power to be supplied to the package. other embodiments may be described and/or claimed.
Inventor(s): Bohan Shan of Chandler AZ (US) for intel corporation, Haobo Chen of Chandler AZ (US) for intel corporation, Srinivas Venkata Ramanuja Pietambaram of Chandler AZ (US) for intel corporation, Bai Nie of Chandler AZ (US) for intel corporation, Gang Duan of Chandler AZ (US) for intel corporation, Kyle Jordan Arrington of Gilbert AZ (US) for intel corporation, Ziyin Lin of Chandler AZ (US) for intel corporation, Hongxia Feng of Chandler AZ (US) for intel corporation, Yiqun Bai of Chandler AZ (US) for intel corporation, Xiaoying Guo of Chandler AZ (US) for intel corporation, Dingying Xu of Chandler AZ (US) for intel corporation
IPC Code(s): H01L23/498, H01L23/00, H01L23/15
CPC Code(s): H01L23/49811
Abstract: an integrated circuit device substrate includes a glass substrate with a first major surface comprising a plateau region, a cavity region, and a wall between the plateau region and the cavity region. the first major surface includes thereon a first dielectric region, and the plateau region includes a plurality of conductive pillars. a second major surface of the glass substrate opposite the first major surface includes thereon a second dielectric layer, wherein the second dielectric layer includes at least one dielectric-free window underlying the cavity region.
Inventor(s): Bohan Shan of Chandler AZ (US) for intel corporation, Haobo Chen of Chandler AZ (US) for intel corporation, Bai Nie of Chandler AZ (US) for intel corporation, Srinivas Venkata Ramanuja Pietambaram of Chandler AZ (US) for intel corporation, Gang Duan of Chandler AZ (US) for intel corporation, Kyle Jordan Arrington of Gilbert AZ (US) for intel corporation, Ziyin Lin of Chandler AZ (US) for intel corporation, Hongxia Feng of Chandler AZ (US) for intel corporation, Yiqun Bai of Chandler AZ (US) for intel corporation, Xiaoying Guo of Chandler AZ (US) for intel corporation, Dingying Xu of Chandler AZ (US) for intel corporation, Kristof Darmawikarta of Chandler AZ (US) for intel corporation
IPC Code(s): H01L23/498, H01L21/48, H01L23/15
CPC Code(s): H01L23/49822
Abstract: an integrated circuit device substrate includes a first glass layer with a redistribution layer mounting region and an integrated circuit device mounting region, wherein a first major surface of the first glass layer is overlain by a first dielectric layer, and wherein the first glass layer includes a first plurality of conductive pillars. a second glass layer is on the redistribution layer mounting region on the first glass layer, wherein the second glass layer includes a second dielectric layer on a second major surface thereof, and wherein the second dielectric layer is bonded to the first dielectric layer on the first major surface of the first glass layer, the second glass layer including a second plurality of conductive pillars electrically interconnected with the first plurality of conductive pillars in the first glass layer.
Inventor(s): Brandon Christian Marin of Gilbert AZ (US) for intel corporation, Sashi Shekhar Kandanur of Phoenix AZ (US) for intel corporation, Srinivas V. Pietambaram of Chandler AZ (US) for intel corporation, Gang Duan of Chandler AZ (US) for intel corporation, Jeremy D. Ecton of Gilbert AZ (US) for intel corporation
IPC Code(s): H01L23/498, H01L21/306
CPC Code(s): H01L23/49827
Abstract: architectures and methods for metal lamination on a glass layer or glass core. the architectures implement dummy anchors to prevent or reduce the delamination of conductive materials from glass surfaces. the anchors hold the conductive pads and conductive material planes down to the glass surface. the architecture includes various combinations of end anchors and through glass via (tgv) anchors.
Inventor(s): Jeremy D. Ecton of Gilbert AZ (US) for intel corporation, Srinivas V. Pietambaram of Chandler AZ (US) for intel corporation, Gang Duan of Chandler AZ (US) for intel corporation, Brandon Christian Marin of Gilbert AZ (US) for intel corporation, Suddhasattwa Nad of Chandler AZ (US) for intel corporation, Oladeji T. Fadayomi of Maricopa AZ (US) for intel corporation, Manuel Gadogbe of Queen Creek AZ (US) for intel corporation, Matthew L. Tingey of Mesa AZ (US) for intel corporation
IPC Code(s): H01L23/498, H01L21/48, H01L23/15
CPC Code(s): H01L23/49827
Abstract: in one embodiment, an integrated circuit package substrate includes a glass layer having at least one roughened surface (e.g., with an average roughness above 100 nm) and a metal (e.g., a metal trace or metal via) in contact with the roughened surface of the glass layer.
Inventor(s): Bohan Shan of Chandler AZ (US) for intel corporation, Haobo Chen of Chandler AZ (US) for intel corporation, Srinivas Venkata Ramanuja Pietambaram of Chandler AZ (US) for intel corporation, Hongxia Feng of Chandler AZ (US) for intel corporation, Gang Duan of Chandler AZ (US) for intel corporation, Xiaoying Guo of Chandler AZ (US) for intel corporation, Yiqun Bai of Chandler AZ (US) for intel corporation, Dingying Xu of Chandler AZ (US) for intel corporation, Bai Nie of Chandler AZ (US) for intel corporation, Kyle Jordan Arrington of Gilbert AZ (US) for intel corporation, Ziyin Lin of Chandler AZ (US) for intel corporation, Rahul N. Manepalli of Chandler AZ (US) for intel corporation, Brandon C. Marin of Gilbert AZ (US) for intel corporation, Jeremy D. Ecton of Gilbert AZ (US) for intel corporation
IPC Code(s): H01L23/498, H01L21/48, H01L23/538
CPC Code(s): H01L23/49894
Abstract: a substrate for an electronic system includes a glass core layer. the glass core layer includes a first surface and a second surface opposite the first surface; and at least one through-glass via (tgv) extending through the glass core layer from the first surface to the second surface. the tgv includes an opening filled with an electrically conductive material; and a via liner including a sidewall material disposed on a sidewall of the opening between the glass of the glass core layer and the electrically conductive material, wherein the sidewall material includes carbon.
Inventor(s): Rachel Guia Parala Giron of Mesa AZ (US) for intel corporation, Darko Grujicic of Chandler AZ (US) for intel corporation, Suddhasattwa Nad of Chandler AZ (US) for intel corporation
IPC Code(s): H01L23/498, H01L21/48
CPC Code(s): H01L23/49894
Abstract: glass substrates with self-assembled monolayers for copper adhesion, and methods of forming the same, are described herein. in one example, a substrate includes one or more glass layers, a self-assembled monolayer on the one or more glass layers, and a conductive layer on the self-assembled monolayer. the conductive layer includes copper, and the self-assembled monolayer is between the one or more glass layers and the conductive layer.
Inventor(s): Haobo Chen of Chandler AZ (US) for intel corporation, Bohan Shan of Chandler AZ (US) for intel corporation, Xiyu Hu of Phoenix AZ (US) for intel corporation, Rhonda Jack of Mesa AZ (US) for intel corporation, Catherine Mau of Phoenix AZ (US) for intel corporation, Hongxia Feng of Chandler AZ (US) for intel corporation, Xiao Liu of Chandler AZ (US) for intel corporation, Wei Wei of Chandler AZ (US) for intel corporation, Srinivas Pietambaram of Chandler AZ (US) for intel corporation, Gang Duan of Chandler AZ (US) for intel corporation, Xiaoying Guo of Chandler AZ (US) for intel corporation, Dingying Xu of Chandler AZ (US) for intel corporation, Kyle Arrington of Gilbert AZ (US) for intel corporation, Ziyin Lin of Chandler AZ (US) for intel corporation, Hiroki Tanaka of Gilbert AZ (US) for intel corporation, Leonel Arana of Phoenix AZ (US) for intel corporation
IPC Code(s): H01L23/498, H01L21/48, H01L23/29, H01L23/31
CPC Code(s): H01L23/49894
Abstract: methods, systems, apparatus, and articles of manufacture to produce integrated circuit (ic) packages having silicon nitride adhesion promoters are disclosed. an example ic package disclosed herein includes a metal layer on a substrate, a layer on the metal layer, the layer including silicon and nitrogen, and solder resist on the layer.
Inventor(s): Yao-Feng Chang of Bellemont AZ (US) for intel corporation
IPC Code(s): H01L23/525, H01L21/768
CPC Code(s): H01L23/5252
Abstract: an apparatus comprising a device layer comprising a plurality of transistors; a first electrode; a second electrode over the first electrode; and a fuse material layer within a via, the via coupling the first and second electrodes together, wherein the fuse material layer is to conduct a non-zero current responsive to a first voltage between the first and second electrodes, and is to form an irreversible open circuit responsive to a second voltage between the first and second electrodes, wherein a magnitude of the second voltage is less than two volts.
Inventor(s): Abhishek Anil SHARMA of Portland OR (US) for intel corporation, Pushkar RANADE of San Jose CA (US) for intel corporation, Wilfred GOMES of Portland OR (US) for intel corporation, Tahir GHANI of Portland OR (US) for intel corporation, Anand S. MURTHY of Portland OR (US) for intel corporation, Sagar SUTHRAM of Portland OR (US) for intel corporation
IPC Code(s): H01L23/528, H01L27/092, H01L29/06, H01L29/423, H01L29/66, H01L29/775
CPC Code(s): H01L23/528
Abstract: structures having routing across layers of channel structures are described. in an example, an integrated circuit structure includes a first stack of horizontal nanowires along a vertical direction. a second stack of horizontal nanowires is along the vertical direction, the second stack of horizontal nanowires beneath the first stack of horizontal nanowires. a conductive routing layer extends laterally between the first stack of horizontal nanowires and the second stack of horizontal nanowires.
20240222272. DOUBLE INTERCONNECTS FOR STITCHED DIES_simplified_abstract_(intel corporation)
Inventor(s): Abhishek Anil SHARMA of Portland OR (US) for intel corporation, Christopher M. PELTO of Beaverton OR (US) for intel corporation, Wilfred GOMES of Portland OR (US) for intel corporation, Tahir GHANI of Portland OR (US) for intel corporation, Anand S. MURTHY of Portland OR (US) for intel corporation
IPC Code(s): H01L23/528, H01L23/522
CPC Code(s): H01L23/528
Abstract: stitched dies having double interconnects are described. for example, an integrated circuit structure includes a first die including a first device layer, a first plurality of metallization layers over the first device layer, and a first conductive interconnection over the first plurality of metallization layers. the integrated circuit structure also includes a second die separated from the first die by a scribe region, the second die including a second device layer, a second plurality of metallization layers over the second device layer, and a second conductive interconnection over the second plurality of metallization layers. the second conductive interconnection extends over the scribe region and is coupled to the first conductive interconnection.
Inventor(s): Praneeth Kumar Akkinepally of Tempe AZ (US) for intel corporation, Sivakumar Nagarajan of Chandler AZ (US) for intel corporation, Nisha Ananthakrishnan of Chandler AZ (US) for intel corporation, Santosh Shaw of Chandler AZ (US) for intel corporation, Wei Gao of Tempe AZ (US) for intel corporation
IPC Code(s): H01L23/528, H01L23/00, H01L23/48, H01L23/522, H01L25/065
CPC Code(s): H01L23/5283
Abstract: integrated circuit (ic) dies, microelectronic assemblies, and related devices and methods, are disclosed herein. for example, in some embodiments, an ic die may include a substrate, a front-end-of-line (feol) layer over the substrate, where the feol layer includes a plurality of transistors, a first back-end-of-line (beol) layer comprising first interconnects, a second beol layer comprising second interconnects, and a third beol layer comprising third interconnects, wherein the first beol layer is between the feol layer and the second beol layer, the second beol layer is between the first beol layer and the third beol layer, and an electrically conductive fill material of the second interconnects is different from an electrically conductive fill material of the first interconnects and from an electrically conductive fill material of the third interconnects.
Inventor(s): Abhishek Anil SHARMA of Portland OR (US) for intel corporation, Sagar SUTHRAM of Portland OR (US) for intel corporation, Pushkar RANADE of San Jose CA (US) for intel corporation, Tahir GHANI of Portland OR (US) for intel corporation, Anand S. MURTHY of Portland OR (US) for intel corporation, Wilfred GOMES of Portland OR (US) for intel corporation
IPC Code(s): H01L23/528, H01L27/088, H01L29/06, H01L29/423, H01L29/775, H05K1/18
CPC Code(s): H01L23/5286
Abstract: structures having lookup table decoders for fpgas with high dram transistor density are described. in an example, an integrated circuit structure includes a plurality of fins or nanowire stacks, individual ones of the plurality of fins or nanowire stacks having a longest dimension along a first direction. a plurality of gate structures is over the plurality of fins or nanowire stacks, individual ones of the plurality of gate structures having a longest dimension along a second direction, wherein the first direction is non-orthogonal to the second direction.
Inventor(s): Jeremy D. Ecton of Gilbert AZ (US) for intel corporation, Brandon Christian Marin of Gilbert AZ (US) for intel corporation, Srinivas V. Pietambaram of Chandler AZ (US) for intel corporation, Gang Duan of Chandler AZ (US) for intel corporation, Suddhasattwa Nad of Chandler AZ (US) for intel corporation
IPC Code(s): H01L23/538, H01L21/48, H01L23/00, H01L23/15, H01L23/42, H01L23/48, H01L25/00, H01L25/16, H01L25/18
CPC Code(s): H01L23/5381
Abstract: technologies for a vertically interconnected glass layer architecture is disclosed. in the illustrative embodiment, an integrated circuit component includes several integrated circuit dies and a glass layer. integrated circuit dies are positioned both above and below the glass layer. the glass layer has a bridge die embedded in a cavity. the bridge die provides interconnects between the various dies and to other components off of the integrated circuit component. the glass layer can enable three-dimensional heterogeneous integration, allowing for fine pitch connections between dies.
Inventor(s): Sameer Paital of Mesa AZ (US) for intel corporation, Gang Duan of Chandler AZ (US) for intel corporation, Srinivas Pietambaram of Chandler AZ (US) for intel corporation, Kristof Darmawikarta of Chandler AZ (US) for intel corporation
IPC Code(s): H01L23/538, H01L21/48, H01L23/00, H01L23/15, H01L23/498
CPC Code(s): H01L23/5386
Abstract: apparatuses, systems, assemblies, and techniques related to forming a metallization structure in a glass core package substrate such that the metallization structure has multiple portions with differing cross-sectional widths with little or no misalignment between the portions are described. such techniques including mounting the glass core substrate to a stage, applying multiple laser exposures to a location of the glass core substrate to define laser treated regions of the glass core substrate corresponding to the portions of the metallization structure, removing the laser treated regions, and filling the openings with metal to form the embedded zero misaligned metallization structure.
Inventor(s): Hongxia Feng of Chandler AZ (US) for intel corporation, Bohan Shan of Chandler AZ (US) for intel corporation, Bai Nie of Chandler AZ (US) for intel corporation, Xiaoxuan Sun of Phoenix AZ (US) for intel corporation, Holly Sawyer of Aloha OR (US) for intel corporation, Tarek Ibrahim of Mesa AZ (US) for intel corporation, Adwait Telang of Portland OR (US) for intel corporation, Dingying Xu of Chandler AZ (US) for intel corporation, Leonel Arana of Phoenix AZ (US) for intel corporation, Xiaoying Guo of Chandler AZ (US) for intel corporation, Ashay Dani of Chandler AZ (US) for intel corporation, Sairam Agraharam of Chandler AZ (US) for intel corporation, Haobo Chen of Chandler AZ (US) for intel corporation, Srinivas Pietambaram of Chandler AZ (US) for intel corporation, Gang Duan of Chandler AZ (US) for intel corporation
IPC Code(s): H01L23/538, H01L23/00, H01L23/498, H01L25/065
CPC Code(s): H01L23/5386
Abstract: methods and apparatus to prevent over-etch in semiconductor packages are disclosed. a disclosed example semiconductor package includes at least one dielectric layer, an interconnect extending at least partially through or from the at least one dielectric layer, and a material on at least a portion of the interconnect, wherein the material comprises at least one of silicon or titanium.
Inventor(s): Mohammad Mamunur RAHMAN of Gilbert AZ (US) for intel corporation, Brandon C. MARIN of Gilbert AZ (US) for intel corporation, Gang DUAN of Chandler AZ (US) for intel corporation
IPC Code(s): H01L23/538, H01L23/00, H01L25/00, H01L25/065
CPC Code(s): H01L23/5389
Abstract: embodiments disclosed herein include electronic packages and methods of forming electronic packages. in an embodiment, the electronic package comprises a die layer, with a first side and a second side opposite from the first side. in an embodiment, the die layer comprises a first die, and a second die. in an embodiment, a bridge is on the first side of the die layer, where the bridge communicatively couples the first die to the second die. in an embodiment, electrically conductive routing is on the second side of the die layer.
Inventor(s): David Shia of Portland OR (US) for intel corporation, Timothy Gosselin of Phoenix AZ (US) for intel corporation, Aravindha Antoniswamy of Phoenix AZ (US) for intel corporation, Sergio Antonio Chan Arguedas of Chandler AZ (US) for intel corporation, Elah Bozorg-Grayeli of Chandler AZ (US) for intel corporation, Johnny Cook, JR. of Glendale AZ (US) for intel corporation, Steven Klein of Chandler AZ (US) for intel corporation, Rick Canham of Hillsboro OR (US) for intel corporation
IPC Code(s): H01L23/544, H01L23/00, H01L23/427, H01L23/49
CPC Code(s): H01L23/544
Abstract: integrated circuit (ic) device substrates and structures for mating and aligning with sockets. an ic device may include a frame on and around a substrate, which may include glass or silicon. the frame may include an alignment feature, such as a notch or hole, to mate with a complementary keying feature of a socket. a heat spreader may be coupled to an ic die and extend beyond the substrate or be coupled to the frame. the heat spreader may include a heat pipe. the ic device may be part of an ic system with the device substrate coupled to a system substrate by a socket configured to mate to the frame.
Inventor(s): Kristof Darmawikarta of Chandler AZ (US) for intel corporation, Srinivas V. Pietambaram of Chandler AZ (US) for intel corporation, Gang Duan of Chandler AZ (US) for intel corporation, Siddharth Alur Narasimha Krishna of Gilbert AZ (US) for intel corporation, Sameer R. Paital of Mesa AZ (US) for intel corporation, Helme A. Castro De la Torre of Gilbert AZ (US) for intel corporation
IPC Code(s): H01L23/58, H01L21/48, H01L23/498
CPC Code(s): H01L23/58
Abstract: technologies for ribbon field-effect transistors with variable fin numbers are disclosed. in an illustrative embodiment, a stack of semiconductor fins is formed, with each semiconductor fin having a source region, a channel region, and a drain region. some or all of the channel regions can be selectively removed, allowing for the drive and/or leakage current to be tuned. in some embodiments, one or more of the semiconductor fins near the top of the stack can be removed. in other embodiments, one or more of the semiconductor fins at or closer to the bottom of the stack can be removed.
Inventor(s): Mahdi Mohammadighaleni of Phoenix AZ (US) for intel corporation, Joshua Stacey of Chandler AZ (US) for intel corporation, Benjamin T. Duong of Phoenix AZ (US) for intel corporation, Thomas S. Heaton of Mesa AZ (US) for intel corporation, Dilan Seneviratne of Phoenix AZ (US) for intel corporation, Rahul N. Manepalli of Chandler AZ (US) for intel corporation
IPC Code(s): H01L23/64, H01G4/20, H01G4/33, H01L23/00, H01L23/498, H05K1/16
CPC Code(s): H01L23/642
Abstract: embodiments described herein enable a microelectronic assembly that includes: a package substrate having a core including a solid continuous glass material with one or more capacitors in the solid continuous glass material and integrated circuit (ic) dies coupled to the package substrate. the structure of each capacitor includes a dielectric structure between two conductive structures. the dielectric structure comprises a layer of organic dielectric material between two layers of crystalline inorganic material. the crystalline inorganic material is in direct contact with one of the two conductive structures.
Inventor(s): Jeremy D. Ecton of Gilbert AZ (US) for intel corporation, Brandon Christian Marin of Gilbert AZ (US) for intel corporation, Srinivas V. Pietambaram of Chandler AZ (US) for intel corporation, Suddhasattwa Nad of Chandler AZ (US) for intel corporation, Gang Duan of Chandler AZ (US) for intel corporation
IPC Code(s): H01L23/00, H01L23/498, H01L23/538, H01L25/065
CPC Code(s): H01L24/08
Abstract: technologies for die recycling for high yield packaging is disclosed. in the illustrative embodiment, a release layer is deposited on one or more dies. the release layer includes conductive pads and a dielectric layer. both the conductive pads and the dielectric layer have melting points between a temperature at which the die assembly will be processed and a temperature at which the die may sustain damage. one or more layers such as redistribution layers are deposited on the release layer. if a fault is discovered in the redistribution layers, the die assembly can be heated up past the melting point of the release layer, allowing the die to be removed. the die can then be cleaned and recycled for another packaging attempt.
Inventor(s): Bohan Shan of Chandler AZ (US) for intel corporation, Hongxia Feng of Chandler AZ (US) for intel corporation, Haobo Chen of Chandler AZ (US) for intel corporation, Srinivas Pietambaram of Chandler AZ (US) for intel corporation, Bai Nie of Chandler AZ (US) for intel corporation, Gang Duan of Chandler AZ (US) for intel corporation, Kyle Arrington of Gilbert AZ (US) for intel corporation, Ziyin Lin of Chandler AZ (US) for intel corporation, Yiqun Bai of Chandler AZ (US) for intel corporation, Xiaoying Guo of Chandler AZ (US) for intel corporation, Dingying Xu of Chandler AZ (US) for intel corporation, Sairam Agraharam of Chandler AZ (US) for intel corporation, Ashay Dani of Chandler AZ (US) for intel corporation, Eric J. M. Moret of Beaverton OR (US) for intel corporation, Tarek Ibrahim of Mesa AZ (US) for intel corporation
IPC Code(s): H01L23/00
CPC Code(s): H01L24/11
Abstract: methods and apparatus for optical thermal treatment in semiconductor packages are disclosed. a disclosed example integrated circuit (ic) package includes a dielectric substrate, an interconnect associated with the dielectric substrate, and light absorption material proximate or surrounding the interconnect, the light absorption material to increase in temperature in response to being exposed to a pulsed light for thermal treatment corresponding to the ic package.
Inventor(s): Bohan Shan of Chandler AZ (US) for intel corporation, Jiaqi Wu of Chandler AZ (US) for intel corporation, Haobo Chen of Chandler AZ (US) for intel corporation, Srinivas Pietambaram of Chandler AZ (US) for intel corporation, Bai Nie of Chandler AZ (US) for intel corporation, Gang Duan of Chandler AZ (US) for intel corporation, Kyle Arrington of Gilbert AZ (US) for intel corporation, Ziyin Lin of Chandler AZ (US) for intel corporation, Hongxia Feng of Chandler AZ (US) for intel corporation, Yiqun Bai of Chandler AZ (US) for intel corporation, Xiaoying Guo of Chandler AZ (US) for intel corporation, Dingying Xu of Chandler AZ (US) for intel corporation
IPC Code(s): H01L23/00, H01L23/538
CPC Code(s): H01L24/16
Abstract: methods and apparatus to reduce solder bump bridging between two substrates. an apparatus includes a first substrate including a first bump and a second bump spaced apart from the first bump, the first bump including a first base, the second bump including a second base; and a second substrate including a third bump and a fourth bump spaced apart from the third bump, the third bump including a third base, the fourth bump including a fourth base, the first base electrically coupled to the third base by first solder, the second base electrically coupled to the fourth base by second solder, the first solder having a first volume, the second solder having a second volume, the first volume less than the second volume.
20240222320. DIRECTLY BONDED MULTICHIP IC DEVICE PACKAGES_simplified_abstract_(intel corporation)
Inventor(s): Suddhasattwa Nad of Chandler AZ (US) for intel corporation, Gang Duan of Chandler AZ (US) for intel corporation, Srinivas Pietambaram of Chandler AZ (US) for intel corporation, Brandon Marin of Gilbert AZ (US) for intel corporation, Jeremy Ecton of Gilbert AZ (US) for intel corporation
IPC Code(s): H01L25/065, H01L21/56, H01L23/00, H01L23/31, H01L23/48, H01L23/538, H01L25/00
CPC Code(s): H01L25/0652
Abstract: multi-chip/die device including two or more substantially coplanar base ic dies directly bonded to a bridge ic die over or under the base ic dies. direct bonding of the bridge ic die provides high pitch interconnect. a package metallization routing structure including conductive vias adjacent to the bridge ic die may be built up and terminate at first level interconnect interfaces. a temporary carrier, such as glass, may be employed to form such multi-chip devices.
Inventor(s): Sagar Suthram of Portland OR (US) for intel corporation, Wilfred Gomes of Portland OR (US) for intel corporation, Nisha Ananthakrishnan of Chandler AZ (US) for intel corporation, Kemal Aygun of Tempe AZ (US) for intel corporation, Ravindranath Vithal Mahajan of Chandler AZ (US) for intel corporation, Debendra Mallik of Chandler AZ (US) for intel corporation, Pushkar Sharad Ranade of San Jose CA (US) for intel corporation, Abhishek A. Sharma of Hillsboro OR (US) for intel corporation
IPC Code(s): H01L25/065
CPC Code(s): H01L25/0652
Abstract: embodiments of a microelectronic assembly include: a first integrated circuit (ic) die having a first memory circuit and a second memory circuit; a second ic die; a third ic die; and a package substrate. the second ic die is between the first ic die and the package substrate. the first ic die includes: a first portion comprising a first active region and a first backend region in contact with the first active region; and a second portion comprising a second active region and a second backend region in contact with the second active region. the first memory circuit is in the first portion, the second memory circuit is in the second portion, the first active region comprises transistors that are larger than transistors in the second active region, and the first backend region comprises conductive traces that have a larger pitch than conductive traces in the second backend region.
Inventor(s): Sagar Suthram of Portland OR (US) for intel corporation, Wilfred Gomes of Portland OR (US) for intel corporation, Nisha Ananthakrishnan of Chandler AZ (US) for intel corporation, Kemal Aygun of Tempe AZ (US) for intel corporation, Ravindranath Vithal Mahajan of Chandler AZ (US) for intel corporation, Debendra Mallik of Chandler AZ (US) for intel corporation, Pushkar Sharad Ranade of San Jose CA (US) for intel corporation, Abhishek A. Sharma of Hillsboro OR (US) for intel corporation
IPC Code(s): H01L25/065, H01L23/522, H01L23/528, H10B10/00, H10B12/00, H10B80/00
CPC Code(s): H01L25/0655
Abstract: embodiments of a microelectronic assembly include: a first integrated circuit (ic) die having a first memory circuit and a second memory circuit; a second ic die; a third ic die; and a package substrate. the first ic die is between the second ic die and the package substrate. the first ic die comprises: a first portion comprising a first active region and a first backend region in contact with the first active region; and a second portion comprising a second active region and a second backend region in contact with the second active region. the first memory circuit is in the first portion, the second memory circuit is in the second portion, the first active region comprises transistors that are larger than transistors in the second active region, and the first backend region comprises conductive traces that have a larger pitch than conductive traces in the second backend region.
Inventor(s): Sagar Suthram of Portland OR (US) for intel corporation, Wilfred Gomes of Portland OR (US) for intel corporation, Nisha Ananthakrishnan of Chandler AZ (US) for intel corporation, Kemal Aygun of Tempe AZ (US) for intel corporation, Ravindranath Vithal Mahajan of Chandler AZ (US) for intel corporation, Debendra Mallik of Chandler AZ (US) for intel corporation, Pushkar Sharad Ranade of San Jose CA (US) for intel corporation, Abhishek A. Sharma of Hillsboro OR (US) for intel corporation
IPC Code(s): H01L25/065, H01L23/522, H01L23/528, H01L23/532, H10B12/00
CPC Code(s): H01L25/0657
Abstract: embodiments of a microelectronic assembly include: a first integrated circuit (ic) die having a first memory circuit and a second memory circuit, a second ic die; a third ic die; and a package substrate. the first ic die comprises: a first portion comprising a first active region and a first backend region in contact with the first active region; and a second portion comprising a second active region and a second backend region in contact with the second active region. the second portion is surrounded by the first portion in plan view, the first memory circuit is in the first portion, the second memory circuit is in the second portion, the first active region comprises transistors that are larger than transistors in the second active region, and the first backend region comprises conductive traces that have a larger pitch than conductive traces in the second backend region.
Inventor(s): Bohan Shan of Chandler AZ (US) for intel corporation, Haobo Chen of Chandler AZ (US) for intel corporation, Bai Nie of Chandler AZ (US) for intel corporation, Srinivas Pietambaram of Chandler AZ (US) for intel corporation, Gang Duan of Chandler AZ (US) for intel corporation, Kyle Arrington of Gilbert AZ (US) for intel corporation, Ziyin Lin of Chandler AZ (US) for intel corporation, Hongxia Feng of Chandler AZ (US) for intel corporation, Yiqun Bai of Chandler AZ (US) for intel corporation, Xiaoying Guo of Chandler AZ (US) for intel corporation, Dingying Xu of Chandler AZ (US) for intel corporation, Kristof Darmawikarta of Chandler AZ (US) for intel corporation
IPC Code(s): H01L25/18, H01L21/48, H01L21/56, H01L23/00, H01L23/15, H01L23/31, H01L23/538, H01L25/00
CPC Code(s): H01L25/18
Abstract: an apparatus is provided which comprises: a plurality of interconnect layers within a substrate, a layer of organic dielectric material over the plurality of interconnect layers, copper pads within the layer of organic dielectric material, a first integrated circuit device copper-to-copper bonded with the copper pads, inorganic dielectric material over the layer of organic dielectric material, the inorganic dielectric material embedding the first integrated circuit device, and the inorganic dielectric material extending across a width of the substrate, and a second integrated circuit device coupled with a substrate surface above the inorganic dielectric material. other embodiments are also disclosed and claimed.
Inventor(s): Bok Eng Cheah of Gelugor (MY) for intel corporation, Seok Ling Lim of Kulim (MY) for intel corporation, Jenny Shio Yin Ong of Bayan Lepas (MY) for intel corporation, Kooi Chi Ooi of Bukit Gambir (MY) for intel corporation, Jackson Chung Peng Kong of Penang (MY) for intel corporation
IPC Code(s): H01L25/18, H01L21/56, H01L23/00, H01L23/31, H01L25/00
CPC Code(s): H01L25/18
Abstract: an apparatus is provided which comprises: a first package, a second package coupled with the first package, the second package comprising a mold layer having a recess on a first mold surface, a first plurality of devices adjacent to the recess and a metal redistribution layer (rdl) coupled to a second mold surface opposite the first mold surface, wherein the mold layer includes a first thickness, wherein the recess includes a second thickness, and wherein the second thickness is less than the first thickness, and an integrated circuit device coupled with both the second package at the recess and with the first package through a plurality of solder bumps. other embodiments are also disclosed and claimed.
Inventor(s): Sagar Suthram of Portland OR (US) for intel corporation, Kuljit S. Bains of Olympia WA (US) for intel corporation, Wilfred Gomes of Portland OR (US) for intel corporation, Don Douglas Josephson of Fort Collins CO (US) for intel corporation, Surhud V. Khare of Buffalo NY (US) for intel corporation, Christopher Philip Mozak of Portland OR (US) for intel corporation, Randy B. Osborne of Beaverton OR (US) for intel corporation, Pushkar Ranade of San Jose CA (US) for intel corporation, Abhishek Anil Sharma of Portland OR (US) for intel corporation
IPC Code(s): H01L25/18, H01L23/00, H01L23/48, H10B80/00
CPC Code(s): H01L25/18
Abstract: in embodiments herein, an integrated circuit device includes a logic die with processor circuitry and a memory die coupled to the logic die. the memory die includes a first memory module comprising a first memory bank and first control circuitry, a second memory module comprising a second memory bank and second control circuitry, and a scribe line on a surface of the memory die between the first memory module and the second memory module. the first memory module is not electrically connected to the second memory module, and each memory module include through silicon vias (tsvs) to electrically connect a top side of the memory module and a bottom side of the memory module (e.g., for three-dimensional stacking in the integrated circuit device).
Inventor(s): Russell K. MORTENSEN of Chandler AZ (US) for intel corporation, Robert M. NICKERSON of Chandler AZ (US) for intel corporation, Nicholas R. WATTS of Phoenix AZ (US) for intel corporation
IPC Code(s): H01L25/18, H01L21/48, H01L23/00, H01L23/498, H01L25/00, H01L25/065, H01L25/10, H05K1/11, H05K3/40
CPC Code(s): H01L25/18
Abstract: an offset interposer includes a land side including land-side ball-grid array (bga) and a package-on-package (pop) side including a pop-side bga. the land-side bga includes two adjacent, spaced-apart land-side pads, and the pop-side bga includes two adjacent, spaced-apart pop-side pads that are coupled to the respective two land-side bga pads through the offset interposer. the land-side bga is configured to interface with a first-level interconnect. the pop-side bga is configured to interface with a pop substrate. each of the two land-side pads has a different footprint than the respective two pop-side pads.
Inventor(s): Andy Chih-Hung WEI of Yamhill OR (US) for intel corporation, Po-Yao KE of Kaohsiung City (TW) for intel corporation, Derchang KAU of Cupertino CA (US) for intel corporation
IPC Code(s): H01L27/02, H01L23/48
CPC Code(s): H01L27/0255
Abstract: structures having stacked electrostatic discharge (esd) for backside power delivery are described. in an example, an integrated circuit structure includes a device layer having a front side opposite a backside. a front side metallization layer is above the front side of the device layer. a silicon substrate is above the front side metallization layer. the silicon substrate has a diode and/or a bipolar junction transistor therein. the diode and/or bipolar junction transistor is coupled to the device layer through the front side metallization layer by one or more conductive structures. a backside metallization layer is below the backside of the device layer.
Inventor(s): Marko Radosavljevic of Portland OR (US) for intel corporation, Jami A. Wiedemer of Scappoose OR (US) for intel corporation, Munzarin F. Qayyum of Hillsboro OR (US) for intel corporation, Cheng-Ying Huang of Vancouver WA (US) for intel corporation, Rohit V. Galatage of Portland OR (US) for intel corporation, Evan A. Clinton of Carrollton GA (US) for intel corporation
IPC Code(s): H01L27/092, H01L21/822, H01L21/8238, H01L29/06, H01L29/08, H01L29/10, H01L29/423, H01L29/66, H01L29/775
CPC Code(s): H01L27/0922
Abstract: technologies for ribbon field-effect transistors with variable nanoribbon channel dimensions are disclosed. in an illustrative embodiment, a stack of semiconductor nanoribbons are formed, with each semiconductor nanoribbon having a source region, a channel region, and a drain region. some or all of the channel regions can be selectively narrowed and/or thinned, allowing for the drive and/or leakage current to be tuned. in some embodiments, one or more of the semiconductor nanoribbons near the top of the stack can be narrowed and/or thinned. in other embodiments, one or more of the semiconductor nanoribbons at or closer to the bottom of the stack can be narrowed and/or thinned.
20240222428. SEEDED GROWTH FOR 2D NANORIBBON TRANSISTORS_simplified_abstract_(intel corporation)
Inventor(s): Chelsey Dorow of Portland OR (US) for intel corporation, Carl H. Naylor of Portland OR (US) for intel corporation, Kirby Maxey of Hillsboro OR (US) for intel corporation, Kevin O'Brien of Portland OR (US) for intel corporation, Ashish Verma Penumatcha of Beaverton OR (US) for intel corporation, Chia-Ching Lin of Portland OR (US) for intel corporation, Uygar Avci of Portland OR (US) for intel corporation, Matthew Metz of Portland OR (US) for intel corporation, Sudarat Lee of Hillsboro OR (US) for intel corporation, Ande Kitamura of Portland OR (US) for intel corporation, Scott B. Clendenning of Portland OR (US) for intel corporation, Mahmut Sami Kavrik of Eugene OR (US) for intel corporation
IPC Code(s): H01L29/06, H01L21/8234, H01L27/088, H01L29/04, H01L29/08, H01L29/22, H01L29/778, H01L29/786
CPC Code(s): H01L29/0673
Abstract: a transistor has multiple channel regions coupling source and drain structures, and a seed material is between one of the source or drain structures and a channel material, which includes a metal and a chalcogen. each channel region may include a nanoribbon. a nanoribbon may have a monocrystalline structure and a thickness of a monolayer, less than 1 nm. a nanoribbon may be free of internal grain boundaries. a nanoribbon may have an internal grain boundary adjacent an end opposite the seed material. the seed material may directly contact the first of the source or drain structures, and the channel material may directly contact the second of the source or drain structures.
Inventor(s): Abhishek Anil SHARMA of Portland OR (US) for intel corporation, Han Wui THEN of Portland OR (US) for intel corporation, Wilfred GOMES of Portland OR (US) for intel corporation, Anand S. MURTHY of Portland OR (US) for intel corporation, Tahir GHANI of Portland OR (US) for intel corporation, Sagar SUTHRAM of Portland OR (US) for intel corporation, Pushkar RANADE of San Jose CA (US) for intel corporation
IPC Code(s): H01L29/16, H01L21/02, H01L27/105
CPC Code(s): H01L29/1608
Abstract: embodiments described herein may be related to apparatuses, processes, systems, and/or techniques for fabricating semiconductor packages that use a sic layer that is coupled with another layer that includes another material. the sic layer may be an active layer that includes devices, such as transistors, that are coupled with devices that may be in the other layer. the sic layer may be coupled with the other layer using fusion bonding, hybrid bonding, layer transfer, and/or bump and island formation techniques. other embodiments may be described and/or claimed.
20240222438. TRANSISTOR INCLUDING WIDE BAND GAP MATERIALS_simplified_abstract_(intel corporation)
Inventor(s): Abhishek Anil SHARMA of Portland OR (US) for intel corporation, Han Wui THEN of Portland OR (US) for intel corporation, Tahir GHANI of Portland OR (US) for intel corporation, Anand S. MURTHY of Portland OR (US) for intel corporation, Wilfred GOMES of Portland OR (US) for intel corporation, Sagar SUTHRAM of Portland OR (US) for intel corporation, Pushkar RANADE of San Jose CA (US) for intel corporation
IPC Code(s): H01L29/26, H01L29/36, H01L29/40, H01L29/423, H01L29/66, H01L29/778
CPC Code(s): H01L29/26
Abstract: embodiments described herein may be related to apparatuses, processes, systems, and/or techniques for designing and fabricating semiconductor packages that include transistors that include wide band gap materials, such as silicon carbide or gallium nitride. other embodiments may be described and/or claimed.
Inventor(s): Samuel James BADER of Hillsboro OR (US) for intel corporation, Han Wui THEN of Portland OR (US) for intel corporation, Ibrahim BAN of Beaverton OR (US) for intel corporation, Heli Chetanbhai VORA of Hillsboro OR (US) for intel corporation, Marko RADOSAVLJEVIC of Portland OR (US) for intel corporation
IPC Code(s): H01L29/267, H01L21/02, H01L21/18, H01L21/3205, H01L29/06, H01L29/10, H01L29/423, H01L29/66, H01L29/778, H01L29/78
CPC Code(s): H01L29/267
Abstract: embodiments described herein may be related to apparatuses, processes, systems, and/or techniques for using layer transfer techniques to bond a silicon layer with a gan layer, where the silicon layer includes a first portion of a device, for example a transistor, and the gan layer includes a second portion of the device. other embodiments may be described and/or claimed.
Inventor(s): Mahmut Sami Kavrik of Eugene OR (US) for intel corporation, Carl Naylor of Portland OR (US) for intel corporation, Chelsey Dorow of Portland OR (US) for intel corporation, Chia-Ching Lin of Portland OR (US) for intel corporation, Dominique Adams of Portland OR (US) for intel corporation, Kevin O'Brien of Portland OR (US) for intel corporation, Matthew Metz of Portland OR (US) for intel corporation, Scott Clendenning of Portland OR (US) for intel corporation, Sudarat Lee of Hillsboro OR (US) for intel corporation, Tristan Tronic of Aloha OR (US) for intel corporation, Uygar Avci of Portland OR (US) for intel corporation
IPC Code(s): H01L29/40, H01L21/04, H01L21/28, H01L21/3213, H01L21/44, H01L29/423, H01L29/45, H01L29/786
CPC Code(s): H01L29/401
Abstract: devices, transistor structures, systems, and techniques, are described herein related to selective gate oxide formation on 2d materials for transistor devices. a transistor structure includes a gate dielectric structure on a 2d semiconductor material layer, and source and drain structures in contact with the gate dielectric structure and on the 2d semiconductor material layer. the source and drain structures include a metal material or metal nitride material and the gate dielectric structure includes an oxide of the metal material or metal nitride material.
20240222447. GATE CUT, AND SOURCE AND DRAIN CONTACTS_simplified_abstract_(intel corporation)
Inventor(s): Reken Patel of Portland OR (US) for intel corporation, Conor P. Puls of Portland OR (US) for intel corporation, Krishna Ganesan of Portland OR (US) for intel corporation, Akitomo Matsubayashi of Beaverton OR (US) for intel corporation, Diana Ivonne Paredes of Portland OR (US) for intel corporation, Sunzida Ferdous of Portland OR (US) for intel corporation, Brian Greene of Portland OR (US) for intel corporation, Lateef Uddin Syed of Portland OR (US) for intel corporation, Kyle T. Horak of Portland OR (US) for intel corporation, Lin Hu of Portland OR (US) for intel corporation, Anupama Bowonder of Portland OR (US) for intel corporation, Swapnadip Ghosh of Hillsboro OR (US) for intel corporation, Amritesh Rai of Tigard OR (US) for intel corporation, Shruti Subramanian of Hillsboro OR (US) for intel corporation, Gordon S. Freeman of Hood River OR (US) for intel corporation
IPC Code(s): H01L29/417, H01L21/28, H01L21/8238, H01L27/092, H01L29/06, H01L29/423, H01L29/66, H01L29/775
CPC Code(s): H01L29/41733
Abstract: an integrated circuit includes a first device, and a laterally adjacent second device. the first device includes a first body of semiconductor material extending laterally from a first source or drain region, a first gate structure on the first body, and a first contact extending vertically upward from the first source or drain region. the second device includes a second body of semiconductor material extending laterally from a second source or drain region, a second gate structure on the second body, and a second contact extending vertically upward from the second source or drain region. a gate cut structure including dielectric material is laterally between the first gate structure and the second gate structure, and also laterally between the first contact and the second contact. in some examples, a third contact extends laterally from the first contact to the second contact and passes over the gate cut structure.
20240222461. BEOL CONTACT METALS FOR 2D TRANSISTORS_simplified_abstract_(intel corporation)
Inventor(s): Ande Kitamura of Portland OR (US) for intel corporation, Carl H. Naylor of Portland OR (US) for intel corporation, Kevin O'Brien of Portland OR (US) for intel corporation, Kirby Maxey of Hillsboro OR (US) for intel corporation, Chelsey Dorow of Portland OR (US) for intel corporation, Ashish Verma Penumatcha of Beaverton OR (US) for intel corporation, Scott B. Clendenning of Portland OR (US) for intel corporation, Uygar Avci of Portland OR (US) for intel corporation, Matthew Metz of Portland OR (US) for intel corporation, Chia-Ching Lin of Portland OR (US) for intel corporation, Sudarat Lee of Hillsboro OR (US) for intel corporation, Mahmut Sami Kavrik of Eugene OR (US) for intel corporation, Carly Rogan of North Plains OR (US) for intel corporation, Paul Gutwin of Williston VT (US) for intel corporation
IPC Code(s): H01L29/45, H01L21/02, H01L21/443, H01L23/528, H01L29/06, H01L29/24, H01L29/417, H01L29/423, H01L29/66, H01L29/76, H01L29/775
CPC Code(s): H01L29/45
Abstract: a transistor in an integrated circuit (ic) die includes source and drain terminals having a bulk material enclosed by a liner material. a nanoribbon channel region couples the source and drain terminals. the nanoribbon may include a transition metal and a chalcogen. the liner material may contact ends and upper and lower surfaces of the nanoribbon. the transistor may be in an interconnect layer. the source and drain terminals may be formed by conformally depositing the liner material over the ends of the nanoribbon and in voids opened in the ic die.
Inventor(s): Abhishek Anil SHARMA of Portland OR (US) for intel corporation, Han Wui THEN of Portland OR (US) for intel corporation, Wilfred GOMES of Portland OR (US) for intel corporation, Tahir GHANI of Portland OR (US) for intel corporation, Anand S. MURTHY of Portland OR (US) for intel corporation, Sagar SUTHRAM of Portland OR (US) for intel corporation, Pushkar RANADE of San Jose CA (US) for intel corporation
IPC Code(s): H01L29/66, H01L29/16, H01L29/20
CPC Code(s): H01L29/66462
Abstract: embodiments described herein may be related to apparatuses, processes, systems, and/or techniques for fabricating semiconductor packages that use high voltage transistors within a sic layer that are coupled with one or more transistors in one or more other layers in a cascode format in order to switch the high voltage transistors in the sic layer using low voltages. other embodiments may be described and/or claimed.
Inventor(s): Punyashloka Debashis of Hillsboro OR (US) for intel corporation, Dmitri Evgenievich Nikonov of Beaverton OR (US) for intel corporation, Ian Alexander Young of Olympia WA (US) for intel corporation, John J. Plombon of Portland OR (US) for intel corporation, Scott B. Clendenning of Portland OR (US) for intel corporation, Mahendra DC of Portland OR (US) for intel corporation
IPC Code(s): H01L29/66, H01F10/12, H01F10/193, H01F10/32, H10N52/01
CPC Code(s): H01L29/66984
Abstract: technologies for high-performance magnetoelectric spin-orbit (meso) logic structures are disclosed. in the illustrative embodiment, the spin-orbit coupling layer of a meso logic structure is a high-entropy perovskite. the use of a high-entropy perovskite provides versatility through tunability, as there is a wide range of possible combinations. additional layers of the meso logic structure may also be perovskites, such as the magnetoelectric layer and ferromagnetic layer. the various perovskite layers may be epitaxially compatible, allowing for growth of high-quality layers.
Inventor(s): Kevin P. O'Brien of Portland OR (US) for intel corporation, Rachel Steinhardt of Beaverton OR (US) for intel corporation, Chelsey Dorow of Portland OR (US) for intel corporation, Carl H. Naylor of Portland OR (US) for intel corporation, Kirby Maxey of Hillsboro OR (US) for intel corporation, Sudarat Lee of Hillsboro OR (US) for intel corporation, Ashish Verma Penumatcha of Beaverton OR (US) for intel corporation, Uygar Avci of Portland OR (US) for intel corporation, Scott Clendenning of Portland OR (US) for intel corporation, Tristan Tronic of Aloha OR (US) for intel corporation, Mahmut Sami Kavrik of Eugene OR (US) for intel corporation, Ande Kitamura of Portland OR (US) for intel corporation
IPC Code(s): H01L29/76, H01L21/02, H01L29/06, H01L29/24, H01L29/423, H01L29/66, H01L29/775
CPC Code(s): H01L29/7606
Abstract: devices, transistor structures, systems, and techniques are described herein related to field effect transistors having a doping layer on metal chalcogenide nanoribbons outside of the channel region. the doping layer is a metal oxide that shifts the electrical characteristics of the nanoribbons and is formed by depositing a metal and oxidizing the metal by exposure to ozone and ultraviolet light.
20240222483. 2D NANORIBBONS UTILIZING SILICON SCAFFOLDING_simplified_abstract_(intel corporation)
Inventor(s): Carl H. Naylor of Portland OR (US) for intel corporation, Kirby Maxey of Hillsboro OR (US) for intel corporation, Kevin O’Brien of Portland OR (US) for intel corporation, Chelsey Dorow of Portland OR (US) for intel corporation, Sudarat Lee of Hillsboro OR (US) for intel corporation, Ashish Verma Penumatcha of Beaverton OR (US) for intel corporation, Uygar Avci of Portland OR (US) for intel corporation, Matthew Metz of Portland OR (US) for intel corporation, Scott B. Clendenning of Portland OR (US) for intel corporation, Chia-Ching Lin of Portland OR (US) for intel corporation, Ande Kitamura of Portland OR (US) for intel corporation, Mahmut Sami Kavrik of Eugene OR (US) for intel corporation
IPC Code(s): H01L29/76, H01L21/02, H01L29/06, H01L29/24, H01L29/423, H01L29/66, H01L29/775
CPC Code(s): H01L29/7606
Abstract: a transistor structure includes a stack of nanoribbons spanning between terminals of the transistor. ends of the nanoribbons include silicon, and channel regions between the ends include a transition metal and a chalcogen. a gate structure over the channel regions includes an insulator between the channel regions and a gate electrode material. contact regions may be formed by modifying portions of the channel regions by adding a dopant to, or altering the crystal structure of, the channel regions. the transistor structure may be in an integrated circuit device.
Inventor(s): Chia-Ching Lin of Portland OR (US) for intel corporation, Kevin P. O'Brien of Portland OR (US) for intel corporation, Ashish Verma Penumatcha of Beaverton OR (US) for intel corporation, Chelsey Dorow of Portland OR (US) for intel corporation, Kirby Maxey of Hillsboro OR (US) for intel corporation, Carl H. Naylor of Portland OR (US) for intel corporation, Tao Chu of Portland OR (US) for intel corporation, Guowei Xu of Portland OR (US) for intel corporation, Uygar Avci of Portland OR (US) for intel corporation, Feng Zhang of Hillsboro OR (US) for intel corporation, Ting-Hsiang Hung of Beaverton OR (US) for intel corporation, Ande Kitamura of Portland OR (US) for intel corporation, Mahmut Sami Kavrik of Eugene OR (US) for intel corporation
IPC Code(s): H01L29/76, H01L21/02, H01L29/06, H01L29/24, H01L29/423, H01L29/66, H01L29/775
CPC Code(s): H01L29/7606
Abstract: transistors and integrated circuitry including a 2d channel material layer within a stack of material layers further including one or more insulator (e.g., dielectric) materials above and/or below the 2d channel material layer. these supporting insulator layers may be non-sacrificial while other material layers within a starting material stack may be sacrificial, replaced, for example, with gate insulator and/or gate material. in some exemplary embodiments, the 2d channel material is a metal chalcogenide and the supporting insulator layer is advantageously a dielectric material composition having a low dielectric constant.
Inventor(s): Mahmut Sami Kavrik of Eugene OR (US) for intel corporation, Tristan Tronic of Aloha OR (US) for intel corporation, Chelsey Dorow of Portland OR (US) for intel corporation, Kevin O?Brien of Portland OR (US) for intel corporation, Uygar Avci of Portland OR (US) for intel corporation, Carl H. Naylor of Portland OR (US) for intel corporation, Chia-Ching Lin of Portland OR (US) for intel corporation, Dominique Adams of Portland OR (US) for intel corporation, Matthew Metz of Portland OR (US) for intel corporation, Ande Kitamura of Portland OR (US) for intel corporation, Scott B. Clendenning of Portland OR (US) for intel corporation
IPC Code(s): H01L29/775, H01L27/088, H01L29/06, H01L29/26, H01L29/423, H01L29/66
CPC Code(s): H01L29/775
Abstract: a transistor structure includes a stack of nanoribbons coupling source and drain terminals. the nanoribbons may each include a pair of crystalline interface layers and a channel layer between the interface layers. the channel layers may be a molecular monolayer, including a metal and a chalcogen, with a thickness of less than 1 nm. the channel layers may be substantially monocrystalline, and the interface layers may be lattice matched to the channel layers. the channel layers may be epitaxially grown over the lattice-matched interface layers. the crystalline interface layers may be grown over sacrificial layers when forming the stack of nanoribbons.
Inventor(s): Hojoon Ryu of Urbana IL (US) for intel corporation, Punyashloka Debashis of Hillsboro OR (US) for intel corporation, Rachel A. Steinhardt of Beaverton OR (US) for intel corporation, Kevin P. O'Brien of Portland OR (US) for intel corporation, John J. Plombon of Portland OR (US) for intel corporation, Dmitri Evgenievich Nikonov of Beaverton OR (US) for intel corporation, Ian Alexander Young of Olympia WA (US) for intel corporation
IPC Code(s): H01L29/78, H01L21/02, H01L21/8256, H01L27/092, H01L29/24, H01L29/51, H01L29/66, H01L29/76
CPC Code(s): H01L29/78391
Abstract: an apparatus, comprising a field effect transistor comprising a ferroelectric material, a channel material comprising a transition metal and a chalcogen, a source and a drain coupled to the channel material, the source and drain comprising a conductive material.
Inventor(s): Bernhard SELL of Portland OR (US) for intel corporation
IPC Code(s): H01L29/78, H01L21/02, H01L21/306, H01L21/308, H01L21/8234, H01L27/088, H01L27/092, H01L27/12, H01L29/06, H01L29/08, H01L29/10, H01L29/16, H01L29/165, H01L29/417, H01L29/49, H01L29/51, H01L29/66, H01L29/786, H10B12/00
CPC Code(s): H01L29/7853
Abstract: semiconductor devices having necked semiconductor bodies and methods of forming semiconductor bodies of varying width are described. for example, a semiconductor device includes a semiconductor body disposed above a substrate. a gate electrode stack is disposed over a portion of the semiconductor body to define a channel region in the semiconductor body under the gate electrode stack. source and drain regions are defined in the semiconductor body on either side of the gate electrode stack. sidewall spacers are disposed adjacent to the gate electrode stack and over only a portion of the source and drain regions. the portion of the source and drain regions under the sidewall spacers has a height and a width greater than a height and a width of the channel region of the semiconductor body.
20240222514. ETCH STOP FOR OXIDE SEMICONDUCTOR DEVICES_simplified_abstract_(intel corporation)
Inventor(s): Christopher Connor of Portland OR (US) for intel corporation, Vishak Venkatraman of Portland OR (US) for intel corporation, Vladimir Nikitin of Portland OR (US) for intel corporation, Yasin Kaya of Hillsboro OR (US) for intel corporation
IPC Code(s): H01L29/786, H01L27/12, H01L29/66
CPC Code(s): H01L29/7869
Abstract: an integrated circuit structure includes a first layer comprising a semiconductor material. in an example, the semiconductor material of the layer comprises an oxide semiconductor material (e.g., comprising a metal and oxygen). the integrated circuit structure further includes a second layer above the first layer, where the second layer includes a metal and one of oxygen or nitrogen (e.g., includes aluminum and oxygen). in an example, the second layer is an etch stop layer. in an example, the second layer has a thickness of at most 20 nanometers. the integrated circuit structure further includes a first source or drain terminal and a second source or drain terminal, where each of the first and second source or drain terminals extends through the second layer and is coupled to the first layer. in an example, the integrated circuit structure is a thin film transistor (tft), where the first layer is a thin film channel structure of the tft.
Inventor(s): Abhishek Anil SHARMA of Portland OR (US) for intel corporation, Sagar SUTHRAM of Portland OR (US) for intel corporation, Wilfred GOMES of Portland OR (US) for intel corporation, Tahir GHANI of Portland OR (US) for intel corporation, Anand S. MURTHY of Portland OR (US) for intel corporation, Pushkar RANADE of San Jose CA (US) for intel corporation
IPC Code(s): H01L29/786, H01L23/48, H01L27/088, H01L29/06, H10B41/10, H10B41/27, H10B43/10, H10B43/27
CPC Code(s): H01L29/78696
Abstract: structures having vertical shared gate high-drive thin film transistors are described. in an example, an integrated circuit structure includes a stack of alternating dielectric layers and metal layers. a trench is through the stack of alternating dielectric layers and metal layers. a semiconductor channel layer is along sides of the trench. a gate dielectric layer is along sides the semiconductor channel layer in the trench. a gate electrode is within sides of the gate dielectric layer.
Inventor(s): Evan A. Clinton of Carrollton GA (US) for intel corporation, Rohit V. Galatage of Portland OR (US) for intel corporation, Cheng-Ying Huang of Vancouver WA (US) for intel corporation, Jack T. Kavalieros of Portland OR (US) for intel corporation, Munzarin F. Qayyum of Hillsboro OR (US) for intel corporation, Marko Radosavljevic of Portland OR (US) for intel corporation, Jami A. Wiedemer of Scappoose OR (US) for intel corporation
IPC Code(s): H01L29/786, H01L29/06, H01L29/423, H01L29/66, H01L29/775
CPC Code(s): H01L29/78696
Abstract: technologies for ribbon field-effect transistors with variable nanoribbon numbers are disclosed. in an illustrative embodiment, a stack of semiconductor nanoribbons is formed, with each semiconductor nanoribbon having a source region, a channel region, and a drain region. some or all of the channel regions can be selectively removed, allowing for the drive and/or leakage current to be tuned. in some embodiments, one or more of the semiconductor nanoribbons near the top of the stack can be removed. in other embodiments, one or more of the semiconductor nanoribbons at or closer to the bottom of the stack can be removed.
20240222728. POWER MANAGEMENT FOR BATTERY GROUP_simplified_abstract_(intel corporation)
Inventor(s): Naoki Matsumura of San Jose CA (US) for intel corporation, Raghavendra R. Rao of Bangalore, Karnataka (IN) for intel corporation, Jagadish Vasudeva Singh of Bangalore, Karnataka (IN) for intel corporation, Ming-Chia Lee of New Taipei City (TW) for intel corporation
IPC Code(s): H01M10/48, H01M50/51
CPC Code(s): H01M10/482
Abstract: in an embodiment, a system may include at least one system component associated with a power load, a battery group, and control circuitry. the battery group may include multiple battery packs connected in a series connection. the control circuitry may: monitor a voltage level of each battery pack in the battery group during a discharge to the power load of the at least one system component; determine discharge capabilities for the battery packs in the battery group; and in response to a determination that the power load of the at least one system component exceeds a lowest discharge capability of the plurality of battery packs in the battery group, reduce the power load of the at least one system component below the lowest discharge capability of the plurality of battery packs in the battery group.
Inventor(s): Tae Young YANG of Portland OR (US) for intel corporation, Zhen ZHOU of Chandler AZ (US) for intel corporation, Shuhei YAMADA of Hillsboro OR (US) for intel corporation, Tolga ACIKALIN of San Jose CA (US) for intel corporation, Kenneth P. FOUST of Beaverton OR (US) for intel corporation, Bryce D. HORINE of Portland OR (US) for intel corporation
IPC Code(s): H01Q1/52, H01Q1/22, H01Q17/00, H01Q19/10
CPC Code(s): H01Q1/526
Abstract: an apparatus may include a substrate including: a first antenna configured to form a first short range wireless interconnection with a first antenna of a further substrate, a second antenna spaced apart from the first antenna, the second antenna is configured to form a second short range wireless interconnection with a second antenna of the further substrate, and a metamaterial configured to form a surface with effective negative permeability within a space formed between a surface of the substrate and a surface of the further substrate for an established short range wireless interconnection of the first short range wireless interconnection and the second short range wireless interconnection.
Inventor(s): Amit Agarwal of Hillsboro OR (US) for intel corporation, Steven K. Hsu of Lake Oswego OR (US) for intel corporation, Mark A. Anders of Hillsboro OR (US) for intel corporation, Ram K. Krishnamurthy of Portland OR (US) for intel corporation
IPC Code(s): H03K4/94, H03K3/037
CPC Code(s): H03K4/94
Abstract: embodiments herein relate to a pulse generator which provides first and second clock pulses to one or more pulsed latches, where the pulse generator replicates a delay of the pulsed latches in providing the first and second clock pulses. the pulse generator can include a replica of latch components in the pulsed latches such as a tri-state inverter, a transmission gate and inverters, where an output of the tri-state inverter is coupled to the transmission gate and to an input of the inverter, and an output of the inverter is coupled to an input of the tri-state inverter. the tri-state inverter can be a modified tri-state inverter with an output forced to “1” when a clock signal is “0.” in one approach, the latch components of the pulse generator are to write a logic 1 when a clock signal goes high.
Inventor(s): Daniel GRUBER of St. Andrae (AT) for intel corporation, Michael KALCHER of Villach (AT) for intel corporation, Martin CLARA of Santa Clara CA (US) for intel corporation
IPC Code(s): H03M1/10
CPC Code(s): H03M1/10
Abstract: a segmented digital-to-analog converter (dac). the segmented dac includes at least two dac segments. the dac includes at least one overrange dac configured to generate a dither subtraction signal based on an overrange dac control data, and a dither control circuit configured to add a dither to the input data for the segmented dac and generate the overrange dac control data to compensate the dither. the dither subtraction signal is combined with the output signals of the dac segments in an analog domain. the dac includes a segment mismatch correction circuit configured to modify the input data for the segmented dac or input data for at least one segment to correct a mismatch error of one or more of the segments and/or the at least one overrange dac.
20240223228. Method and apparatus for crest factor reduction_simplified_abstract_(intel corporation)
Inventor(s): Kannan RAJAMANI of Basking Ridge NJ (US) for intel corporation, Sunitha MOTIPALLI of POMPANO BEACH FL (US) for intel corporation, Albert MOLINA of Novelda (ES) for intel corporation, Joseph OTHMER of Ocean NJ (US) for intel corporation, Kameran AZADET of San Ramon CA (US) for intel corporation
IPC Code(s): H04B1/04, H04L27/26
CPC Code(s): H04B1/0475
Abstract: an apparatus and method for performing crest factor reduction (cfr). a peak detection circuit detects peaks from input signal samples based on a first threshold. the first threshold is higher than a second threshold that is determined based on a target peak-to-average power ratio (papr). a gain computation circuit determines a gain factor for at least one detected peak. a scaled cancellation pulse generation circuit generates a scaled cancellation pulse for the at least one detected peak based on the gain factor. a combiner circuit combines the scaled cancellation pulse with the input signal samples to generate an output signal. a hard clipping circuit may compress the output signal based on the second threshold. the first threshold is set slightly higher than the second threshold.
Inventor(s): Albert MOLINA of Novelda (ES) for intel corporation, Kameran AZADET of San Ramon CA (US) for intel corporation, Hazar YUKSEL of San Francisco CA (US) for intel corporation
IPC Code(s): H04B1/04, H03F3/24
CPC Code(s): H04B1/0475
Abstract: an apparatus is proposed comprising interface circuitry configured to receive a plurality of samples causing an output signal of a power amplifier. the apparatus further comprises processing circuitry configured to allocate at least one sample of the plurality of samples to a bin based on a characteristic of the at least one sample and determine whether a predistortion for samples allocated to the bin is to be updated based on a number of samples allocated to the bin.
Inventor(s): Ritesh A. BHAT of Portland OR (US) for intel corporation, Steven CALLENDER of Denver CO (US) for intel corporation
IPC Code(s): H04B1/44, H04B1/04
CPC Code(s): H04B1/44
Abstract: disclosed herein is a radio frequency (rf) circuit for a transmit/receive switch that includes an antenna coupled to a receive path through a first coupled transmission line. the antenna is also coupled to a transmit path through a second coupled transmission line. the rf circuit includes a receiver switch configured to selectively present to the receive path a high impedance or a low impedance to ground and a transmitter switch configured to selectively present to the transmit path a high impedance or a low impedance to ground. the receiver switch and/or transmitter switch may be independently supplied with a bias voltage that depends on whether the circuit is operating in a transmit mode or receive mode. the rf circuit may have improved insertion loss, bandwidth, and linearity, while also providing robustness to electrostatic discharge (esd).
20240223244. ENHANCED TONE ALLOCATION_simplified_abstract_(intel corporation)
Inventor(s): Xiaogang Chen of Portland OR (US) for intel corporation, Qinghua Li of San Ramon CA (US) for intel corporation, Feng Jiang of Santa Clara CA (US) for intel corporation, Assaf Gurevitz of Ramat Hasharon (IL) for intel corporation, Shlomi Vituri of Tel Aviv (IL) for intel corporation
IPC Code(s): H04B7/0452, H04W72/12
CPC Code(s): H04B7/0452
Abstract: this disclosure describes systems, methods, and devices related to enhanced tone allocation. a device may schedule a number of station devices to be included in a physical layer (phy) protocol data unit (ppdu) for a multiple-user multiple-input multiple-output (mu-mimo) transmission. the device may limit a number of resource units (rus) to be used in the ppdu for the mu-mimo transmission. the device may use a minimum ru size to be at least 242 tones for the mu-mimo transmission. the device may cause to send the ppdu to the number of station devices.
Inventor(s): Rui Huang of Beijing, 11 (CN) for intel corporation, IIya Bolotin of Nizhny-Novgorod (RU) for intel corporation, Andrey Chervyakov of Nizhny-Novgorod (RU) for intel corporation, Hua Li of Arlington VA (US) for intel corporation, Meng Zhang of Beijing (CN) for intel corporation, Candy Yiu of Portland OR (US) for intel corporation, Youn Heo of Sunnyvale CA (US) for intel corporation
IPC Code(s): H04L5/00
CPC Code(s): H04L5/0035
Abstract: an apparatus and system for use of a pre-configured gap are described. the network signals a preconfigured gap via radio resource control (rrc) signaling and follows a bandwidth part (bwp) to activate/deactivate the gap upon bwp switching. the rrc signaling indicates whether a measurement gap is a pre-configured gap. pre-configured frequency range 1 (fr1) and fr2 gaps are able to be configured simultaneously using rrc signaling. similarly, legacy gaps and pre-configured gaps are able to be configured simultaneously using rrc signaling. the pre-configured gap may be autonomously or implicitly activated triggered by downlink control information (dci) or timer-based bwp switching—in some cases under predetermined network conditions.
Inventor(s): Sergey PANTELEEV of Kildare (IE) for intel corporation, Debdeep CHATTERJEE of San Jose CA (US) for intel corporation, Fatemeh HAMIDI-SEPEHR of San Jose CA (US) for intel corporation, Salvatore TALARICO of Santa Clara CA (US) for intel corporation, Toufiqul ISLAM of Santa Clara CA (US) for intel corporation
IPC Code(s): H04L5/00, H04W72/541
CPC Code(s): H04L5/0057
Abstract: various embodiments herein provide techniques related to cwi for a wideband and one or more sub-bands of the wideband. in embodiments, a user equipment (ue) transmit a wideband channel quality index (cqi) report related to the channel state information (csi) of the wideband. the ue may further identify, from the set of 2, 3, 4, and 5, a number of bits to use for a sub-band cqi report related to a sub-band of the one or more sub-bands, and transmit a sub-band cqi report based on the identified number of bits. other embodiments may be described and/or claimed.
Inventor(s): Ned M. SMITH of Beaverton OR (US) for intel corporation, Mostafa ELSAID of Karlsruhe (DE) for intel corporation
IPC Code(s): H04L9/32, G06F21/62
CPC Code(s): H04L9/321
Abstract: various examples relate to a concept for an attestation recommendation service. an apparatus comprises interface circuitry, machine-readable instructions, and processor circuitry to execute the machine-readable instructions to provide an attestation recommendation service, by obtaining, from a requester, information on a first proposed set of attributes to be used for attestation of the requester by an attestation verification service, determining, based on the information on the first proposed set of attributes and based on a desired privacy score of the requester, a second proposed set of attributes to be used for the attestation, and providing information to the requester, the information comprising the second proposed set of attributes.
Inventor(s): Alan Hwang of New York NY (US) for intel corporation, Solmaz Ghaznavi of Portland OR (US) for intel corporation, Santosh Ghosh of Hillsboro OR (US) for intel corporation
IPC Code(s): H04L9/32, H04L9/30
CPC Code(s): H04L9/3247
Abstract: techniques for performing digital signature verification are described. digital signature verification circuitry includes a memory; and signature verification circuitry, including secure hash algorithm (sha) circuitry; message representative generator circuitry; tree verification circuitry; and hypertree verification circuitry.
20240223384. IPU BASED OPERATORS_simplified_abstract_(intel corporation)
Inventor(s): Francesc GUIM BERNAT of Barcelona (ES) for intel corporation
IPC Code(s): H04L9/32
CPC Code(s): H04L9/3263
Abstract: methods and apparatus for attestation and execution of operators. the apparatus is configured to be implemented in a compute platform including at least one processing unit, and is configured to perform client-side attestation operations with an operator attestation service to validate an operator to be executed on the apparatus or a processing unit on the compute platform. the apparatus is also configured to fetch an operator from an operator catalog, compute a hash over the operator, and send a message containing the hash and operator identifier (id) (or digest containing the same with optional signing) to the operator attestation service, which validates the operator by looking up a valid hash for the operator using the operator id and comparing the hashes. the apparatus is also configured to maintain and enforce tenant rules relating to execution of operators, and includes a cache for caching validated operators.
Inventor(s): Yizhi YAO of Chandler AZ (US) for intel corporation, Joey CHOU of Santa Clara CA (US) for intel corporation
IPC Code(s): H04L12/14, H04L41/0894
CPC Code(s): H04L12/1407
Abstract: various embodiments herein provide techniques related to an edge application server (eas) lifecycle management (lcm) entity. specifically, in embodiments, a logic such as a charging enablement function (cef) may generate charging data related to the eas lcm entity and transmit, based on the charging data, a charging data request to a charging function (chf). other embodiments may be described and/or claimed.
Inventor(s): Hossein ALAVI of Portland OR (US) for intel corporation, Elan BANIN of Raanana (IL) for intel corporation, Ofir DEGANI of Nes-Ammin (IL) for intel corporation, Ashoke RAVI of Portland OR (US) for intel corporation
IPC Code(s): H04L27/00, H04L27/26
CPC Code(s): H04L27/0014
Abstract: a system includes a processor configured to determine a frequency offset between a first local oscillator and a second local oscillator using a combined radio signal received at a first transceiver circuit; wherein the combined radio signal comprises a first signal transmitted by the first transceiver circuit and a second signal transmitted by a second transceiver circuit.
Inventor(s): Christopher Gutierrez of HILLSBORO OR (US) for intel corporation, Vuk Lesi of Cornelius OR (US) for intel corporation, Marcio Juliato of Portland OR (US) for intel corporation, Manoj Sastry of Portland OR (US) for intel corporation, Shabbir Ahmed of Beaverton OR (US) for intel corporation
IPC Code(s): H04L9/40, H04J3/06
CPC Code(s): H04L63/1425
Abstract: techniques include receiving a message with time information at an ingress queue for an ingress interface of an intrusion detection system (ids), the ids to monitor a network node of a time-synchronized network (tsn), generating an entrance timestamp for the message, the entrance timestamp to comprise a time value representing when the message is received at the ingress queue of the ingress interface of the ids, inspecting the message for indications of a security attack by the ids, generating an exit timestamp for the message, the exit timestamp to comprise a time value representing when the message is received at an egress queue of an egress interface of the ids, and generating an inspection time interval associated with the ids, the inspection time interval to represent a time interval between the entrance timestamp and the exit timestamp for the message while transiting the ids. other embodiments are described and claimed.
Inventor(s): Vuk Lesi of Cornelius OR (US) for intel corporation, Christopher Gutierrez of HILLSBORO OR (US) for intel corporation, Shabbir Ahmed of Beaverton OR (US) for intel corporation, Marcio Juliato of Portland OR (US) for intel corporation, Manoj Sastry of Portland OR (US) for intel corporation
IPC Code(s): H04L9/40, G06F1/12
CPC Code(s): H04L63/1466
Abstract: techniques include receiving a message with time information from a clock leader by a clock follower in a time-synchronized network (tsn), the time information to synchronize a clock to a network time for the tsn, retrieving an actual time offset value for the message, the actual time offset value to comprise a value between an actual sending time and an actual receiving time of the message, retrieving an estimated time offset value for the message, the estimated time offset value to comprise a value between an estimated sending time and an estimated receiving time of the message, the estimated time offset value generated using a physics-aware model of the tsn and a clock adjustment value for the clock based on the time information, and determining whether the time information for the message was modified to cause the clock to desynchronize based on difference information. other embodiments are described and claimed.
Inventor(s): Rajesh Poornachandran of Portland OR (US) for intel corporation, Ned M. Smith of Beaverton OR (US) for intel corporation, Sunil K. Cheruvu of Tempe AZ (US) for intel corporation
IPC Code(s): H04L9/40, H04L41/0866
CPC Code(s): H04L63/20
Abstract: the technology described herein includes determining a security quality of service (qos) profile matching configuration attributes of a first computing system, generating an interdependency flow graph based at least in part on the security qos profile and the configuration attributes, generating a recommended configuration for the first computing system from the interdependency flow graph, and sending the recommended configuration to a second computing system.
Inventor(s): Michael PAULITSCH of Ottobrunn (DE) for intel corporation, Ignacio J. ALVAREZ of Portland OR (US) for intel corporation, Fabian OBORIL of Karlsruhe (DE) for intel corporation, Florian GEISSLER of Munich (DE) for intel corporation, Ralf GRAEFE of Haar (DE) for intel corporation, Yang PENG of Munich (DE) for intel corporation, Norbert STOEFFLER of Graefeling (DE) for intel corporation, Neslihan KOSE CIHANGIR of Munich (DE) for intel corporation
IPC Code(s): H04N23/741, G01S17/86, G01S17/931, H04N5/265, H04N23/16, H04N23/72, H04N23/74, H04N23/951
CPC Code(s): H04N23/741
Abstract: disclosed herein are devices, methods, and systems for providing an externally augmented camera that may utilize external light sources of a separate sensor to emit light toward a scene so as to provide accurate imaging of the scene, even in dark or low-light situations or where the scene has a high dynamic range of brightness. the externally augmented camera system may include a sensor with a light source capable of emitting light toward a scene, a camera separate from the light source, where the camera includes a detector capable of detecting emitted light from the light source. the externally augmented camera system also causes the sensor to emit light toward the scene via the light source, causes the camera to capture image data of the scene that has been illuminated by emitted light from the light source, and generates an image of the scene based on the image data.
20240223948. MICROPHONE CHANNEL SELF-NOISE SILENCING_simplified_abstract_(intel corporation)
Inventor(s): Adam Kupryjanow of Gdansk (PL) for intel corporation, Przemyslaw Maziewski of Gdansk (PL) for intel corporation, Lukasz Pindor of Pruszcz Gdanski (PL) for intel corporation, Sebastian Rosenkiewicz of Gdansk (PL) for intel corporation
IPC Code(s): H04R3/04
CPC Code(s): H04R3/04
Abstract: a user computing device includes a microphone to generate an audio signal and a self-noise silencer to generate a feature set corresponding to the audio signal, where the input feature identifies, for each of a plurality of frequency components in the audio signal, a respective magnitude value. at least a portion of the feature set is provided as an input to a machine learning model trained to infer frequencies contributing to self-noise generated at the microphone. an attenuation mask is generated, based on an output of the machine learning model, that identifies an attenuation value for at least a subset of the plurality of frequency components. the attenuation mask is applied to at least the subset of the magnitude values of the plurality of frequency components to remove self-noise from the audio signal and generate a denoised version of the audio signal.
Inventor(s): Balvinder SINGH of Bhilai (IN) for intel corporation, Sheetal BHASIN of Bangalore (IN) for intel corporation, Gila KAMHI of Zichron Yaakov (IL) for intel corporation, Denis KLIMOV of Beer Sheba (IL) for intel corporation
IPC Code(s): H04W4/02, H04N21/436, H04W4/80, H04W76/10
CPC Code(s): H04W4/023
Abstract: an apparatus for controlling output of media content is provided. the apparatus comprises interface circuitry configured to receive input data at least indicating a current state of a radio connection of a wearable device and a respective proximity of the wearable device to one or more playback-capable devices, the radio connection being used to transfer the media content. the apparatus further comprises processing circuitry configured to determine, based on the input data, one or more of the wearable device and the one or more playback-capable devices for output of the media content, and generate, based on the determination, output data for controlling the output of the media content.
Inventor(s): Gila Kamhi of Zichron Yaakov (IL) for intel corporation, Oren Haggai of Kefar Sava (IL) for intel corporation, Prasanna Desai of Elfin Forest CA (US) for intel corporation
IPC Code(s): H04W4/08, H04W4/80, H04W76/10
CPC Code(s): H04W4/08
Abstract: for example, a bluetooth (bt) device may be configured to identify metadata in broadcast messages received at the bt device from a plurality of bt audio source devices; and to select from the plurality of bt audio source devices at least one recommended bt audio source device for a user of the bt device for broadcast audio sharing with one or more other users in an audio sharing community of the user of the bt device. for example, the recommended bt audio source device may be selected from the plurality of bt audio source devices based on the metadata in the broadcast messages, and based on audio consumption information corresponding to the audio sharing community of the user of the bt device.
Inventor(s): Gregory ERMOLAEV of Santa Clara CA (US) for intel corporation, Gang XIONG of Portland OR (US) for intel corporation, Sergey SOSNIN of Santa Clara CA (US) for intel corporation
IPC Code(s): H04W72/1268, H04L1/00, H04W72/0446, H04W72/21
CPC Code(s): H04W72/1268
Abstract: various embodiments herein provide techniques for uplink transport block transmission over multiple slots, e.g. using bit interleaving and/or rate matching. other embodiments may be described and claimed.
Inventor(s): Gang XIONG of Portland OR (US) for intel corporation, Debdeep CHATTERJEE of San Jose CA (US) for intel corporation, Yingyang LI of Santa Clara CA (US) for intel corporation, Sergey SOSNIN of Santa Clara CA (US) for intel corporation, Gregory ERMOLAEV of Santa Clara CA (US) for intel corporation
IPC Code(s): H04W72/1268, H04B7/06, H04W72/0446, H04W72/232
CPC Code(s): H04W72/1268
Abstract: various embodiments herein provide techniques related to identifying, when a user equipment (ue) is in a fifth generation (5g) or new radio (nr) cellular network, a data that is to be transmitted in a transport block over multiple slots (tboms) in a configured grant (cg) physical uplink shared channel (pusch); identifying, based on an indication received from a base station, a number of repetitions for transmission of the pusch; and transmitting, based on the indication, the tboms in the pusch over the multiple slots. other embodiments may be described and/or claimed.
Inventor(s): Gang XIONG of Portland OR (US) for intel corporation, Yi WANG of Santa Clara CA (US) for intel corporation, Yingyang LI of Santa Clara CA (US) for intel corporation, Daewon LEE of Portland OR (US) for intel corporation
IPC Code(s): H04W72/1268, H04L1/1812, H04L5/14, H04W56/00, H04W72/232
CPC Code(s): H04W72/1268
Abstract: various embodiments herein provide techniques for determination of hybrid automatic repeat request (harq) process identifier (id). the techniques may be used, for example, for multi-transmission scheduling by a single downlink control information (dci) and/or in higher carrier frequencies. other embodiments may be described and claimed.
Inventor(s): Ofir Klein of Petah Tikva (IL) for intel corporation, Ehud Reshef of Qiryat Tivon (IL) for intel corporation, Uri Parker of Shimshit (IL) for intel corporation, Danny Alexander of Neve Efraim Monoson (IL) for intel corporation, Nevo Idan of Zichron Ya'akov (IL) for intel corporation, Maxim Stepanov of Jerusalem (IL) for intel corporation, Michael Shachar of Kfar Glikson (IL) for intel corporation
IPC Code(s): H04W74/08
CPC Code(s): H04W74/0816
Abstract: for example, a wireless communication device may be configured to transmit a reservation frame to reserve a wireless communication medium for a transmit opportunity (txop). for example, the txop may be configured to cover a first reserved duration and a second reserved duration. for example, the first reserved duration may be configured for at least one self-transmission of the sta, and the second reserved duration may be configured for communication of at least one non-self-transmission by the sta. for example, the wireless communication device may be configured to transmit the at least one self-transmission during the first duration. for example, the self-transmission may be configured for transmission from a transmitter of the sta to a receiver of the sta.
20240224463. METHODS AND APPARATUS FOR FAN CONTROL_simplified_abstract_(intel corporation)
Inventor(s): Ali Kalantarian of Richmond Hill (CA) for intel corporation, Saanjali Maharaj of Toronto (CA) for intel corporation, Tejas Shah of Austin TX (US) for intel corporation, Tamara Low Foon of Toronto (CA) for intel corporation, Mirui Wang of Oshawa (CA) for intel corporation
IPC Code(s): H05K7/20, G06F1/20
CPC Code(s): H05K7/20209
Abstract: methods, apparatus, systems, and articles of manufacture are disclosed. an example system includes interface circuitry; first programmable circuitry; and instructions to cause the first programmable circuitry to: determine, based on a first signal output by a first sensor, a first temperature at a first location that is associated with second programmable circuitry; determine, based on a second signal output by a second sensor, a second temperature at a second location that is different than the first location; set a first thermal setpoint for the second programmable circuitry in response to the second temperature failing to satisfy a threshold value; and set a second thermal setpoint for the second programmable circuitry in response to the second temperature satisfying the threshold value, wherein the second thermal setpoint is higher than the first thermal setpoint.
Inventor(s): Abhishek Anil SHARMA of Portland OR (US) for intel corporation, Sagar SUTHRAM of Portland OR (US) for intel corporation, Tahir GHANI of Portland OR (US) for intel corporation, Anand S. MURTHY of Portland OR (US) for intel corporation, Wilfred GOMES of Portland OR (US) for intel corporation
IPC Code(s): H10B10/00, H01L23/48, H01L25/065, H10B12/00
CPC Code(s): H10B10/125
Abstract: structures having two-level memory are described. in an example, an integrated circuit structure includes an sram layer including transistors. a dram layer is vertically spaced apart from the transistors of the sram layer. a metallization structure is between the transistors of the sram layer and the dram layer.
Inventor(s): Abhishek Anil SHARMA of Portland OR (US) for intel corporation, Han Wui THEN of Portland OR (US) for intel corporation, Pushkar RANADE of San Jose CA (US) for intel corporation, Wilfred GOMES of Portland OR (US) for intel corporation, Sagar SUTHRAM of Portland OR (US) for intel corporation, Tahir GHANI of Portland OR (US) for intel corporation, Anand S. MURTHY of Portland OR (US) for intel corporation
IPC Code(s): H10B12/00
CPC Code(s): H01L27/1082
Abstract: embodiments described herein may be related to apparatuses, processes, systems, and/or techniques for fabricating semiconductor packages that include dram using wide band gap materials, such as sic or gan to reduce transistor leakage. in addition, transistors may be fabricated adding one or more extra layers between a source and a drain of a transistor and the contact of the source of the drain to increase the effective electrical gate length of the transistor to further reduce leakage. in addition, for these transistors, a thickness of the body below the gate may be made narrow to improve gate control. other embodiments may be described and/or claimed.
Inventor(s): Abhishek Anil SHARMA of Portland OR (US) for intel corporation, Tahir GHANI of Portland OR (US) for intel corporation, Anand S. MURTHY of Portland OR (US) for intel corporation, Wilfred GOMES of Portland OR (US) for intel corporation, Pushkar RANADE of San Jose CA (US) for intel corporation, Sagar SUTHRAM of Portland OR (US) for intel corporation
IPC Code(s): H10B12/00, H01L27/088, H01L29/06, H01L29/78, H01L29/786
CPC Code(s): H10B12/36
Abstract: structures having bit-cost scaling with relaxed transistor area are described. in an example, an integrated circuit structure includes a plurality of plate lines along a first direction. a transistor is beneath the plurality of plate lines, with a direction of a first source or drain to a gate to a second source or drain of the transistor being a second direction orthogonal to the first direction. a plurality of capacitor structures is over the plurality of plate lines, individual ones of the plurality of capacitor structures coupled to a corresponding one of the plurality of plate lines. the plurality of capacitor structures has a staggered arrangement from a plan view perspective.
Inventor(s): Abhishek Anil SHARMA of Portland OR (US) for intel corporation, Tahir GHANI of Portland OR (US) for intel corporation, Jack T. KAVALIEROS of Portland OR (US) for intel corporation, Anand S. MURTHY of Portland OR (US) for intel corporation, Wilfred GOMES of Portland OR (US) for intel corporation
IPC Code(s): H10B51/30
CPC Code(s): H10B51/30
Abstract: structures having layer select transistors for shared peripherals in memory are described. in an example, an integrated circuit structure includes a memory structure layer including a capacitor array coupled to a plurality of plate lines. a memory transistor layer is beneath the memory structure layer, the memory transistor layer including front end transistors coupled to corresponding capacitors of the capacitor array of the memory structure layer. a select transistor layer is over the memory structure layer, the select transistor layer including backend transistors having a channel composition different than the front end transistors. one or more of the backend transistors is coupled to one or more of the plurality of plate lines of the memory structure layer.
Inventor(s): Suddhasattwa Nad of Chandler AZ (US) for intel corporation, Gang Duan of Chandler AZ (US) for intel corporation, Srinivas Pietambaram of Chandler AZ (US) for intel corporation, Brandon Marin of Gilbert AZ (US) for intel corporation, Jeremy Ecton of Gilbert AZ (US) for intel corporation
IPC Code(s): H10B80/00, H01L21/48, H01L23/15, H01L23/498
CPC Code(s): H10B80/00
Abstract: multi-chip/die device including a logic ic die facing a first side of a glass substrate and a memory ic die facing, and coupled to, the logic ic die. first ones of first metallization features of the logic ic die are coupled to through-glass vias extending through a thickness of the glass substrate. the memory ic die is coupled to second ones of the first metallization features, either directly or by way of other through-glass vias. the logic ic die and/or memory ic die may be directly bonded to the through-glass vias or may be attached by solder. the logic ic die or memory ic die may be embedded within the glass substrate. through-glass vias within a region beyond an edge of the memory ic die may couple the logic ic die to a host component either through a routing structure built up adjacent the memory ic die, or through solder features attached to the glass substrate adjacent to the memory ic die.
Inventor(s): Punyashloka Debashis of Hillsboro OR (US) for intel corporation, Dmitri Evgenievich Nikonov of Beaverton OR (US) for intel corporation, Ian Alexander Young of Olympia WA (US) for intel corporation, Hai Li of Portland OR (US) for intel corporation
IPC Code(s): H10N50/85, G11C11/16, H01F10/32, H03K19/18, H10N52/80
CPC Code(s): H10N50/85
Abstract: valleytronic magnetoelectric spin-orbit (meso) logic devices comprise a charge-to-spin conversion input module that comprises a magnetoelectric capacitor. the input module converts a differential input voltage into a magnetization orientation of a ferromagnet possessing in-plane anisotropy (ipa) through exchange coupling between the ipa ferromagnet and the magnetoelectric layer of the capacitor. the magnetization orientation of the ipa ferromagnet can represent the logic state of the valleytronic meso device. a spin-to-charge conversion output module comprises a ferromagnet possessing perpendicular magnetic anisotropy (pma) and a 2d valleytronic material. the ima and pma ferromagnets are chirally-coupled through dzaloshinskii-moriya interaction, which causes the perpendicular magnetic orientation of the pma ferromagnet to switch with the in-plane magnetization orientation of the ipa ferromagnet. the logic state of the device is read through injection of spin-polarized current from the pma ferromagnet into the 2d valleytronic layer, which converts the injected spin-polarized current into a differential output current.
- Intel Corporation
- B25J9/16
- CPC B25J9/1666
- Intel corporation
- B25J15/06
- B25J11/00
- H05K3/36
- CPC B25J15/0683
- B32B17/10
- B32B7/12
- B32B17/02
- B65D85/48
- CPC B32B17/10642
- G01N23/18
- H01L21/67
- CPC G01N23/18
- G01R31/28
- G01R1/07
- CPC G01R31/2834
- G01R31/317
- CPC G01R31/31705
- G02B6/12
- G02B6/13
- H01L23/538
- H01L25/00
- H01L25/18
- CPC G02B6/12004
- G02B6/122
- G02B1/02
- G02B3/00
- CPC G02B6/122
- G02B6/138
- CPC G02B6/1221
- G02B6/35
- G02B6/42
- H01L23/498
- CPC G02B6/35
- CPC G02B6/356
- CPC G02B6/4212
- H01L25/16
- CPC G02B6/4214
- H01L21/48
- H01L23/15
- G02B5/10
- CPC G02B6/4246
- G05B19/418
- G01R1/073
- H01L21/768
- CPC G05B19/41875
- G06F3/06
- CPC G06F3/0616
- G06F9/30
- CPC G06F9/30036
- G06F30/343
- G06F12/0875
- CPC G06F9/30047
- G06F9/38
- G06F9/50
- G06F9/54
- CPC G06F9/30087
- G06F9/4401
- G06F9/455
- G06F12/1009
- G06F21/78
- H04L9/30
- H04L9/32
- CPC G06F9/4403
- G06F1/3231
- H04W52/02
- CPC G06F9/4418
- G06F9/48
- G06F11/263
- CPC G06F9/4812
- G06F5/01
- G06F7/487
- CPC G06F9/5027
- G06F9/52
- CPC G06F9/522
- G06F11/10
- H04L9/08
- CPC G06F11/1044
- G06F11/34
- CPC G06F11/3466
- G06F12/0802
- CPC G06F12/0802
- G06F12/0806
- CPC G06F12/0806
- G06F12/121
- G06F12/0895
- CPC G06F12/121
- G06F12/14
- CPC G06F12/1408
- G06F15/80
- CPC G06F15/80
- G06F13/16
- CPC G06F15/8046
- G06F21/57
- CPC G06F21/57
- CPC G06F21/575
- G06F21/60
- G06F21/85
- CPC G06F21/602
- G06F21/54
- G06F21/55
- G06F21/71
- H04W12/71
- CPC G06F21/71
- G06F30/392
- CPC G06F30/392
- G06F30/398
- CPC G06F30/398
- G06N3/063
- G06F9/448
- G06N5/04
- CPC G06N3/063
- G06T15/00
- G06N3/045
- G06T15/04
- G06T15/50
- G06T17/20
- CPC G06T15/005
- G06T15/80
- G06T1/20
- G06T1/60
- CPC G06T15/80
- G10K11/178
- H04R1/10
- CPC G10K11/17823
- G10L15/34
- G10L15/16
- G10L15/28
- CPC G10L15/34
- G11C11/409
- H01L23/522
- H01L23/528
- CPC G11C11/409
- H01G4/01
- H01G4/30
- H01G4/33
- CPC H01G4/01
- H01G4/012
- H01G4/252
- CPC H01G4/33
- H01J37/317
- H01L21/027
- H01L21/033
- H01L21/311
- H01L21/3213
- CPC H01J37/3174
- H01J37/32
- H01L21/3105
- CPC H01J37/32715
- H01L21/02
- H01L21/04
- H01L23/31
- CPC H01L21/02568
- CPC H01L21/0274
- H01L21/266
- H01L21/265
- CPC H01L21/266
- H01L21/306
- H01L21/321
- CPC H01L21/30604
- H01L21/3065
- CPC H01L21/3212
- CPC H01L21/3213
- H01L23/00
- H01L23/495
- H01L25/065
- CPC H01L21/4842
- H01L21/683
- H01L21/687
- CPC H01L21/6833
- C09J7/24
- C09J7/29
- C09J7/38
- C09J11/04
- H01L23/60
- CPC H01L21/6836
- CPC H01L23/15
- H01L23/16
- CPC H01L23/16
- H01L21/56
- H01L23/29
- H01L25/10
- CPC H01L23/3135
- H01L23/367
- H01L23/42
- H01L23/48
- CPC H01L23/367
- H01L27/088
- CPC H01L23/481
- CPC H01L23/49811
- CPC H01L23/49822
- CPC H01L23/49827
- CPC H01L23/49894
- H01L23/525
- CPC H01L23/5252
- H01L27/092
- H01L29/06
- H01L29/423
- H01L29/66
- H01L29/775
- CPC H01L23/528
- CPC H01L23/5283
- H05K1/18
- CPC H01L23/5286
- CPC H01L23/5381
- CPC H01L23/5386
- CPC H01L23/5389
- H01L23/544
- H01L23/427
- H01L23/49
- CPC H01L23/544
- H01L23/58
- CPC H01L23/58
- H01L23/64
- H01G4/20
- H05K1/16
- CPC H01L23/642
- CPC H01L24/08
- CPC H01L24/11
- CPC H01L24/16
- CPC H01L25/0652
- H10B10/00
- H10B12/00
- H10B80/00
- CPC H01L25/0655
- H01L23/532
- CPC H01L25/0657
- CPC H01L25/18
- H05K1/11
- H05K3/40
- H01L27/02
- CPC H01L27/0255
- H01L21/822
- H01L21/8238
- H01L29/08
- H01L29/10
- CPC H01L27/0922
- H01L21/8234
- H01L29/04
- H01L29/22
- H01L29/778
- H01L29/786
- CPC H01L29/0673
- H01L29/16
- H01L27/105
- CPC H01L29/1608
- H01L29/26
- H01L29/36
- H01L29/40
- CPC H01L29/26
- H01L29/267
- H01L21/18
- H01L21/3205
- H01L29/78
- CPC H01L29/267
- H01L21/28
- H01L21/44
- H01L29/45
- CPC H01L29/401
- H01L29/417
- CPC H01L29/41733
- H01L21/443
- H01L29/24
- H01L29/76
- CPC H01L29/45
- H01L29/20
- CPC H01L29/66462
- H01F10/12
- H01F10/193
- H01F10/32
- H10N52/01
- CPC H01L29/66984
- CPC H01L29/7606
- CPC H01L29/775
- H01L21/8256
- H01L29/51
- CPC H01L29/78391
- H01L21/308
- H01L27/12
- H01L29/165
- H01L29/49
- CPC H01L29/7853
- CPC H01L29/7869
- H10B41/10
- H10B41/27
- H10B43/10
- H10B43/27
- CPC H01L29/78696
- H01M10/48
- H01M50/51
- CPC H01M10/482
- H01Q1/52
- H01Q1/22
- H01Q17/00
- H01Q19/10
- CPC H01Q1/526
- H03K4/94
- H03K3/037
- CPC H03K4/94
- H03M1/10
- CPC H03M1/10
- H04B1/04
- H04L27/26
- CPC H04B1/0475
- H03F3/24
- H04B1/44
- CPC H04B1/44
- H04B7/0452
- H04W72/12
- CPC H04B7/0452
- H04L5/00
- CPC H04L5/0035
- H04W72/541
- CPC H04L5/0057
- G06F21/62
- CPC H04L9/321
- CPC H04L9/3247
- CPC H04L9/3263
- H04L12/14
- H04L41/0894
- CPC H04L12/1407
- H04L27/00
- CPC H04L27/0014
- H04L9/40
- H04J3/06
- CPC H04L63/1425
- G06F1/12
- CPC H04L63/1466
- H04L41/0866
- CPC H04L63/20
- H04N23/741
- G01S17/86
- G01S17/931
- H04N5/265
- H04N23/16
- H04N23/72
- H04N23/74
- H04N23/951
- CPC H04N23/741
- H04R3/04
- CPC H04R3/04
- H04W4/02
- H04N21/436
- H04W4/80
- H04W76/10
- CPC H04W4/023
- H04W4/08
- CPC H04W4/08
- H04W72/1268
- H04L1/00
- H04W72/0446
- H04W72/21
- CPC H04W72/1268
- H04B7/06
- H04W72/232
- H04L1/1812
- H04L5/14
- H04W56/00
- H04W74/08
- CPC H04W74/0816
- H05K7/20
- G06F1/20
- CPC H05K7/20209
- CPC H10B10/125
- CPC H01L27/1082
- CPC H10B12/36
- H10B51/30
- CPC H10B51/30
- CPC H10B80/00
- H10N50/85
- G11C11/16
- H03K19/18
- H10N52/80
- CPC H10N50/85
