Intel Corporation patent applications on July 25th, 2024
Patent Applications by Intel Corporation on July 25th, 2024
Intel Corporation: 25 patent applications
Intel Corporation has applied for patents in the areas of G06F9/30 (4), H04W24/10 (3), H04W72/0457 (2), H01L21/02 (2), H04W72/0453 (2) H04W24/10 (2), A63F13/355 (1), H01L23/562 (1), H04W72/1268 (1), H04W72/0453 (1)
With keywords such as: device, data, network, measurement, devices, based, instruction, processing, methods, and embodiments in patent application abstracts.
Patent Applications by Intel Corporation
20240245990. SYSTEM ARCHITECTURE FOR CLOUD GAMING_simplified_abstract_(intel corporation)
Inventor(s): Makarand DHARMAPURIKAR of Saratoga CA (US) for intel corporation, Rajabali KODURI of Saratoga CA (US) for intel corporation, Vijay BAHIRJI of Hillsboro OR (US) for intel corporation, Toby OPFERMAN of Beaverton OR (US) for intel corporation, Scott G. CHRISTIAN of Aberdeen WA (US) for intel corporation, Rajeev PENMATSA of Folsom CA (US) for intel corporation, Selvakumar PANNEER of Portland OR (US) for intel corporation
IPC Code(s): A63F13/355
CPC Code(s): A63F13/355
Abstract: described herein is a cloud-based gaming system in which graphics processing operations of a cloud-based game can be performed on a client device. client-based graphics processing can be enabled in response to a determination that the client includes a graphics processor having a performance that exceeds a minimum threshold. when a game is remotely executed and streamed to a client, the client is configurable to provide network feedback that can be used to adjust execution and/or encoding for the game.
Inventor(s): Francesc GUIM BERNAT of Barcelona (ES) for intel corporation, Karthik KUMAR of Chandler AZ (US) for intel corporation, Marcos CARRANZA of Portland OR (US) for intel corporation, Rajesh POORNACHANDRAN of Portland OR (US) for intel corporation, Thomas WILLHALM of Sandhausen (DE) for intel corporation
IPC Code(s): G06F3/06
CPC Code(s): G06F3/0653
Abstract: various examples of the present disclosure relate to apparatuses, devices, methods, and computer programs for providing and processing information characterizing a non-uniform memory architecture. an apparatus for a computer system comprises processing circuitry to determine a presence of one or more memory devices connected to at least one processor of the computer system via a serial communication-based processor-to-memory interface, the one or more memory devices being part of a non-uniform memory architecture used by the computer system, determine at least one characteristic for the one or more memory devices by estimating or measuring a performance of the one or more memory devices as observed by the at least one processor, and provide information on the at least one characteristic of the one or more memory devices as part of information characterizing the non-uniform memory architecture.
20240248702. FIRMWARE UPDATE TECHNOLOGIES_simplified_abstract_(intel corporation)
Inventor(s): Murugasamy K. NACHIMUTHU of Beaverton OR (US) for intel corporation, Yidong WU of Shanghai (CN) for intel corporation, Jiaxin WU of Shanghai (CN) for intel corporation, Ruixia LI of Shanghai (CN) for intel corporation
IPC Code(s): G06F8/65
CPC Code(s): G06F8/65
Abstract: it includes updating firmware on a device during operation of the device by: migrating a service executing on the device for execution on a second device; causing the device to enter a disabled state; storing the firmware for access by the device; and causing the device to reset, wherein the device reset comprises the device executing the stored firmware. it can include selecting a device to operate as a boot strap processor, wherein the selected device is one of a group of devices that are to execute the updated firmware and wherein the boot strap processor performs the causing the device to enter a disabled state, storing the firmware for access by the device, and causing the device to reset. the group of devices can comprise a group of threads within a central processing unit (cpu) socket. the group of devices can comprise central processing units (cpus) within a cpu package.
20240248720. INSTRUCTIONS TO CONVERT FROM FP16 TO BF8_simplified_abstract_(intel corporation)
Inventor(s): Alexander Heinecke of San Jose CA (US) for intel corporation, Naveen Mellempudi of Bangalore (IN) for intel corporation, Robert Valentine of Kiryat Tivon (IL) for intel corporation, Mark Charney of Lexington MA (US) for intel corporation, Christopher Hughes of Santa Clara CA (US) for intel corporation, Evangelos Georganas of San Mateo CA (US) for intel corporation, Zeev Sperber of Zichron Yackov (IL) for intel corporation, Amit Gradstein of Binyamina (IL) for intel corporation, Simon Rubanovich of Haifa (IL) for intel corporation
IPC Code(s): G06F9/30, G06F7/499, H03M7/24
CPC Code(s): G06F9/30145
Abstract: techniques for converting fp16 data elements to bf8 data elements using a single instruction are described. an exemplary apparatus includes decoder circuitry to decode a single instruction, the single instruction to include a one or more fields to identify a source operand, one or more fields to identify a destination operand, and one or more fields for an opcode, the opcode to indicate that execution circuitry is to convert packed half-precision floating-point data from the identified source to packed bfloat8 data and store the packed bfloat8 data into corresponding data element positions of the identified destination operand; and execution circuitry to execute the decoded instruction according to the opcode to convert packed half-precision floating-point data from the identified source to packed bfloat8 data and store the packed bfloat8 data into corresponding data element positions.
Inventor(s): Eliezer WEISSMANN of Haifa (IL) for intel corporation, Mark CHARNEY of Lexington MA (US) for intel corporation, Michael MISHAELI of Haifa (IL) for intel corporation, Robert VALENTINE of Kiryat Tivon (IL) for intel corporation, Itai RAVID of Beit Itzhaq (IL) for intel corporation, Jason W. BRANDT of Austin TX (US) for intel corporation, Gilbert NEIGER of Portland OR (US) for intel corporation, Baruch CHAIKIN of D.N. Misgav (IL) for intel corporation, Efraim ROTEM of Santa Clara CA (US) for intel corporation
IPC Code(s): G06F9/38, G06F9/30
CPC Code(s): G06F9/3851
Abstract: systems, methods, and apparatuses relating to instructions to reset software thread runtime property histories in a hardware processor are described. in one embodiment, a hardware processor includes a hardware guide scheduler comprising a plurality of software thread runtime property histories; a decoder to decode a single instruction into a decoded single instruction, the single instruction having a field that identifies a model-specific register; and an execution circuit to execute the decoded single instruction to check that an enable bit of the model-specific register is set, and when the enable bit is set, to reset the plurality of software thread runtime property histories of the hardware guide scheduler.
Inventor(s): Sundar Nadathur of Cupertino CA (US) for intel corporation, Pratik M. Marolia of Hillsboro (OR) for intel corporation, Henry M. Mitchel of Wayne NJ (US) for intel corporation, Joseph J. Grecco of Saddle Brook NJ (US) for intel corporation, Utkarsh Y. Kakaiya of Folsom CA (US) for intel corporation, David A. Munday of Santa Cruz CA (US) for intel corporation
IPC Code(s): G06F11/07
CPC Code(s): G06F11/0793
Abstract: systems, methods, and devices for isolating a misbehaving accelerator circuit, such as an accelerator function unit or an accelerated function context, are provided. an integrated circuit may include a region that includes an accelerator circuit. when the accelerator circuit issues a request, another region of the integrated circuit or a processor connected to the integrated circuit may determine whether there is a misbehavior associated with the request and, in response to determining that there is a misbehavior associated with the request, may perform a misbehavior response to mitigate a negative impact of the misbehavior of the accelerator circuit.
Inventor(s): Eliezer WEISSMANN of Haifa (IL) for intel corporation, Efraim ROTEM of Haifa (IL) for intel corporation, Doron RAJWAN of Rishon Le-Zion (IL) for intel corporation, Hisham ABU SALAH of Majdal shams (IL) for intel corporation, Ariel GUR of Atlit (IL) for intel corporation, Guy M. THERIEN of Beaverton OR (US) for intel corporation, Russell J. FENGER of Beaverton OR (US) for intel corporation
IPC Code(s): G06F13/24, G06F1/3234, G06F1/3287, G06F1/329, G06F9/30, G06F9/44, G06F9/4401
CPC Code(s): G06F13/24
Abstract: systems, methods, and apparatuses relating to hardware control of processor performance levels are described. in one embodiment, a processor includes a plurality of logical processing elements; and a power management circuit to change a highest non-guaranteed performance level and a highest guaranteed performance level for each of the plurality of logical processing elements, and set a notification in a status register when the highest non-guaranteed performance level is changed to a new highest non-guaranteed performance level.
Inventor(s): Rajesh POORNACHANDRAN of Portland OR (US) for intel corporation, Marcos CARRANZA of Portland OR (US) for intel corporation
IPC Code(s): G06F21/10, G06F21/12, G06F21/60
CPC Code(s): G06F21/107
Abstract: various examples relate to apparatuses, devices, methods, and non-transitory machine-readable storage media for presenting content and for a node of a blockchain network. an apparatus for presenting content is to obtain the content, obtain, from at least one decentralized application referenced by the content, at least one license for using the content, and present the content in accordance with the at least one license.
Inventor(s): Rajesh POORNACHANDRAN of PORTLAND OR (US) for intel corporation, Francesc GUIM BERNAT of Barcelona (ES) for intel corporation, Marcos CARRANZA of Portland OR (US) for intel corporation, Cesar MARTINEZ-SPESSOT of Hillsboro OR (US) for intel corporation, Mario Jose DIVAN KOLLER of Hillsboro OR (US) for intel corporation
IPC Code(s): G06Q20/38, G06Q20/40, G06Q30/0283
CPC Code(s): G06Q20/389
Abstract: various examples of the present disclosure relate to methods, apparatuses, devices, and computer programs for peers of a blockchain network. a method for distributing tasks to web3 peers of a blockchain network comprises identifying, during execution of a smart contract, a plurality of tasks to be performed by one or more peers of the blockchain network, determining capabilities of the peers of the blockchain network, wherein at least one capability of at least one peer of the blockchain network is unlocked as an on-demand unlock of the capability at the respective peer, and distributing the plurality of tasks to the one or more peers based on the capabilities of the peers of the blockchain network.
Inventor(s): Dmitry Rudoy of Haifa (IL) for intel corporation, Rakefet Kol of Haifa (IL) for intel corporation, Noam Elron of Tel Aviv (IL) for intel corporation, Noam Levy of Karmiel (IL) for intel corporation
IPC Code(s): G06T5/50, G06T3/40, G06T5/20, G06T7/10
CPC Code(s): G06T5/50
Abstract: a high-level understanding of the scene captured by a camera allows for the use of scene-level understanding in the processing of the captured image. a downscaled image of a captured scene is generated and used as a basis for artificial intelligence analysis before the full image of the captured scene is processed. the downscaled image is generated concurrently with the capturing of the raw image at the image sensor and before full image signal processor (isp) processing. neural networks and other ai algorithms can be applied directly to the downscaled image to perform high-level understanding using minimal resources. the processing of the full scale captured image can be adapted to specific scenarios based on the understanding rather than undergoing all-purpose processing. the high-level understanding is provided to the full image processing pipe for enhancements in image quality, video conferencing, face detection, and other user experiences.
20240249795. MODE REGISTER UPDATE (MRUPD) MODE_simplified_abstract_(intel corporation)
Inventor(s): Saravanan SETHURAMAN of Portland OR (US) for intel corporation, Tonia M. ROSE of Wendell NC (US) for intel corporation
IPC Code(s): G11C29/56
CPC Code(s): G11C29/56004
Abstract: a configuration register update mode can be implemented as an mrupd (mode register update) mode for a dram (dynamic random access memory) device. in one example, the mrupd can also be applied to update an rcd (registering clock driver). in the update mode, the memory device (either the rcd or the dram) can perform configuration of any number of configuration registers with in-band register writes. the in-band register writes can be used to configure dfe (decision feedback equalization) settings, as well as other configuration settings for non-dfe configurations of a memory device interface.
20240249946. GATE SPACING IN INTEGRATED CIRCUIT STRUCTURES_simplified_abstract_(intel corporation)
Inventor(s): Charles Henry Wallace of Portland OR (US) for intel corporation, Mohit K. Haran of Hillsboro OR (US) for intel corporation, Paul A. Nyhus of Portland OR (US) for intel corporation, Gurpreet Singh of Portland OR (US) for intel corporation, Eungnak Han of Portland OR (US) for intel corporation, David Nathan Shykind of Buxton OR (US) for intel corporation, Sean Michael Pursel of Hillsboro OR (US) for intel corporation
IPC Code(s): H01L21/28, H01L21/02, H01L21/306, H01L21/308, H01L21/8234, H01L27/088, H01L29/06, H01L29/423, H01L29/66, H01L29/786
CPC Code(s): H01L21/28123
Abstract: discussed herein is gate spacing in integrated circuit (ic) structures, as well as related methods and components. for example, in some embodiments, an ic structure may include: a first gate metal having a longitudinal axis; a second gate metal, wherein the longitudinal axis of the first gate metal is aligned with a longitudinal axis of the second gate metal; a first gate contact above the first gate metal; a second gate contact above the second gate metal; and an unordered region having an unordered lamellar pattern, wherein the unordered region is coplanar with the first gate contact and the second gate contact.
Inventor(s): Ebony L. MAYS of Hillsboro OR (US) for intel corporation, Bruce J. TUFTS of Banks OR (US) for intel corporation
IPC Code(s): H01L21/762, H01L21/02, H01L29/06
CPC Code(s): H01L21/76224
Abstract: disclosed herein are methods for manufacturing ic components using bottom-up fill of openings with a dielectric material. in one aspect, an exemplary method includes, first, depositing a solid dielectric liner on the inner surfaces of the openings using a non-flowable process, and subsequently filling the remaining empty volume of the openings with a fill dielectric using a flowable process. such a combination method may maximize the individual strengths of the non-flowable and flowable processes due to the synergetic effect achieved by their combined use, while reducing their respective drawbacks. assemblies and devices manufactured using such methods are disclosed as well.
Inventor(s): Srinivas PIETAMBARAM of Chandler AZ (US) for intel corporation, Gang DUAN of Chandler AZ (US) for intel corporation, Deepak KULKARNI of Chandler AZ (US) for intel corporation, Rahul MANEPALLI of Chandler AZ (US) for intel corporation, Xiaoying GUO of Chandler AZ (US) for intel corporation
IPC Code(s): H01L23/00, H01L21/48, H01L21/56, H01L23/31, H01L23/538
CPC Code(s): H01L23/562
Abstract: embodiments disclosed herein include electronic packages and methods of forming such electronic packages. in an embodiment, the electronic package comprises a mold layer having a first surface and a second surface opposite the first surface, and a plurality of first dies embedded in the mold layer. in an embodiment, each of the plurality of first dies has a surface that is substantially coplanar with the first surface of the mold layer. in an embodiment, the electronic package further comprises a second die embedded in the mold layer. in an embodiment, the second die is positioned between the plurality of first dies and the second surface of the mold layer.
Inventor(s): Jason W. BRANDT of Austin TX (US) for intel corporation
IPC Code(s): H04L9/32, G06F9/30, H04L9/08
CPC Code(s): H04L9/3226
Abstract: systems, methods, and apparatuses relating to circuitry to implement an instruction to create and/or use data that is restricted in how it can be used are described. in one embodiment, a hardware processor comprises a decoder of a core to decode a single instruction into a decoded single instruction, the single instruction comprising a first input operand of a handle including a ciphertext of an encryption key (e.g., cryptographic key), an authentication tag, and additional authentication data, and a second input operand of data encrypted with the encryption key, and an execution unit of the core to execute the decoded single instruction to: perform a first check of the authentication tag against the ciphertext and the additional authentication data for any modification to the ciphertext or the additional authentication data, perform a second check of a current request of the core against one or more restrictions specified by the additional authentication data of the handle, decrypt the ciphertext to generate the encryption key only when the first check indicates no modification to the ciphertext or the additional authentication data, and the second check indicates the one or more restrictions are not violated, decrypt the data encrypted with the encryption key to generate unencrypted data, and provide the unencrypted data as a resultant of the single instruction.
20240250873. ADJUSTMENT OF TRANSMISSION SCHEDULING HIERARCHY_simplified_abstract_(intel corporation)
Inventor(s): Benjamin H. SHELTON of Eugene OR (US) for intel corporation, Erik G. CARRILLO of Austin TX (US) for intel corporation
IPC Code(s): H04L41/0813, H04L41/122
CPC Code(s): H04L41/0813
Abstract: examples described herein relate to network interface device configured to adjust a first configuration of a first packet transmission scheduling hierarchy associated with a virtual function (vf) to a second configuration of a second transmission scheduling hierarchy for the vf. the configuring the network interface device to utilize the second configuration for the vf can be delayed until occurrence of a trigger event.
20240250887. MANAGEMENT DATA ANALYTICS_simplified_abstract_(intel corporation)
Inventor(s): Yizhi Yao of Chandler AZ (US) for intel corporation, Joey Chou of Santa Clara CA (US) for intel corporation
IPC Code(s): H04L43/06, G06N5/04, G06N20/00, H04L41/0631, H04L41/147, H04L41/16, H04L41/5009, H04L41/5067, H04L43/04
CPC Code(s): H04L43/06
Abstract: disclosed embodiments are related to management data analytics (mda) relation with self-organizing network (son) functions and coverage issues analysis use case. an mda service (mdas) obtains input data related to one or more managed networks and services from one or more data sources; generates an analytics report based on analysis of the input data; and sends an analytics report to a self-organizing network (son) function for root cause analysis of ongoing issues, prevention of potential issues, and/or prediction of network or service demands. the analytics report may describe an identified network or cell coverage issue related to the son function. other embodiments may be described and/or claimed.
Inventor(s): Fan He of Shanghai (CN) for intel corporation, Yunbiao Lin of Shanghai (CN) for intel corporation, Changliang Wang of Bellevue WA (US) for intel corporation, Yue Heng of Shanghai (CN) for intel corporation
IPC Code(s): H04N19/164, G06N3/092, H04N19/172, H04N19/196, H04N19/42, H04N19/80
CPC Code(s): H04N19/164
Abstract: techniques related to video coding with fast low-latency bitstream size control includes detecting outliers and determining a target bitstream size based on the outlier and reinforcement-learning.
Inventor(s): Rui Huang of Beijing, 11 (CN) for intel corporation, Andrey Chervyakov of Nizhny Novgorod (RU) for intel corporation, Meng Zhang of Beijing (CN) for intel corporation, Hua Li of Arlington VA (US) for intel corporation, Ilya Bolotin of Nizhny-Novgorod (RU) for intel corporation
IPC Code(s): H04W24/10, H04W24/08
CPC Code(s): H04W24/10
Abstract: a user equipment (ue) configured for operation in a fifth-generation new radio (5gnr) network performs synchronization signal block (ssb) based radio resource management (rrm) measurements with or without measurement gaps. the ue may decode network signalling or that triggers a status change of a pre-configured measurement gap. the ue may perform the ssb based rrm measurements with measurement gaps when the network signalling that triggered a pre-configured measurement gap status change activated the pre-configured measurement gap. the ue may deactivate the pre-configured measurement gap and perform the ssb based rrm measurements without measurement gaps when the network signalling that triggered a pre-configured measurement gap status change deactivated the pre-configured measurement gap. the ue may also encode a measurement report for transmission to the network which may include measurements results from the ssb based rrm measurements performed during a measurement reporting delay period. the number of samples of the ssb based rrm measurements that are included in the measurement report may be based at least in part on measurement gap status changes triggered during the measurement reporting delay period.
Inventor(s): Rui HUANG of Santa Clara CA (US) for intel corporation, Meng ZHANG of Beijing (CN) for intel corporation, Andrey CHERVYAKOV of Kildare (IE) for intel corporation, Candy YIU of Santa Clara CA (US) for intel corporation, Hua LI of Santa Clara CA (US) for intel corporation, Ilya BOLOTIN of Santa Clara CA (US) for intel corporation
IPC Code(s): H04W24/10, H04L5/00, H04W72/0457, H04W76/20
CPC Code(s): H04W24/10
Abstract: various embodiments herein provide techniques related to a user equipment (ue). in embodiments, the ue may identify occurrence of a triggering event related to a configured preconfigured measurement gap (pre-mg). further, the ue may check, based on occurrence of the triggering event, a status of the configured pre-mg. further, the ue may change, based on the occurrence of the triggering event, the status of the configured pre-mg. other embodiments may be described and/or claimed.
Inventor(s): Zongrui DING of Portland OR (US) for intel corporation, Qian LI of Portland OR (US) for intel corporation, Sangeetha L. BANGOLAE of Santa Clara CA (US) for intel corporation, Sudeep PALAT of Gloucestershire (GB) for intel corporation, Xiaopeng TONG of Beijing (CN) for intel corporation, Alexandre Saso STOJANOVSKI of Paris 75 (FR) for intel corporation, Ching-Yu LIAO of Santa Clara CA (US) for intel corporation
IPC Code(s): H04W48/08
CPC Code(s): H04W48/08
Abstract: various embodiments herein may relate to system information blocks (sibs) for augmented computing in cellular networks. in particular, some embodiments may be directed to system information associated with computing service support in cellular networks. other embodiments may be disclosed or claimed.
Inventor(s): Hua LI of Santa Clara CA (US) for intel corporation, Meng ZHANG of Beijing (CN) for intel corporation, Rui HUANG of Santa Clara CA (US) for intel corporation, Andrey CHERVYAKOV of Kildare (IE) for intel corporation, In-Seok HWANG of Santa Clara CA (US) for intel corporation, Richard BURBIDGE of Shrivenham (GB) for intel corporation, Ilya BOLOTIN of Santa Clara CA (US) for intel corporation
IPC Code(s): H04W56/00, H04B17/318, H04W24/10
CPC Code(s): H04W56/0015
Abstract: various embodiments herein provide techniques related to a user equipment (ue). in embodiments, the ue may identify a received transmission from a serving cell or another cell (cdp) that has a different physical cell identifier (pci) than the serving cell. the ue may identify, based on a sharing factor related to the serving cell and a sharing factor related to the cdp, an updated sharing factor. the ue may perform, based on the updated sharing factor, a measurement related to the transmission. other embodiments may be described and/or claimed.
Inventor(s): Xiaogang Chen of Portland OR (US) for intel corporation, Qinghua Li of San Ramon CA (US) for intel corporation, Thomas J. Kenney of Portland OR (US) for intel corporation
IPC Code(s): H04W72/0453, H04B7/0452
CPC Code(s): H04W72/0453
Abstract: this disclosure describes systems, methods, and devices related to extremely high throughput (eht) resource unit (ru) allocation. a device may utilize a tone plan to generate an eht frame to be sent using an 80 mhz frequency band, wherein the tone plan comprises a plurality of null tones. the device may encode one or more resource units (rus) for the eht frame, wherein the one or more rus comprise at least one of a 26-tone ru, a 52-tone ru, a 106-tone ru, a 242-tone ru, a 484-tone ru, or a 996-tone ru, wherein the 106-tone ru, the 242-tone ru, and the 484-tone ru comprise null tones located at least at subcarriers �258, �257, �256, �255, and �254. the device may cause to send the eht frame to a first station device using the 80 mhz frequency band.
Inventor(s): Gang Xiong of Beaverton OR (US) for intel corporation, Yingyang Li of Beijing (CN) for intel corporation, Yi Wang of Beijing (CN) for intel corporation
IPC Code(s): H04W72/1268, H04W72/0453, H04W72/0457, H04W72/1273, H04W72/231
CPC Code(s): H04W72/1268
Abstract: an apparatus and system of providing resource allocation for pdsch and/or pusch transmissions with multi-cell scheduling are described. for multi-cell scheduling, one or more of a carrier indicator, bandwidth part (bwp) indication, ul/sul indicator, frequency domain resource allocation (fdra) and/or time domain resource allocation (tdra) may be provided by a ng-ran node to a ue. in some cases, a carrier indication bitmap may be provided in downlink channel information to indicate single or multi-cell scheduling, as well as the scheduled cells.
20240251522. THERMAL CONTROL FOR PROCESSOR-BASED DEVICES_simplified_abstract_(intel corporation)
Inventor(s): Yanbing Sun of Shanghai (CN) for intel corporation, Chao Sun of Shanghai (CN) for intel corporation, Jie Yan of Shanghai (CN) for intel corporation, Xiaoguo Liang of Shanghai (CN) for intel corporation, Lihui Wu of Shanghai (CN) for intel corporation
IPC Code(s): H05K7/20
CPC Code(s): H05K7/20154
Abstract: the present disclosure is directed to systems and methods of improving the thermal performance of processor-based devices. such thermal performance improvement may include a rotatable mount; a first heat sink including a first surface and a second surface, the first surface of the first heat sink to be thermally coupled to a semiconductor device on a substrate, the second surface of the first heat sink thermally coupled to the rotatable mount; and a second heat sink including a third surface, the third surface of the second heat sink coupled to the rotatable mount, the second heat sink structured to rotate relative to the first heat sink when a portion of the rotatable mount rotates between a first position and a second position.
- Intel Corporation
- A63F13/355
- CPC A63F13/355
- Intel corporation
- G06F3/06
- CPC G06F3/0653
- G06F8/65
- CPC G06F8/65
- G06F9/30
- G06F7/499
- H03M7/24
- CPC G06F9/30145
- G06F9/38
- CPC G06F9/3851
- G06F11/07
- CPC G06F11/0793
- G06F13/24
- G06F1/3234
- G06F1/3287
- G06F1/329
- G06F9/44
- G06F9/4401
- CPC G06F13/24
- G06F21/10
- G06F21/12
- G06F21/60
- CPC G06F21/107
- G06Q20/38
- G06Q20/40
- G06Q30/0283
- CPC G06Q20/389
- G06T5/50
- G06T3/40
- G06T5/20
- G06T7/10
- CPC G06T5/50
- G11C29/56
- CPC G11C29/56004
- H01L21/28
- H01L21/02
- H01L21/306
- H01L21/308
- H01L21/8234
- H01L27/088
- H01L29/06
- H01L29/423
- H01L29/66
- H01L29/786
- CPC H01L21/28123
- H01L21/762
- CPC H01L21/76224
- H01L23/00
- H01L21/48
- H01L21/56
- H01L23/31
- H01L23/538
- CPC H01L23/562
- H04L9/32
- H04L9/08
- CPC H04L9/3226
- H04L41/0813
- H04L41/122
- CPC H04L41/0813
- H04L43/06
- G06N5/04
- G06N20/00
- H04L41/0631
- H04L41/147
- H04L41/16
- H04L41/5009
- H04L41/5067
- H04L43/04
- CPC H04L43/06
- H04N19/164
- G06N3/092
- H04N19/172
- H04N19/196
- H04N19/42
- H04N19/80
- CPC H04N19/164
- H04W24/10
- H04W24/08
- CPC H04W24/10
- H04L5/00
- H04W72/0457
- H04W76/20
- H04W48/08
- CPC H04W48/08
- H04W56/00
- H04B17/318
- CPC H04W56/0015
- H04W72/0453
- H04B7/0452
- CPC H04W72/0453
- H04W72/1268
- H04W72/1273
- H04W72/231
- CPC H04W72/1268
- H05K7/20
- CPC H05K7/20154
