Intel Corporation patent applications on July 18th, 2024
Patent Applications by Intel Corporation on July 18th, 2024
Intel Corporation: 45 patent applications
Intel Corporation has applied for patents in the areas of G06F13/16 (4), H01L23/00 (4), H01L23/538 (3), H01L23/522 (3), G06F9/4401 (3) H01L24/14 (2), G03F1/60 (1), H01Q9/0414 (1), G09G5/006 (1), G11C5/04 (1)
With keywords such as: device, memory, based, circuitry, data, include, layer, apparatus, disclosed, and processor in patent application abstracts.
Patent Applications by Intel Corporation
20240241434. PHOTOMASKS HAVING INTERMEDIATE BARRIER LAYERS_simplified_abstract_(intel corporation)
Inventor(s): Yongbae Kim of San Jose CA (US) for intel corporation
IPC Code(s): G03F1/60, G03F1/54
CPC Code(s): G03F1/60
Abstract: photomasks having intermediate barrier layers are disclosed. an example photomask comprises a substrate including a multilayer region, the multilayer region including alternating layers of a first material and a second material different from the first material, a capping layer, and an intermediate layer separating the capping layer and the substrate, the intermediate layer including a third material different from the first material and different from the second material.
Inventor(s): Marvin Paik of Portland OR (US) for intel corporation, Charles H. Wallace of Portland OR (US) for intel corporation, Leonard Guler of Hillsboro OR (US) for intel corporation, Elliot N. Tan of Portland OR (US) for intel corporation, Shengsi Liu of Portland OR (US) for intel corporation, Vivek Vishwakarma of Brush Priarie WA (US) for intel corporation, Izabela Samek of Hillsboro OR (US) for intel corporation, Mohammadreza Soleymaniha of Cedar Park TX (US) for intel corporation
IPC Code(s): G03F7/20, G03F7/00, H01L21/027
CPC Code(s): G03F7/2022
Abstract: apparatus and methods are disclosed. an example lithography apparatus includes an ultraviolet (uv) source to expose a photoresist layer to uv light; and an extreme ultraviolet (euv) source coupled to the uv source, the euv source to expose the photoresist layer to euv light to via a photomask, a combination of the uv light and the euv light provide a pattern on the photoresist layer when a developer solution is applied to the photoresist layer.
20240241554. FAN ENCLOSURE WITH ADJUSTABLE SIDE VENTING_simplified_abstract_(intel corporation)
Inventor(s): Xiyong Tian of Beijing (CN) for intel corporation, Chunlin Bai of ChengDu (CN) for intel corporation, Baoci George Sun of Folsom CA (US) for intel corporation, Li Zhang of Shenzhen (CN) for intel corporation, Chiu Lun Ronald Cheng of Kowloon (HK) for intel corporation
IPC Code(s): G06F1/20, H05K7/20
CPC Code(s): G06F1/206
Abstract: particular embodiments described herein provide for an electronic device that can be configured to include a first heat source, a second heat source, and a fan inside a fan enclosure between the first heat source and the second heat source. the fan enclosure includes a main vent to direct air from the fan towards a heatsink and one or more side vents to direct air from the fan towards the first heat source or the second heat source.
Inventor(s): Rob Sims of Forest Grove OR (US) for intel corporation, Deepak Ganapathy of Folsom OR (US) for intel corporation, Sivasankara Reddy Juturu of Hillsboro OR (US) for intel corporation, Sudheer Nair of Portland OR (US) for intel corporation
IPC Code(s): G06F1/28, G06F1/3206
CPC Code(s): G06F1/28
Abstract: techniques are described for incorporating telemetry related to power source loading and the frequency of power-control events as part of a power balancing algorithm to control an electronic devices' power budgeting among devices sharing a common power source. the techniques utilize telemetry and control loop algorithms to dynamically balance the power between two or more electronic components, which may include a cpu and a gpu. the techniques as described herein function to monitor power source loading as well as the frequency of a predetermined set of events, which may include performance and/or power control events. based on this information, the power budgets of the devices may be dynamically adjusted up or down to maximize performance, in contrast with the conventional usage of artificial static performance caps.
Inventor(s): Robert Pawlowski of Beaverton OR (US) for intel corporation, Shruti Sharma of Beaverton OR (US) for intel corporation, Fabio Checconi of Fremont CA (US) for intel corporation, Sriram Aananthakrishnan of Lubbock TX (US) for intel corporation, Jesmin Jahan Tithi of San Jose CA (US) for intel corporation, Jordi Wolfson-Pou of Santa Clara CA (US) for intel corporation, Joshua B. Fryman of Corvallis OR (US) for intel corporation
IPC Code(s): G06F3/06
CPC Code(s): G06F3/0613
Abstract: systems, apparatuses and methods may provide for technology that includes a plurality of hash management buffers corresponding to a plurality of pipelines, wherein each hash management buffer in the plurality of hash management buffers is adjacent to a pipeline in the plurality of pipelines, and wherein a first hash management buffer is to issue one or more hash packets associated with one or more hash operations on a hash table. the technology may also include a plurality of hash engines corresponding to a plurality of dynamic random access memories (drams), wherein each hash engine in the plurality of hash engines is adjacent to a dram in the plurality of drams, and wherein one or more of the hash engines is to initialize a target memory destination associated with the hash table and conduct the one or more hash operations in response to the one or more hash packets.
Inventor(s): Sean R. Atsatt of Santa Cruz CA (US) for intel corporation, Ilya K. Ganusov of San Jose CA (US) for intel corporation
IPC Code(s): G06F3/06, G06N3/08
CPC Code(s): G06F3/0622
Abstract: systems and methods described herein may relate to providing a dynamically configurable circuitry able to be programed using a microsector granularity. furthermore, selective partial reconfiguration operations may be performed use write operations to write a new configuration over existing configurations to selectively reprogram a portion of programmable logic. a quasi-delay insensitive (qdi) shift register and/or control circuitry receiving data and commands from an access register disposed between portions of programmable logic may enable at least some of the operations described.
20240241690. ACOUSTIC REMOTE CONTROL INTERFACE FOR HEADSETS_simplified_abstract_(intel corporation)
Inventor(s): Sebastian Rosenkiewicz of Gdansk (PL) for intel corporation, Adam Kupryjanow of Gdansk (PL) for intel corporation, Lukasz Pindor of Pruszcz Gdanski, Pomorskie, 83-000 (PL) for intel corporation
IPC Code(s): G06F3/16, H04R1/10
CPC Code(s): G06F3/165
Abstract: techniques are provided herein for implementing headset control functions for low-end consumer-grade headsets using a firmware module implemented in the computing platform. the techniques can include a microphone mute function, a headset speaker volume function, and other headset functions. in particular, acoustic events are utilized to control headset functions. because the headset control components are inside system firmware, the headset control module is endpoint agnostic and will work with any headset coupled to the computing platform. the computing device through which a voice call is implemented can include an event trigger detector, which detects selected acoustic events and triggers a corresponding action. the system allows for control of the voice call via custom user acoustic events. in some examples, the acoustic event that mutes the microphone can be a finger tap. a finger tap generally has a short duration and is easily detectable.
Inventor(s): Abhishek Rhisheekesan of Kottayam (IN) for intel corporation, Shashank Lakshminarayana of Bangalore (IN) for intel corporation, Subramaniam Maiyuran of Gold River CA (US) for intel corporation
IPC Code(s): G06F7/483, G06F1/03, G06F7/487, G06F7/498, G06F7/544
CPC Code(s): G06F7/483
Abstract: a processor to facilitate execution of a single-precision floating point operation on an operand is disclosed. the processor includes one or more execution units, each having a plurality of floating point units to execute one or more instructions to perform the single-precision floating point operation on the operand, including performing a floating point operation on an exponent component of the operand; and performing a floating point operation on a mantissa component of the operand, comprising dividing the mantissa component into a first sub-component and a second sub-component, determining a result of the floating point operation for the first sub-component and determining a result of the floating point operation for the second sub-component, and returning a result of the floating point operation.
Inventor(s): Naveen MELLEMPUDI of Bangalore (IN) for intel corporation, Alexander F. HEINECKE of San Jose CA (US) for intel corporation, Robert VALENTINE of Kiryat Tivon (IL) for intel corporation, Mark J. CHARNEY of Lexington MA (US) for intel corporation, Christopher J. HUGHES of Santa Clara CA (US) for intel corporation, Evangelos GEORGANAS of San Mateo CA (US) for intel corporation, Zeev SPERBER of Zichron Yackov (IL) for intel corporation, Amit GRADSTEIN of Binyamina (IL) for intel corporation, Simon RUBANOVICH of Haifa (IL) for intel corporation
IPC Code(s): G06F9/30, G06F7/499, G06F9/38
CPC Code(s): G06F9/30036
Abstract: systems, methods, and apparatuses relating to 8-bit floating-point matrix dot product instructions are described. a processor embodiment includes fetch circuitry to fetch an instruction having fields to specify an opcode and locations of a destination matrix having single-precision elements, a first source matrix, and a second source matrix, the source matrices having elements that each comprise a quadruple of 8-bit floating-point values, the opcode to indicate execution circuitry is to cause, for each element of the first source matrix and corresponding element of the second source matrix, a conversion of the 8-bit floating-point values to single-precision values, a multiplication of different pairs of converted single-precision values to generate plurality of results, and an accumulation of the results with previous contents of a corresponding element of the destination matrix, decode circuitry to decode the fetched instruction, and the execution circuitry to respond to the decoded instruction as specified by the opcode.
20240241730. MULTI DEVICE MEDIA MANAGEMENT_simplified_abstract_(intel corporation)
Inventor(s): ABHISHEK SRIVASTAV of Bangalore (IN) for intel corporation, SMIT KAPILA of BANGALORE (IN) for intel corporation, SRIKANTH POTLURI of FOLSOM CA (US) for intel corporation, MIN SUET LIM of GELUGOR (MY) for intel corporation, PRAVEEN GARAGA of BANGALORE (IN) for intel corporation, SANGEETA MANEPALLI of CHANDLER AZ (US) for intel corporation, DAVID BIRNBAUM of MODIIN (IL) for intel corporation
IPC Code(s): G06F9/4401
CPC Code(s): G06F9/4411
Abstract: systems, apparatus, articles of manufacture, and methods are disclosed for multi device media management. an example electronic device disclosed herein includes interface circuitry to obtain a notification packet from a client device; machine readable instructions; and at least one processor circuit to be programmed by the machine readable instructions to: to identify a subsystem of the electronic device to be controlled based on the notification packet; and change an operating parameter of the subsystem based on the notification packet.
20240241761. CLOUD-BASED SCALE-UP SYSTEM COMPOSITION_simplified_abstract_(intel corporation)
Inventor(s): Mohan J. Kumar of Aloha OR (US) for intel corporation, Murugasamy K. Nachimuthu of Beaverton OR (US) for intel corporation, Krishna Bhuyan of Sammamish WA (US) for intel corporation
IPC Code(s): G06F9/50, G06F3/06, G06F7/06, G06F8/65, G06F8/654, G06F8/656, G06F8/658, G06F9/38, G06F9/4401, G06F9/455, G06F9/48, G06F9/54, G06F11/07, G06F11/30, G06F11/34, G06F12/02, G06F12/06, G06F13/16, G06F16/174, G06F21/57, G06F21/62, G06F21/73, G06F21/76, G06T1/20, G06T1/60, G06T9/00, H01R13/453, H01R13/631, H03K19/173, H03M7/30, H03M7/40, H03M7/42, H04L9/08, H04L12/28, H04L12/46, H04L41/044, H04L41/0816, H04L41/0853, H04L41/12, H04L43/04, H04L43/06, H04L43/08, H04L43/0894, H04L47/20, H04L47/2441, H04L49/104, H04L61/5007, H04L67/10, H04L67/1014, H04L67/63, H04L67/75, H05K7/14, G06F11/14, G06F15/80, G06F16/28, H04L9/40, H04L41/046, H04L41/0896, H04L41/142, H04L47/78, H04Q11/00
CPC Code(s): G06F9/505
Abstract: technologies for composing a managed node with multiple processors on multiple compute sleds to cooperatively execute a workload include a memory, one or more processors connected to the memory, and an accelerator. the accelerator further includes a coherence logic unit that is configured to receive a node configuration request to execute a workload. the node configuration request identifies the compute sled and a second compute sled to be included in a managed node. the coherence logic unit is further configured to modify a portion of local working data associated with the workload on the compute sled in the memory with the one or more processors of the compute sled, determine coherence data indicative of the modification made by the one or more processors of the compute sled to the local working data in the memory, and send the coherence data to the second compute sled of the managed node.
Inventor(s): Joseph Jacob Grecco of Saddle Brook NJ (US) for intel corporation, Kianoosh Zandifar of Beaverton OR (US) for intel corporation, Kimberly Malone of San Jose CA (US) for intel corporation, Scott Peterson of Beaverton OR (US) for intel corporation
IPC Code(s): G06F9/54
CPC Code(s): G06F9/544
Abstract: disclosed examples implement inter-process communication using a shared memory with a shared heap. disclosed examples send a request from a first process to a second process, the request to cause allocation of a shared heap in shared memory; determine a first virtual address range of the first process for the shared heap in the shared memory based on the first virtual address range matching a second virtual address range from the second process in the shared memory; and write information from the first process to the shared heap, the information to be accessed by the second process from the shared heap.
Inventor(s): Shen ZHOU of Shanghai (CN) for intel corporation, Cong LI of Shanghai (CN) for intel corporation, Kuljit S. BAINS of Olympia WA (US) for intel corporation, Ugonna ECHERUO of Hillsboro OR (US) for intel corporation, Reza E. DAFTARI of Tustin CA (US) for intel corporation, Theodros YIGZAW of Sherwood OR (US) for intel corporation, Mariusz ORIOL of Gdynia (PL) for intel corporation
IPC Code(s): G06F11/07
CPC Code(s): G06F11/073
Abstract: a system () can respond to detection of an uncorrectable error (ue) () in memory () based on fault-aware analysis. the fault-aware analysis enables the system () to generate a determination of a specific hardware element of the memory () that caused the detected ue (). in response to detection of a ue (), the system () can correlate a hardware configuration () of the memory () device with historical data indicating memory () faults for hardware elements of the hardware configuration (). based on a determination of the specific component that likely caused the ue (), the system () can issue a corrective action for the specific hardware element based on the determination.
Inventor(s): Tao Xu of Shanghai (CN) for intel corporation, Shijie Liu of Shanghai (CN) for intel corporation, Kevin Yufu Li of Shanghai (CN) for intel corporation, Lei Zhu of Shanghai (CN) for intel corporation, Sarathy Jayakumar of Portland OR (US) for intel corporation
IPC Code(s): G06F11/20
CPC Code(s): G06F11/2094
Abstract: a disclosed example includes setting a corrected error threshold value for a memory rank; recording, in a corrected error bank record memory structure, corrected errors for memory banks in the memory rank; maintaining, in the corrected error bank record memory structure, counts of the corrected errors for the memory banks; and notifying runtime error handling circuitry in response to at least one of the counts of the corrected errors satisfying a threshold value.
Inventor(s): Junyuan WANG of Shanghai (CN) for intel corporation, Haoxiang SUN of Shanghai (CN) for intel corporation, Xin ZENG of Shanghai (CN) for intel corporation, Maksim LUKOSHKOV of Clarecastle (IE) for intel corporation, Weigang LI of Shanghai (CN) for intel corporation, Zijuan FAN of Shanghai (CN) for intel corporation, Jun XU of Shanghai (CN) for intel corporation
IPC Code(s): G06F12/0862
CPC Code(s): G06F12/0862
Abstract: techniques to reduce data processing latency for a device. circuitry at a device coupled with a host processor can facilitate execution of parallel tasks associated with processing data for a service offloaded to the device from the host processor. the parallel tasks can include prefetching information for address translations related to a shared virtual memory (svm) space that is shared between the device and the host processor and prefetching data to be processed by device in relation to the offloaded service.
Inventor(s): Anil kumar Nama of Bengaluru (IN) for intel corporation, Usha of Bengaluru (IN) for intel corporation, Kunal Ashwinkumar Shah of Bengaluru (IN) for intel corporation, Manjunatha B M of Bengaluru (IN) for intel corporation, Varsha Vithal Baikar of Bengaluru (IN) for intel corporation, Shailendra Singh Chauhan of Bengaluru (IN) for intel corporation, Muhammed Naseef Murikkumkadan of Kalikavu (IN) for intel corporation
IPC Code(s): G06F13/10, G06F3/14, G06F3/147, G06F9/4401
CPC Code(s): G06F13/10
Abstract: systems, apparatus, articles of manufacture, and methods for external display power loss detection and sleep state recovery are disclosed. example apparatus disclosed herein include first circuitry to set an output of the first circuitry to a first logic value after a determination that a compute device is to enter a sleep state, and set the output to a second logic value after a determination that the compute device is to exit the sleep state. disclosed example apparatus also include second circuitry to switch control of a hot plug detect (hpd) input of high-definition multimedia interface (hdmi) circuitry between an output of power loss sensing circuitry and an hpd line of an hdmi port of the hdmi circuitry based on the output of the first circuitry.
Inventor(s): Saravanan SETHURAMAN of Portland OR (US) for intel corporation, Tonia M. ROSE of Wendell NC (US) for intel corporation, Caroline GRIMES of Raleigh NC (US) for intel corporation
IPC Code(s): G06F13/16, G06F9/30, G06F13/42
CPC Code(s): G06F13/1668
Abstract: training a physical interface between a memory device and a memory controller can be performed with an autonomous sweep. the sweep can occur without commands from the host to trigger each parameter sweep. with a two dimensional sweep, instead of interrupting a training mode for a first parameter to sweep a second parameter, circuitry in the memory can automatically sweep the second parameter in the training mode for the first parameter.
20240241843. NETWORK CONTROLLER LOW LATENCY DATA PATH_simplified_abstract_(intel corporation)
Inventor(s): Kishore Kasichainula of Johns Creek GA (US) for intel corporation
IPC Code(s): G06F13/16, H04L49/356, H04L49/901
CPC Code(s): G06F13/1673
Abstract: a network controller is coupled to a memory associated with a hardware accelerator and includes a first port to couple to a host system, wherein the host system comprises system memory and a second port to receive data over a network. the network controller comprises circuitry to determine that the data is to be written directly to the memory instead of to the system memory and write the data to the memory for consumption by the hardware accelerator.
Inventor(s): Min Zhang of Shanghai (CN) for intel corporation, Di Pei of Minhang Distric (CN) for intel corporation, Gang Cao of Shanghai (CN) for intel corporation, Changpeng Liu of Shanghai (CN) for intel corporation, Ziye Yang of Shanghai (CN) for intel corporation
IPC Code(s): G06F13/28, G06F13/16
CPC Code(s): G06F13/28
Abstract: a network interface device includes a port with protocol circuitry to couple to a host device by a link compliant with a compute express link (cxl) protocol. the network interface device further includes a memory and logic to support emulation of a file system by the host device of at least a portion of the memory, where the link is used for direct memory accesses for requests or responses associated with the emulation of the file system.
20240241854. APPARATUS AND METHOD_simplified_abstract_(intel corporation)
Inventor(s): Garrett CLAY of Beaverton OR (US) for intel corporation, Jaemon FRANKO of Gig Harbor WA (US) for intel corporation, Heung-for CHENG of Hillsboro OR (US) for intel corporation
IPC Code(s): G06F15/80, G06F1/20
CPC Code(s): G06F15/80
Abstract: some aspects of the present disclosure relate to an apparatus comprising memory circuitry, machine-readable instructions, and processor circuitry to execute the machine-readable instructions to obtain a physical layout of a first processor circuitry comprising a plurality of processor cores and thermal information of the plurality of processor cores and to determine a first processor core of the plurality of processor cores to execute a first work-load based on the physical layout of the first processor circuitry and the thermal information of the plurality of processor cores.
Inventor(s): Ilil Blum Shem-Tov of Kiryat Tivon (IL) for intel corporation, Miriam Engel of Jerusalem (IL) for intel corporation, Viki Almog-Ayzenberg of Haifa (IL) for intel corporation, Dan Horovitz of Rishon Letzion (IL) for intel corporation, Ilya Nelkenbaum of Tirat Karmel (IL) for intel corporation
IPC Code(s): G06F21/62, G06T5/70, G06V10/56, G06V40/16
CPC Code(s): G06F21/6254
Abstract: systems, apparatus, articles of manufacture, and methods are disclosed. an example includes interface circuitry to access an image frame from a video stream during a presentation of the video stream, the image frame depicting a face; machine-readable instructions; and at least one processor circuit to be programmed by the machine-readable instructions to: determine that the face is associated with at least one of a person-specific privacy policy or a group privacy policy; obtain an obfuscation rule from the at least one of the person-specific privacy policy or the group privacy policy; determine an obfuscation state for the face in the video stream based on at least one of the obfuscation rule or a system operator policy; and cause the presentation of the video stream to depict the face based on the obfuscation state.
20240242067. OPTICAL NEURAL NETWORK ACCELERATOR_simplified_abstract_(intel corporation)
Inventor(s): Songtao Liu of Santa Clara CA (US) for intel corporation, Haisheng Rong of Pleasanton CA (US) for intel corporation, Mozhgan Mansuri of Portland OR (US) for intel corporation, Ram Krishnamurthy of Portland OR (US) for intel corporation
IPC Code(s): G06N3/067
CPC Code(s): G06N3/067
Abstract: systems, apparatuses and methods include technology that executes, with a first plurality of panels, a first matrix-matrix multiplication operation of a first layer of an optical neural network (onn) to generate output optical signals based on input optical signals that pass through an optical path of the onn, and weights of the first layer of the onn. the first plurality of panels includes an input panel, a weight panel and a photodetector panel. the executing includes generating, with the input panel, the input optical signals, where the input optical signals represent an input to the first matrix-matrix multiplication operation of the first layer of the onn, representing, with the weight panel, the weights of the first layer of the onn, and generating, with the photodetector panel, output photodetector signals based on the output optical signals that are generated based on the input optical signals and the weights.
Inventor(s): Ria Cheruvu of Tempe AZ (US) for intel corporation, Anahit Tarkhanyan of Santa Clara CA (US) for intel corporation
IPC Code(s): G06N20/00, G06F9/30, H04L9/32
CPC Code(s): G06N20/00
Abstract: embodiments are directed to immutable watermarking for authenticating and verifying artificial intelligence (ai)-generated output. an embodiment of a system includes a processor of a monitoring system, wherein the processor is to: receive first content from a first device and second content from a second device, wherein the first content comprises output of inferences of a machine learning (ml) model as applied to captured content at the first device; extracting, from a digital signature corresponding to the first content, a global unique identifier (guid) of the ml model that generated the first content; verify the extracted guid against data obtained from a shared registry, the data comprising identifying information of the ml model including the guid; in response to successfully verifying the extracted guid, provide the first content for consumption at an application and indicate that the content is generated by the ml model having verified authenticity.
Inventor(s): Vaibhavdeep Singh of Chandigarh (IN) for intel corporation, Hemant Sathish of Bangalore (IN) for intel corporation, Rohit Sundaram of Bangalore (IN) for intel corporation, Anjali Praveen of Bangalore (IN) for intel corporation
IPC Code(s): G06Q20/40
CPC Code(s): G06Q20/4014
Abstract: methods and apparatus for one-time password detection and alert are disclosed. a disclosed example apparatus includes machine readable instructions, and at least one processor circuit to be programmed by the machine readable instructions to classify, with a trained machine-learning model, messages of a messaging platform of a computing device as one of a financial transaction or a non-financial transaction, and provide a warning based on a one-time password (otp) message of the messages being classified as a financial transaction.
Inventor(s): Liwei Liao of Beijing (CN) for intel corporation, Ming Lu of Beijing (CN) for intel corporation, Xiaofeng Tong of Beijing (CN) for intel corporation, Wenlong Li of Beijing (CN) for intel corporation
IPC Code(s): G06V10/25, G06T7/246, G06T7/292, G06V10/82, G06V20/40
CPC Code(s): G06V10/25
Abstract: techniques related to game focus estimation in team sports for multi-camera immersive video are discussed. such techniques include selecting regions of a scene comprising a sporting event, generating a node graph and sets of features for the selected regions, and determining a game focus region of the selected regions by applying a graph node classification model based on the node graph and sets of features.
Inventor(s): Kedar Karanje of Karnataka (IN) for intel corporation, Satish Koli of Bangalore (IN) for intel corporation, Sitanshu Nanavati of Bangalore (IN) for intel corporation, Bhavesh Kumar Arya of Bangalore (IN) for intel corporation, Shaik Sameeruddin of Vijayawada (IN) for intel corporation
IPC Code(s): G09G5/00
CPC Code(s): G09G5/006
Abstract: systems, apparatuses and methods may provide for technology that identifies a parameter of an internal display, populates a lookup table with the parameter and alternative configuration data if the parameter is related to power consumption, detects a trigger condition during operation of the computing system, and reconfigures the internal display from a first state to a second state in response to the trigger condition based on the lookup table and the alternative configuration data, wherein the internal display and/or a system on chip (soc) associated with the internal display consumes a reduced amount of power in the second state relative to the first state.
20240242740. DUAL IN-LINE MEMORY MODULE RETAINER_simplified_abstract_(intel corporation)
Inventor(s): Phil GENG of Washougal WA (US) for intel corporation, Xiang LI of Portland OR (US) for intel corporation, George VERGIS of Portland OR (US) for intel corporation
IPC Code(s): G11C5/04, H05K1/14, H05K1/18
CPC Code(s): G11C5/04
Abstract: a retainer to inhibit movement of dual in-line memory modules (dimms) that are removably inserted into connectors attached to a printed circuit board (pcb) of a system. inhibiting movement of the dimms, especially taller dimms, such as the higher height 2 u and 4 u dimms, mitigates the effects of operational vibration causing intermittent electrical discontinuity between dimm and the pcb. the retainer inhibits movement of dimms at the connector component level by constraining all or a portion of top edges of dimms inserted into connectors. the retainer is implemented independently of the design of the system-level chassis. the retainer is shaped into any of a bracket or frame from multiple rigid horizontal, vertical and oblique members that permit airflow to the dimms and connectors retained therein.
Inventor(s): Kevin L. Lin of Beaverton OR (US) for intel corporation, Sukru Yemenicioglu of Santa Clara CA (US) for intel corporation, Patrick Morrow of Portland OR (US) for intel corporation, Richard Schenker of Portland OR (US) for intel corporation, Mauro Kobrinsky of Portland OR (US) for intel corporation
IPC Code(s): H01L23/498, H01L21/768, H01L27/088, H05K1/11, H05K3/00, H05K3/40
CPC Code(s): H01L23/49827
Abstract: an integrated circuit interconnect level including a lower metallization line vertically spaced from upper metallization lines. lower metallization lines may be self-aligned to upper metallization lines enabling increased metallization line width without sacrificing line density for a given interconnect level. combinations of upper and lower metallization lines within an interconnect metallization level may be designed to control intra-layer resistance/capacitance of integrated circuit interconnect. dielectric material between two adjacent co-planar metallization lines may be recessed or deposited selectively to the metallization lines. supplemental metallization may then be deposited and planarized. a top surface of the supplemental metallization may either be recessed to form lower metallization lines between upper metallization lines, or planarized with dielectric material to form upper metallization lines between lower metallization lines. vias to upper and lower metallization line may extend another metallization level.
Inventor(s): Kristof DARMAWIKARTA of Chandler AZ (US) for intel corporation, Hiroki TANAKA of GILBERT AZ (US) for intel corporation, Robert MAY of Chandler AZ (US) for intel corporation, Sameer PAITAL of Chandler AZ (US) for intel corporation, Bai NIE of Chandler AZ (US) for intel corporation, Jesse JONES of Chandler AZ (US) for intel corporation, Chung Kwang Christopher TAN of Chandler AZ (US) for intel corporation
IPC Code(s): H01L23/538, H01L23/00, H01L23/522
CPC Code(s): H01L23/538
Abstract: embodiments include an electronic package with an embedded multi-interconnect bridge (emib) and methods of making such packages. embodiments include a first layer, that is an organic material and a second layer disposed over the first layer. in an embodiment, a cavity is formed through the second layer to expose a first surface of the first layer. a bridge substrate is in the cavity and is supported by the first surface of the first layer. embodiments include a first die over the second layer that is electrically coupled to a first contact on the bridge substrate, and a second die over the second layer that is electrically coupled to a second contact on the bridge substrate. in an embodiment the first die is electrically coupled to the second die by the bridge substrate.
Inventor(s): Ryan Joseph Carrazzone of Chandler AZ (US) for intel corporation, Anastasia Arrington of Queen Creek AZ (US) for intel corporation, Haobo Chen of Chandler AZ (US) for intel corporation, Hongxia Feng of Chandler AZ (US) for intel corporation, Catherine Ka-Yan Mau of Phoenix AZ (US) for intel corporation, Kyle Matthew McElhinny of Tempe AZ (US) for intel corporation, Dingying Xu of Chandler AZ (US) for intel corporation
IPC Code(s): H01L23/00, H01L21/48, H01L23/498, H01L23/538, H01L25/065
CPC Code(s): H01L24/14
Abstract: systems, apparatus, articles of manufacture, and methods to reduce variation in height of bumps after flow are disclosed. an example apparatus includes a substrate of an integrated circuit package, a first bump on the substrate, a second bump on the substrate, and a third bump on the substrate. the first bump includes first solder on a first metal pad. the first metal pad has a first width and a first thickness. the second bump includes second solder on a second metal pad. the second metal pad has a second width and a second thickness. the second width is less than the first width. the second thickness matches the first thickness. the third bump includes third solder on a third metal pad. the third metal pad has a third width. the third width less than the second width.
20240243088. COPPERLESS REGIONS TO CONTROL PLATING GROWTH_simplified_abstract_(intel corporation)
Inventor(s): Brandon C. MARIN of Gilbert AZ (US) for intel corporation, Jung Kyu HAN of Chandler AZ (US) for intel corporation, Thomas HEATON of Mesa AZ (US) for intel corporation, Ali LEHAF of Phoenix AZ (US) for intel corporation, Rahul MANEPALLI of Chandler AZ (US) for intel corporation, Srinivas PIETAMBARAM of Chandler AZ (US) for intel corporation, Jacob VEHONSKY of Gilbert AZ (US) for intel corporation
IPC Code(s): H01L23/00, C25D3/38, C25D5/02, C25D7/12
CPC Code(s): H01L24/14
Abstract: embodiments of the present disclosure may generally relate to systems, apparatus, and/or processes directed to manufacturing a package having a substrate with a first side and a second side opposite the first side, where a copper layer is coupled with a first region of the first side of the substrate and includes a plurality of bumps coupled with the first region of the first side of the substrate where one or more second regions on the first side of the substrate not coupled with a copper layer, and where a layout of the one or more second regions on the first side of the substrate is to vary a growth, respectively, of each of the plurality of bumps during a plating process by modifying a local copper density of each of the plurality of bumps.
20240243099. HYPERCHIP_simplified_abstract_(intel corporation)
Inventor(s): Mark T. BOHR of Aloha OR (US) for intel corporation, Wilfred GOMES of Portland OR (US) for intel corporation, Rajesh KUMAR of Portland OR (US) for intel corporation, Pooya TADAYON of Portland OR (US) for intel corporation, Doug INGERLY of Portland OR (US) for intel corporation
IPC Code(s): H01L25/065, H01L23/00, H01L23/522, H01L23/538
CPC Code(s): H01L25/0655
Abstract: hyperchip structures and methods of fabricating hyperchips are described. in an example, an integrated circuit assembly includes a first integrated circuit chip having a device side opposite a backside. the device side includes a plurality of transistor devices and a plurality of device side contact points. the backside includes a plurality of backside contacts. a second integrated circuit chip includes a device side having a plurality of device contact points thereon. the second integrated circuit chip is on the first integrated circuit chip in a device side to device side configuration. ones of the plurality of device contact points of the second integrated circuit chip are coupled to ones of the plurality of device contact points of the first integrated circuit chip. the second integrated circuit chip is smaller than the first integrated circuit chip from a plan view perspective.
Inventor(s): Ritesh K. DAS of Hillsboro OR (US) for intel corporation, Kiran CHIKKADI of Hillsboro OR (US) for intel corporation, Ryan PEARCE of Beaverton OR (US) for intel corporation
IPC Code(s): H01L29/78, H01L29/49, H01L21/02
CPC Code(s): H01L29/7855
Abstract: self-aligned gate endcap (sage) architectures with vertical sidewalls, and methods of fabricating self-aligned gate endcap (sage) architectures with vertical sidewalls, are described. in an example, an integrated circuit structure includes a semiconductor fin having sidewalls along a length of the semiconductor fin, each sidewall tapering outwardly from a top of the semiconductor fin toward a bottom of the semiconductor fin. a gate endcap isolation structure is spaced apart from the semiconductor fin and has a length parallel with the length of the semiconductor fin. the gate endcap isolation structure has a substantially vertical sidewall laterally facing one of the outwardly tapering sidewalls of the semiconductor fin.
Inventor(s): Biswajeet GUHA of Hillsboro OR (US) for intel corporation, William HSU of Portland OR (US) for intel corporation, Leonard P. GULER of Hillsboro OR (US) for intel corporation, Dax M. CRUM of Beaverton OR (US) for intel corporation, Tahir GHANI of Portland OR (US) for intel corporation
IPC Code(s): H01L29/78, H01L21/02, H01L21/8234, H01L23/522, H01L29/06, H01L29/08, H01L29/423
CPC Code(s): H01L29/7856
Abstract: self-aligned gate endcap (sage) architectures with gate-all-around devices, and methods of fabricating self-aligned gate endcap (sage) architectures with gate-all-around devices, are described. in an example, an integrated circuit structure includes a semiconductor fin above a substrate and having a length in a first direction. a nanowire is over the semiconductor fin. a gate structure is over the nanowire and the semiconductor fin, the gate structure having a first end opposite a second end in a second direction, orthogonal to the first direction. a pair of gate endcap isolation structures is included, where a first of the pair of gate endcap isolation structures is spaced equally from a first side of the semiconductor fin as a second of the pair of gate endcap isolation structures is spaced from a second side of the semiconductor fin.
Inventor(s): Erkan Alpman of Portland OR (US) for intel corporation, Arnaud Lucres Amadjikpe of Beaverton OR (US) for intel corporation, Omer Asaf of Oranit (IL) for intel corporation, Kameran Azadet of San Ramon CA (US) for intel corporation, Rotem Banin of Even Yehuda (IL) for intel corporation, Miroslav Baryakh of Petach Tikva (IL) for intel corporation, Anat Bazov of Petach Tikva (IL) for intel corporation, Stefano Brenna of Hillsboro OR (US) for intel corporation, Bryan K. Casper of Portland OR (US) for intel corporation, Anandaroop Chakrabarti of Beaverton OR (US) for intel corporation, Gregory Chance of Chandler AZ (US) for intel corporation, Debabani Choudhury of Thousand Oaks CA (US) for intel corporation, Emanuel Cohen of Zichron Yaacov (IL) for intel corporation, Claudio Da Silva of Portland OR (US) for intel corporation, Sidharth Dalmia of Fair Oaks CA (US) for intel corporation, Saeid Daneshgar Asl of Portland OR (US) for intel corporation, Kaushik Dasgupta of Hillsboro OR (US) for intel corporation, Kunal Datta of Los Angeles CA (US) for intel corporation, Ofir Degani of Haifa (IL) for intel corporation, Amr M. Fahim of Portland OR (US) for intel corporation, Amit Freiman of Haifa (IL) for intel corporation, Michael Genossar of Modiin (IL) for intel corporation, Eran Gerson of Pardes Hana (IL) for intel corporation, Eyal Goldberger of Moshav Beherotaim (IL) for intel corporation, Eshel Gordon of Aloney Aba (IL) for intel corporation, Meir Gordon of Holon (IL) for intel corporation, Josef Hagn of Neubiberg (DE) for intel corporation, Shinwon Kang of San Francisco CA (US) for intel corporation, Te Yu Kao of San Jose CA (US) for intel corporation, Noam Kogan of Tel Aviv (IL) for intel corporation, Mikko S. Komulainen of Oulu (FI) for intel corporation, Igal Yehuda Kushnir of Hod Hasharon (IL) for intel corporation, Saku Lahti of Tampere (FI) for intel corporation, Mikko M. Lampinen of Nokia (FI) for intel corporation, Naftali Landsberg of Ramat Gan (IL) for intel corporation, Wook Bong Lee of San Jose CA (US) for intel corporation, Run Levinger of Tel Aviv (IL) for intel corporation, Albert Molina of Alcobenda (ES) for intel corporation, Resti Montoya Moreno of Helsinki (FI) for intel corporation, Tawfiq Musah of Hillsboro OR (US) for intel corporation, Nathan G. Narevsky of Portland OR (US) for intel corporation, Hosein Nikopour of San Jose CA (US) for intel corporation, Oner Orhan of San Jose CA (US) for intel corporation, Georgios Palaskas of Portland OR (US) for intel corporation, Stefano Pellerano of Beaverton OR (US) for intel corporation, Ron Pongratz of Tel Aviv (IL) for intel corporation, Ashoke Ravi of Portland OR (US) for intel corporation, Shmuel Ravid of Haifa (IL) for intel corporation, Peter Andrew Sagazio of Portland OR (US) for intel corporation, Eren Sasoglu of Mountain View CA (US) for intel corporation, Lior Shakedd of Kfar Bilu (IL) for intel corporation, Gadi Shor of Tel Aviv (IL) for intel corporation, Baljit Singh of San Jose CA (US) for intel corporation, Menashe Soffer of Katzir (IL) for intel corporation, Ra'anan Sover of Haifa (IL) for intel corporation, Shilpa Talwar of Cupertino CA (US) for intel corporation, Nebil Tanzi of Hoffman Estates IL (US) for intel corporation, Moshe Teplitsky of Tel-Aviv (IL) for intel corporation, Chintan S. Thakkar of Portland OR (US) for intel corporation, Jayprakash Thakur of BANGALORE (IN) for intel corporation, Avi Tsarfati of Rishon Le Zion (IL) for intel corporation, Marian Verhelst of Portland OR (US) for intel corporation, Yossi Tsfati of Rishon Le Zion (IL) for intel corporation, Nir Weisman of Hod Hasharon (IL) for intel corporation, Shuhei Yamada of Hillsboro OR (US) for intel corporation, Ana M. Yepes of Portland OR (US) for intel corporation, Duncan Kitchin of Beaverton OR (US) for intel corporation
IPC Code(s): H01Q9/04, H01Q1/24, H01Q1/38, H01Q1/48, H01Q3/24, H01Q5/47, H01Q21/24, H03L7/14, H04B1/3827, H04B7/0456, H04B7/06, H04B15/04
CPC Code(s): H01Q9/0414
Abstract: millimeter wave (mmwave) technology, apparatuses, and methods that relate to transceivers, receivers, and antenna structures for wireless communications are described. the various aspects include co-located millimeter wave (mmwave) and near-field communication (nfc) antennas, scalable phased array radio transceiver architecture (sparta), phased array distributed communication system with mimo support and phase noise synchronization over a single coax cable, communicating rf signals over cable (rfoc) in a distributed phased array communication system, clock noise leakage reduction, if-to-rf companion chip for backwards and forwards compatibility and modularity, on-package matching networks, 5g scalable receiver (rx) architecture, among others.
Inventor(s): Junyuan WANG of Shanghai (CN) for intel corporation, Kapil SOOD of Washougal WA (US) for intel corporation, Brian WILL of Phoenix AZ (US) for intel corporation, Thomas Joseph O'DWYER of Cashel (IE) for intel corporation, Zijuan FAN of Shanghai (CN) for intel corporation, Kaijie GUO of Shanghai (CN) for intel corporation, Maksim LUKOSHKOV of Clarecastle (IE) for intel corporation, Seosamh O'RIORDAIN of Ennis (IE) for intel corporation, Jun XU of Shanghai (CN) for intel corporation, Guodong ZHU of Shanghai (CN) for intel corporation, Siming WAN of Shanghai (CN) for intel corporation
IPC Code(s): H04L9/30
CPC Code(s): H04L9/3066
Abstract: methods and apparatus for customers key protection for cloud native deployments. compute resources for a compute platform comprising platform hardware including one or more processors are allocated to one or more customers that use the compute resources to execute applications and/or services used to perform customer workloads. the compute platform includes a per-part device key that is used to generate hardware protected key used by the applications and services. mechanisms are provided to ensure hardware protected keys can only be accessed by associated customers and/or customer applications and services, while preventing other customers and/or applications and services from accessing the hardware protected keys. the hardware protected keys include keys employing various forms of rsa and ecc wrapped private keys (wpks) including rsa wpks, rsa chinese remainder theorem crt wpk and ecc wpks.
Inventor(s): Yizhi YAO of Chandler AZ (US) for intel corporation, Joey CHOU of Santa Clara CA (US) for intel corporation
IPC Code(s): H04L12/14, H04L41/0823, H04L43/0876
CPC Code(s): H04L12/1407
Abstract: various embodiments herein relate to a logical element configured to consume a management service (mns). the logical element may further identify, based on consumption of the mns, a performance measurement related to usage of an edge enabling infrastructure resource for an edge application server (eas); generate, based on the performance measurement, charging data related to the edge enabling infrastructure; and transmit an indication of the charging data to a second logical clement of the cellular system. the logical element may further identify, based on the transmitted indication of the charging data, a charging data response received from the second logical element. other embodiments may be described and/or claimed.
Inventor(s): Bruce MCLOUGHLIN of Saratoga CA (US) for intel corporation
IPC Code(s): H04L25/03, G06F13/42, H04B10/073, H04B10/077, H04B10/40
CPC Code(s): H04L25/03878
Abstract: examples described herein relate to link training between network connected devices. in some examples, an amount to extend link training is determined. the amount to extend link training can be determined by: receiving, by a receiver in a first device, signals over a lane from a transmitter in a second device, the signals indicating capability to extend link training time and amount to extend link training time; determining, at the first device, a link training time based on a default link training time and an amount to extend link training time; and performing link training based on the determined link training time. in some examples, the determined amount is highest common denominator of the received identified capability and transmitted indicated capability.
Inventor(s): Yu Xia of Beijing (CN) for intel corporation, Fuwen Li of Beijing (CN) for intel corporation, Wei Gao of Beijing (CN) for intel corporation
IPC Code(s): H04N9/73, G06T5/50, G06T7/11, H04N5/52
CPC Code(s): H04N9/73
Abstract: a method, system, and article provide unified automatic white balancing for multi-image processing.
Inventor(s): Ying Luo of Shanghai (CN) for intel corporation, Hua Zhang of Shanghai (CN) for intel corporation, Xiaomin Chen of Shanghai (CN) for intel corporation, Xin Kang of Shanghai (CN) for intel corporation
IPC Code(s): H04N13/117, H04N13/194, H04N13/332, H04N13/366, H04N21/81
CPC Code(s): H04N13/117
Abstract: techniques related to viewport selection in immersive video contexts are discussed. such techniques include generating multiple viewport predictions each for a future time interval and based on different prediction models, ranking the viewport predictions using error descriptors of the prediction models, selecting a viewport prediction for the future time intervals using the ranking, and correcting the selected viewport predictions using the error descriptors.
Inventor(s): Chandrasekaran Sakthivel of Cupertino CA (US) for intel corporation, Jerome Anand of Bengaluru (IN) for intel corporation, Srikanth Potluri of Folsom CA (US) for intel corporation, Michael Daniel Rosenzweig of Queen Creek AZ (US) for intel corporation, Passant V. Karunaratne of Chandler AZ (US) for intel corporation, Chia-Hung Sophia Kuo of Folsom CA (US) for intel corporation
IPC Code(s): H04N19/132, H04N19/164, H04N19/172, H04N19/50, H04N19/895
CPC Code(s): H04N19/132
Abstract: systems, apparatus, articles of manufacture, and methods to implement predictive video decoding and rendering based on artificial intelligence are disclosed. example apparatus disclosed herein are to predict that rendering of a video frame of a media stream will be unsynchronized with rendering of corresponding audio data of the media stream. disclosed example apparatus are also to generate a synthetic frame based on a machine learning model to replace the video frame. disclosed example apparatus are further to cause the synthetic frame to be rendered with the corresponding audio data.
Inventor(s): Hector Cordourier Maruri of Guadalajara (MX) for intel corporation, Jesus Ferrer Romero of Guadalajara (MX) for intel corporation, Willem Beltman of West Linn OR (US) for intel corporation, Georg Stemmer of Munich (DE) for intel corporation
IPC Code(s): H04S7/00, G10L19/008, G10L19/02, G10L25/30, H04S3/00
CPC Code(s): H04S7/304
Abstract: techniques are provided herein for providing binaural sound signals that are virtually rotated to match head rotation, such that audio output to headphones is perceived to maintain its location relative to user when a user turns their head. in particular, techniques are presented to extract spherical location information already embedded in binaural signals to generate binaural sound signals that change to match head rotation. a deep-learning based audio regression method can use a 2-channel binaural audio signal and a rotation angle as input, and generate a new binaural audio output signal with the rotated environment corresponding to the rotation angle. the deep-learning based audio regression method can be implemented as a neural network, and can include deep learning operations, such as convolution, pooling, elementwise operation, linear operation, and nonlinear operation. a deep learning operation may be performed on internal parameters of the dnns and one or more activations.
Inventor(s): Guotong WANG of Santa Clara CA (US) for intel corporation, Alexei DAVYDOV of Santa Clara CA (US) for intel corporation, Dong HAN of Santa Clara CA (US) for intel corporation, Bishwarup MONDAL of San Ramon CA (US) for intel corporation, Avik SENGUPTA of San Jose CA (US) for intel corporation
IPC Code(s): H04W72/044
CPC Code(s): H04W72/044
Abstract: systems, apparatuses, methods, and computer-readable media are provided for simultaneous uplink transmission from a user equipment (ue) using multiple antenna panels and/or targeting multiple transmission-reception points (trps). for example, techniques for codebook-based and/or non-codebook based transmission from multiple antenna panels are described. embodiments further include techniques for codebook subset configuration. furthermore, embodiments include techniques for power control and/or power sharing for transmissions from a ue to multiple trps. other embodiments may be described or claimed.
Inventor(s): Smit Kapila of Bangalore (IN) for intel corporation, Jeff Ku of Taipei (TW) for intel corporation, Min Suet Lim of Penang (MY) for intel corporation, Sarma Vmk Vedhanabhatla of Bengaluru (IN) for intel corporation
IPC Code(s): H05K5/02
CPC Code(s): H05K5/0213
Abstract: techniques are described to dynamically adjust the open air ratio (oar) while ensuring compliance with regulatory requirements. an adjustable thermal vent assembly is described that dynamically adjusts the oar for inlet/outlet vents depending on the current use case. the adjustable thermal vent assembly functions to increase the grating spacing only when a triggering condition is met that ensures that a corresponding thermal vent location is inaccessible. such temporarily inaccessible regions may include the bottom cover of an electronic device when positioned on the surface of an object, for thermal intake vents, or the rear portion of an electronic device when the display cover exceeds a predetermined angle, for thermal exhaust vents.
Inventor(s): Prabhakar SUBRAHMANYAM of San Jose CA (US) for intel corporation, Pooya TADAYON of Portland OR (US) for intel corporation, Yi XIA of Campbell CA (US) for intel corporation, Ying-Feng PANG of San Jose CA (US) for intel corporation, Mark BIANCO of Mountain View CA (US) for intel corporation
IPC Code(s): H05K7/20
CPC Code(s): H05K7/20809
Abstract: an apparatus is described. the apparatus includes a chip package cooling assembly chamber having one or more features to receive one or more heat pipes that receive heat generated by one or more semiconductor devices that reside outside the chip package. in detail, the heat pipes that are thermally coupled to the vr fet heat sinks are attached to the outside of the cold plate (again, they can be screwed to the cold plate with a thermal interface material between them). thus, heat generated by the vr fets is transferred to the vr fet heatsinks and the chip package cold plate via the heat pipes. the heat is then transferred to the fluid while it runs through the cold plate and is removed from the system by the fluid as it exits the outlet.
- Intel Corporation
- G03F1/60
- G03F1/54
- CPC G03F1/60
- Intel corporation
- G03F7/20
- G03F7/00
- H01L21/027
- CPC G03F7/2022
- G06F1/20
- H05K7/20
- CPC G06F1/206
- G06F1/28
- G06F1/3206
- CPC G06F1/28
- G06F3/06
- CPC G06F3/0613
- G06N3/08
- CPC G06F3/0622
- G06F3/16
- H04R1/10
- CPC G06F3/165
- G06F7/483
- G06F1/03
- G06F7/487
- G06F7/498
- G06F7/544
- CPC G06F7/483
- G06F9/30
- G06F7/499
- G06F9/38
- CPC G06F9/30036
- G06F9/4401
- CPC G06F9/4411
- G06F9/50
- G06F7/06
- G06F8/65
- G06F8/654
- G06F8/656
- G06F8/658
- G06F9/455
- G06F9/48
- G06F9/54
- G06F11/07
- G06F11/30
- G06F11/34
- G06F12/02
- G06F12/06
- G06F13/16
- G06F16/174
- G06F21/57
- G06F21/62
- G06F21/73
- G06F21/76
- G06T1/20
- G06T1/60
- G06T9/00
- H01R13/453
- H01R13/631
- H03K19/173
- H03M7/30
- H03M7/40
- H03M7/42
- H04L9/08
- H04L12/28
- H04L12/46
- H04L41/044
- H04L41/0816
- H04L41/0853
- H04L41/12
- H04L43/04
- H04L43/06
- H04L43/08
- H04L43/0894
- H04L47/20
- H04L47/2441
- H04L49/104
- H04L61/5007
- H04L67/10
- H04L67/1014
- H04L67/63
- H04L67/75
- H05K7/14
- G06F11/14
- G06F15/80
- G06F16/28
- H04L9/40
- H04L41/046
- H04L41/0896
- H04L41/142
- H04L47/78
- H04Q11/00
- CPC G06F9/505
- CPC G06F9/544
- CPC G06F11/073
- G06F11/20
- CPC G06F11/2094
- G06F12/0862
- CPC G06F12/0862
- G06F13/10
- G06F3/14
- G06F3/147
- CPC G06F13/10
- G06F13/42
- CPC G06F13/1668
- H04L49/356
- H04L49/901
- CPC G06F13/1673
- G06F13/28
- CPC G06F13/28
- CPC G06F15/80
- G06T5/70
- G06V10/56
- G06V40/16
- CPC G06F21/6254
- G06N3/067
- CPC G06N3/067
- G06N20/00
- H04L9/32
- CPC G06N20/00
- G06Q20/40
- CPC G06Q20/4014
- G06V10/25
- G06T7/246
- G06T7/292
- G06V10/82
- G06V20/40
- CPC G06V10/25
- G09G5/00
- CPC G09G5/006
- G11C5/04
- H05K1/14
- H05K1/18
- CPC G11C5/04
- H01L23/498
- H01L21/768
- H01L27/088
- H05K1/11
- H05K3/00
- H05K3/40
- CPC H01L23/49827
- H01L23/538
- H01L23/00
- H01L23/522
- CPC H01L23/538
- H01L21/48
- H01L25/065
- CPC H01L24/14
- C25D3/38
- C25D5/02
- C25D7/12
- CPC H01L25/0655
- H01L29/78
- H01L29/49
- H01L21/02
- CPC H01L29/7855
- H01L21/8234
- H01L29/06
- H01L29/08
- H01L29/423
- CPC H01L29/7856
- H01Q9/04
- H01Q1/24
- H01Q1/38
- H01Q1/48
- H01Q3/24
- H01Q5/47
- H01Q21/24
- H03L7/14
- H04B1/3827
- H04B7/0456
- H04B7/06
- H04B15/04
- CPC H01Q9/0414
- H04L9/30
- CPC H04L9/3066
- H04L12/14
- H04L41/0823
- H04L43/0876
- CPC H04L12/1407
- H04L25/03
- H04B10/073
- H04B10/077
- H04B10/40
- CPC H04L25/03878
- H04N9/73
- G06T5/50
- G06T7/11
- H04N5/52
- CPC H04N9/73
- H04N13/117
- H04N13/194
- H04N13/332
- H04N13/366
- H04N21/81
- CPC H04N13/117
- H04N19/132
- H04N19/164
- H04N19/172
- H04N19/50
- H04N19/895
- CPC H04N19/132
- H04S7/00
- G10L19/008
- G10L19/02
- G10L25/30
- H04S3/00
- CPC H04S7/304
- H04W72/044
- CPC H04W72/044
- H05K5/02
- CPC H05K5/0213
- CPC H05K7/20809
