Intel Corporation patent applications on July 11th, 2024
Patent Applications by Intel Corporation on July 11th, 2024
Intel Corporation: 73 patent applications
Intel Corporation has applied for patents in the areas of H04L5/00 (6), H04W72/232 (5), G06F9/48 (4), G06F3/01 (4), G06T1/60 (4) H04L5/0051 (3), G06F1/206 (2), G01D5/353 (1), H04L45/124 (1), H04L41/5003 (1)
With keywords such as: data, device, based, apparatus, embodiments, circuitry, memory, processing, user, and herein in patent application abstracts.
Patent Applications by Intel Corporation
Inventor(s): Ngoc Duy VU of Ho Chi Minh (VN) for intel corporation, Nguyen Hoang Tan LE of Ho Chi Minh (VN) for intel corporation, Minh Anh Khoa NGUYEN of Bien Hoa (VN) for intel corporation
IPC Code(s): G01D5/353, B65B11/52, B65B57/02
CPC Code(s): G01D5/353
Abstract: the disclosure is directed to apparatus and methods for detection of out of position (oop) components in a carrier tape forming machine. an apparatus includes cross track sensors coupled to the bus interface circuitry, the cross track sensors configured to detect oop components prior to overlaying the components on the carrier tape with cover tape, optical sensors to detect the oop components on the carrier tape after overlaying with cover tape and prior to sealing and to detect reflections from oop components seated on the carrier tape, an amplifier coupled to the optical sensors to amplify signals generated by the optical sensors and set a range for determining whether the components are oop, and relays to receive indications of detected oop components, and a controller coupled to the relays to stop the carrier tape forming machine as a function of signals received by the relays.
20240230516. WAFER-LEVEL BOND STRENGTH MEASUREMENT_simplified_abstract_(intel corporation)
Inventor(s): Khaled AHMED of San Jose CA (US) for intel corporation
IPC Code(s): G01N19/04
CPC Code(s): G01N19/04
Abstract: this disclosure describes systems, methods, and devices related to bond strength measurement. a device may comprise a first portion of a plate connected to a movement mechanism, a second portion of the plate comprising a sticky probe and a third portion of the plate comprising a mirror with a reflective side pointing outwards. the device may further comprise an optical fiber sensor assembly comprising an optical fiber bundle for sending light through a first optical fiber and receiving light reflected from the mirror through a second optical fiber.
Inventor(s): Chia How Low of Simpang Ampat (MY) for intel corporation, Roger Cheng of Campbell CA (US) for intel corporation
IPC Code(s): G01R19/10
CPC Code(s): G01R19/10
Abstract: embodiments herein relate to a circuit for evaluating the ground voltage of each circuit partition of a number of circuit partitions, one partition at a time. once the ground voltage is determined, a corresponding code is stored to control a leakage circuit coupled to the ground node. the leakage circuit provides a leakage current based on the code to offset the ground voltage to a target voltage, which may be common for each of the partitions. the circuit can include a voltage source which supplies a stair step increasing voltage to a comparator. the comparator compares the voltage of the voltage source to the ground node voltage and provides an output which changes when the two input voltages are approximately equal, within a tolerance. the circuit may include a finite state machine for managing the process.
Inventor(s): Timothy C. Johnston of Sacramento CA (US) for intel corporation, Seongtae Jeong of Portland OR (US) for intel corporation, Talha Khan of HIllsboro OR (US) for intel corporation, Anjan Raghunathan of Portland OR (US) for intel corporation
IPC Code(s): G03F1/36
CPC Code(s): G03F1/36
Abstract: this disclosure describes systems, methods, and devices related to optical proximity corrections to an integrated circuit photomask. a method may include identifying a first contour of a first adjacent polygon of a photomask predicted for a first polygon of an integrated circuit, the first contour excluding a first corner formed by a first edge and a second edge of the first polygon; identifying a second contour of a second adjacent polygon of a photomask predicted for a second polygon of the integrated circuit, the second contour excluding a second corner formed by a third edge and a fourth edge of the second polygon; generating a fast contour prediction based on corner rounding associated with the first contour and the second contour; and generating, based on the fast contour prediction, a minimum distance between the first contour and the second contour, the minimum distance associated with the optical proximity corrections.
Inventor(s): TOMER RIDER of Naahryia (IL) for intel corporation, RAMON C. OLMO of Hillsboro OR (US) for intel corporation, DOR LEVY of Jerusalem (IL) for intel corporation, SHAHAR TAITE of Kfar Saba (IL) for intel corporation
IPC Code(s): G06F1/16
CPC Code(s): G06F1/1652
Abstract: a mechanism is described for facilitating dynamic detection and intelligent use of segmentation on flexible display screens according to one embodiment. a method of embodiments, as described herein, includes detecting, via one or more touch sensors, alterations in current in and around one or more areas of a flexible display screen, where the alterations represent pressure being applied to cause at least one of bending, rolling, and curving of the flexible display screen at the one or more areas. the method may further include dividing the flexible display screen into a plurality of zones corresponding to the one or more areas, where the marking/dividing logic is further to mark a plurality of portions of the plurality of zones to serve as a plurality of segments. the method may further include facilitating displaying of contents via the plurality of segments of the flexible display screen.
Inventor(s): Columbia Mishra of Hillsboro OR (US) for intel corporation, Carin Ruiz of Portland OR (US) for intel corporation, Helin Cao of Portland OR (US) for intel corporation, Soethiha Soe of Beaverton OR (US) for intel corporation, James Hermerding, II of Vancouver WA (US) for intel corporation, Bijendra Singh of Bangalore (IN) for intel corporation, Navneet Singh of Bangalore (IN) for intel corporation
IPC Code(s): G06F1/20, G06F1/32, G06F3/01, G06V10/774, G06V40/10, G06V40/16, G10L25/51, H04B1/3827
CPC Code(s): G06F1/206
Abstract: apparatus and methods for thermal management of electronic user devices are disclosed herein. an example apparatus includes at least one of a user presence detection analyzer to identify a presence of a user relative to an electronic device based on first sensor data generated by a first sensor or at least one of an image data analyzer or a motion data analyzer to determine a gesture of the user relative to the device based on second sensor data generated by a second sensor; a thermal constraint selector to select a thermal constraint for a temperature of an exterior surface of the electronic device based on one or more of the presence of the user or the gesture; and a power source manager to adjust a power level for a processor of the electronic device based on the thermal constraint.
Inventor(s): Manish SHARMA of Bangalore (IN) for intel corporation, Vikas MISHRA of Chandler AZ (US) for intel corporation, Richard Marian THOMAIYAR of Trichy (IN) for intel corporation, Vikram BODIREDDY of Keelpudur (IN) for intel corporation, Ashraf JAVEED of Bangalore (IN) for intel corporation, Satish MUTHIYALU of Bangalore (IN) for intel corporation
IPC Code(s): G06F1/20
CPC Code(s): G06F1/206
Abstract: apparatus and methods for implementing an adaptive dynamic temperature range (dtr) control mechanism to extend dynamic temperature range. a dtr control manager is provided to initiate retrain/recalibrate high-speed io (input-output) links without link reset and extend the dynamic temperature range to the entire operating range based on thermal and other conditions. the dtr control manager ensures optimized retraining/recalibration of the link, which is based on system level parameters (like ambient temperature, fan speed, thermal zone of the devices etc.) and other environmental conditions. in some embodiments the mechanism or algorithm of the dtr control manager can be implemented in a bmc (baseboard management controller) or the like and hence enables the adaptive dtr solution in an operating system (os) agnostic and seamless manner.
Inventor(s): Yoav Babajani of Rishon Le Zion (IL) for intel corporation, Hisham Abu Salah of Santa Clara CA (US) for intel corporation, Nadav Shulman of Tel Mond (IL) for intel corporation, Nir Misgav of Ein Hahoresh (IL) for intel corporation, Arik Gihon of Rishon Le Zion (IL) for intel corporation
IPC Code(s): G06F1/324, G06F1/3206
CPC Code(s): G06F1/324
Abstract: embodiments herein relate to a technique to be performed by a power control unit (pcu) of an electronic device. specifically, the pcu may identify, based on a metric related to an activity level of a processor core of a multi-core processor of the electronic device, first, second, and third weights that are respectively related to first, second, and third cores of the multi-core processor. based on these weights, the pcu may identify a number of active processor cores of the multi-core processor, and alter a frequency limit of the multi-core processor accordingly. other embodiments may be described and claimed.
Inventor(s): Efraim ROTEM of Santa Clara CA (US) for intel corporation, Eliezer WEISSMANN of Haifa (IL) for intel corporation, Doron RAJWAN of Rishon Lezion (IL) for intel corporation, Yoni AIZIK of Haifa (IL) for intel corporation, Esfir NATANZON of Haifa (IL) for intel corporation, Nir ROSENZWEIG of Givat Ella (IL) for intel corporation, Nadav SHULMAN of Tel Mond (IL) for intel corporation, Bart PLACKLE of Diest (BE) for intel corporation
IPC Code(s): G06F1/329, G06F9/48
CPC Code(s): G06F1/329
Abstract: embodiments include apparatuses, methods, and systems including a power control unit to control different power consumptions by one or more processors to operate different applications. the power control unit may receive power information that may include a priority information for each application to be operated on the one or more processors, determine to control, based on the power information for different applications, different power consumptions by the one or more processors to operate the different applications. other embodiments may also be described and claimed.
20240231473. ADAPTIVE VOLTAGE SHUTDOWN DEMOTION_simplified_abstract_(intel corporation)
Inventor(s): Patrick Kam-shing Leung of Portland OR (US) for intel corporation, Akshay Parnami of San Bruno CA (US) for intel corporation, Jianwei Dai of Portland OR (US) for intel corporation, Saranya Sridaran Iyengar of Portland OR (US) for intel corporation, Michael F. Mallen of Portland OR (US) for intel corporation
IPC Code(s): G06F1/3296, G06F1/3287
CPC Code(s): G06F1/3296
Abstract: embodiments described herein may include apparatus, systems, techniques, and/or processes that are directed to adaptively determining an optimum time frame or demotion threshold for when to power down a voltage rail of an idle device. the demotion threshold is typically the point where the energy cost for maintaining power to the device is approximately the same as or exceeds the energy cost of removing power to the device. the demotion threshold may vary with system conditions and may be based on device leakage current, wake voltage, capacitance, voltage regulator power consumption, current workload and the like. a power control unit in the computing system may manage the voltage of the device and determine the optimum demotion threshold. the power control unit may rely on physical inputs such as fuses on a motherboard, system inputs supplied by a manufacturer, current condition inputs and may be implemented in the device's or the system's software or firmware. by calculating the adaptive demotion threshold, power may be optimized based on platform-to-platform design variation and/or device part-to-part variation.
Inventor(s): Ravindra A. Babu of Bangalore (IN) for intel corporation, Sashank Ms of Bangalore (IN) for intel corporation, Satyanantha R. Musunuri of Bangalore (IN) for intel corporation, Sagar C. Pawar of Bangalore (IN) for intel corporation, Kalyan K. Kaipa of Bangalore (IN) for intel corporation, Vijayakumar Balakrishnan of Bangalore (IN) for intel corporation, Sameer Kp of Bangalore (IN) for intel corporation
IPC Code(s): G06F3/01, G02B27/01, G06T1/20
CPC Code(s): G06F3/012
Abstract: when the speed of head movement exceeds the processing capability of the system, a reduced depiction is displayed. as one example, the resolution may be reduced using coarse pixel shading in order to create a new depiction at the speed of head movement. in accordance with another embodiment, only the region the user is looking at is processed in full resolution and the remainder of the depiction is processed at lower resolution. in still another embodiment, the background depictions may be blurred or grayed out to reduce processing time.
Inventor(s): He XU of Beijing (CN) for intel corporation
IPC Code(s): G06F3/01, G06V10/25, G06V10/44
CPC Code(s): G06F3/013
Abstract: a method and apparatus for unlocking a device or an application on the device based on gaze tracking. an image randomly selected from a set of images. each image in the set of images includes a plurality of feature points and a sequence of feature points is pre-defined for each image. the selected image is presented to a user. a trajectory of gaze points of the user on the selected image presented to the user is determined. it is then determined whether the trajectory of gaze points of the user matches the pre-defined sequence of feature points on the selected image. the device or the application on the device is unlocked if the trajectory of gaze points of the user matches the pre-defined sequence of feature points on the selected image.
Inventor(s): Vinod Govindapillai of Tampere (FI) for intel corporation, Tomer Rider of Naahriya (IL) for intel corporation
IPC Code(s): G06F3/01, G06F1/16, G06F3/04817, G06F3/0482, G06F3/0485
CPC Code(s): G06F3/017
Abstract: computing devices, computer-readable storage media, and methods associated with human computer interaction. in embodiments, a computing device may include a display, a processor coupled with the display, a user interface engine and one or more applications to be operated on the processor. in embodiments, the user interface engine or the one or more applications may be configured to detect movement of the portable computing device indicating a direction a user of the portable computing device would like a portion of the user interface to move and cause the portion of the user interface to be moved, from a current location on the display to another location on the display, in accordance with the indicated direction. such movement may facilitate the user to interact with the portion of the user interface via the interaction zone of the display. other embodiments may be described and/or claimed.
Inventor(s): Joydeep Ray of Folsom CA (US) for intel corporation, Michael Apodaca of El Dorado Hills CA (US) for intel corporation, Yoav Harel of Carmichael CA (US) for intel corporation, Guei-Yuan Lueh of San Jose CA (US) for intel corporation, John A. Wiegert of Aloha OR (US) for intel corporation
IPC Code(s): G06F3/06, G06T1/60
CPC Code(s): G06F3/061
Abstract: embodiments described herein provide a technique to enable access to entries in a surface state or sampler state using 64-bit virtual addresses. one embodiment provides a graphics core that includes memory access circuitry configured to facilitate access to the memory by functional units of the graphics core. the memory access circuitry is configured to receive a message to access an entry in a surface state or a sampler state associated with a parallel processing operation. the message specifies a base address for a surface state entry or sampler state entry. the circuitry can add the base address and the offset to determine a 64-bit virtual address for the entry in the surface state entry or the sampler state and submit a memory access request to the memory to access the entry of the surface state or sampler state.
Inventor(s): Subrata BANIK of Bangalore (IN) for intel corporation, Rajesh POORNACHANDRAN of Portland OR (US) for intel corporation, Vincent ZIMMER of Issaquah WA (US) for intel corporation, Utkarsh Y. KAKAIYA of El Dorado Hills CA (US) for intel corporation
IPC Code(s): G06F8/65, G06F1/3212
CPC Code(s): G06F8/65
Abstract: the technology disclosed herein includes getting a system update configuration for managing updating of at least one of a software component and a firmware component of a computing system powered by a battery; determining an estimated system update time of usage of the battery to update the at least one of the software component and the firmware component based at least in part on the system update configuration; updating the at least one of the software component and the firmware component when resource requirements of the system update configuration are met and the estimated system update time is less than or equal to a minimum remaining time of usage of the battery; and deferring the updating when the resource requirements of the system update configuration are not met or the estimated system update time is greater than the minimum remaining time of usage of the battery.
Inventor(s): Arnab Raha of San Jose CA (US) for intel corporation, Deepak Mathaikutty of Chandler AZ (US) for intel corporation, Debabrata Mohapatra of San Jose CA (US) for intel corporation, Sang Kyun Kim of San Jose CA (US) for intel corporation, Gautham Chinya of Sunnyvale CA (US) for intel corporation, Cormac Brick of San Francisco CA (US) for intel corporation
IPC Code(s): G06F9/445, G06F9/30, G06F9/50, G06N20/00, H03K19/177, H03K19/20
CPC Code(s): G06F9/445
Abstract: methods, apparatus, systems, and articles of manufacture to load data into an accelerator are disclosed. an example apparatus includes data provider circuitry to load a first section and an additional amount of compressed machine learning parameter data into a processor engine. processor engine circuitry executes a machine learning operation using the first section of compressed machine learning parameter data. a compressed local data re-user circuitry determines if a second section is present in the additional amount of compressed machine learning parameter data. the processor engine circuitry executes a machine learning operation using the second section when the second section is present in the additional amount of compressed machine learning parameter data.
Inventor(s): Li Xu of Shanghai 31 (CN) for intel corporation, Haihao Xiang of Shanghai (CN) for intel corporation, Feng Chen of Shanghai 31 (CN) for intel corporation, Travis Schluessler of Berthoud CO (US) for intel corporation, Yuheng Zhang of Shanghai (CN) for intel corporation, Sen Lin of Beijing (CN) for intel corporation
IPC Code(s): G06F9/448, G06F16/215, G06T1/20, G06T1/60
CPC Code(s): G06F9/4488
Abstract: embodiments are generally directed to a system and method for adapting executable object to a processing unit. an embodiment of a method to adapt an executable object from a first processing unit to a second processing unit, comprises: adapting the executable object optimized for the first processing unit of a first architecture, to the second processing unit of a second architecture, wherein the second architecture is different from the first architecture, wherein the executable object is adapted to perform on the second processing unit based on a plurality of performance metrics collected while the executable object is performed on the first processing unit and the second processing unit.
20240231893. AI-ASSISTED CONTEXT-AWARE PIPELINE CREATION_simplified_abstract_(intel corporation)
Inventor(s): Richard Chuang of Chandler AZ (US) for intel corporation, Yu Zhang of Beijing (CN) for intel corporation
IPC Code(s): G06F9/48, G06F40/284
CPC Code(s): G06F9/485
Abstract: ai-assisted pipeline copilot techniques are described herein. in one example, a workflow method using an ai-assisted pipeline copilot involves receiving pipeline information from a user for an artificial intelligence (ai) pipeline and identifying key words in the pipeline information. a recommended next task component to add to the ai pipeline is then determined using a neural network model based on: a mapping of the key words to ai pipeline stages and one or more previous task components added to the ai pipeline. connections between the recommended next task and the existing pipeline can also be inferred with a second neural network model. the recommended next task components and connections can then be provided to the user (e.g., with a graphical user interface).
20240231957. NAMED AND CLUSTER BARRIERS_simplified_abstract_(intel corporation)
Inventor(s): Fangwen Fu of Folsom CA (US) for intel corporation, Chunhui Mei of San Diego CA (US) for intel corporation, John A. Wiegert of Aloha OR (US) for intel corporation, Yongsheng Liu of San Diego CA (US) for intel corporation, Ben J. Ashbaugh of Folsom CA (US) for intel corporation
IPC Code(s): G06F9/52, G06F9/48
CPC Code(s): G06F9/522
Abstract: embodiments described herein provide a technique to facilitate the synchronization of workgroups executed on multiple graphics cores of a graphics core cluster. one embodiment provides a graphics core including a cache memory and a graphics core coupled with the cache memory. the graphics core includes execution resources to execute an instruction via a plurality of hardware threads and barrier circuitry to synchronize execution of the plurality of hardware threads, wherein the barrier circuitry is configured to provide a plurality of re-usable named barriers.
20240232056. A Concept for Generating a Test Specification_simplified_abstract_(intel corporation)
Inventor(s): Junjun SHAN of Shanghai (CN) for intel corporation, Yi QIAN of Shanghai (CN) for intel corporation, Xiangyang WU of Shanghai (CN) for intel corporation, Qian OUYANG of Shanghai (CN) for intel corporation, Minggui CAO of Shanghai (CN) for intel corporation, Junjie MAO of Shanghai (CN) for intel corporation, Jian Jun CHEN of Shanghai (CN) for intel corporation
IPC Code(s): G06F11/36
CPC Code(s): G06F11/3676
Abstract: examples relate to an apparatus, a device, a method, and a computer program for generating a test specification for testing software code of a function under test. the apparatus for generating the test specification for testing software code of a function under test comprises circuitry configured to extract a plurality of symbols from the software code of the function under test, generate a plurality of test vectors with corresponding sets of expected results for the function under test based on the plurality of symbols, and generate a test specification based on the plurality of test vectors and the corresponding sets of expected results.
Inventor(s): John A. Wiegert of Aloha OR (US) for intel corporation, Joydeep Ray of Folsom CA (US) for intel corporation, Vasanth Ranganathan of El Dorado Hills CA (US) for intel corporation, Biju George of Folsom CA (US) for intel corporation, Fangwen Fu of Folsom CA (US) for intel corporation, Abhishek R. Appu of El Dorado Hills CA (US) for intel corporation, Chunhui Mei of San Diego CA (US) for intel corporation, Changwon Rhee of Rocklin CA (US) for intel corporation
IPC Code(s): G06F12/0855
CPC Code(s): G06F12/0857
Abstract: embodiments described herein provide a technique to facilitate the broadcast or multicast of asynchronous loads to shared local memory of a plurality of graphics cores within a graphics core cluster. one embodiment provides a graphics processor including a cache memory a graphics core cluster coupled with the cache memory. the graphics core cluster includes a plurality of graphics cores. the plurality of graphics cores includes a graphics core configured to receive a designation as a producer graphics core for a multicast load, read data from the cache memory; and transmit the data read from the cache memory to a consumer graphics core of the plurality of graphics cores.
20240232094. SECTOR CACHE FOR COMPRESSION_simplified_abstract_(intel corporation)
Inventor(s): Abhishek R. Appu of El Dorado Hills CA (US) for intel corporation, Altug Koker of El Dorado Hills CA (US) for intel corporation, Joydeep Ray of Folsom CA (US) for intel corporation, David Puffer of Tempe AZ (US) for intel corporation, Prasoonkumar Surti of Folsom CA (US) for intel corporation, Lakshminarayanan Striramassarma of El Dorado Hills CA (US) for intel corporation, Vasanth Ranganathan of El Dorado Hills CA (US) for intel corporation, Kiran C. Veernapu of Bangalore (IN) for intel corporation, Balaji Vembu of Folsom CA (US) for intel corporation, Pattabhiraman K of Bangalore (IN) for intel corporation
IPC Code(s): G06F12/0877, G06F12/0802, G06F12/0806, G06F12/0846, G06F12/0855, G06F12/0868, G06F12/0893, G06F12/126, G06T1/60
CPC Code(s): G06F12/0877
Abstract: one embodiment provides circuitry coupled with cache memory and a memory interface, the circuitry to compress compute data at multiple cache line granularity, and a processing resource coupled with the memory interface and the cache memory. the processing resource is configured to perform a general-purpose compute operation on compute data associated with multiple cache lines of the cache memory. the circuitry is configured to compress the compute data before a write of the compute data via the memory interface to the memory bus, in association with a read of the compute data associated with the multiple cache lines via the memory interface, decompress the compute data, and provide the decompressed compute data to the processing resource.
20240232096. HARDWARE ASSISTED MEMORY ACCESS TRACKING_simplified_abstract_(intel corporation)
Inventor(s): Sanjay Kumar of Hillsboro OR (US) for intel corporation, Phillip Lantz of Cornelius OR (US) for intel corporation, Rajesh Sankaran of Portland OR (US) for intel corporation, David Hansen of Portland OR (US) for intel corporation, Evgeny V. Voevodin of Portland OR (US) for intel corporation, Andrew Anderson of Forest Grove OR (US) for intel corporation, Lizhen You of Beijing (CN) for intel corporation, Xin Zhou of Beijing (CN) for intel corporation, Nikhil Talpallikar of Portland OR (US) for intel corporation
IPC Code(s): G06F12/1009
CPC Code(s): G06F12/1009
Abstract: an embodiment of an integrated circuit may comprise an array of hardware counters, and circuitry communicatively coupled to the array of hardware counters, the circuitry to count accesses to one or more selected pages of a memory with the array of hardware counters. other embodiments are disclosed and claimed.
20240232097. DATA TRANSFER ENCRYPTION MECHANISM_simplified_abstract_(intel corporation)
Inventor(s): Marcin Andrzej Chrapek of Zurich (CH) for intel corporation, Reshma Lal of Portland OR (US) for intel corporation
IPC Code(s): G06F12/1027, G06F12/0882, G06F12/14
CPC Code(s): G06F12/1027
Abstract: an apparatus comprising translator circuitry to receive a plurality of physical addresses of memory data, determine an offset associated with each of the physical page addresses and apply a tweak seed to each offset to generate a plurality of tweaks.
Inventor(s): Himanshu Kaul of Portland OR (US) for intel corporation, Mark A. Anders of Hillsboro OR (US) for intel corporation, Gregory K. Chen of Portland OR (US) for intel corporation
IPC Code(s): G06F13/40, H04L12/54, H04L49/10
CPC Code(s): G06F13/4022
Abstract: an apparatus includes a first port set that includes an input port and an output port. the apparatus further includes a plurality of second port sets. each of the second port sets includes an input port coupled to the output port of the first port set and an output port coupled to the input port of the first port set. the plurality of second port sets are to each communicate at a first maximum bandwidth and the first port set is to communicate at a second maximum bandwidth that is higher than the first maximum bandwidth.
20240232122. DISAGGREGATED DIE WITH INPUT/OUTPUT (I/O) TILES_simplified_abstract_(intel corporation)
Inventor(s): Andrew Paul Collins of Chandler AZ (US) for intel corporation, Mahesh Krishnappayya Kumashikar of Bangalore (IN) for intel corporation, Srikanth Nimmagadda of Bangalore (IN) for intel corporation
IPC Code(s): G06F13/42, G06F9/38, G06F13/40
CPC Code(s): G06F13/4221
Abstract: embodiments may relate to a microelectronic assembly including a substrate; a first die electrically coupled to the substrate, wherein the first die includes a first edge, a second edge, a third edge opposite the first edge, and a fourth edge opposite the second edge; and a second die electrically coupled to the substrate adjacent to the second edge of the first die and communicatively coupled to the first die, wherein the second die includes a fifth edge and a sixth edge opposite the fifth edge, and wherein the fifth edge of the second die is substantially aligned with the first edge of the first die and the sixth edge of the second die extends beyond the third edge of the first die, where the first die includes a processor die and the second die includes an input/output (i/o) die.
Inventor(s): Kunapareddy CHIRANJEEVI of Hyderabad (IN) for intel corporation, Sakina PITALWALA of Bangalore (IN) for intel corporation, Karthik VARADARAJAN RAJAGOPAL of Bangalore (IN) for intel corporation
IPC Code(s): G06F30/398, G06F30/27
CPC Code(s): G06F30/398
Abstract: this disclosure describes systems, methods, and devices related to using artificial intelligence to validate performance of integrated circuit features. a device may extract, from instruction files, microinstructions source and destination registers; generate a dependency graph including macroinstructions as nodes and dependencies between macroinstructions as edges between the nodes; generate, based on the dependency graph, a frequency distribution of instructions from trace files, performance univariate autoregressive conditionally heteroscedastic (perf uarch) stat files, and register transfer language (rtl) stat files, predictors for a machine learning model; generate, based on the perf uarch stat files and the rtl stat files, ratios of perf uarch stats to rtl stats as target stat ratios; generate, using the predictors and the machine learning model, predicted ratios of perf uarch stats to rtl stats; and generate, using greedy constrained optimization, based on the target stat ratios and the predicted ratios, recommended traces for debugging.
Inventor(s): Rajesh Poornachandran of Portland OR (US) for intel corporation, Kaushik Balasubramanian of Beaverton OR (US) for intel corporation, Karan Puttannaiah of Hillsboro OR (US) for intel corporation
IPC Code(s): G06F9/50, G06F9/38, G06F9/48
CPC Code(s): G06F9/505
Abstract: apparatus, articles of manufacture, and methods for managing processing units are disclosed. an example apparatus includes first processor circuitry to implement a central processing unit and second processor circuitry to perform at least one of first operations, second operations or third operations to obtain a resource request associated with a first workload; determine if a processing resource of a programmable network device is available to perform processing for the workload; determine if a second workload can be migrated from execution on the programmable network device; based on the determination that the second workload can be migrated, cause the second workload to be migrated; and cause the first workload to execute on the processing resource of the programmable network device.
Inventor(s): Shengze Wang of Santa Clara CA (US) for intel corporation, Alexey Supikov of Santa Clara CA (US) for intel corporation, Joshua Ratcliff of San Jose CA (US) for intel corporation, Ronald Azuma of San Jose CA (US) for intel corporation
IPC Code(s): G06T1/20, G06N3/08, G06N5/04, G06T7/00
CPC Code(s): G06T1/20
Abstract: described herein is a graphics processor comprising a system interconnect and a graphics processor cluster coupled with the system interconnect. the graphics processor cluster includes circuitry configurable to generate per-frame neural representations of a multi-view video via incremental training and transferal of weights.
Inventor(s): Scott JANUS of Loomis CA (US) for intel corporation, Prasoonkumar SURTI of Folsom CA (US) for intel corporation, Karthik VAIDYANATHAN of San Francisco CA (US) for intel corporation, Alexey SUPIKOV of San Jose CA (US) for intel corporation, Gabor LIKTOR of San Francisco CA (US) for intel corporation, Carsten BENTHIN of Voelklingen (DE) for intel corporation, Philip LAWS of Santa Clara CA (US) for intel corporation, Michael DOYLE of Santa Clara CA (US) for intel corporation
IPC Code(s): G06T15/06, G06T1/60, G06T15/00, G06T17/00
CPC Code(s): G06T15/06
Abstract: apparatus and method for a hierarchical beam tracer. for example, one embodiment of an apparatus comprises: a beam generator to generate beam data associated with a beam projected into a graphics scene; a bounding volume hierarchy (bvh) generator to generate bvh data comprising a plurality of hierarchically arranged bvh nodes; a hierarchical beam-based traversal unit to determine whether the beam intersects a current bvh node and, if so, to responsively subdivide the beam into n child beams to test against the current bvh node and/or to traverse further down the bvh hierarchy to select a new bvh node, wherein the hierarchical beam-based traversal unit is to iteratively subdivide successive intersecting child beams and/or to continue to traverse down the bvh hierarchy until a leaf node is reached with which at least one final child beam is determined to intersect; the hierarchical beam-based traversal unit to generate a plurality of rays within the final child beam; and intersection hardware logic to perform intersection testing for any rays intersecting the leaf node, the intersection testing to determine intersections between the rays intersecting the leaf node and primitives bounded by the leaf node.
Inventor(s): Brent E. INSKO of Portland OR (US) for intel corporation, Prasoonkumar SURTI of Folsom CA (US) for intel corporation
IPC Code(s): G06T15/40, G06T15/00, H04N13/279, H04N13/344, H04N13/383, H04N13/398
CPC Code(s): G06T15/405
Abstract: an apparatus and method are described for performing an early depth test on graphics data. for example, one embodiment of a graphics processing apparatus comprises: early depth test circuitry to perform an early depth test on blocks of pixels to determine whether all pixels in the block of pixels can be resolved by the early depth test; a plurality of execution circuits to execute pixel shading operations on the blocks of pixels; and a scheduler circuit to schedule the blocks of pixels for the pixel shading operations, the scheduler circuit to prioritize the blocks of pixels in accordance with the determination as to whether all pixels in the block of pixels can be resolved by the early depth test.
Inventor(s): Anthony Rhodes of Portland OR (US) for intel corporation
IPC Code(s): G06V20/40, G06V10/80, G06V10/82
CPC Code(s): G06V20/49
Abstract: systems, apparatus, articles of manufacture, and methods are disclosed to enhance action segmentation model with causal explanation capability. an example apparatus includes an interface circuitry to access a pre-trained action segmentation model, instructions, and processor circuitry to at least one of instantiate or execute the machine readable instructions to obtain action segmentation data from the pre-trained action segmentation model, the action segmentation data indicating action prediction for one or more frames of a video sequence, combine the obtained action segmentation data with input features extracted from the one or more video frames, and identify an antecedent action of at least one frame of the video sequence based on pooled importance scores for the frame, the pooled importance scores being calculated from the combined action segmentation data and input features.
Inventor(s): Frederik Pasch of Karlsruhe (DE) for intel corporation, Fabian Oboril of Karlsruhe (DE) for intel corporation, Cornelius Buerkle of Karlsruhe (DE) for intel corporation, Satish Chandra Jha of Portland OR (US) for intel corporation, Vesh Raj Sharma Banjade of Portland OR (US) for intel corporation, Kathiravetpillai Sivanesan of Portland OR (US) for intel corporation, Arvind Merwaday of Beaverton OR (US) for intel corporation, S M Iftekharul Alam of Hillsboro OR (US) for intel corporation, Ned M. Smith of Beaverton OR (US) for intel corporation, Kuilin Clark Chen of Portland OR (US) for intel corporation, Leanardo Gomes Baltar of Muenchen (DE) for intel corporation, Suman A. Sehra of Folsom CA (US) for intel corporation, Soo Jin Tan of Shanghai (CN) for intel corporation, Markus Dominik Mueck of Unterhaching (DE) for intel corporation
IPC Code(s): G08G1/07, G06V20/54, G06V40/20, G08G1/005, G08G1/16
CPC Code(s): G08G1/07
Abstract: systems and methods for dynamically controlling an infrastructure item are disclosed. the systems and methods may include receiving environmental data. the environmental data may capture behavior of a crossing user. an intent of the crossing user may be determined based on the environmental data. a setting of the infrastructure item may be changed based on the intent of the crossing user.
Inventor(s): S M Iftekharul Alam of Hillsboro OR (US) for intel corporation, Kuilin Clark Chen of Portland OR (US) for intel corporation, Leonardo Gomes Baltar of Muenchen (DE) for intel corporation, Satish Jha of Portland OR (US) for intel corporation, Arvind Merwaday of Beaverton OR (US) for intel corporation, Markus Dominik Mueck of Unterhaching (DE) for intel corporation, Suman Sehra of Folsom CA (US) for intel corporation, Vesh Raj Sharma Banjade of Portland OR (US) for intel corporation, Kathiravetpillai Sivanesan of Portland OR (US) for intel corporation, Soo Jin Tan of Shanghai (CN) for intel corporation
IPC Code(s): G08G1/0967, B60W60/00, H04W4/40, H04W4/90
CPC Code(s): G08G1/096725
Abstract: a component of an intelligent transportation infrastructure system, the component including: processing means; and a non-transitory computer-readable storage medium including instructions that, when executed by the processing means, cause the processing means to: receive, from a vehicle having autonomous driving capabilities, an autonomous driving disengagement request message; determine, based on perception data or analytics related to the vehicle or a vicinity of the vehicle, a disengagement level of a multiple-disengagement-level protocol and a corresponding post-disengagement vehicle action; and transmit to the vehicle an autonomous driving disengagement response message including a post-disengagement vehicle action instruction.
Inventor(s): Srinivas PIETAMBARAM of Chandler AZ (US) for intel corporation, Robert L. SANKMAN of Phoenix AZ (US) for intel corporation, Rahul MANEPALLI of Chandler AZ (US) for intel corporation, Gang DUAN of Chandler AZ (US) for intel corporation, Debendra MALLIK of Chandler AZ (US) for intel corporation
IPC Code(s): H01L23/15, H01L23/31, H01L23/495, H01L23/498, H01L23/538
CPC Code(s): H01L23/15
Abstract: embodiments disclosed herein include electronic packages and methods of forming such packages. in an embodiment, the electronic package comprises a glass substrate, with a plurality of first pads on a first surface of the glass substrate, a plurality of second pads on a second surface of the glass substrate that is opposite from the first surface, a plurality of through glass vias (tgvs), wherein each tgv electrically couples a first pad to a second pad, wherein the plurality of first pads have a first pitch, and wherein the plurality of second pads have a second pitch that is greater than the first pitch, a bridge substrate over the glass substrate, a first die electrically coupled to first pads and the bridge substrate, and a second die electrically coupled to first pads and the bridge substrate, wherein the bridge substrate electrically couples the first die to the second die.
Inventor(s): Min Suet Lim of Gelugor (MY) for intel corporation, Telesphor Kamgaing of Chandler AZ (US) for intel corporation, Ilan Ronen of Hadera (IL) for intel corporation, Kavitha Nagarajan of Bangalore KA (IN) for intel corporation, Chee Kheong Yoon of Beyan Lepas (MY) for intel corporation, Chu Aun Lim of Hillsboro OR (US) for intel corporation, Eng Huat Goh of Penang (MY) for intel corporation, Jooi Wah Wong of Bukit Mertajam (MY) for intel corporation
IPC Code(s): H01L23/367, H01L23/42, H01L23/532
CPC Code(s): H01L23/367
Abstract: described herein are integrated circuit devices that include semiconductor devices near the center of the device, rather than towards the top or bottom of the device. in this arrangement, heat can become trapped inside the device. metal fill, such as copper, is formed within a portion of the device, e.g., over the semiconductor devices and any front side interconnect structures, to transfer heat away from the semiconductor devices and towards a heat spreader.
Inventor(s): Shrenik KOTHARI of Phoenix AZ (US) for intel corporation, Chandra Mohan JHA of Tempe AZ (US) for intel corporation, Weihua TANG of Chandler AZ (US) for intel corporation, Robert SANKMAN of Phoenix AZ (US) for intel corporation, Xavier BRUN of Chandler AZ (US) for intel corporation, Pooya TADAYON of Portland OR (US) for intel corporation
IPC Code(s): H01L23/42, H01L23/00, H01L23/367, H01L23/373, H01L23/495, H01L23/522, H01L23/538, H01L25/07
CPC Code(s): H01L23/42
Abstract: embodiments disclosed herein include semiconductor dies and methods of forming such dies. in an embodiment, the semiconductor die comprises a semiconductor substrate, an active device layer in the semiconductor substrate, where the active device layer comprises one or more transistors, an interconnect layer over a first surface of the active device layer, a first bonding layer over a surface of the semiconductor substrate, a second bonding layer secured to the first bonding layer, and a heat spreader attached to the second bonding layer.
Inventor(s): Bok Eng CHEAH of Gelugor (MY) for intel corporation, Seok Ling LIM of Kulim Kedah (MY) for intel corporation, Jenny Shio Yin ONG of Bayan Lepas (MY) for intel corporation, Jackson Chung Peng KONG of Tanjung Tokong (MY) for intel corporation, Kooi Chi OOI of Gelugor (MY) for intel corporation
IPC Code(s): H01L23/498, H01L21/48, H01L23/64, H01L25/00, H01L25/065, H01L25/16, H01L25/18
CPC Code(s): H01L23/49833
Abstract: a device is provided, including a package substrate including at least one opening extending through the package substrate, and an interconnect structure including a first segment and a second segment. the first segment may extend under a bottom surface of the package substrate and may further extend beyond a footprint of the package substrate. the second segment may extend vertically from the first segment and may extend at least partially through the at least one opening of the package substrate.
20240234303. INTEGRATED INDUCTOR OVER TRANSISTOR LAYER_simplified_abstract_(intel corporation)
Inventor(s): Min Suet Lim of Gelugor (MY) for intel corporation, Telesphor Kamgaing of Chandler AZ (US) for intel corporation, Chee Kheong Yoon of Beyan Lepas (MY) for intel corporation, Chu Aun Lim of Hillsboro OR (US) for intel corporation, Eng Huat Goh of Penang (MY) for intel corporation, Jooi Wah Wong of Bukit Mertajam (MY) for intel corporation, Kavitha Nagarajan of Bangalore KA (IN) for intel corporation
IPC Code(s): H01L23/522, H01L49/02
CPC Code(s): H01L23/5227
Abstract: described herein are integrated circuit devices that include semiconductor devices near the center of the device, rather than towards the top or bottom of the device, and integrated inductors formed over the semiconductor devices. power delivery to the device is on the opposite side of the semiconductor devices. the integrated inductors may be used for power step-down to reduce device thickness and/or a number of power rails.
20240234422. STACKED FORKSHEET TRANSISTORS_simplified_abstract_(intel corporation)
Inventor(s): Cheng-Ying HUANG of Portland OR (US) for intel corporation, Gilbert DEWEY of Beaverton OR (US) for intel corporation, Anh PHAN of Beaverton OR (US) for intel corporation, Nicole K. THOMAS of Portland OR (US) for intel corporation, Urusa ALAAN of Hillsboro OR (US) for intel corporation, Seung Hoon SUNG of Portland OR (US) for intel corporation, Christopher M. NEUMANN of Portland OR (US) for intel corporation, Willy RACHMADY of Beaverton OR (US) for intel corporation, Patrick MORROW of Portland OR (US) for intel corporation, Hui Jae YOO of Portland OR (US) for intel corporation, Richard E. SCHENKER of Portland OR (US) for intel corporation, Marko RADOSAVLJEVIC of Portland OR (US) for intel corporation, Jack T. KAVALIEROS of Portland OR (US) for intel corporation, Ehren MANNEBACH of Beaverton OR (US) for intel corporation
IPC Code(s): H01L27/092, H01L29/06, H01L29/423, H01L29/775, H01L29/78, H10B12/00
CPC Code(s): H01L27/0924
Abstract: embodiments disclosed herein include stacked forksheet transistor devices, and methods of fabricating stacked forksheet transistor devices. in an example, an integrated circuit structure includes a backbone. a first transistor device includes a first vertical stack of semiconductor channels adjacent to an edge of the backbone. a second transistor device includes a second vertical stack of semiconductor channels adjacent to the edge of the backbone. the second transistor device is stacked on the first transistor device.
Inventor(s): Abhishek A. Sharma of Hillsboro OR (US) for intel corporation, Arnab Sen Gupta of Beaverton OR (US) for intel corporation, Travis W. LaJoie of Forest Grove OR (US) for intel corporation, Sarah Atanasov of Beaverton OR (US) for intel corporation, Chieh-Jen Ku of Hillsboro OR (US) for intel corporation, Bernhard Sell of Portland OR (US) for intel corporation, Noriyuki Sato of Hillsboro OR (US) for intel corporation, Van Le of Beaverton OR (US) for intel corporation, Matthew Metz of Portland OR (US) for intel corporation, Hui Jae Yoo of Hillsboro OR (US) for intel corporation, Pei-Hua Wang of HIllsboro OR (US) for intel corporation
IPC Code(s): H01L29/786, H01L29/66, H10B61/00, H10B63/00
CPC Code(s): H01L29/7869
Abstract: a thin film transistor (tft) structure includes a gate electrode, a gate dielectric layer on the gate electrode, a channel layer including a semiconductor material with a first polarity on the gate dielectric layer. the tft structure also includes a multi-layer material stack on the channel layer, opposite the gate dielectric layer, an interlayer dielectric (ild) material over the multi-layer material stack and beyond a sidewall of the channel layer. the tft structure further includes source and drain contacts through the interlayer dielectric material, and in contact with the channel layer, where the multi-layer material stack includes a barrier layer including oxygen and a metal in contact with the channel layer, where the barrier layer has a second polarity. a sealant layer is in contact with the barrier layer, where the sealant layer and the ild have a different composition.
Inventor(s): Minki Cho of Portland OR (US) for intel corporation, Balkaran Gill of Cornelius OR (US) for intel corporation, Anisur Rahman of Beaverton OR (US) for intel corporation, Ketul B. Sutaria of Beaverton OR (US) for intel corporation
IPC Code(s): H03K17/14, G06F1/08
CPC Code(s): H03K17/14
Abstract: this disclosure describes systems, methods, and devices related to clock gating. a device may detect that gating of a local clock of a computer core is enabled; detect, based on the detection that the gating is enabled, that a clock gating condition for the local clock is satisfied; and set a clock gating polarity of the local clock based on the detection that the clock gating condition for the local clock is satisfied.
Inventor(s): Hao Luo of Milpitas CA (US) for intel corporation, Somnath Kundu of Hillsboro OR (US) for intel corporation, Brent R. Carlton of Portland OR (US) for intel corporation
IPC Code(s): H03L7/099, H03L7/093
CPC Code(s): H03L7/0992
Abstract: embodiments herein relate to a sampling phase-locked loop (pll) with a compensation circuit for reducing ripples due to the use of a fractional n divider. the compensation circuit includes a ripple amplifier and a ripple divider. the ripple amplifier receives an output voltage, vmain, of a main sampling circuit of the pll and amplifies its alternating current (ac) components. the amplified output voltage is provided to a ripple integrator which samples the minimum and maximum values to provide inputs to an operational amplifier (op amp). an output of the op amp is fed back to a digital-to-analog converter (dac), which provides a corresponding compensation voltage, vcomp. vcomp is added to vmain to provide a final output control voltage, vctrl, to control a voltage-controlled oscillator (vco) of the pll.
Inventor(s): Peter PAWLIUK of Tempe AZ (US) for intel corporation, Gregory CHANCE of Chandler AZ (US) for intel corporation
IPC Code(s): H04B1/10
CPC Code(s): H04B1/1027
Abstract: a radio frequency front end device includes an antenna interface, configured to receive a signal representing a radio transmission; a radio frequency detector, wherein the signal includes a first signal in a first frequency range and a second signal in a second frequency range, adjacent to the first frequency range, and wherein the radio frequency detector is configured to detect the second signal within the second frequency range; and a processor, configured to select, based on the second signal, a sampling window size for a sampling window of a signal windowing procedure for the first signal in the first frequency range; and implement the signal windowing procedure on the first signal at the sampling window size.
Inventor(s): Sundar Krishnamurthy of Dublin CA (US) for intel corporation, Conor O'Keeffe of Cork (IE) for intel corporation, Deepak Dasalukunte of Beaverton OR (US) for intel corporation, Finbarr O'Regan of Innishannon, Cork (IE) for intel corporation, Abhinav Vinod of San Jose CA (US) for intel corporation
IPC Code(s): H04B7/185
CPC Code(s): H04B7/1855
Abstract: an apparatus can include transceiver circuitry to receive an input signal from a target apparatus. the apparatus can further include a processing circuitry to determine position information of a source object and a target object. based on the position information, the processing circuitry can calculate a relative velocity and determine a doppler shift or carrier frequency offset in the input signal based on the relative velocity. the processing circuitry can adjust a local oscillator frequency based on a doppler measured using the position information in an initial link acquisition phase. the processing circuitry can track the doppler continuously over a range of tens of gigahertz accounting for doppler phase ambiguities, and correct for a tracked doppler shift by partially adjusting a local oscillator frequency and by correcting a residual doppler shift digitally.
Inventor(s): NAUSHEEN ANSARI of Folsom CA (US) for intel corporation, ZIV KABIRY of Haifa (IL) for intel corporation, GAL YEDIDIA of Haifa (IL) for intel corporation
IPC Code(s): H04L1/00, H03M5/14, H03M13/15, H03M13/29, H03M13/31
CPC Code(s): H04L1/0057
Abstract: disclosed herein are techniques to provide forward error correction for a high-speed interconnect symbol stream, such as, displayport. the symbol stream may be split into fec blocks and parity bits generated for each of the fec blocks. the parity bits may be interleaved, encoded, and transmitted over an interconnect along with the symbol stream to provide forward error correction for the symbol stream.
Inventor(s): Guotong WANG of Santa Clara CA (US) for intel corporation, Alexei DAVYDOV of Santa Clara CA (US) for intel corporation
IPC Code(s): H04L5/00
CPC Code(s): H04L5/0051
Abstract: systems, apparatus, methods, and computer-readable media provided for collision handling for sounding reference signal (srs) transmission include one or more processors to receive configuration information for a first sounding reference signal (srs) resource set and a second srs resource set, wherein there is a guard period between srs occasions of the first srs resource set and respective srs occasions of the second srs resource set, determine that a first srs occasion of the first srs resource set and a second srs occasion of the second srs resource set are dropped based on a collision handling rule and encode an uplink message for transmission in the guard period between the first and second srs occasions based on the determination.
Inventor(s): Guotong WANG of Santa Clara CA (US) for intel corporation, Alexei DAVYDOV of Santa Clara CA (US) for intel corporation
IPC Code(s): H04L5/00, H04W72/232
CPC Code(s): H04L5/0051
Abstract: systems, apparatuses, methods, and computer-readable media are provided for enhanced phase tracking reference signal (ptrs) operation. additionally, embodiments are provided for partial sounding and/or frequency hopping for sounding reference signal (srs) with repetition. other embodiments may be described and claimed.
Inventor(s): Guotong WANG of Santa Clara CA (US) for intel corporation, Alexei DAVYDOV of Santa Clara CA (US) for intel corporation
IPC Code(s): H04L5/00, H04B7/0404, H04B7/06
CPC Code(s): H04L5/0051
Abstract: systems, apparatuses, methods, and computer-readable media are provided for configuration and collision handling for time-overlapped transmission of uplink signals from multiple antenna panels of a user equipment (ue). the uplink signals may include, e.g., a sounding reference signal (srs) and/or a physical uplink control channel (pucch). other embodiments may be described and claimed.
Inventor(s): Ilya BOLOTIN of Santa Clara CA (US) for intel corporation, Meng ZHANG of Beijing (CN) for intel corporation, Andrey CHERVYAKOV of Maynooth (IE) for intel corporation, Hua LI of Santa Clara CA (US) for intel corporation, Rui HUANG of Santa Clara CA (US) for intel corporation
IPC Code(s): H04L5/00, H04B7/06
CPC Code(s): H04L5/0094
Abstract: this disclosure describes an apparatus comprising a memory to store downlink (dl) transmission configuration indicator (tci) state chain information, and a processing circuitry, coupled with the memory, to retrieve the dl tci state chain information from the memory, wherein the dl tci state information includes an indication of a source reference signal (rs) for a synchronization signal block (ssb) associated with a physical cell identifier that is different from an identifier of a serving cell, and monitor an ssb based on the dl tci state chain information.
20240235906. PRECODING DURING LINK ESTABLISHMENT_simplified_abstract_(intel corporation)
Inventor(s): Andrew K. LILLIE of Chandler AZ (US) for intel corporation, Itamar LEVIN of Holon (IL) for intel corporation, Yaniv SABAG of Kfar Shmuel (IL) for intel corporation, Kent C. LUSTED of Aloha OR (US) for intel corporation
IPC Code(s): H04L25/49, H04L25/03
CPC Code(s): H04L25/4917
Abstract: examples described herein relate to an ethernet physical layer transceiver (phy) circuitry for use in frame communication with a remote link partner. in some example, the ethernet phy circuitry can include physical medium dependent (pmd) circuitry and transmitter circuitry and receiver circuitry for use in the frame communication. in some examples, the pmd circuitry is to perform link training with a partner transmitter and selectively request the partner transmitter to apply a modulation scheme with precoding during the link training based on a magnitude of one or more equalizer coefficient values.
20240235931. SERVICE PROVISION TO IoT DEVICES_simplified_abstract_(intel corporation)
Inventor(s): Keith Nolan of Mullingar (IE) for intel corporation, Mark Kelly of Leixlip (IE) for intel corporation, Michael Nolan of Maynooth (IE) for intel corporation, Davide Carboni of London (GB) for intel corporation, Cliodhna Ni Scanaill of Broadford (IE) for intel corporation, Eugene Ryan of Glasnevin (IE) for intel corporation, Richard Davies of Dublin (IE) for intel corporation, John Brady of Celbridge (IE) for intel corporation
IPC Code(s): H04L41/0806, G06F16/182, H04L9/00, H04L9/08, H04L9/32, H04L41/12, H04L45/00, H04L61/4505, H04L61/5069, H04L67/10, H04L67/104, H04L67/1087, H04L67/12, H04L67/562, H04L69/18, H04L69/22, H04W4/08, H04W4/70, H04W12/69, H04W84/18, H04W84/22
CPC Code(s): H04L41/0806
Abstract: an internet of things (iot) network includes an orchestrator to issue service management requests, a service coordinator to identify components to participate in the service, and a component to perform a network service element. an iot network includes an iot device with service enumerator, contract enumerator, and join contract function. an iot network apparatus includes permissions guide drafter for discovered peers, and permissions guide action executor. an iot network apparatus includes floating service permissions guide drafter for discovered hosts, host hardware selector, floating service permissions guide executor, and service wallet value transferor. an iot network apparatus includes permissions guide drafter for first and second discovered peers, parameter weight calculator, permissions guide term generator, and permissions guide action executor. an iot network includes an iot device with resource hardware component identifier, processor to process a received indication of an external module hardware requirement, an external module comparer, and deactivation signal transmitter.
Inventor(s): John Joseph Browne of Limerick (IE) for intel corporation, Francesc Guim Bernat of Barcelona (ES) for intel corporation, Kshitij Arun Doshi of Tempe AZ (US) for intel corporation, Adrian Hoban of Cratloe (IE) for intel corporation, David Cremins of Toomaline (IE) for intel corporation, Thijs Metsch of Bruehl (DE) for intel corporation, Susanne M. Balle of Hudson NH (US) for intel corporation, Christopher MacNamara of Limerick (IE) for intel corporation, Przemyslaw Perycz of Sopot (PL) for intel corporation, Emma Cecilia Collins of Limerick (IE) for intel corporation, Timothy Verrall of Pleasant Hill CA (US) for intel corporation
IPC Code(s): H04L41/5003
CPC Code(s): H04L41/5003
Abstract: various systems and methods for autonomously monitoring intent-driven end-to-end (e2e) orchestration are described herein. an orchestration system is configured to: receive, at the orchestration system, an intent-based service level objective (slo) for execution of a plurality of tasks; generate a common context that relates the slo to the execution of the plurality of tasks; select a plurality of monitors to monitor the execution of the plurality of tasks, the plurality of monitors to log a plurality of key performance indicators; generate a domain context for the plurality of tasks; configure an analytics system with the plurality of monitors and the plurality of key performance indicators correlated by the domain contexts; deploy the plurality of monitors to collect telemetry; monitor the execution of the plurality of tasks using the telemetry from the plurality of monitors; and perform a responsive action based on the telemetry.
Inventor(s): Uma S. CHUNDURI of Fremont CA (US) for intel corporation
IPC Code(s): H04L45/12, H04L45/00, H04L45/02
CPC Code(s): H04L45/124
Abstract: the present disclosure is generally related to edge computing, cloud computing, data centers, network communication, network topologies, traffic engineering, data packet routing techniques, switch fabric technologies, and communication system implementations, and in particular, to preferred path routing techniques and traffic engineering in fabric switch topologies with deterministic services.
Inventor(s): Luis Kida of Beaverton OR (US) for intel corporation, Reshma Lal of Portland OR (US) for intel corporation
IPC Code(s): H04L9/40, G06F9/50, G06F13/28, H04L9/08, H04L9/32
CPC Code(s): H04L63/0485
Abstract: an apparatus to facilitate protecting data transfer between a secure application and networked devices is disclosed. the apparatus includes a processor to provide a trusted execution environment (tee) to run an application, wherein the processor is to: generate, via the application in the tee, encrypted data, wherein the encrypted data comprises a payload; copy, via the application in the tee, the encrypted data to a local buffer; interface, using the application in the tee, with a source network interface controller (nic) to initiate a copy over a network of the encrypted data from the local buffer to a remote buffer of a remote platform; and communicate, after completing the copy of the network of the encrypted data, at least one message with the remote platform to indicate that the encrypted data is available and to enable the remote platform to verify integrity of the encrypted data.
Inventor(s): Sangeetha L. BANGOLAE of Santa Clara CA (US) for intel corporation, Zongrui DING of Portland OR (US) for intel corporation, Qian LI of Portland OR (US) for intel corporation, Sudeep PALAT of Gloucestershire (GB) for intel corporation, Youn Hyoung HEO of Santa Clara CA (US) for intel corporation, Alexandre Saso STOJANOVSKI of Paris 75 (FR) for intel corporation, Thomas LUETZENKIRCHEN of Taufkirchen BY (DE) for intel corporation, Ching-Yu LIAO of Santa Clara CA (US) for intel corporation, Abhijeet KOLEKAR of Portland OR (US) for intel corporation
IPC Code(s): H04L67/1097, H04W28/02
CPC Code(s): H04L67/1097
Abstract: various embodiments herein are directed to remote direct memory access (rdma) support in cellular networks. in particular, some embodiments may relate to enhancements to rdma over cellular network (rocn) protocols.
Inventor(s): Gang Shen of Hillsboro OR (US) for intel corporation, Guangxin Xu of Shanghai (CN) for intel corporation, Jill Boyce of Portland OR (US) for intel corporation
IPC Code(s): H04N19/167, H04N13/178, H04N13/194, H04N13/366, H04N19/119, H04N19/172, H04N19/597
CPC Code(s): H04N19/167
Abstract: methods, apparatus, systems, and articles of manufacture are disclosed to reduce latency during viewport switching in immersive video. an example apparatus include at least one memory, instructions in the apparatus, and processor circuitry to execute the instructions to: obtain a first bitstream having a first encoded frame and a second encoded frame, the second encoded frame encoded at a higher resolution than the first encoded frame and having a coding dependency on the first encoded frame, rewrite the first bitstream into a second bitstream based on field of view information, the second bitstream including a third encoded frame indicative of a portion of the second encoded frame that corresponds to the field of view information and including the first encoded frame, and transmit the second bitstream to a client device for decoding and rendering the portion of the second encoded frame.
20240236541. ADAPTIVE AMBIENT LISTENING FOR AUDIO SYSTEMS_simplified_abstract_(intel corporation)
Inventor(s): Oren Haggai of Kefar Sava (IL) for intel corporation, Gila Kamhi of Zichron Yaakov (IL) for intel corporation, Shmuel Markovich Golan of RAMAT HASHARON (IL) for intel corporation, Shuki Perlman of Zur-Hadassa (IL) for intel corporation, Prasanna Desai of Elfin Forest CA (US) for intel corporation
IPC Code(s): H04R1/10, G06F3/16, H04R1/08
CPC Code(s): H04R1/1041
Abstract: an apparatus can include at least one audio device configured to detect sound. the apparatus can further include processing circuitry to determine presence of a relevant sound relevant to a user of the apparatus based on a user preference or an audio device parameter. the processing circuitry can further, responsive to detecting presence of the relevant sound, provide a control command to a user listening device to command the user listening device to provide the relevant sound to a microphone of the user listening device.
Inventor(s): Qian Li of Beaverton OR (US) for intel corporation, Geng Wu of Portland OR (US) for intel corporation
IPC Code(s): H04W8/22, H04L41/342, H04W8/18, H04W72/232
CPC Code(s): H04W8/22
Abstract: an apparatus and system are described to provide functions and procedures in a data-centric infrastructure (dci). the logical architecture includes an infrastructure orchestration function and controller. interactions between the infrastructure orchestration function and controller include a function request to form or release a logical computing node, or modify the logical computing node through addition or removal of at least one of a function-dedicated computing (fdc) function, a data plane (dp) function, or a function-dedicated network (fdn) function to the logical computing node. the controller configures the fdc/dp/fdn functions and sends a response indicating completion of operations performed by the controller that are related to the function request.
Inventor(s): Meng ZHANG of Beijing (CN) for intel corporation, Andrey CHERVYAKOV of Maynooth (IE) for intel corporation, Rui HUANG of Santa Clara CA (US) for intel corporation, Hua LI of Santa Clara CA (US) for intel corporation, Ilya BOLOTIN of Santa Clara CA (US) for intel corporation
IPC Code(s): H04W36/00, H04W76/28
CPC Code(s): H04W36/0088
Abstract: the invention relates to an apparatus comprising: memory to store measurement gap configuration information associated with network switching for a user equipment (ue); and processing circuitry to: retrieve the measurement gap configuration information from the memory, wherein the measurement gap configuration information includes a measurement gap pattern having: a measurement gap length (mgl) of 20 ms, 40 ms, 80 ms, or 160 ms, and a measurement gap repetition period of 5120 ms; and encode a message for transmission to the ue that includes the measurement gap configuration information.
Inventor(s): Sangeetha L. BANGOLAE of Santa Clara CA (US) for intel corporation, Zongrui DING of Portland OR (US) for intel corporation, Alexandre Saso STOJANOVSKI of Paris 75 (FR) for intel corporation, Qian LI of Portland OR (US) for intel corporation, Sudeep PALAT of Gloucestershire (GB) for intel corporation, Thomas LUETZENKIRCHEN of Taufkirchen BY (DE) for intel corporation, Youn Hyoung HEO of Santa Clara CA (US) for intel corporation, Ching-Yu LIAO of Santa Clara CA (US) for intel corporation, Abhijeet KOLEKAR of Portland OR (US) for intel corporation
IPC Code(s): H04W48/18, H04W8/22, H04W76/20
CPC Code(s): H04W48/18
Abstract: various embodiments herein are directed to radio access network (ran) computing service support with distributed units (dus). in particular, some embodiments are directed to to the architecture and corresponding control plane functions and protocols for ran-based computation offloading using compute resource at a next-generation nodeb (gnb) du. other embodiments be disclosed or claimed.
20240236900. BANDWIDTH PART SWITCHING DELAY DERIVATION_simplified_abstract_(intel corporation)
Inventor(s): Ilya BOLOTIN of Santa Clara CA (US) for intel corporation, Meng ZHANG of Beijing (CN) for intel corporation, Andrey CHERVYAKOV of Kildare (IE) for intel corporation, Hua LI of Santa Clara CA (US) for intel corporation, Rui HUANG of Santa Clara CA (US) for intel corporation
IPC Code(s): H04W56/00, H04W72/12, H04W72/232
CPC Code(s): H04W56/005
Abstract: various embodiments herein are directed to determining a bandwidth part (bwp) switching delay based on a maximum receive timing difference (mrtd) between two cells. a user equipment (ue) is configured to: determine timing information that includes a maximum receive timing difference (mrtd) between a first cell from which the ue receives downlink control information (dci) and a second cell where a bandwidth part (bwp) switch is to occur; determine a bwp switching delay based on the mrtd; and perform the bwp switch based on the determined bwp switching delay.
Inventor(s): Ansab Ali of Hillsboro OR (US) for intel corporation, Yi Guo of Shanghai (CN) for intel corporation, Youn Hyoung Heo of Sunnyvale CA (US) for intel corporation, Sudeep K. Palat of Cheltenham (GB) for intel corporation
IPC Code(s): H04W64/00, G01S5/02
CPC Code(s): H04W64/003
Abstract: an apparatus and system of validity conditions for pre-configured assistance data used during a long term evolution (lte) positioning protocol (lpp) location procedure are described. the validity conditions are used to determine whether or not the assistance data remains valid for performing location measurements. the validity conditions may indicate that the assistance data is limited to a single positioning session or may be used for multiple sessions. in the latter case, the validity conditions may indicate geographic, timing, or number of sessions limitations. when the ue determines that the assistance data is no longer valid based on the validity conditions, the ue may request new assistance data prior to performing the measurements.
Inventor(s): Ilya BOLOTIN of Santa Clara CA (US) for intel corporation, Andrey CHERVYAKOV of Kildare (IE) for intel corporation, Meng ZHANG of Beijing (CN) for intel corporation, Hua LI of Santa Clara CA (US) for intel corporation, Rui HUANG of Santa Clara CA (US) for intel corporation
IPC Code(s): H04W72/0446, H04W72/231
CPC Code(s): H04W72/0446
Abstract: various embodiments herein provide techniques to avoid inter-symbol interference during transmission configuration indicator (tci) state switching in high-speed train (hst) deployments. for example, a gap may be added between the validity of a first tci state and a second tci state when switching from the first tci state to the second tci state in a high speed scenario (e.g., power class 6). the techniques may be used for communication in new radio (nr) frequency range 2 (fr2).
Inventor(s): Yingyang LI of Santa Clara CA (US) for intel corporation, Gang XIONG of Portland OR (US) for intel corporation, Daewon LEE of Portland OR (US) for intel corporation, Yi WANG of Santa Clara CA (US) for intel corporation
IPC Code(s): H04W72/1273, H04L5/00, H04W72/232
CPC Code(s): H04W72/1273
Abstract: various embodiments herein provide techniques to determine valid and invalid physical downlink shared channels (pdschs) and/or physical uplink shared channels (puschs) with multi-pdsch and/or pusch scheduling. embodiments further relate to determination of transmission configuration indicator (tci) state and/or quasi co-location (qcl) for multi-pdsch and/or pusch scheduling. other embodiments may be described and claimed.
20240237025. HARQ-ACK TRANSMISSION_simplified_abstract_(intel corporation)
Inventor(s): Yingyang Li of Beijing (CN) for intel corporation, Gang Xiong of Portland OR (US) for intel corporation, Daewon Lee of Portland OR (US) for intel corporation, Alexei Davydov of Nizhny Novgorod (RU) for intel corporation, Prerana Rane of Newark CA (US) for intel corporation
IPC Code(s): H04W72/232, H04L1/1812, H04W72/1273, H04W76/28
CPC Code(s): H04W72/232
Abstract: various embodiments herein provide techniques related to hybrid automatic repeat request acknowledgement (harq-ack) transmission in cellular networks. some embodiments may relate to harq-ack transmission in networks that use a relatively high carrier frequency (e.g., a carrier frequency above approximately 52.6 gigahertz (ghz)). some embodiments may relate to harq-ack codebook size determination for multi-physical downlink shared channel (pdsch) scheduling. some embodiments may relate to downlink control and harq-ack transmission for multi-pdsch scheduling. other embodiments may be described and/or claimed.
Inventor(s): Andrey Chervyakov of Nizhny Novgorod (RU) for intel corporation, Rui Huang of Beijing (CN) for intel corporation, Hua Li of Beijing (CN) for intel corporation, Yi Guo of Shanghai (CN) for intel corporation, Qiming Li of Beijing (CN) for intel corporation
IPC Code(s): H04W72/51, H04L5/00, H04W56/00, H04W72/54
CPC Code(s): H04W72/51
Abstract: an apparatus of a new radio (nr) node b (gnb), a method, and a storage medium. one or more processors of the apparatus are to: encode for transmission to a user equipment (ue) a message to configure the ue with a measurement gap pattern for positioning reference signal (prs) measurements; and set a gap pattern length of a measurement gap corresponding to the measurement gap pattern depending on whether an overlap exists between a prs to be measured and one or more other nr data scheduled to be received by the ue.
Inventor(s): Xiaogang Chen of Hillsboro OR (US) for intel corporation, Qinghua Li of San Ramon CA (US) for intel corporation, Feng Jiang of Sunnyvale CA (US) for intel corporation, Ziv Avital of Kadima (IL) for intel corporation, Po-Kai Huang of San Jose CA (US) for intel corporation
IPC Code(s): H04W74/00, G06F11/10, H04W72/0446, H04W72/0453, H04W72/20, H04W72/54, H04W84/12
CPC Code(s): H04W74/002
Abstract: an extremely high throughput (eht) station (sta) configured for trigger based (tb) transmission may decode an trigger frame (tf) received from an access point (ap). the tf may include an assignment of resources comprising one or more 20 mhz channels. the eht sta may determine which of the one or more assigned channels are available for transmission and which of the allocated channels are unavailable when the eht sta is assigned more than one 20 mhz channel. the eht sta may encode a eht tb ppdu in response to the trigger frame. the eht tb ppdu may be encoded to include an eht preamble followed by a data field. the eht preamble may be encoded to indicate channel availability. the eht sta may generate signalling to cause the eht sta to transmit the encoded eht tb ppdu only on the assigned channels that have been determined to be available.
Inventor(s): Salvatore TALARICO of Santa Clara CA (US) for intel corporation, Debdeep CHATTERJEE of San Jose CA (US) for intel corporation, Yi WANG of Santa Clara CA (US) for intel corporation, Toufiqul ISLAM of Santa Clara CA (US) for intel corporation, Sergey PANTELEEV of Kildare (IE) for intel corporation
IPC Code(s): H04W74/0808, H04W74/00
CPC Code(s): H04W74/0808
Abstract: various embodiments herein are directed to priority-based transmissions and cancellation indications in semi-static channel access mode. other embodiments may be disclosed or claimed.
Inventor(s): Seau Sian LIM of Santa Clara CA (US) for intel corporation, Marta MARTINEZ TARRADELL of Portland OR (US) for intel corporation, Yi GUO of Shanghai (CN) for intel corporation, Sudeep PALAT of Gloucestershire (GB) for intel corporation, Candy YIU of Santa Clara CA (US) for intel corporation, Yujian ZHANG of Santa Clara CA (US) for intel corporation, Ansab ALI of Beaverton OR (US) for intel corporation, Youn Hyoung HEO of Santa Clara CA (US) for intel corporation
IPC Code(s): H04W74/0833, H04W74/00
CPC Code(s): H04W74/0833
Abstract: various embodiments herein are directed to using random access channel (rach) configuration parameters to identify multiple features and combinations of features. in particular, some embodiments are directed to extensions to rach configuration information elements (ies) to identify multiple features and feature combinations.
Inventor(s): Yi HUANG of Shanghai (CN) for intel corporation, Xiaoning YE of Portland OR (US) for intel corporation, Kai XIAO of Portland OR (US) for intel corporation, James A. McCALL of Portland OR (US) for intel corporation, Yanjie ZHU of Folsom CA (US) for intel corporation
IPC Code(s): H05K1/02, H05K1/11, H05K1/14
CPC Code(s): H05K1/0253
Abstract: an apparatus is described. the apparatus includes a memory module. the memory module includes a first printed circuit board having a first transmission line. the first printed circuit board has memory chips disposed thereon. the memory module includes a second printed board having a second transmission line that is coupled to the first transmission line to form a signal path through the first and second printed circuit boards. the second printed circuit board has greater flexibility than the first printed circuit board. the memory module includes a connector to align an i/o that is coupled to the second transmission line with a corresponding i/o that is associated with a motherboard that is to send and/or receive a signal to and/or from the signal path.
Inventor(s): Ifiok UMOH of San Jose CA (US) for intel corporation, Luz Karine SANDOVAL GRANADOS of Zapopan (MX) for intel corporation, Alberto CARRILLO VAZQUEZ of Zapopan (MX) for intel corporation, Quresh BOHRA of San Jose CA (US) for intel corporation, Diego Mauricio CORTES HERNANDEZ of Beaverton OR (US) for intel corporation
IPC Code(s): H05K1/18, H01R12/57
CPC Code(s): H05K1/181
Abstract: methods and apparatus for staggered flip pin smt (surface mount technology) connectors to reduce crosstalk on high-speed channels. contact feet on the board-side of a connector are flipped to increase the physical separation between contacts carrying transmit (tx) and contacts carrying receive (rx) signals. meanwhile, for some embodiments the input receptacle side of the connectors are the same as that defined by standards such as sff-8482, sff-8630, sff-8680 standards and the pci-sig, sff-8639 module specification. this enables the connectors to work with existing devices employing these standards, such as nvme drives. in one aspect, the connectors comprise modified versions of u.2 and u.3 connectors where selected board-side contacts (e.g., tx−, tx+, optional gnd) and the mating contact pads used for smt dual mount termination are staggered. in one aspect, the connector solutions are targeted for pcie 5.0 and later nvme implementations, noting the principles and techniques disclosed may apply to other high-speed channels.
Inventor(s): Shoghi Effendi RAJAGOPAL of Kulim (MY) for intel corporation
IPC Code(s): H05K13/08, H05K13/04
CPC Code(s): H05K13/0812
Abstract: the disclosure is directed to apparatus and methods for manufacturing including a collaborative robot, a camera operatively coupled to the collaborative robot, a memory coupled to the collaborative robot, and processing circuitry coupled to the memory, the processing circuitry configured to receive image data of at least one component intended for a printed circuit board (pcb), the image data collected by the camera operatively coupled to the collaborative robot, determine, based on the image data, a coordinate location for the component, and secure the component to the pcb using an end effector of the collaborative robot based on the received image data. in one embodiment, the collaborative robot is configured to operate alongside a human, the collaborative robot in combination with the camera configured to manufacture a computer system with the pcb.
- Intel Corporation
- G01D5/353
- B65B11/52
- B65B57/02
- CPC G01D5/353
- Intel corporation
- G01N19/04
- CPC G01N19/04
- G01R19/10
- CPC G01R19/10
- G03F1/36
- CPC G03F1/36
- G06F1/16
- CPC G06F1/1652
- G06F1/20
- G06F1/32
- G06F3/01
- G06V10/774
- G06V40/10
- G06V40/16
- G10L25/51
- H04B1/3827
- CPC G06F1/206
- G06F1/324
- G06F1/3206
- CPC G06F1/324
- G06F1/329
- G06F9/48
- CPC G06F1/329
- G06F1/3296
- G06F1/3287
- CPC G06F1/3296
- G02B27/01
- G06T1/20
- CPC G06F3/012
- G06V10/25
- G06V10/44
- CPC G06F3/013
- G06F3/04817
- G06F3/0482
- G06F3/0485
- CPC G06F3/017
- G06F3/06
- G06T1/60
- CPC G06F3/061
- G06F8/65
- G06F1/3212
- CPC G06F8/65
- G06F9/445
- G06F9/30
- G06F9/50
- G06N20/00
- H03K19/177
- H03K19/20
- CPC G06F9/445
- G06F9/448
- G06F16/215
- CPC G06F9/4488
- G06F40/284
- CPC G06F9/485
- G06F9/52
- CPC G06F9/522
- G06F11/36
- CPC G06F11/3676
- G06F12/0855
- CPC G06F12/0857
- G06F12/0877
- G06F12/0802
- G06F12/0806
- G06F12/0846
- G06F12/0868
- G06F12/0893
- G06F12/126
- CPC G06F12/0877
- G06F12/1009
- CPC G06F12/1009
- G06F12/1027
- G06F12/0882
- G06F12/14
- CPC G06F12/1027
- G06F13/40
- H04L12/54
- H04L49/10
- CPC G06F13/4022
- G06F13/42
- G06F9/38
- CPC G06F13/4221
- G06F30/398
- G06F30/27
- CPC G06F30/398
- CPC G06F9/505
- G06N3/08
- G06N5/04
- G06T7/00
- CPC G06T1/20
- G06T15/06
- G06T15/00
- G06T17/00
- CPC G06T15/06
- G06T15/40
- H04N13/279
- H04N13/344
- H04N13/383
- H04N13/398
- CPC G06T15/405
- G06V20/40
- G06V10/80
- G06V10/82
- CPC G06V20/49
- G08G1/07
- G06V20/54
- G06V40/20
- G08G1/005
- G08G1/16
- CPC G08G1/07
- G08G1/0967
- B60W60/00
- H04W4/40
- H04W4/90
- CPC G08G1/096725
- H01L23/15
- H01L23/31
- H01L23/495
- H01L23/498
- H01L23/538
- CPC H01L23/15
- H01L23/367
- H01L23/42
- H01L23/532
- CPC H01L23/367
- H01L23/00
- H01L23/373
- H01L23/522
- H01L25/07
- CPC H01L23/42
- H01L21/48
- H01L23/64
- H01L25/00
- H01L25/065
- H01L25/16
- H01L25/18
- CPC H01L23/49833
- H01L49/02
- CPC H01L23/5227
- H01L27/092
- H01L29/06
- H01L29/423
- H01L29/775
- H01L29/78
- H10B12/00
- CPC H01L27/0924
- H01L29/786
- H01L29/66
- H10B61/00
- H10B63/00
- CPC H01L29/7869
- H03K17/14
- G06F1/08
- CPC H03K17/14
- H03L7/099
- H03L7/093
- CPC H03L7/0992
- H04B1/10
- CPC H04B1/1027
- H04B7/185
- CPC H04B7/1855
- H04L1/00
- H03M5/14
- H03M13/15
- H03M13/29
- H03M13/31
- CPC H04L1/0057
- H04L5/00
- CPC H04L5/0051
- H04W72/232
- H04B7/0404
- H04B7/06
- CPC H04L5/0094
- H04L25/49
- H04L25/03
- CPC H04L25/4917
- H04L41/0806
- G06F16/182
- H04L9/00
- H04L9/08
- H04L9/32
- H04L41/12
- H04L45/00
- H04L61/4505
- H04L61/5069
- H04L67/10
- H04L67/104
- H04L67/1087
- H04L67/12
- H04L67/562
- H04L69/18
- H04L69/22
- H04W4/08
- H04W4/70
- H04W12/69
- H04W84/18
- H04W84/22
- CPC H04L41/0806
- H04L41/5003
- CPC H04L41/5003
- H04L45/12
- H04L45/02
- CPC H04L45/124
- H04L9/40
- G06F13/28
- CPC H04L63/0485
- H04L67/1097
- H04W28/02
- CPC H04L67/1097
- H04N19/167
- H04N13/178
- H04N13/194
- H04N13/366
- H04N19/119
- H04N19/172
- H04N19/597
- CPC H04N19/167
- H04R1/10
- G06F3/16
- H04R1/08
- CPC H04R1/1041
- H04W8/22
- H04L41/342
- H04W8/18
- CPC H04W8/22
- H04W36/00
- H04W76/28
- CPC H04W36/0088
- H04W48/18
- H04W76/20
- CPC H04W48/18
- H04W56/00
- H04W72/12
- CPC H04W56/005
- H04W64/00
- G01S5/02
- CPC H04W64/003
- H04W72/0446
- H04W72/231
- CPC H04W72/0446
- H04W72/1273
- CPC H04W72/1273
- H04L1/1812
- CPC H04W72/232
- H04W72/51
- H04W72/54
- CPC H04W72/51
- H04W74/00
- G06F11/10
- H04W72/0453
- H04W72/20
- H04W84/12
- CPC H04W74/002
- H04W74/0808
- CPC H04W74/0808
- H04W74/0833
- CPC H04W74/0833
- H05K1/02
- H05K1/11
- H05K1/14
- CPC H05K1/0253
- H05K1/18
- H01R12/57
- CPC H05K1/181
- H05K13/08
- H05K13/04
- CPC H05K13/0812
