Intel Corporation patent applications on January 30th, 2025
Patent Applications by Intel Corporation on January 30th, 2025
Intel Corporation: 30 patent applications
Intel Corporation has applied for patents in the areas of G06F9/30 (4), H01L25/065 (2), H01L23/538 (2), H04L67/12 (2), H04L67/10 (2) G01B9/02027 (1), G06T15/005 (1), H04N19/96 (1), H04L65/1069 (1), H04L63/107 (1)
With keywords such as: device, data, based, circuitry, including, network, disclosed, interface, processing, and input in patent application abstracts.
Patent Applications by Intel Corporation
Inventor(s): Wenhua Lin of Fremont CA (US) for intel corporation, Boris Vulovic of Campbell CA (US) for intel corporation
IPC Code(s): G01B9/02015
CPC Code(s): G01B9/02027
Abstract: disclosed herein are embodiments of a broadband wavemeter system comprising: a laser source to generate an optical signal having one or more wavelengths; a tap to separate a portion of the optical signal from the laser source; a splitter to split an incoming optical signal from the tap into a plurality of outgoing optical signals; a plurality of wavemeters, each one in the plurality to receive one of the outgoing optical signals from the splitter, in which each wavemeter in the plurality of wavemeters comprises a mach-zehnder interferometer (mzi), and each wavemeter has at least one of free spectral range (fsr) detuning and center wavelength detuning, and a control circuit to collate outputs from individual ones of the plurality of wavemeters to monitor, detect and control the laser source.
Inventor(s): Qing De XIA of Shanghai (CN) for intel corporation, Yan LU of Shanghai (CN) for intel corporation, Ji ZHANG of Shanghai (CN) for intel corporation, Juan ZOU of Shanghai (CN) for intel corporation, Matan LEVY of Tzur Moshe (IL) for intel corporation, Joy PODDAR of Bangalore (IN) for intel corporation, Amir RUBIN of Kiryat Ono (IL) for intel corporation, Amit SINGHAL of Bangalore (IN) for intel corporation
IPC Code(s): G01S13/88, G01S13/36, H04B1/3827
CPC Code(s): G01S13/88
Abstract: disclosed herein are devices, systems, and methods for detecting and classifying the proximity of a human to a wireless antenna. the device may include a processor configured to receive information representing an incident wave and a reflected wave of a transmission on the wireless antenna. the processor may also be configured to analyze the information using one or more classification models, wherein each of the one or more classification models comprise a machine-learning-based classifier that determines, based on the information, whether the object is within a threshold proximity to the wireless antenna, a classification of the object, and/or a separation-distance between the wireless antenna and the object.
Inventor(s): Boris Vulovic of Campbell CA (US) for intel corporation, Wenhua Lin of Fremont CA (US) for intel corporation
IPC Code(s): G02B6/12, G02B6/122, G02B6/125, G02B6/136
CPC Code(s): G02B6/12004
Abstract: disclosed herein are embodiments of a waveguide structure, comprising: a deep rib waveguide on a slab and a plurality of shallow rib waveguides on the slab. the deep rib waveguide has a first etch-depth, the plurality of shallow rib waveguides has a second etch-depth, and the first etch-depth is greater than the second etch-depth.
Inventor(s): Kok Yoong Foo of Butterworth (MY) for intel corporation, Sze Yin Lee of Georgetown (MY) for intel corporation
IPC Code(s): G06F1/08, G06F12/02
CPC Code(s): G06F1/08
Abstract: a fifo may use lookahead circuitry to boost performance and reduce data transfer latency by reducing the fipo operation cycles when operating in the store and forward mode. the lookahead circuitry may increase data transfer rate of the fifo between two integrated circuit devices that use different clock frequencies. the use of the lookahead circuitry with the fifo may also reduce power consumption of the fifo, allow storage media of the fifo to be smaller, and free up valuable die space for other circuitry.
Inventor(s): Venkateshan UDHAYAN of Portland OR (US) for intel corporation, Chia-Hung S. KUO of Folsom CA (US) for intel corporation, Antonio S. CHENG of Portland OR (US) for intel corporation, Lawrence FALKENSTEIN of Beaverton OR (US) for intel corporation, Swetha KARLAPUDI of Portland OR (US) for intel corporation, Brian WILK of Portland OR (US) for intel corporation, Michael SHUSTERMAN of Portland OR (US) for intel corporation, Deepak Samuel KIRUBAKARAN of Hillsboro OR (US) for intel corporation, Rajshree CHABUKSWAR of Sunnyvale CA (US) for intel corporation
IPC Code(s): G06F1/3228, G06F9/48
CPC Code(s): G06F1/3228
Abstract: a method and system for power management and scheduling based on human interface device (hid) input types. a user input is received via an hid, and an hid input type of the user input is determined. the hid input type is then provided to a power management controller and/or an operating system scheduler, and power management and/or scheduling are performed based on the hid input type. an operating frequency of a processor or a processor core of the system may be adjusted based on the hid input type. one of the processor cores in a hybrid system such as a p-core or an e-core may be selected for a task based on the hid input type.
20250036361. FLOATING-POINT CONVERSION VIA AN INTEGER UNIT_simplified_abstract_(intel corporation)
Inventor(s): Supratim Pal of Folsom CA (US) for intel corporation, Jiasheng Chen of El Dorado Hills CA (US) for intel corporation, Kevin Hurd of Flagler Beach FL (US) for intel corporation, Jorge E. Parra Osorio of El Dorado Hills CA (US) for intel corporation, Christopher Spencer of Chuluota FL (US) for intel corporation, Guei-Yuan Lueh of San Jose CA (US) for intel corporation, Pradeep K. Golconda of El Dorado Hills CA (US) for intel corporation, Fangwen Fu of Folsom CA (US) for intel corporation, Wei Xiong of Fremont CA (US) for intel corporation, Hongzheng Li of Sunnyvale CA (US) for intel corporation, James Valerio of North Plains OR (US) for intel corporation, Mukundan Swaminathan of San Ramon CA (US) for intel corporation, Nicholas Murphy of The Sands (GB) for intel corporation, Shuai Mu of San Diego CA (US) for intel corporation, Clifford Gibson of Hertfordshire (GB) for intel corporation, Buqi Cheng of San Jose CA (US) for intel corporation
IPC Code(s): G06F7/483
CPC Code(s): G06F7/483
Abstract: described herein is a graphics processor comprising a memory interface and a graphics processing cluster coupled with the memory interface. the graphics processing cluster includes a multi-lane parallel floating-point unit and a multi-lane parallel integer unit. the multi-lane parallel integer unit includes an integer pipeline including a plurality of parallel integer logic units configured to perform integer compute operations on a plurality of input data elements and a format conversion pipeline including a plurality of parallel format conversion units configured to convert a plurality of input data elements from a first one of a plurality of datatype formats to a second one of the plurality of datatype formats, the plurality of datatype formats including integer and floating-point formats.
Inventor(s): Supratim Pal of Folsom CA (US) for intel corporation, Jiasheng Chen of El Dorado Hills CA (US) for intel corporation, Christopher Spencer of Chuluota FL (US) for intel corporation, Jorge E. Parra Osorio of El Dorado Hills CA (US) for intel corporation, Kevin Hurd of Flagler Beach FL (US) for intel corporation, Guei-Yuan Lueh of San Jose CA (US) for intel corporation, Pradeep K. Golconda of El Dorado Hills CA (US) for intel corporation, Fangwen Fu of Folsom CA (US) for intel corporation, Wei Xiong of Fremont CA (US) for intel corporation, Hongzheng Li of Sunnyvale CA (US) for intel corporation, James Valerio of North Plains OR (US) for intel corporation, Mukundan Swaminathan of San Ramon CA (US) for intel corporation, Nicholas Murphy of The Sands (GB) for intel corporation, Shuai Mu of San Diego CA (US) for intel corporation, Clifford Gibson of Hertfordshire (GB) for intel corporation, Buqi Cheng of San Jose CA (US) for intel corporation
IPC Code(s): G06F9/30, G06F9/38
CPC Code(s): G06F9/30192
Abstract: described herein is a graphics processor comprising a memory interface and a graphics processing cluster coupled with the memory interface. the graphics processing cluster includes a plurality of processing resources. a processing resource of the plurality of processing resources includes a source crossbar communicatively coupled with a register file, the source crossbar to reorder data elements of a source operand and a format conversion pipeline to convert a plurality of input data elements specified by the source operand from a first format of a plurality of datatype formats to a second format of the plurality of datatype formats, the plurality of datatype formats including integer and floating-point formats.
Inventor(s): Balaji Vembu of Folsom CA (US) for intel corporation, Abhishek R. Appu of El Dorado Hills CA (US) for intel corporation, Joydeep Ray of Folsom CA (US) for intel corporation, Altug Koker of El Dorado Hills CA (US) for intel corporation
IPC Code(s): G06F9/46, G06F9/38, G06F9/48, G06F9/50, G06F9/52, G06F9/54, G06F12/0842, G06F12/0866, G06F12/0897, G06F15/16, G06F15/76, G06T1/20, G06T1/60
CPC Code(s): G06F9/46
Abstract: an apparatus to facilitate thread scheduling is disclosed. the apparatus includes logic to store barrier usage data based on a magnitude of barrier messages in an application kernel and a scheduler to schedule execution of threads across a plurality of multiprocessors based on the barrier usage data.
20250036477. MICROSERVICE PROVISION AND MANAGEMENT_simplified_abstract_(intel corporation)
Inventor(s): Katalin Bartfai-Walcott of El Dorado Hills CA (US) for intel corporation, Peggy J. Irelan of Chandler AZ (US) for intel corporation, Hassnaa Moustafa of San Jose CA (US) for intel corporation
IPC Code(s): G06F9/50, H04L67/10, H04L67/12
CPC Code(s): G06F9/5061
Abstract: a compute system that includes an internet of things (iot) device is provided. the iot device includes a common services interface (csi) to create a self-managing network of devices with other nodes comprising the csi.
Inventor(s): Ilya K. Ganusov of San Jose CA (US) for intel corporation, Ashish Gupta of San Jose CA (US) for intel corporation, Chee Hak Teh of Bayan Lepas (MY) for intel corporation, Sean R. Atsatt of Santa Cruz CA (US) for intel corporation, Scott Jeremy Weber of Piedmont CA (US) for intel corporation, Parivallal Kannan of San Jose CA (US) for intel corporation, Aman Gupta of Austin TX (US) for intel corporation, Gary Brian Wallichs of San Jose CA (US) for intel corporation
IPC Code(s): G06F15/78, H04L45/60, H04L49/109
CPC Code(s): G06F15/7825
Abstract: systems and methods described herein may relate to data transactions involving a microsector architecture. control circuitry may organize transactions to and from the microsector architecture to, for example, enable direct addressing transactions as well as batch transactions across multiple microsectors. a data path disposed between programmable logic circuitry of a column of microsectors and a column of row controllers may form a micro-network-on-chip used by a network-on-chip to interface with the programmable logic circuitry.
Inventor(s): Prasoonkumar Surti of Folsom CA (US) for intel corporation, Abhishek R. Appu of El Dorado Hills CA (US) for intel corporation, Karol Szerszen of Hillsboro OR (US) for intel corporation, Eric Liskay of Folsom CA (US) for intel corporation, Karthik Vaidyanathan of San Francisco CA (US) for intel corporation
IPC Code(s): G06F16/22, G06N20/00, G06T1/20
CPC Code(s): G06F16/2237
Abstract: embodiments are generally directed to compression for compression for sparse data structures utilizing mode search approximation. an embodiment of an apparatus includes one or more processors including a graphics processor to process data; and a memory for storage of data, including compressed data. the one or more processors are to provide for compression of a data structure, including identification of a mode in the data structure, the data structure including a plurality of values and the mode being a most repeated value in a data structure, wherein identification of the mode includes application of a mode approximation operation, and encoding of an output vector to include the identified mode, a significance map to indicate locations at which the mode is present in the data structure, and remaining uncompressed data from the data structure.
Inventor(s): Bin XING of Hillsboro OR (US) for intel corporation, Mona VIJ of Hillsboro OR (US) for intel corporation, Rajesh POORNACHANDRAN of Portland OR (US) for intel corporation, Barry HUNTLEY of Hillsboro OR (US) for intel corporation, Scott CONSTABLE of Portland OR (US) for intel corporation, Yuan XIAO of Chicago IL (US) for intel corporation, Xiang CHENG of Atlanta GA (US) for intel corporation
IPC Code(s): G06F21/54, G06F9/30, G06F21/55
CPC Code(s): G06F21/54
Abstract: in one embodiment, an apparatus comprises a cache to store a plurality of instructions and data associated with a trusted execution environment; instruction processing circuitry to execute the plurality of instructions and process the data, the plurality of instructions including one or more instructions with memory operands, wherein responsive to an interrupt or an exception, the instruction processing circuitry is to pause processing the plurality of instructions and execute a handler; and decode circuitry to partially decode a next instruction of the plurality of instructions to be processed following execution of the handler to determine if the next instruction indicates a memory access and, if so, to calculate at least one corresponding memory address, wherein the partial decode is performed in accordance with one or more constant time programming restrictions.
Inventor(s): Daniel Biederman of Saratoga CA (US) for intel corporation, Yadong Li of Portland OR (US) for intel corporation, Hemant Koka of Lathrop CA (US) for intel corporation, Jackson Ellis of Fort Collins CO (US) for intel corporation, Salma Johnson of Littleton MA (US) for intel corporation
IPC Code(s): G06F21/60, G06F21/78
CPC Code(s): G06F21/602
Abstract: an apparatus is disclosed that includes a network interface device comprising processors to implement network interface device functionality and communication protocol engine circuitry, wherein the network interface device is to: receive a request to write data to a memory node communicably coupled to the network interface device; identify network information corresponding to the request, wherein the network information includes at least one of quality of service (qos), physical function (pf), virtual function (vf), name space identifier (nsid), flow id, service level objectives (slos), or process address space id (pasid); identify characteristics of the memory node, wherein the characteristics include at least page size of the memory node; and cause the data to be coalesced with other data on the memory node based on the network information and the characteristics.
Inventor(s): Alexander Kozlov of Dubai (AE) for intel corporation, Liubov Talamanova of Dun Laoghaire (IE) for intel corporation, Yury Gorbachev of Dubai (AE) for intel corporation
IPC Code(s): G06F40/284, G06F12/126
CPC Code(s): G06F40/284
Abstract: systems, apparatus, articles of manufacture, and methods are disclosed to evict tokens from a key value cache. an example apparatus includes interface circuitry, machine readable instructions, and programmable circuitry to at least one of instantiate or execute the machine readable instructions to: determine score history values for tokens based on attention scores associated with the tokens, wherein a token is a numerical representation of text, after a number of tokens present in the key value cache exceeds a threshold number of tokens, compute group importance scores for groups of tokens based on score history values of the tokens in the groups of tokens, identify low-ranked groups of tokens having lowest group importance scores, the low-ranked groups of tokens associated with an eviction range in the key value cache, and remove an identified low-ranked group of tokens from the eviction range of the key value cache.
Inventor(s): Arnab Raha of San Jose CA (US) for intel corporation, Debabrata Mohapatra of San Jose CA (US) for intel corporation, Gautham Chinya of Sunnyvale CA (US) for intel corporation, Guruguhanathan Venkataramanan of Livermore CA (US) for intel corporation, Sang Kyun Kim of San Jose CA (US) for intel corporation, Deepak Mathaikutty of Chandler AZ (US) for intel corporation, Raymond Sung of San Francisco CA (US) for intel corporation, Cormac Brick of San Francisco CA (US) for intel corporation
IPC Code(s): G06N3/063, G06F9/30, G06N3/04
CPC Code(s): G06N3/063
Abstract: embodiments of the present disclosure are directed toward techniques and configurations enhancing the performance of hardware (hw) accelerators. disclosed embodiments include static mac scaling arrangement, which includes architectures and techniques for scaling the performance per unit of power and performance per area of hw accelerators. disclosed embodiments also include dynamic mac scaling arrangement, which includes architectures and techniques for dynamically scaling the number of active multiply-and-accumulate (mac) within an hw accelerator based on activation and weight sparsity. other embodiments may be described and/or claimed.
Inventor(s): Andrei Anufriev of Taufkirchen (DE) for intel corporation, Alexander Kozlov of Dubai (AE) for intel corporation, Yury Gorbachev of Novgorod (RU) for intel corporation
IPC Code(s): G06N20/00
CPC Code(s): G06N20/00
Abstract: systems, apparatuses and methods may provide for technology that accesses a pre-trained artificial intelligence (ai) model, quantizes a plurality of weights of the pre-trained ai model to generate a compressed ai model, and applies normalization correction to the compressed ai model to generate an output ai model.
Inventor(s): Jiasheng Chen of El Dorado Hills CA (US) for intel corporation, Supratim Pal of Folsom CA (US) for intel corporation, Kevin Hurd of Flagler Beach FL (US) for intel corporation, Jorge E. Parra Osorio of El Dorado Hills CA (US) for intel corporation, Christopher Spencer of Chuluota FL (US) for intel corporation, Takashi Nakagawa of Folsom CA (US) for intel corporation, Guei-Yuan Lueh of San Jose CA (US) for intel corporation, Pradeep K. Golconda of El Dorado Hills CA (US) for intel corporation, James Valerio of North Plains OR (US) for intel corporation, Mukundan Swaminathan of San Ramon CA (US) for intel corporation, Nicholas Murphy of The Sands (GB) for intel corporation, Clifford Gibson of Hertfordshire (GB) for intel corporation, Li-An Tang of El Dorado Hills CA (US) for intel corporation, Fangwen Fu of Folsom CA (US) for intel corporation, Kaiyu Chen of San Jose CA (US) for intel corporation, Buqi Cheng of San Jose CA (US) for intel corporation
IPC Code(s): G06T15/00, G06F9/30
CPC Code(s): G06T15/005
Abstract: described herein is a graphics processor comprising an instruction cache and a plurality of processing elements coupled with the instruction cache. the plurality of processing elements include functional units configured to provide an integer pipeline to execute instructions to perform operations on integer data elements. the integer pipeline including a first multiplier and a second multiplier, the first multiplier and the second multiplier configured to execute operations for a single instruction.
Inventor(s): Prasoonkumar Surti of Folsom CA (US) for intel corporation, Abhishek R. Appu of El Dorado Hills CA (US) for intel corporation, Joydeep Ray of Folsom CA (US) for intel corporation
IPC Code(s): G06T15/50, G06T1/60, G06T11/20, G06T11/40, G06T15/80
CPC Code(s): G06T15/503
Abstract: systems, apparatuses and methods may provide for technology that selects an anti-aliasing mode for a vertex of a primitive based on a parameter associated with the vertex and generates a coverage mask based on the selected anti-aliasing mode. additionally, one or more pixels corresponding to the vertex may be shaded based at least partly on the coverage mask, wherein the selected anti-aliasing mode varies across a plurality of vertices in the primitive.
Inventor(s): Rita Chattopadhyay of Chandler AZ (US) for intel corporation, Atul Divekar of Folsom CA (US) for intel corporation
IPC Code(s): G06V20/64, G06V10/771, G06V10/82
CPC Code(s): G06V20/64
Abstract: example systems, apparatus, articles of manufacture, and methods to detect and locate objects in three-dimensional (3d) point clouds are disclosed. examples apparatus disclosed herein apply at least one of a template or a mask at a sample point of an overhead view of a 3d point cloud to identify a candidate cluster of points in the 3d point cloud, the candidate cluster to satisfy an occupancy target. disclosed example apparatus also input the candidate cluster to a neural network, the neural network trained to output a feature vector for the candidate cluster. disclosed example apparatus further process the feature vector to output parameters associated with an object classification and a bounding box for an object corresponding to the candidate cluster.
20250038114. ELECTRICAL INTERCONNECT BRIDGE_simplified_abstract_(intel corporation)
Inventor(s): Srinivas V. PIETAMBARAM of Gilbert AZ (US) for intel corporation, Rahul N. MANEPALLI of Chandler AZ (US) for intel corporation
IPC Code(s): H01L23/538, H01L21/48, H01L23/00, H01L23/498, H01L25/065
CPC Code(s): H01L23/5381
Abstract: electrical interconnect bridge technology is disclosed. an electrical interconnect bridge can include a bridge substrate formed of a mold compound material. the electrical interconnect bridge can also include a plurality of routing layers within the bridge substrate, each routing layer having a plurality of fine line and space (fls) traces. in addition, the electrical interconnect bridge can include a via extending through the substrate and electrically coupling at least one of the fls traces in one of the routing layers to at least one of the fls traces in another of the routing layers.
Inventor(s): Zhichao ZHANG of Chandler AZ (US) for intel corporation, Kemal AYGÜN of Tempe AZ (US) for intel corporation, Suresh V. POTHUKUCHI of Chandler AZ (US) for intel corporation, Xiaoqian LI of Chandler AZ (US) for intel corporation, Omkar KARHADE of Chandler AZ (US) for intel corporation
IPC Code(s): H01L25/18, G02B6/42, H01L23/373, H01L23/538, H01L25/00
CPC Code(s): H01L25/18
Abstract: embodiments described herein may be related to apparatuses, processes, and techniques related to disaggregating co-packaged soc and photonic integrated circuits on an multichip package. the photonic integrated circuits may also be silicon photonics engines. in embodiments, multiple socs and photonic integrated circuits may be electrically coupled, respectively, into modules, with multiple modules then incorporated into an mcp using a stacked die structure. other embodiments may be described and/or claimed.
Inventor(s): Duanni Huang of San Jose CA (US) for intel corporation, Haisheng Rong of Pleasanton CA (US) for intel corporation, Xinru Wu of San Jose CA (US) for intel corporation
IPC Code(s): H01S5/40, H01S5/00, H01S5/06, H01S5/125
CPC Code(s): H01S5/4087
Abstract: integrated photonic devices, packages, and systems are disclosed. an example photonic device includes a laser device with a laser cavity having three sections. the three sections include, respectively, an active region, a waveguide, and a grating arranged along a longitudinal axis of the cavity. materials of these three sections of the laser device are selected so that a toc of the grating is between a toc of the active region and a toc of the waveguide.
Inventor(s): Pawel Trella of Gdansk (PL) for intel corporation, Przemyslaw Maziewski of Gdansk (PL) for intel corporation, Damian Koszewski of Gdansk (PL) for intel corporation, Jan Banas of Gdansk (PL) for intel corporation, Piotr Klinke of Szczecin (PL) for intel corporation, Maciej Kuklinowski of Gdansk (PL) for intel corporation
IPC Code(s): H04K3/00
CPC Code(s): H04K3/42
Abstract: a system, article, device, apparatus, and method of audio processing comprises receiving, by processor circuitry, audible audio signal data of intermodulation distortion products (idps) based on ultrasonic audio signals received by at least one microphone of an audio device. the method also compares the audible audio signal data to ultrasonic audio signal data of the ultrasonic audio signals. thereafter, the method determines a plurality of susceptibility values each of a different ultrasonic frequency based on the comparing, wherein the plurality of susceptibility values represent an ultrasonic attack susceptibility of the audio device.
Inventor(s): Shahar Gross of Nes-Tziona (IL) for intel corporation, Eyal Tzabar of Rosh Haayin (IL) for intel corporation, Slava Vaysman of Nazareth Illit (IL) for intel corporation, Shlomi Vituri of Tel Aviv (IL) for intel corporation
IPC Code(s): H04L27/26
CPC Code(s): H04L27/2614
Abstract: techniques are disclosed for determining customized frequency rotation values for a number of wireless channel configurations. the channel configurations may define various parameters of a wireless channel in accordance with a communication protocol, such as the channel bandwidth, the number of sub-channels, and which of the sub-channels may be punctured. the frequency rotation values may be obtained by determining the peak to average power ratio (papr) values for different combinations of frequency rotation values that are applied to the sub-channels of the wireless channel on a per-configuration basis. thus, for each configuration, the lowest maximum papr or other suitable threshold value may be used to identify the frequency rotation values for that particular configuration. the frequency rotation values may then be applied at run time based upon the current wireless channel configuration for data transmissions via the wireless channel.
20250039041. Blockchains For Securing IoT Devices_simplified_abstract_(intel corporation)
Inventor(s): Ned M. Smith of Beaverton OR (US) for intel corporation, Keith Nolan of Mullingar (IE) for intel corporation, Mark Kelly of Leixlip (IE) for intel corporation, Michael Nolan of Maynooth (IE) for intel corporation, John Brady of Celbridge (IE) for intel corporation, Thiago Macieira of Hillsboro OR (US) for intel corporation, Zheng Zhang of Portland OR (US) for intel corporation, Glen J. Anderson of Beaverton OR (US) for intel corporation, Igor Muttik of Aylesbury (GB) for intel corporation
IPC Code(s): H04L41/0806, G06F16/182, H04L9/00, H04L9/08, H04L9/32, H04L41/12, H04L45/00, H04L61/4505, H04L61/5069, H04L67/10, H04L67/104, H04L67/1087, H04L67/12, H04L67/562, H04L69/18, H04L69/22, H04W4/08, H04W4/70, H04W12/69, H04W84/18, H04W84/22
CPC Code(s): H04L41/0806
Abstract: a trusted communications environment includes a primary participant with a group creator and a distributed ledger, and a secondary participant with communication credentials. an internet of things (iot) network includes a trusted execution environment with a chain history for a blockchain, a root-of-trust for chaining, and a root-of-trust for archives. an iot network includes an iot device with a communication system, an onboarding tool, a device discoverer, a trust builder, a shared domain creator, and a shared resource directory. an iot network includes an iot device with a communication system, a policy decision engine, a policy repository, a policy enforcement engine, and a peer monitor. an iot network includes an iot device with a host environment and a trusted reliability engine to apply a failover action if the host environment fails. an iot network includes an iot server including secure booter/measurer, trust anchor, authenticator, key manager, and key generator.
20250039086. PACKET ROUTING IN A SWITCH_simplified_abstract_(intel corporation)
Inventor(s): Mitu AGGARWAL of Portland OR (US) for intel corporation, Robert VALIQUETTE of Carignan (CA) for intel corporation, Grzegorz NITKA of Gdansk (PL) for intel corporation, Lukasz KUPCZAK of Kraków (PL) for intel corporation
IPC Code(s): H04L45/74
CPC Code(s): H04L45/74
Abstract: examples described herein relate to a switch circuitry that includes an interface to a first ingress port; an interface to a second ingress port; and circuitry. in some examples, the circuitry is to associate the first ingress port with a first virtual function (vf); associate the second ingress port with a second vf; and based on a configuration and receipt of a first packet at the first ingress port, cause the first packet to be filtered, wherein the first packet is addressed to the second vf.
Inventor(s): Dan HOROVITZ of Rishon Lezion (IL) for intel corporation, Ilil BLUM SHEM-TOV of Kiryat Tivon (IL) for intel corporation, Yoni KAHANA of Kfar Hess (IL) for intel corporation, Yaron KLEIN of Rosh Haayin (IL) for intel corporation, Assaf GUREVITZ of Ramat Hasharon (IL) for intel corporation
IPC Code(s): H04L9/40, H04B7/06, H04L41/16
CPC Code(s): H04L63/107
Abstract: provided is a method for location-based access control in a wireless network. the location of a user device is determined based on a channel state information (csi) matrix of the user device as trusted or untrusted. based on the trust state, which is trusted or untrusted, of the user device, access control is performed. in some examples, in order to determine the trust state of the user device, the csi matrix of the user device needs to be input into a machine learning model or be compared with csi matrices corresponding to multiple trusted locations using a similarity measure. because the access control is based on the location of the user device, the conveniency and accuracy of the access control could be better than that made by some other security measures, such as password-based mechanisms.
Inventor(s): Jithin Valappilekandy of Bangalore (IN) for intel corporation, Smit Kapila of Bangalore (IN) for intel corporation, Sangeeta Manepalli of Chandler AZ (US) for intel corporation, Balvinder Pal Singh of Bhilai (IN) for intel corporation, Abhishek Srivastav of Bangalore (IN) for intel corporation
IPC Code(s): H04L65/1069, H04W4/80
CPC Code(s): H04L65/1069
Abstract: this disclosure describes systems, methods, and devices for remotely controlling device settings for collaboration sessions. a device may identify an alphanumeric handle based on a location identifier of a first location associated with the device and a collaboration session identifier for a collaboration session of a collaboration application executed by the device; generate a bluetooth low energy (ble) advertising packet including a header and a payload, the header including the alphanumeric handle and a hardware identifier that identifies the device; transmit the ble advertising packet; identify an authentication request received from a second device in the collaboration session, the authentication request including the alphanumeric handle; authenticate the second device based on the alphanumeric handle; and transmit a ble notification packet including an indication of a volume at which the second device is to set a speaker for the collaboration session.
Inventor(s): Amin NURUDDIN of Folsom CA (US) for intel corporation, Hiu-Fai CHAN of Rancho Cordova CA (US) for intel corporation
IPC Code(s): H04N19/96, H04N19/169, H04N19/176, H04N19/186, H04N19/80
CPC Code(s): H04N19/96
Abstract: this disclosure describes systems, methods, and devices related to enhanced video coding. a device may receive encoded bitstream data of a frame with multiple tiles. the device may divide each tile into multiple coding tree units (ctus). the device may decode luma and chroma pixels of each ctu using either a single-tree mode or a dual-tree mode. the device may execute a cross-component linear model (cclm) prediction to predict chroma pixels based on decoded luma pixels. the device may store the decoded luma pixels and the predicted chroma pixels in a storage.
Inventor(s): Han Wui THEN of Portland OR (US) for intel corporation, Marko RADOSAVLJEVIC of Portland OR (US) for intel corporation, Pratik KOIRALA of Portland OR (US) for intel corporation, Nicole K. THOMAS of Portland OR (US) for intel corporation, Paul B. FISCHER of Portland OR (US) for intel corporation, Adel A. ELSHERBINI of Chandler AZ (US) for intel corporation, Tushar TALUKDAR of Willsonville OR (US) for intel corporation, Johanna M. SWAN of Scottsdale AZ (US) for intel corporation, Wilfred GOMES of Portland OR (US) for intel corporation, Robert S. CHAU of Beaverton OR (US) for intel corporation, Beomseok CHOI of Chandler AZ (US) for intel corporation
IPC Code(s): H01L27/06, H01L21/765, H01L23/00, H01L23/48, H01L23/498, H01L23/64, H01L25/00, H01L25/065, H01L27/092, H01L29/06, H01L29/20, H01L29/205, H01L29/40, H01L29/423, H01L29/66, H01L29/778, H01L29/786
CPC Code(s): H01L27/0605
Abstract: gallium nitride (gan) three-dimensional integrated circuit technology is described. in an example, an integrated circuit structure includes a layer including gallium and nitrogen, a plurality of gate structures over the layer including gallium and nitrogen, a source region on a first side of the plurality of gate structures, a drain region on a second side of the plurality of gate structures, the second side opposite the first side, and a drain field plate above the drain region wherein the drain field plate is coupled to the source region. in another example, a semiconductor package includes a package substrate. a first integrated circuit (ic) die is coupled to the package substrate. the first ic die includes a gan device layer and a si-based cmos layer.
- Intel Corporation
- G01B9/02015
- CPC G01B9/02027
- Intel corporation
- G01S13/88
- G01S13/36
- H04B1/3827
- CPC G01S13/88
- G02B6/12
- G02B6/122
- G02B6/125
- G02B6/136
- CPC G02B6/12004
- G06F1/08
- G06F12/02
- CPC G06F1/08
- G06F1/3228
- G06F9/48
- CPC G06F1/3228
- G06F7/483
- CPC G06F7/483
- G06F9/30
- G06F9/38
- CPC G06F9/30192
- G06F9/46
- G06F9/50
- G06F9/52
- G06F9/54
- G06F12/0842
- G06F12/0866
- G06F12/0897
- G06F15/16
- G06F15/76
- G06T1/20
- G06T1/60
- CPC G06F9/46
- H04L67/10
- H04L67/12
- CPC G06F9/5061
- G06F15/78
- H04L45/60
- H04L49/109
- CPC G06F15/7825
- G06F16/22
- G06N20/00
- CPC G06F16/2237
- G06F21/54
- G06F21/55
- CPC G06F21/54
- G06F21/60
- G06F21/78
- CPC G06F21/602
- G06F40/284
- G06F12/126
- CPC G06F40/284
- G06N3/063
- G06N3/04
- CPC G06N3/063
- CPC G06N20/00
- G06T15/00
- CPC G06T15/005
- G06T15/50
- G06T11/20
- G06T11/40
- G06T15/80
- CPC G06T15/503
- G06V20/64
- G06V10/771
- G06V10/82
- CPC G06V20/64
- H01L23/538
- H01L21/48
- H01L23/00
- H01L23/498
- H01L25/065
- CPC H01L23/5381
- H01L25/18
- G02B6/42
- H01L23/373
- H01L25/00
- CPC H01L25/18
- H01S5/40
- H01S5/00
- H01S5/06
- H01S5/125
- CPC H01S5/4087
- H04K3/00
- CPC H04K3/42
- H04L27/26
- CPC H04L27/2614
- H04L41/0806
- G06F16/182
- H04L9/00
- H04L9/08
- H04L9/32
- H04L41/12
- H04L45/00
- H04L61/4505
- H04L61/5069
- H04L67/104
- H04L67/1087
- H04L67/562
- H04L69/18
- H04L69/22
- H04W4/08
- H04W4/70
- H04W12/69
- H04W84/18
- H04W84/22
- CPC H04L41/0806
- H04L45/74
- CPC H04L45/74
- H04L9/40
- H04B7/06
- H04L41/16
- CPC H04L63/107
- H04L65/1069
- H04W4/80
- CPC H04L65/1069
- H04N19/96
- H04N19/169
- H04N19/176
- H04N19/186
- H04N19/80
- CPC H04N19/96
- H01L27/06
- H01L21/765
- H01L23/48
- H01L23/64
- H01L27/092
- H01L29/06
- H01L29/20
- H01L29/205
- H01L29/40
- H01L29/423
- H01L29/66
- H01L29/778
- H01L29/786
- CPC H01L27/0605
