Intel Corporation patent applications on January 2nd, 2025
Patent Applications by Intel Corporation on January 2nd, 2025
Intel Corporation: 160 patent applications
Intel Corporation has applied for patents in the areas of H01L23/00 (17), H01L25/065 (14), H01L29/775 (13), H01L29/423 (13), H01L29/06 (13) H01L23/49822 (5), H01L23/66 (3), H01L23/15 (3), H01L29/78391 (3), H01L23/544 (3)
With keywords such as: layer, circuit, material, data, device, include, circuitry, coupled, structure, and having in patent application abstracts.
Patent Applications by Intel Corporation
Inventor(s): Javier Sebastian Turek of Beaverton OR (US) for intel corporation, Leobardo Campos Macias of Guadalajara (MX) for intel corporation, Javier Felip Leon of Hillsboro OR (US) for intel corporation
IPC Code(s): B25J9/16
CPC Code(s): B25J9/1661
Abstract: techniques are disclosed for task error correction for robots, such as collaborative robots (cobots). a controller of a robot may include an error detector to detect an error in a performance of a human-robot collaborative task, and an error corrector to correct the detected error. the error corrector may include a correction planner and a facilitator. the correction planner may determine an error correction plan based on the detected error. the error correction plan may include corrective subtasks to control the cobot to correct the detected error. the facilitator may determine a facilitation plan based on the determined error correction plan. the facilitation plan including an assistance subtask configured to control the cobot to assist a human operator in correcting the detected error. the error corrector may generate a control signal to control the cobot based on the correction plan and the facilitation plan.
Inventor(s): Javier Felip Leon of Hillsboro OR (US) for intel corporation, David Gomez Gutierrez of Tlaquepaque (MX) for intel corporation, Rafael De La Guardia Gonzalez of Guadalajara (MX) for intel corporation, David Gonzalez Aguirre of Portland OR (US) for intel corporation, Leobardo Campos Macias of Guadalajara (MX) for intel corporation
IPC Code(s): B25J9/16
CPC Code(s): B25J9/1679
Abstract: various aspects of techniques, systems, and use cases may be used for probabilistic automatic determination of an action for a robotic device. a technique may include identifying a current context of a robotic device, determining from the current context, a set of actions performable by the robotic device corresponding to at least one object, the set of actions including one or more affordances generated from a basic skills library for the robotic device, and automatically selecting an action of the set of actions based on an acyclic graph describing action paths. the technique may include outputting control signals that, when executed, cause the robotic device to perform the action to interact with the at least one object.
Inventor(s): David Gonzalez Aguirre of Portland OR (US) for intel corporation
IPC Code(s): B25J9/16, B25J15/12, G06T7/215, G06T7/80
CPC Code(s): B25J9/1697
Abstract: a robotic system, including: a robot having an arm with a multi-fingered soft gripper that is formed of a compliant material; an image sensor fixedly mounted on the arm to move with the multi-fingered soft gripper, and operable to capture image data of the multi-fingered soft gripper composed of a compliant material; and processor circuitry operable to generate a model of a state of the multi-fingered soft gripper by: controlling the arm to move in a predefined motion pattern while the image sensor captures the image data; deriving an optical flow based on the image data and consecutive arm kinematic and velocity frame states; and segmenting between a multi-fingered soft gripper portion and a background portion of the image data based on the optical flow, wherein static regions of the optical flow represent the multi-fingered soft gripper portion, dynamic regions of the optical flow represent the background portion, and non-coherent regions of the optical flow represent contour between the multi-fingered soft gripper portion and the background portion of the image data.
Inventor(s): Abhishek SRIVASTAV of Bangalore (IN) for intel corporation, Smit KAPILA of Bangalore (IN) for intel corporation, Pawel TRELLA of Gdansk (PL) for intel corporation, Jeff KU of Taipei (TW) for intel corporation, Prakash KURMA RAJU of Bangalore (IN) for intel corporation, Dominik STANCZAK of Gdansk (PL) for intel corporation
IPC Code(s): F04D29/46, F04D29/42, F04D29/58
CPC Code(s): F04D29/464
Abstract: an apparatus and system for reducing air turbulence in a fan using a flow shaper. the fan including an impeller, a first outlet, and a second outlet. the flow shaper including a partition structure arranged at an inflection area between the first outlet and the second outlet. the flow shaper further including a first fin for the first outlet defining a first channel between the partition structure and the first fin. the first channel extending from a proximity of the impeller to the first outlet.
Inventor(s): Juha Paavola of Hillsboro OR (US) for intel corporation, Kari Mansukoski of Hillsboro OR (US) for intel corporation, Sami Heinisuo of Dallas OR (US) for intel corporation
IPC Code(s): F28D15/04, F28D15/02
CPC Code(s): F28D15/046
Abstract: techniques are disclosed for manufacturing a heat pipe that includes a variable wall thickness and/or a variable diameter. the heat pipe may be formed by subjecting a pipe to a thickness processing and an expansion processing. the heat pipe may include a first portion and a second portion. the first portion may have a first diameter and a first wall thickness. the second portion may have a second diameter larger than the first diameter, and a second wall thickness larger than the first wall thickness.
Inventor(s): Krzysztof DOMANSKI of Neubiberg (DE) for intel corporation, Manhar MUDDU of Vijayawada (IN) for intel corporation
IPC Code(s): G01R31/26
CPC Code(s): G01R31/2621
Abstract: a non-transitory computer readable medium is provided. the non-transitory computer readable medium having instructions stored therein that when executed by a processor cause the processor to: receive current information of a semiconductor device, calculate an absolute current value of the semiconductor device from the current information and compare the absolute current value with a first threshold; receive information regarding a duration of a forward bias of the semiconductor device and compare the duration with a second threshold if the absolute current value is more than the first threshold; perform a layout review of tap spacing of selected semiconductor device components; and output safe operation area (soa) information indicating a forward bias junction result based on the absolute current value, the duration of forward bias and the layout review.
Inventor(s): Vijay HOSAMANI of Bangalore (IN) for intel corporation, Vikas Mishra of Chandler AZ (US) for intel corporation, Kavitha Nagarajan of Bangalore (IN) for intel corporation, Zaman Zaid Mulla of Mumbai (IN) for intel corporation
IPC Code(s): G01R31/28, H05K1/02
CPC Code(s): G01R31/2896
Abstract: the present disclosure generally relates to an electronic system including a semiconductor package and a circuit board. the semiconductor package and the circuit board may include contact structures configurable to have an output terminal of one contact structure connected to an input terminal of another contact structure so as to render a continuous electrical pathway through the contact structures, wherein the contact structures may be configured in a daisy chain manner forming a series connection, and wherein the continuous electrical pathway may render an output pattern in response to an electrical stimulus introduced to the electronic system.
Inventor(s): Rakesh Kandula of Bangalore (IN) for intel corporation
IPC Code(s): G01R31/28
CPC Code(s): G01R31/2896
Abstract: systems, apparatus, articles of manufacture, and methods are disclosed to perform infield testing of a system in a package. an example die includes transmit circuits to communicate via respective communication channels and control circuitry to cause a first one of the transmit circuits to send a first pattern over a first one of the communication channels. additionally, the example control circuitry is to cause second ones of the transmit circuits to respectively send a second pattern over second respective ones of the communication channels, the second pattern being at least one of an inverse of the first pattern or identical to the first pattern.
20250004121. High End Imaging Radar_simplified_abstract_(intel corporation)
Inventor(s): Arnaud AMADJIKPE of Beaverton OR (US) for intel corporation, Timo Sakari HUUSARI of Hillsboro OR (US) for intel corporation, Tae Young YANG of Portland OR (US) for intel corporation, Hossein ALAVI of Portland OR (US) for intel corporation, Steven CALLENDER of Denver CO (US) for intel corporation, Bradley JACKSON of Hillsboro OR (US) for intel corporation, Ofer MARKISH of Ra'anana (IL) for intel corporation, Woorim SHIN of Portland OR (US) for intel corporation, Shengbo XU of Newark CA (US) for intel corporation, Zhen ZHOU of Chandler AZ (US) for intel corporation, Wei QIAN of Walnut CA (US) for intel corporation, Mengyuan HUANG of Cupertino CA (US) for intel corporation
IPC Code(s): G01S13/42, G01S7/35, G01S13/89
CPC Code(s): G01S13/426
Abstract: disclosed herein is a lens antenna system that includes a reconfigurable aperture configured to receive a source beam. the reconfigurable aperture also provides an output beam based on a surface impedance distribution of the reconfigurable aperture and the received source beam. the control device is operatively coupled to the reconfigurable aperture, wherein the control device is configured to control the surface impedance distribution of the reconfigurable aperture to configure and reconfigure a beam pattern of the output beam. a plurality of antenna elements may be physically positioned proximate the reconfigurable aperture, wherein the plurality of antennas may be configured to generate the source beam.
Inventor(s): Jianyong Mo of Chandler AZ (US) for intel corporation, Fan Fan of Chandler AZ (US) for intel corporation, Liang Zhang of Chandler AZ (US) for intel corporation
IPC Code(s): G02B6/26, G02B3/00
CPC Code(s): G02B6/262
Abstract: technologies for beam expansion in monolithic glass substrates are disclosed. in an illustrative embodiment, lenses in a glass substrate may be formed using a laser, either by changing the index of refraction or as part of a two-step etching process. a seam may be prepared and etched, separating the glass substrate into two components, one of which will be part of an optical plug and one of which will be part of an optical receptacle. the optical plug has a cavity into which an optical fiber can be placed. in use, the lens in the glass substrate of the optical plug collimates light from the optical fiber into a beam. when the optical plug is mated with the optical receptacle, the beam is aligned to the lens and a waveguide in the optical receptacle. the large size of the beam relaxes the alignment tolerance for the optical plug and receptacle.
Inventor(s): Dekang CHEN of Chandler AZ (US) for intel corporation, Nicholas PSAILA of Lanark (GB) for intel corporation, Zhichao ZHANG of Chandler AZ (US) for intel corporation, Eric J.M. MORET of Beaverton OR (US) for intel corporation, Wesley B. MORGAN of Lake Oswego OR (US) for intel corporation, Srikant NEKKANTY of Chandler AZ (US) for intel corporation, Sang Yup KIM of Sunnyvale CA (US) for intel corporation, Mohanraj PRABHUGOUD of Beaverton OR (US) for intel corporation, Chao TIAN of Bozeman MT (US) for intel corporation
IPC Code(s): G02B6/27, G02B6/42
CPC Code(s): G02B6/2746
Abstract: multichannel optical assemblies for optical io (input output) systems are provided. the optical assemblies comprise an optical isolator. in some examples the optical assemblies also comprise an array of grin lenses. in other examples, the optical assemblies also comprise micromirrors.
Inventor(s): Chia-Pin Chiu of Tempe AZ (US) for intel corporation, Tim T. Hoang of San Jose CA (US) for intel corporation, Kaveh Hosseini of Livermore CA (US) for intel corporation, Omkar G. Karhade of Chandler AZ (US) for intel corporation
IPC Code(s): G02B6/30, G02B6/42
CPC Code(s): G02B6/30
Abstract: in one embodiment, an integrated circuit package includes a first (top) package substrate, a photonics integrated circuit (pic) die coupled to the first package substrate, and a second package substrate coupled to a bottom side of the first package substrate. the package further includes a pedestal coupled to a top side of the second package substrate in an area of the second package substrate that extends beyond an edge of the first package substrate at which the pic die is located.
Inventor(s): Nicholas D. Psaila of Lanark (GB) for intel corporation
IPC Code(s): G02B6/42, G02B6/02
CPC Code(s): G02B6/4214
Abstract: technologies for hybrid optical chip-to-chip coupling are disclosed. in an illustrative embodiment, light from a waveguide in a photonic integrated circuit (pic) die is collimated using a micromirror and directed towards a glass substrate. another micromirror in the glass substrate focuses the light into a waveguide defined in a bulk layer of the glass substrate. in the illustrative embodiment, the waveguide is directly written into the bulk layer using an ultrafast laser. the glass substrate also has waveguides with a large difference in the index of refraction in a layer above the bulk substrate, such as silicon nitride waveguides in silicon oxide cladding. the directly-written waveguides can be evanescently coupled to the silicon nitride waveguides. the silicon nitride waveguides can then be used for two-dimensional routing throughout the glass substrate. the light can be coupled back into a directly-written waveguide before it is transmitted to another pic die.
Inventor(s): Waiyapot Suttawassuntorn of Nonthaburi (TH) for intel corporation, Young Seok Oh of Palo Alto CA (US) for intel corporation, Aggachai Sooksai of Bang Pa-In (TH) for intel corporation, Nathaphol Jarupongvanich of Pathumthani (TH) for intel corporation
IPC Code(s): G02B6/42, G02B6/02
CPC Code(s): G02B6/4227
Abstract: systems, apparatus, articles of manufacture, and methods to facilitate alignment of optical components are disclosed. an example apparatus includes programmable circuitry to at least one of instantiate or execute the machine readable instructions to: monitor optical power outputs of different cores in a linear array of cores in a multi-core optical fiber as a lens is moved relative to the multi-core optical fiber. the optical power outputs are based on light that is emitted from a photonic integrated circuit and passes through the lens. the programmable circuitry is to determine a final position for the lens relative to the photonic integrated circuit based on the optical power outputs.
Inventor(s): Dowon Kim of Singapore (SG) for intel corporation, Archana Ashok of Chandler AZ (US) for intel corporation, Suohai Mei of Sunnyvale CA (US) for intel corporation
IPC Code(s): G02B6/42
CPC Code(s): G02B6/4233
Abstract: architecture and method for passive-active optical alignment of photonic integrated circuit (pic) and an optical connector or fiber array unit (fau). v-grooves are created on the surface of the pic die and features are created on the fau to extend from the fau into the respective v-grooves. the passive alignment aspect includes using moderate precision pick and place equipment to place the fau connector on the pic die and mate the features into the v-grooves (i.e., assembling one or more sliding joints). the sliding joints limit movement between the components to a single degree of freedom. the active alignment aspect of the present disclosure includes manipulating the sliding joint, in the available degree of freedom, to actively search for the optimal optical power in optical coupling between the fau and the pic die.
Inventor(s): Sufi R. Ahmed of Chandler AZ (US) for intel corporation, Shan Zhong of Chandler AZ (US) for intel corporation, Eric J. M. Moret of Beaverton OR (US) for intel corporation, Yang Wu of Chandler AZ (US) for intel corporation
IPC Code(s): G02B6/42
CPC Code(s): G02B6/4243
Abstract: photonic integrated circuits and optical couplers with improved process tolerance, and methods of forming the same, are disclosed herein. in one example, an integrated circuit package includes a photonic integrated circuit (pic) to send or receive optical signals and an optical coupler to optically couple the pic to one or more optical fibers. the pic includes a first interface with at least two recesses and one or more grooves positioned between the recesses, and the optical coupler includes a second interface with at least two protrusions and one or more ridges positioned between the protrusions (or vice versa). the protrusions on the optical coupler are mated with the recesses on the pic, and the ridges on the optical coupler are mated with the grooves on the pic.
Inventor(s): Debabani Choudhury of Thousand Oaks CA (US) for intel corporation, Huimin Chen of Beaverton OR (US) for intel corporation, Eric Gantner of Portland OR (US) for intel corporation, Stephen Hall of Middleton ID (US) for intel corporation, Cooper Levy of Portland OR (US) for intel corporation, Shawn Mceuen of Portland OR (US) for intel corporation, Luis Paniagua Acuna of Alajuela (CR) for intel corporation, Peter Sagazio of Portland OR (US) for intel corporation, Harry Skinner of Beaverton OR (US) for intel corporation, Kerry Stevens of Beaverton OR (US) for intel corporation, Ana Yepes of Portland OR (US) for intel corporation
IPC Code(s): G02B6/42, G02B6/44
CPC Code(s): G02B6/4279
Abstract: a rotatable circular waveguide structure is described that may comprise circular waveguide sections configured to propagate electromagnetic radiation. the circular waveguide sections may enable data signals to be transmitted between portions of an electronic device, such as a chassis and display portion, which may be rotatable with respect to one another. the rotatable circular waveguide structure may comprise one or more circular waveguide sections that are routed through a hinge of the electronic device, as well as one or more rotatable junctions. the rotatable junctions enable a rotation of circular waveguide sections with respect to one another as the coupled portions of the electronic device are also rotated. the rotatable circular waveguide structure may replace the use of data cables that are conventionally used to carry data signals between portions of an electronic device.
Inventor(s): Xiaoqian Li of Chandler AZ (US) for intel corporation, Vidya Jayaram of Chandler AZ (US) for intel corporation, Ravindranath V. Mahajan of Chandler AZ (US) for intel corporation, Saikumar Jayaraman of Chandler AZ (US) for intel corporation
IPC Code(s): G02B6/42
CPC Code(s): G02B6/428
Abstract: an apparatus comprising an interposer to couple conductive contacts of a substrate to conductive contacts of an integrated circuit device, wherein the interposer comprises a cavity proximate conductive contacts of the interposer, the conductive contacts of the interposer to couple to conductive contacts of a photonics integrated circuit (pic).
Inventor(s): Mohanraj Prabhugoud of Beaverton OR (US) for intel corporation, David Shia of Portland OR (US) for intel corporation, Tarek A. Ibrahim of Mesa AZ (US) for intel corporation, Yuxin Fang of Chandler AZ (US) for intel corporation
IPC Code(s): G02B6/42
CPC Code(s): G02B6/4292
Abstract: technologies for substrate features for a pluggable optical connectors in an integrated circuit package are disclosed. in the illustrative embodiment, a substrate includes a cavity cut through a substrate of the integrated circuit package. sidewalls of the cavity establish coarse lateral alignment features for an optical plug. the optical plug and optical socket include additional alignment features to more precisely align optical fibers in the optical plug to an optical interposer mounted on the substrate. the cavity cut through the substrate may also include indents that can mate with protrusions of the optical plug to retain the optical plug. the optical interposer may be mounted on a recessed shelf in the substrate.
20250004227. ADAPTERS FOR HETEROGENOUS OPTICAL CONNECTORS_simplified_abstract_(intel corporation)
Inventor(s): Wesley B. Morgan of Lake Oswego OR (US) for intel corporation, Sufi R. Ahmed of Chandler AZ (US) for intel corporation
IPC Code(s): G02B6/42
CPC Code(s): G02B6/4293
Abstract: embodiments of optical adapters, and methods of forming and using the same, are disclosed herein. in one example, an optical adapter includes a first interface to mate with a first optical connector, a second interface to mate with a second optical connector, and a plurality of waveguides extending through the optical adapter from the first interface to the second interface. the first interface includes a first set of alignment features to align the optical adapter with the first optical connector, and the second interface includes a second set of alignment features to align the optical adapter with the second optical connector. further, when the first interface is mated with the first optical connector and the second interface is mated with the second optical connector, the first and second optical connectors are optically coupled via the waveguides.
Inventor(s): Joseph BLOXHAM of Laveen AZ (US) for intel corporation, Jeremy D. ECTON of Gilbert AZ (US) for intel corporation
IPC Code(s): G03F7/30
CPC Code(s): G03F7/3092
Abstract: devices, systems, and methods for conditioning a solvent return flow from a photolithographic process used for semiconductor processing are presented. reuse of materials in semiconductor processing can provide environmental and manufacturing cost advantages. devices for conditioning a solvent return flow from a photolithographic process and systems for photolithographic processes include a baffle system and a light system. methods for reusing a solvent from a photolithographic process include passing the solvent through a conditioning device having a baffle system and a light system.
Inventor(s): Yongbae KIM of San Jose CA (US) for intel corporation
IPC Code(s): G03F7/00, G03F1/22
CPC Code(s): G03F7/706845
Abstract: devices and processes for managing electrostatic charge on lithographic photomasks for semiconductor fabrication are provided. exemplary devices include sensors for measuring the electrostatic charge on a lithographic photomask and charge injectors for modifying the electrostatic charge on a lithographic photomask. exemplary devices are capable of attaching to carriers for lithographic photomasks. exemplary processes include measuring the electrostatic charge on a lithographic photomask, calculating the amount that the electrostatic charge should be increased or decreased, and modifying the amount of electrostatic charge.
Inventor(s): Alexey Supikov of Santa Clara CA (US) for intel corporation, Qiong Huang of San Jose CA (US) for intel corporation, Ronald T. Azuma of San Jose CA (US) for intel corporation
IPC Code(s): G03H1/08, G03H1/04, G06N3/02, G06N3/067, G06T1/20, G06T7/00, G06T7/66, G06T9/00, G06T19/00
CPC Code(s): G03H1/0808
Abstract: techniques related to generating holographic images for a holographic heads up display are discussed. such techniques include application of a machine learning model to the target image to generate data that is used to enable the determination of a phase pattern via an iterative propagation feedback model. the iterative propagation feedback model is used to generate a feedback strength value, which is then used to generate a phase diffraction pattern for presentation at a holographic plane of the heads up display.
20250004490. VOLTAGE COMPENSATION FOR REDUCED POWER STATES_simplified_abstract_(intel corporation)
Inventor(s): Yoni AIZIK of Haifa (IL) for intel corporation, Yevgeni SABIN of Haifa (IL) for intel corporation, Sagi WEISS of Binyamina (IL) for intel corporation, Dor ZVIK of Herzelia (IL) for intel corporation, Itai FEIT of Ramat Hasharon (IL) for intel corporation, Lisa EZRA of Kfar Saba (IL) for intel corporation, Yossi BEN SIMON of Karmiel (IL) for intel corporation, Nir MISGAV of Ein Hahoresh (IL) for intel corporation, Yulia OKUNEV of Tirat Carmel (IL) for intel corporation, Arik GIHON of Rishon Le Zion (IL) for intel corporation, Yoav BABAJANI of Rishon Le Zion (IL) for intel corporation, Pavel MIKHLIN of Raanana (IL) for intel corporation
IPC Code(s): G05F1/46
CPC Code(s): G05F1/46
Abstract: presented are temperature-monitoring supply voltage compensation techniques. some techniques allow for a supply voltage to be monitored and compensated during a reduced power state, even when a control unit circuit that controls the supply voltage is in the reduced power state.
Inventor(s): Juha T. Paavola of Hillsboro OR (US) for intel corporation, Sami M. Heinisuo of Dallas OR (US) for intel corporation, Kari Pekka Johannes Mansukoski of Hillsboro OR (US) for intel corporation, Shawn S. McEuen of Portland OR (US) for intel corporation
IPC Code(s): G06F1/16, H01H13/7073, H01H13/785
CPC Code(s): G06F1/1662
Abstract: in one embodiment, a keyboard includes keys disposed in respective holes of a housing, a set of first conductive pads coupled to respective keys, and a set of second conductive pads coupled to surfaces of the housing defining respective holes. the keys are configured such that the first conductive pad of a key is not in contact with a second conductive pad of a hole corresponding to the key when the key is in a first position (e.g., not actuated), and the first conductive pad of the key is in contact with the second conductive pad of the hole corresponding to the key when the key is in a second position (e.g., actuated).
Inventor(s): Adwait Purandare of Beaverton OR (US) for intel corporation, Ankush Varma of Portland OR (US) for intel corporation, Nilanjan Palit of Northborough MA (US) for intel corporation, Yuval Bustan of Moshav Mismeret (IL) for intel corporation, Eran Barnett of Haifa (IL) for intel corporation, Eliezer Weissman of Haifa (IL) for intel corporation, Stanley Chen of Portland OR (US) for intel corporation, Arjan Van De Ven of Portland OR (US) for intel corporation
IPC Code(s): G06F1/3296, G06F1/324
CPC Code(s): G06F1/3296
Abstract: techniques and mechanisms for determining operation a processor core which is in a common power delivery domain with one or more other processor cores. in an embodiment, an execution of instructions by a first core of a processor module is selectively throttled based on the detection of a single violation condition. the throttling is performed while the cores of the processor module are each maintained in a current power state. the single violation condition comprises a violation of a test criteria by the first core, while the one or more other cores of the module each satisfy the test criteria. in the case of a multiple violation condition, each core of the processor module is transitioned from one power state to another power state. in another embodiment, the test criteria includes or is otherwise based on a threshold level of a dynamic capacitance for a given core.
20250004577. STYLUS TRAJECTORY PREDICTION_simplified_abstract_(intel corporation)
Inventor(s): Niranjan Mylarappa Gowda of Hillsboro OR (US) for intel corporation, Antonio S. Cheng of Portland OR (US) for intel corporation, Andrey Belogolovy of Hillsboro OR (US) for intel corporation, Evgeny Stupachenko of San Jose CA (US) for intel corporation
IPC Code(s): G06F3/0354
CPC Code(s): G06F3/03545
Abstract: system and techniques for predicting a stylus position while interacting on a surface are described herein. the prediction begins by obtaining a set of points that are derived from a stylus moving on a surface. an artificial neural network (ann) may be invoked on an input set. here, the input set is based on the set of points from the stylus. the ann is configured to output a next point from the input set, and the ann is trained to minimize angular error for the next point over other errors. once the next point is provided by the ann, the next point may be communicated for rendering on a display.
20250004716. SYSTEMS, METHODS, AND APPARATUSES FOR TILE LOAD_simplified_abstract_(intel corporation)
Inventor(s): Robert VALENTINE of Kiryat Tivon (IL) for intel corporation, Menachem ADELMAN of Haifa (IL) for intel corporation, Milind B. GIRKAR of Sunnyvale CA (US) for intel corporation, Zeev SPERBER of Zichron Yackov (IL) for intel corporation, Mark J. CHARNEY of Lexington MA (US) for intel corporation, Bret L. TOLL of Hillsboro OR (US) for intel corporation, Rinat RAPPOPORT of Haifa (IL) for intel corporation, Jesus Corbal of King City OR (US) for intel corporation, Stanislav SHWARTSMAN of Haifa (IL) for intel corporation, Dan BAUM of Haifa (IL) for intel corporation, Igor YANOVER of Yokneam Illit (IL) for intel corporation, Alexander F. HEINECKE of San Jose CA (US) for intel corporation, Barukh ZIV of Haifa (IL) for intel corporation, Elmoustapha OULD-AHMED-VALL of Chandler AZ (US) for intel corporation, Yuri GEBIL of Nahariya (IL) for intel corporation, Raanan SADE of Kibutz Sarid (IL) for intel corporation
IPC Code(s): G06F7/485, G06F7/487, G06F7/76, G06F9/30, G06F9/38, G06F17/16
CPC Code(s): G06F7/485
Abstract: embodiments detailed herein relate to matrix operations. in particular, the loading of a matrix (tile) from memory. for example, support for a loading instruction is described in the form of decode circuitry to decode an instruction having fields for an opcode, a destination matrix operand identifier, and source memory information, and execution circuitry to execute the decoded instruction to load groups of strided data elements from memory into configured rows of the identified destination matrix operand to memory.
Inventor(s): Robert Valentine of Kiryat Tivon (IL) for intel corporation, Galina Ryvchin of Haifa (IL) for intel corporation, Piotr Majcher of Straszyn (PL) for intel corporation, Mark J. Charney of Lexington MA (US) for intel corporation, Elmoustapha Ould-Ahmed-Vall of Chandler AZ (US) for intel corporation, Jesus Corbal of King City OR (US) for intel corporation, Milind B. Girkar of Sunnyvale CA (US) for intel corporation, Zeev Sperber of Zichron Yackov (IL) for intel corporation, Simon Rubanovich of Haifa (IL) for intel corporation, Amit Gradstein of Binyamina (IL) for intel corporation
IPC Code(s): G06F9/30, G06F7/544, G06F9/38
CPC Code(s): G06F9/30014
Abstract: embodiments of systems, apparatuses, and methods for fused multiple add. in some embodiments, a decoder decodes a single instruction having an opcode, a destination field representing a destination operand, and fields for a first, second, and third packed data source operand, wherein packed data elements of the first and second packed data source operand are of a first, different size than a second size of packed data elements of the third packed data operand. execution circuitry then executes the decoded single instruction to perform, for each packed data element position of the destination operand, a multiplication of a m n-sized packed data elements from the first and second packed data sources that correspond to a packed data element position of the third packed data source, add of results from these multiplications to a full-sized packed data element of a packed data element position of the third packed data source, and storage of the addition result in a packed data element position destination corresponding to the packed data element position of the third packed data source, wherein m is equal to the full-sized packed data element divided by n.
Inventor(s): Michael ESPIG of Newberg OR (US) for intel corporation, Menachem ADELMAN of Modi'in (IL) for intel corporation, Jonathan COMBS of Austin TX (US) for intel corporation, Amit GRADSTEIN of Binyamina (IL) for intel corporation, Christopher J. HUGHES of Santa Clara CA (US) for intel corporation, Vivekananthan SANJEEPAN of Portland OR (US) for intel corporation, Wing Shek WONG of Austin TX (US) for intel corporation
IPC Code(s): G06F9/30
CPC Code(s): G06F9/30036
Abstract: techniques for providing 512-bit operands or smaller are described. in some examples, a prefix of an instruction is utilized to define the operand (vector) length. for example, an instruction is to at least include fields for a prefix, an opcode, and operand addressing information, wherein the prefix and addressing information are to be used by decoder circuitry to determine support for a particular a vector length for one or more operands of the instance of the single instruction and the opcode is to indicate one or more operations to perform on the one or more operands.
Inventor(s): Santosh Ghosh of Hillsboro OR (US) for intel corporation, Christoph Dobraunig of St. Veit an der Glan (AT) for intel corporation, Manoj Sastry of Portland OR (US) for intel corporation, Rotem Ohana Peretz of Kfar Zeitim (IL) for intel corporation, Regev Shemy of Kiryat Ata (IL) for intel corporation
IPC Code(s): G06F9/30
CPC Code(s): G06F9/30145
Abstract: circuitry and methods for implementing one or more keccak permutation instructions are described. in certain examples, a hardware processor (e.g., core) includes decoder circuitry to decode a first instruction into a decoded first instruction, the first instruction comprising identifiers of a first register to store a first word of keccak state value, a second register to store a second word of keccak state value and a third word of keccak state value, and a third register to store a fourth word of keccak state value and a fifth word of keccak state value according to a sha3 standard, and an opcode to indicate vector execution circuitry comprising a plurality of lanes is to use only a single lane of the plurality of lanes to perform a column parities operation of a theta step of a keccak permutation according to the sha3 standard to determine a computed parity value for an input of the first word of keccak state value, the second word of keccak state value, the third word of keccak state value, the fourth word of keccak state value, and the fifth word of keccak state value, and store the computed parity value into an unused upper word of the first register; and the vector execution circuitry to execute the decoded first instruction according to the opcode.
Inventor(s): Kamlesh PILLAI of Bangalore (IN) for intel corporation, Vinodh GOPAL of Westborough MA (US) for intel corporation, Gurpreet Singh KALSI of Portland OR (US) for intel corporation, Sreenivas SUBRAMONEY of Bangalore (IN) for intel corporation, Wajdi K. FEGHALI of Boston MA (US) for intel corporation
IPC Code(s): G06F9/30
CPC Code(s): G06F9/30181
Abstract: apparatus and method for a decompression hardware copy engine with efficient sequence overlapping copy. for example, one embodiment of an apparatus comprises: a plurality of processing cores, one or more of the plurality of processing cores to execute program code to produce a plurality of literals and sequences from a compressed data stream; and decompression acceleration circuitry to generate a decompressed data stream based on the plurality of literals and sequences, the decompression acceleration circuitry comprising: a sequence pre-processor circuit to process batches of sequences of the plurality of sequences and generate a plurality of copy instructions, the sequence pre-processor circuit to merge multiple copy operations corresponding to multiple sequences into a merged copy instruction; and a copy engine circuit to execute the copy instructions to produce the decompressed data stream.
Inventor(s): Christopher J. HUGHES of Santa Clara CA (US) for intel corporation, Zhe WANG of San Jose CA (US) for intel corporation, Dan BAUM of Haifa (IL) for intel corporation, Venkateswara Rao MADDURI of Austin TX (US) for intel corporation, Chen DAN of Hadera (IL) for intel corporation, Joseph NUZMAN of Haifa (IL) for intel corporation
IPC Code(s): G06F9/38, G06F9/30
CPC Code(s): G06F9/3802
Abstract: an apparatus and method are described for prefetching data with hints. for example, one embodiment of a processor comprises: a plurality of cores to process instructions; a first core of the plurality of cores comprising: decoder circuitry to decode instructions indicating memory operations including load operations of a first type with shared data hints and load operations of a second type without shared data hints; execution circuitry to execute the instructions to perform the memory operations; data prefetch circuitry to store tracking data in a tracking data structure responsive to the memory operations, a portion of the tracking data associated with the first type of load operations; and the data prefetch circuitry to detect memory access patterns using the tracking data, the data prefetch circuitry to responsively issue one or more prefetch operations using shared data hints based, at least in part, on the portion of the tracking data associated with the first type of load operations.
Inventor(s): Zeshan Chishti of Hillsboro OR (US) for intel corporation, Jeffrey Cook of Portland OR (US) for intel corporation, Thomas McDonald of Austin TX (US) for intel corporation
IPC Code(s): G06F9/38
CPC Code(s): G06F9/3818
Abstract: systems, methods, and apparatuses relating to hardware for auto-predication for loops with dynamically varying iteration counts are disclosed. in an embodiment, a processor core includes a decoder to decode instructions into decoded instructions, an execution unit to execute the decoded instructions, a branch predictor circuit to predict a future outcome of a branch instruction, and a branch predication manager circuit to identify a plurality of popular iteration counts for a loop and to predicate a region including a number of loop iterations equal to one of the plurality of popular iteration counts.
Inventor(s): Zeshan CHISHTI of Beaverton OR (US) for intel corporation, Gilles POKAM of Livermore CA (US) for intel corporation, Julien SEBOT of Portland OR (US) for intel corporation, Ahmed YOUSSEF of Tigard OR (US) for intel corporation, Henry WONG of Hillsboro OR (US) for intel corporation, Michael UPTON of Seattle WA (US) for intel corporation, Srikanth SRINIVASAN of Portland OR (US) for intel corporation
IPC Code(s): G06F9/38
CPC Code(s): G06F9/3848
Abstract: methods and apparatus to implement adaptive branch prediction throttling are disclosed. in one embodiment, the method comprises determining, based on looking up a branch confidence data structure, whether a current branch in execution of a single thread is a low confidence branch in which a branch predictor of a processor has a low level of certainty that outcome of the current branch is predicted correctly; and comparing a branch misprediction rate, a microinstruction waste rate, and a cache missing rate of the single thread with their corresponding thresholds. the method further comprises throttling branch prediction of the current branch based on the determination of the current branch being a low confidence branch and one or more thresholds for the branch misprediction rate, the microinstructions waste rate, and the cache missing rate of the single thread being crossed.
Inventor(s): David Gonzalez Aquirre of Portland OR (US) for intel corporation, Rafael De La Guardia Gonzalez of Teuchitlan (MX) for intel corporation, Javier Felip Leon of Hillsboro OR (US) for intel corporation, Javier Perez-Ramirez of North Plains OR (US) for intel corporation, Julio Zamora Esquivel of West Sacramento CA (US) for intel corporation
IPC Code(s): G06F9/46
CPC Code(s): G06F9/465
Abstract: a component of an edge server, including: processor circuitry; and a non-transitory computer-readable storage medium including instructions that, when executed by the processor circuitry, cause the processor circuitry to: distribute, to a client device, tokens that enable its end device to execute respective asynchronous adaptive motion primitives (amps) of a task graph of a task, wherein an amp is a motion primitive of encoded motion factoring in motion updates from the end device; receive amp task execution status messages during execution of the amps; and dynamically update the distribution of the token or the task graph based on the amp task execution status messages to modify a trajectory of the end device.
Inventor(s): Jeroen Leijten of Hulsel (NL) for intel corporation
IPC Code(s): G06F9/48
CPC Code(s): G06F9/4881
Abstract: techniques for hardware based acceleration of synchronous data flow graphs for data-driven multi-core signal processing systems are described. in certain examples, a system includes a processor comprising a processing circuit to perform a task of a synchronous data flow graph, an input memory for the task of the synchronous data flow graph, an output memory for the task of the synchronous data flow graph, and a synchronous data flow manager circuit to store user-visible state for the input memory and the output memory; and a synchronous data flow functional circuit, coupled to the processor, to cause the processing circuit to perform the task based on the user-visible state from the synchronous data flow manager circuit.
Inventor(s): Yoav Babajani of Rishon Le Zion (IL) for intel corporation, Efraim Rotem of Haifa (IL) for intel corporation, Gideon Reisfeld of Haifa (IL) for intel corporation, Somvir Singh Dahiya of Hillsboro OR (US) for intel corporation, Yevgeni Sabin of Haifa (IL) for intel corporation
IPC Code(s): G06F9/48, G06F1/26
CPC Code(s): G06F9/4893
Abstract: techniques and mechanisms for determining a mode by which a processor is to be transitioned between power states. in one embodiment, circuitry selectively transitions power management of the processor to or from a limited power states (lps) mode which, as compared to an alternative power management mode, makes a relatively limited number of two or more power states available to the processor. a transition to or from the lps mode is performed based on a thermal condition such as one which is based on a skin temperature of a housing structure in which the processor is disposed. in another embodiment, transitions between the two or more power states is performed, during the lps mode, based on a pendency of a software workload, or based on a completion of such a software workload.
Inventor(s): Sourav SAHA of Bangalore (IN) for intel corporation
IPC Code(s): G06F9/50
CPC Code(s): G06F9/5038
Abstract: disclosed are methods and systems for re-allocating compute resources between running eda jobs. for example, while jobs are running, they may be monitored to select those whose runtimes may be improved by giving them additional memory and/or core resources.
Inventor(s): Yevgeni Sabin of Haifa (IL) for intel corporation, Madhusudan Chidambaram of Bangalore (IN) for intel corporation, Refael Mizrahi of Raanana (IL) for intel corporation, Efraim Rotem of Santa Clara CA (US) for intel corporation, Rajshree A. Chabukswar of Sunnyvale CA (US) for intel corporation, Eliezer Weissmann of Haifa (IL) for intel corporation, Stephen H. Gunther of Beaverton OR (US) for intel corporation, Hisham Abu-Salah of Santa Clara CA (US) for intel corporation, Sneha Gohad of San Jose CA (US) for intel corporation, Anusha Ramachandran of Bengaluru (IN) for intel corporation, Praveen Koduru of Bangalore (IN) for intel corporation, Hadas Beja of Yehud (IL) for intel corporation, Nofar Mani of Giv'atayim (IL) for intel corporation, Hadar Ringel of Ramat Yishai (IL) for intel corporation, Avishai Wagner of Santa Clara CA (US) for intel corporation
IPC Code(s): G06F9/50, G06F9/54
CPC Code(s): G06F9/505
Abstract: in one embodiment, a processor includes: at least one first core to execute instructions; at least one second core to execute instructions; and a control circuit coupled to the at least one first core and the at least one second core. the control circuit may be configured to: receive workload telemetry information regarding a workload for execution on the processor; determine a qos distribution based at least in part on the workload telemetry information; receive a predicted workload type, the predicted workload type based at least in part on the qos distribution; and cause at least one of the at least one first core or the at least one second core to be parked based on the predicted workload type and the qos distribution. other embodiments are described and claimed.
Inventor(s): Rajkishore Barik of Santa Clara CA (US) for intel corporation, Stephan A. Herhut of Santa Clara CA (US) for intel corporation, Jaswanth Sreeram of San Jose CA (US) for intel corporation, Tatiana Shpeisman of Menlo Park CA (US) for intel corporation, Richard L. Hudson of Florence MA (US) for intel corporation
IPC Code(s): G06F9/50, G06F13/42
CPC Code(s): G06F9/5083
Abstract: disclosed examples include scheduler circuitry to allocate a first task to a first work queue in memory; and a first processor circuit of a first type, the first processor circuit to cause movement of the first task from the first work queue to a second work queue in the memory, the second work queue accessible by a second processor circuit of a second type, the movement atomically performed via a read operation and a write operation to update the second work queue in a same bus cycle to prevent multiple entities from moving the first task in the same bus cycle.
Inventor(s): Beeman STRONG of Portland OR (US) for intel corporation, Stanislav BRATANOV of Portland OR (US) for intel corporation, Markus METZGER of Ulm (DE) for intel corporation, Jason W. BRANDT of Austin TX (US) for intel corporation, Stalinselvaraj JEYASINGH of Beaverton OR (US) for intel corporation
IPC Code(s): G06F11/07
CPC Code(s): G06F11/079
Abstract: apparatus and method for a processor trace trigger tracing. a processor, comprising: a plurality of processing cores configurable as a plurality of logical processors; processor trace circuitry to perform trace operations to capture and process information related to program code executed by one or more of the logical processors; a debug unit to perform debug operations and collect debug data related to execution of the program code; a performance monitoring unit (pmu) comprising a plurality of counter registers, the pmu to collect performance data related to execution of the program code; and a plurality of trigger units, each trigger unit associated with a logical processor of the plurality of logical processors and configured to communicate trigger event data to the processor trace circuitry in response to trigger events received from at least one of the debug unit and the pmu in accordance with values of configuration bits in a corresponding trigger unit configuration register.
Inventor(s): Yanxin ZHAO of Shanghai (CN) for intel corporation, Tao XU of Shanghai (CN) for intel corporation, Yufu LI of Shanghai (CN) for intel corporation, Shijie LIU of Shanghai (CN) for intel corporation, Lei ZHU of Shanghai (CN) for intel corporation
IPC Code(s): G06F11/10
CPC Code(s): G06F11/106
Abstract: a method and system for error check and scrub (ecs) error data collection and reporting for a memory device. a controller includes circuitry and a buffer. the circuitry may be configured to read ecs error data from a register of a memory device and calculate an ecs error increase rate based on the ecs error data. the circuitry may be configured to inform basic input output system (bios) by interrupt if a total number of ecs errors reaches or exceeds an ecs error number threshold or if the ecs error increase rate reaches or exceeds an ecs error rate threshold. the controller may be an out-of-band device, e.g., a baseboard management controller or a memory micro controller.
Inventor(s): David M. Durham of Beaverton OR (US) for intel corporation, Sergej Deutsch of Hillsboro OR (US) for intel corporation, Salmin Sultana of Hillsboro OR (US) for intel corporation, Karanvir Grewal of Hillsboro OR (US) for intel corporation
IPC Code(s): G06F11/10, G06F9/30, G06F21/60
CPC Code(s): G06F11/1068
Abstract: techniques for error correction with memory safety and compartmentalization are described. in an embodiment, an apparatus includes a processor to provide a first set of data bits and a first tag in connection with a store operation, and an error correcting code (ecc) generation circuit to generate a first set of ecc bits based on a first set of data bits and a first tag.
Inventor(s): Brandon GORDON of Campbell CA (US) for intel corporation, Yi PENG of Newark CA (US) for intel corporation, krishna NAGAR of Union City CA (US) for intel corporation, Nathan KRUEGER of Kalispell MT (US) for intel corporation
IPC Code(s): G06F11/18
CPC Code(s): G06F11/181
Abstract: an apparatus and method for redundant data processing with graceful degrading functionality. for example, one embodiment of an apparatus comprises: three processing elements operable in a first redundancy mode, the three processing elements to execute a same sequence of instructions to produce three corresponding results; detection circuitry to detect when any one processing element of the three processing elements produces a different result from the other two processing elements of the three processing elements; tracking circuitry to associate an error with the one processing element when it produces the different result from the other two processing elements, wherein if an error threshold is reached for the one processing element, the other two processing elements are to operate in a second redundancy mode excluding the one processing element.
Inventor(s): Sridharan SAKTHIVELU of DuPont WA (US) for intel corporation, Kaushik BALASUBRAMANIAN of Beaverton OR (US) for intel corporation, Krishna SURYA of Portland OR (US) for intel corporation
IPC Code(s): G06F11/27
CPC Code(s): G06F11/27
Abstract: methods and apparatus to implement proactive hardware error screening are disclosed. in one embodiment, a computer processing system includes a plurality of computational units to execute tasks for one or more applications; a plurality of sensors collects measurement data of the plurality of computational units, to collect measurement data of the plurality of computational units; a data structure indicating hardware health statuses of the plurality of computational units determined based on the measurement data is stored in a storage; and the plurality of computational units is scheduled to perform task execution on the computer processing system for the one or more applications based on the hardware health statuses of the plurality of computational units indicated in the data structure, wherein a first computational unit is excluded from the task execution when a corresponding first hardware health status of the first computational unit indicates an impending hardware failure.
Inventor(s): Huimin Chen of Beaverton OR (US) for intel corporation, James Akiyama of Tigard OR (US) for intel corporation, John Howard of Hillsboro OR (US) for intel corporation, Venkataramani Gopalakrishnan of Folsom CA (US) for intel corporation, Nirmala Bailur of Bangalore (IN) for intel corporation
IPC Code(s): G06F13/38, G06F13/40
CPC Code(s): G06F13/382
Abstract: systems, apparatus, articles of manufacture, and methods are disclosed to route display stream data. an example system disclosed herein to route display stream data includes a circuit board comprising decoding circuitry to decode peripheral component interconnect express (pcie) data packets into a display port stream data, the pcie data packets encoded by a discrete graphics circuitry, and a universal serial bus (usb) connector on the circuit board coupled to the decoding circuitry, wherein the usb connector is to output the display port stream data.
20250004981. MULTI-TILE MEMORY MANAGEMENT_simplified_abstract_(intel corporation)
Inventor(s): Abhishek R. Appu of El Dorado Hills CA (US) for intel corporation, Altug Koker of El Dorado Hills CA (US) for intel corporation, Aravindh Anantaraman of Folsom CA (US) for intel corporation, Elmoustapha Ould-Ahmed-Vall of Chandler AZ (US) for intel corporation, Valentin Andrei of San Jose CA (US) for intel corporation, Nicolas Galoppo Von Borries of Portland OR (US) for intel corporation, Varghese George of Folsom CA (US) for intel corporation, Mike Macpherson of Portland OR (US) for intel corporation, Subramaniam Maiyuran of Gold River CA (US) for intel corporation, Joydeep Ray of Folsom CA (US) for intel corporation, Lakshminarayana Striramassarma of Folsom CA (US) for intel corporation, Scott Janus of Loomis CA (US) for intel corporation, Brent Insko of Portland OR (US) for intel corporation, Vasanth Ranganathan of El Dorado Hills CA (US) for intel corporation, Kamal Sinha of Rancho Cordova CA (US) for intel corporation, Arthur Hunter of Cameron Park CA (US) for intel corporation, Prasoonkumar Surti of Folsom CA (US) for intel corporation, David Puffer of Tempe AZ (US) for intel corporation, James Valerio of North Plains OR (US) for intel corporation, Ankur N. Shah of Folsom CA (US) for intel corporation
IPC Code(s): G06F15/78, G06F7/544, G06F7/575, G06F7/58, G06F9/30, G06F9/38, G06F9/50, G06F12/02, G06F12/06, G06F12/0802, G06F12/0804, G06F12/0811, G06F12/0862, G06F12/0866, G06F12/0871, G06F12/0875, G06F12/0882, G06F12/0891, G06F12/0893, G06F12/0895, G06F12/0897, G06F12/1009, G06F12/128, G06F15/80, G06F17/16, G06F17/18, G06N3/08, G06T1/20, G06T1/60, G06T15/06, H03M7/46
CPC Code(s): G06F15/7839
Abstract: methods and apparatus relating to techniques for multi-tile memory management. in an example, a graphics processor includes an interposer, a first chiplet coupled with the interposer, the first chiplet including a graphics processing resource and an interconnect network coupled with the graphics processing resource, cache circuitry coupled with the graphics processing resource via the interconnect network, and a second chiplet coupled with the first chiplet via the interposer, the second chiplet including a memory-side cache and a memory controller coupled with the memory-side cache. the memory controller is configured to enable access to a high-bandwidth memory (hbm) device, the memory-side cache is configured to cache data associated with a memory access performed via the memory controller, and the cache circuitry is logically positioned between the graphics processing resource and a chiplet interface.
Inventor(s): Raghavan KUMAR of Hillsboro OR (US) for intel corporation, AppaRao CHALLAGUNDLA of Austin TX (US) for intel corporation, Sanu K. MATHEW of Portland OR (US) for intel corporation, Christopher B. WILKERSON of Portland OR (US) for intel corporation, Adish VARTAK of Palo Alto CA (US) for intel corporation, Sachin TANEJA of Hillsboro OR (US) for intel corporation, Minxuan ZHOU of San Diego CA (US) for intel corporation, Lalith Dharmesh KETHARESWARAN of Austin TX (US) for intel corporation
IPC Code(s): G06F17/14
CPC Code(s): G06F17/14
Abstract: examples include techniques for contention-free routing for number-theoretic-transform (ntt) or inverse-ntt (intt) computations routed through a parallel processing device. examples include a tile array that includes a plurality of tiles arranged in a 2-dimensional mesh interconnect-based architecture. each tile includes a plurality of compute elements configured to execute ntt or intt computations associated with a fully homomorphic encryption workload.
Inventor(s): Sachin TANEJA of Hillsboro OR (US) for intel corporation, Sanu K. MATHEW of Portland OR (US) for intel corporation, Raghavan KUMAR of Hillsboro OR (US) for intel corporation, Nojan SHEYBANI of San Diego CA (US) for intel corporation, Vikram B. SURESH of Portland OR (US) for intel corporation
IPC Code(s): G06F17/14
CPC Code(s): G06F17/14
Abstract: examples include techniques for twiddle factor generation for number-theoretic-transform (ntt) or inverse-ntt (intt) computations by a compute element. the compute element can be included in a parallel processing device. examples include receiving information to generate a twiddle factor for use by the compute element to execute an ntt or an intt computation for an n-degree polynomial, obtain data for a power of 2 of a root of unity from a memory resident on a same chip or die as the compute element and generate the twiddle factor using the obtained data based, at least in part, on the received information.
Inventor(s): Sachin TANEJA of Hillsboro OR (US) for intel corporation, Sanu K. MATHEW of Portland OR (US) for intel corporation, Raghavan KUMAR of Hillsboro OR (US) for intel corporation, Nojan SHEYBANI of San Diego CA (US) for intel corporation, Vikram B. SURESH of Portland OR (US) for intel corporation
IPC Code(s): G06F17/15, H04L9/00
CPC Code(s): G06F17/156
Abstract: examples include techniques for twiddle factor generation for number-theoretic-transform (ntt) or inverse-ntt (intt) computations by a compute element. the compute element can be included in a parallel processing device. examples include receiving information to generate a twiddle factor for use by the compute element to execute an ntt or an intt computation for an n-degree polynomial, obtain data for a power of 2 of a root of unity from a memory resident on a same chip or die as the compute element and generate the twiddle factor using the obtained data based, at least in part, on the received information.
Inventor(s): David M. Durham of Beaverton OR (US) for intel corporation
IPC Code(s): G06F21/54, G06F21/55
CPC Code(s): G06F21/54
Abstract: techniques for instruction tagging for intra-object memory tagging are described. in an embodiment, an apparatus includes an instruction decoder to decode a first instruction having an instruction tag value; and execution circuitry coupled to the instruction decoder, the execution circuitry to perform one or more operations corresponding to the first instruction, including generating a first data tag value based on the instruction tag value and a relative enumeration in a pointer to data.
20250005138. EXPLICIT INTEGRITY CHECK VALUE INITIALIZATION_simplified_abstract_(intel corporation)
Inventor(s): Michael LeMay of Hillsboro OR (US) for intel corporation, David M. Durham of Beaverton OR (US) for intel corporation
IPC Code(s): G06F21/54, G06F21/78
CPC Code(s): G06F21/54
Abstract: techniques for explicit integrity check value initialization are described. in an embodiment, an apparatus includes an instruction decoder to decode a single instruction to set an integrity check value icv corresponding to a destination location in a memory; and execution circuitry coupled to the instruction decoder, the execution circuitry to perform one or more operations corresponding to the single instruction, including storing data indicated by the single instruction into the destination location, and storing the icv in the memory.
Inventor(s): Hisham SHAFI of San Jose CA (US) for intel corporation, Scott CAPE of Portland OR (US) for intel corporation, Jeffrey WIEDEMEIER of Austin TX (US) for intel corporation
IPC Code(s): G06F21/57, G06F9/30, G06F21/64
CPC Code(s): G06F21/57
Abstract: an apparatus and method are described for authenticating extended service microcode updates. for example, one embodiment of a method comprises: storing extended service microcode update (mcu) in a memory of a processor; reading processor signature data, platform identification data, and processor extended service data from one or more registers of the processor; identifying mcu extended service period data based on processor signature data and platform identification data; determining whether to apply the extended service mcu on the processor based on a comparison between the mcu extended service period data and the processor extended service data.
Inventor(s): Avinash CHANDRASEKARAN of Mountain View CA (US) for intel corporation, Murugasamy K. NACHIMUTHU of Beaverton OR (US) for intel corporation, Mariusz ORIOL of Gdynia (PL) for intel corporation, Piotr MATUSZCZAK of Kawle Dolne (PL) for intel corporation
IPC Code(s): G06F21/57, G06F8/65, G06F21/44
CPC Code(s): G06F21/572
Abstract: an apparatus and method are described for staging and activating microcode of a processor. for example, one embodiment of a processor comprises: a plurality of functional blocks, each functional block operable, at least in part, based on microcode and including a non-volatile memory to store a corresponding microcode update (mcu); a plurality of mcu staging memories, each mcu staging memory to temporarily store one or more of the mcus for one or more corresponding functional blocks of the plurality of functional blocks; authentication hardware logic to attempt to validate each mcu of the one or more mcus stored in each mcu staging memory, wherein each mcu is to be copied to a non-volatile memory of a corresponding functional block only after a successful authentication.
Inventor(s): Iwan Grau of Tampa FL (US) for intel corporation, Anas Hlayhel of Gilbert AZ (US) for intel corporation, Santosh Ghosh of Hillsboro OR (US) for intel corporation, Sonal Waydande of Austin TX (US) for intel corporation, Matthew Wise of Santa Clara CA (US) for intel corporation, William Penner of Olympia WA (US) for intel corporation, Enrico Carrieri of Placerville CA (US) for intel corporation
IPC Code(s): G06F21/72, G06F21/74
CPC Code(s): G06F21/72
Abstract: an example of an apparatus may include first circuitry that is to be selectively locked and unlocked, second circuitry to process one or more tokens including an unlock token for the first circuitry, and hardware authentication circuitry to authenticate the unlock token for the first circuitry in response to a request from the second circuitry. the apparatus may further include hardware ungate circuitry to selectively gate and ungate one or more features of the first circuitry in response to an indication that the first circuitry is one of locked or unlocked. other examples are disclosed and claimed.
Inventor(s): Dumitru-Daniel DINU of Chandler AZ (US) for intel corporation, Santosh GHOSH of Hillsboro OR (US) for intel corporation, Avinash VARNA of Chandler AZ (US) for intel corporation, Manoj SASTRY of Portland OR (US) for intel corporation
IPC Code(s): G06F21/75
CPC Code(s): G06F21/75
Abstract: techniques for improved keccak execution resilient to physical side-channel attacks are described. in some examples, a keccak round datapath includes a first path including a theta step, a rho step, a pi step, and an iota step to process a masked version of the 1600-bit input state, a second path including a theta step, a rho step, and a pi step to process a mask 1600-bit input state, and a masked chi step shared by the first path and second path.
Inventor(s): Debayan Das of Hillsboro OR (US) for intel corporation, Santosh Ghosh of Hillsboro OR (US) for intel corporation, Manoj Sastry of Portland OR (US) for intel corporation
IPC Code(s): G06F21/75
CPC Code(s): G06F21/755
Abstract: techniques for attenuation and obfuscation to mitigate power and/or electromagnetic (em) field attacks on encryption circuitry are described. in certain examples, a system includes a processor core; and an accelerator coupled to the processor core, the accelerator comprising: encryption circuitry, coupled to a power source, to encrypt data into encrypted data, time-domain obfuscation control circuitry to connect and disconnect one or more capacitors to the encryption circuitry during the encrypt to provide obfuscation across a time-domain to maintain a software observable power consumption of the accelerator to about a value, and signature attenuation control circuitry to selectively connect the encryption circuitry during the encrypt to a shunt to drain power to maintain the software observable power consumption of the accelerator at about the value.
Inventor(s): Stephan WAGNER of Portland OR (US) for intel corporation, Matthew K. GUMBEL of Portland OR (US) for intel corporation
IPC Code(s): G06F30/394
CPC Code(s): G06F30/394
Abstract: methods for layout decomposition of photolithographic masks are provided. the decomposition creates domains that can be sent to independent computing resources for optimization. a first partition is created for the photolithographic mask design. buffer regions are created around photolithographic features and a search distance is selected. the buffer regions and search distance are used in a pathfinding algorithm to determine new boundaries for new domains. the methods can be stored, for example, on at least one machine-readable storage medium as non-transitory instructions.
20250005254. INTEGRATED CIRCUIT CONNECTION AS A DEVICE_simplified_abstract_(intel corporation)
Inventor(s): Nicolas RICHAUD of Rome (IT) for intel corporation, Krzysztof DOMANSKI of Neubiberg (DE) for intel corporation, Michael LANGENBUCH of Munich (DE) for intel corporation
IPC Code(s): G06F30/398, G06F30/392
CPC Code(s): G06F30/398
Abstract: a non-transitory computer readable medium is provided having instructions stored therein that when executed by a processor cause the processor to select a device interface component layout from a plurality of device interface component layouts based on a set of parameters, wherein each device interface component layout corresponds to an interface structure of a shared integrated circuit semiconductor device component; perform at least one compatibility verification process for the selected device interface component layout with regard to an environment of the device interface component at a predetermined position in the integrated circuit semiconductor device; and output a compatibility verification information indicating a result of the at least one compatibility verification process for the selected device interface component layout.
Inventor(s): Dmitry Gorokhov of Nizhny Novgorod (RU) for intel corporation, Alexander Kozlov of Nizhny Novgorod (RU) for intel corporation
IPC Code(s): G06N3/082, G06F18/2113, G06N3/063, G06N5/04
CPC Code(s): G06N3/082
Abstract: systems, apparatuses and methods may provide for technology that aggregates contextual information from a first network layer in a neural network having a second network layer coupled to an output of the first network layer, wherein the context information is to be aggregated in real-time and after a training of the neural network, and wherein the context information is to include channel values. additionally, the technology may conduct an importance classification of the aggregated context information and selectively exclude one or more channels in the first network layer from consideration by the second network layer based on the importance classification.
Inventor(s): Mario Jose Divan Koller of Hillsboro OR (US) for intel corporation, Mariano Ortega De Mues of Hillsboro OR (US) for intel corporation, Marcos Emanuel Carranza of Portland OR (US) for intel corporation, Cesar Ignacio Martinez-Spessot of Hillsboro OR (US) for intel corporation, Mateo Guzman of Beaverton OR (US) for intel corporation, Francesc Guim Bernat of Barcelona (ES) for intel corporation, John Joseph Browne of Limerick (IE) for intel corporation, Mats Gustav Agerstam of Portland OR (US) for intel corporation, Gavin Bartlett Lewis of Hillsboro OR (US) for intel corporation, Abhishek Pillai of Beaverton OR (US) for intel corporation, Tejaswini Sirlapu of Hillsboro OR (US) for intel corporation
IPC Code(s): G06N20/00
CPC Code(s): G06N20/00
Abstract: systems, apparatus, articles of manufacture, and methods are disclosed to provide recommendations for device management. an example non-transitory machine readable storage medium comprising instructions to cause programmable circuitry to at least: determine an action to be performed for a plurality of computing devices, the action includes information about the computing devices and an operation to be performed on the computing devices; compare the action with a plurality of prior actions; and report a predicted result based on a similarity of the action with at least one of the plurality of prior actions.
20250005703. COMPUTE OPTIMIZATION MECHANISM_simplified_abstract_(intel corporation)
Inventor(s): Abhishek R. Appu of El Dorado Hills CA (US) for intel corporation, Altug Koker of El Dorado Hills CA (US) for intel corporation, Linda L. Hurd of Cool CA (US) for intel corporation, Dukhwan Kim of San Jose CA (US) for intel corporation, Mike B. Macpherson of Portland OR (US) for intel corporation, John C. Weast of Portland OR (US) for intel corporation, Feng Chen of Shanghai (CN) for intel corporation, Farshad Akhbari of Chandler AZ (US) for intel corporation, Narayan Srinivasa of Portland OR (US) for intel corporation, Nadathur Rajagopalan Satish of Santa Clara CA (US) for intel corporation, Joydeep Ray of Folsom CA (US) for intel corporation, Ping T. Tang of Edison NJ (US) for intel corporation, Michael S. Strickland of Sunnyvale CA (US) for intel corporation, Xiaoming Chen of Shanghai (CN) for intel corporation, Anbang Yao of Beijing (CN) for intel corporation, Tatiana Shpeisman of Menlo Park CA (US) for intel corporation
IPC Code(s): G06T1/20, G06F3/14, G06F9/30, G06F9/38, G06N3/044, G06N3/045, G06N3/063, G06N3/084, G06T15/00, G06T15/04, G09G5/36
CPC Code(s): G06T1/20
Abstract: an apparatus to facilitate compute optimization is disclosed. the apparatus includes a mixed precision core including mixed-precision execution circuitry to execute one or more of the mixed-precision instructions to perform a mixed-precision dot-product operation comprising to perform a set of multiply and accumulate operations.
Inventor(s): Noam Elron of Tel Aviv (IL) for intel corporation, Alexander Itskovich of Haifa (IL) for intel corporation, Shahar S Yuval of Haifa (IL) for intel corporation, Noam Levy of Karmiel (IL) for intel corporation
IPC Code(s): G06T3/4053, G06N3/08, G06T3/4046, G06T5/50, G06T5/70
CPC Code(s): G06T3/4053
Abstract: example methods, apparatus, systems, and articles directed to real-time super-resolution image processing using neural networks are disclosed. example apparatus disclosed herein cause a neural network to process an input frame of input video, the input video having a first resolution, the neural network trained to upscale the input frame to a second resolution, the neural network trained to reduce a presence of one or more types of image imperfections in the input frame. disclosed example apparatus also obtain, from the neural network, an output frame at the second resolution. disclosed example apparatus further cause the output frame to be presented as part of an output video at the second resolution.
20250005720. RESIZING FOR ENHANCED INFERENCE_simplified_abstract_(intel corporation)
Inventor(s): Sebastian Possos of Sammamish WA (US) for intel corporation, Penne Lee of Bellevue WA (US) for intel corporation, Yi-jen Chiu of San Jose CA (US) for intel corporation, Eric Palmer of La Grange KY (US) for intel corporation
IPC Code(s): G06T5/60, G06T3/4046, G06T7/00, G06T7/246
CPC Code(s): G06T5/60
Abstract: the lack of knowledge about a downstream consumer using a resized image can lead to poor inference quality of a machine learning model. inference quality can be improved when the resizing algorithm to produce resized images closely matches the one used during training of the machine learning model. to achieve this technical task, a resizer can be made aware of downstream consumer information and apply a suitable resizing algorithm. in one scenario, the downstream consumer information is received as metadata from a downstream process. in another scenario, an optimal resizing option can be determined to maximize inference quality. in yet another scenario, a likely resizing option can be determined by assessing a filtering profile determined based on a known original image and a known resized image.
Inventor(s): Dmitry Rudoy of Haifa (IL) for intel corporation, Rakefet Kol of Haifa (IL) for intel corporation, Noam Elron of Tel Aviv (IL) for intel corporation, Noam Levy of Karmiel (IL) for intel corporation
IPC Code(s): G06T7/194, G06T3/40, G06T7/11
CPC Code(s): G06T7/194
Abstract: systems, apparatus, articles of manufacture, and methods are disclosed to process images using segmentation. an example apparatus includes interface circuitry, machine readable instructions, and programmable circuitry to at least one of instantiate or execute the machine readable instructions to generate a scaled frame from an input video frame, segment, with a neural network, the scaled frame to generate a scaled segmentation map based on the scaled frame, the scaled segmentation map to associate pixels of the scaled frame with ones of a plurality of segments in the scaled frame, and generate an output video frame based on the input video frame and an upscaled version of the scaled segmentation map.
Inventor(s): Mallari C. Hanchate of Bangalore (IN) for intel corporation, Bharatkumar Mahajan of Bangalore (IN) for intel corporation, Manisha Raiguru of Bangalore (IN) for intel corporation, Krishna Kishore Nidamanuri of Bangalore (IN) for intel corporation
IPC Code(s): G06V10/60, G06T5/00, G06V10/25, G09G3/3208
CPC Code(s): G06V10/60
Abstract: various embodiments herein provide apparatuses, systems, and methods associated with a region-based power saving scheme for a display, such as an organic light-emitting diode (oled) display. in embodiments, pixels of an image may be allocated to two or more subsets including a first subset that corresponds to a region of interest (roi). the two or more subsets may further include a second subset that includes some or all of the pixels that are outside of the roi. a more aggressive power saving scheme may be applied to the second subset compared with the first subset (which may or may not undergo a power saving scheme). in some embodiments, a saturation level of the pixels of the second subset may be increased in addition to the dimming. other embodiments may be described and claimed.
Inventor(s): Cornelius BUERKLE of Karlsruhe (DE) for intel corporation, Fabian OBORIL of Karlsruhe (DE) for intel corporation
IPC Code(s): G06V20/59, B60K35/28, B60K35/29, G06V10/75, G06V10/82, G06V10/94, G06V10/98
CPC Code(s): G06V20/59
Abstract: a safety device comprising: an image data analyzer configured to receive data representing an image for display on a vehicle display; to identify a safety-relevant part of the image based on the data; to determine a value representing the identified safety-relevant part of the image; and a safety checker configured to compare the value with a reference value; wherein the safety device is configured to implement a first mode of operation if the comparison of the value with the reference value is within a comparison range; and to implement a second mode of operation different from the first mode of operation if the comparison of the value with the reference value is outside the comparison range.
Inventor(s): Susanta Bhattacharjee of Bangalore (IN) for intel corporation, Kunjal Parikh of Fremont CA (US) for intel corporation
IPC Code(s): G09G3/20, G09G3/3208
CPC Code(s): G09G3/2096
Abstract: a device, including: processing circuitry operable to determine boosted subpixel values for subpixels in a camera under display (cud) area of a display panel, wherein each boosted subpixel value is based on a ratio of a non-cud subpixel aperture area to a cud subpixel aperture area for a corresponding subpixel of the display panel; and a display driver operable to boost a brightness of each subpixel in the cud area based on the respective boosted subpixel value.
20250006139. BACKLIGHT ADJUSTMENT TECHNOLOGIES_simplified_abstract_(intel corporation)
Inventor(s): Susanta BHATTACHARJEE of Bangalore (IN) for intel corporation, Mohafiz Ulla KHAN of Bangalore (IN) for intel corporation, Greeshma VK of Mysore (IN) for intel corporation, Ashish ROY of Jaipur (IN) for intel corporation
IPC Code(s): G09G3/34
CPC Code(s): G09G3/3406
Abstract: a system that includes at least one processor that is to execute a software to: determine pixel value adjustments based on a limit on contrast loss and to reduce power consumption of a display connected to the display interface and provide the pixel value adjustments to the display interface to apply to pixels of a video frame.
Inventor(s): Richmond Hicks of Aloha OR (US) for intel corporation, Arthur J. Runyan of Folsom CA (US) for intel corporation, Nausheen Ansari of Folsom CA (US) for intel corporation, Narayan Biswal of Folsom CA (US) for intel corporation
IPC Code(s): G09G5/22, G06F3/01, G09G5/377, H04N19/107, H04N19/159, H04N19/174
CPC Code(s): G09G5/227
Abstract: a system for reducing bandwidth and/or reducing power consumed by a display may comprise a display having a background plane and a region of interest plane that may be identified by a gaze tracker. the region of interest may be of a higher quality picture. in some embodiments, the display may be a large panel display and in others a head mounted display (hmd).
20250006234. LEAKAGE COMPENSATED DYNAMIC LATCH_simplified_abstract_(intel corporation)
Inventor(s): Ganesan Iyer of Phoenix AZ (US) for intel corporation, Anupama A. Thaploo of Folsom CA (US) for intel corporation, Ananthakrishnan Ponnileth Rajendran of Rancho Cordova CA (US) for intel corporation
IPC Code(s): G11C7/10, G11C7/22
CPC Code(s): G11C7/106
Abstract: some embodiments include input stage of a latch to receive input data information and clock information; a memory node coupled to the input stage to store information based on the input data information; an output stage of the latch coupled to the memory node and including an output node to provide output data information based on the information stored at the memory node; a first circuit to provide a first circuit path between the memory node and a first node in the input stage; and a second circuit to provide a second circuit path between the memory node and a second node in the input stage.
Inventor(s): Sarah Atanasov of Beaverton OR (US) for intel corporation, Elijah Karpov of Portland OR (US) for intel corporation, Nazila Haratipour of Portland OR (US) for intel corporation, Sou-Chi Chang of Portland OR (US) for intel corporation, Tristan Tronic of Aloha OR (US) for intel corporation
IPC Code(s): H01G7/06, H10B53/00
CPC Code(s): H01G7/06
Abstract: apparatuses, memory systems, capacitor structures, and techniques related to ferroelectric capacitors having a hafnium-zirconium oxide film between the electrodes of the capacitor are discussed. the hafnium-zirconium oxide film is thin and has large crystallite grains. the thin large grain hafnium-zirconium oxide film having large grains is formed by depositing a thick hafnium-zirconium oxide film and annealing the thick hafnium-zirconium oxide film to establish the large grain size, and etching back the hafnium-zirconium oxide film to the desired thickness for deployment in the ferroelectric capacitor.
Inventor(s): Chia-Ching Lin of Portland OR (US) for intel corporation, Sou-Chi Chang of Portland OR (US) for intel corporation, Ashish Verma Penumatcha of Hillsboro OR (US) for intel corporation, Nazila Haratipour of Hillsboro OR (US) for intel corporation, Seung Hoon Sung of Portland OR (US) for intel corporation, Owen Y. Loh of Portland OR (US) for intel corporation, Jack Kavalieros of Portland OR (US) for intel corporation, Uygar E. Avci of Portland OR (US) for intel corporation, Ian A. Young of Portland OR (US) for intel corporation
IPC Code(s): H01G7/06, H10B12/00
CPC Code(s): H01G7/06
Abstract: described is a ferroelectric-based capacitor that improves reliability of a ferroelectric memory by using low-leakage insulating thin film. in one example, the low-leakage insulating thin film is positioned between a bottom electrode and a ferroelectric oxide. in another example, the low-leakage insulating thin film is positioned between a top electrode and ferroelectric oxide. in yet another example, the low-leakage insulating thin film is positioned in the middle of ferroelectric oxide to reduce the leakage current and improve reliability of the ferroelectric oxide.
Inventor(s): Allen Gardiner of Portland OR (US) for intel corporation, Nikhil Mehta of Portland OR (US) for intel corporation, Shu Zhou of Portland OR (US) for intel corporation, Travis LaJoie of Forest Grove OR (US) for intel corporation, Shem Ogadhoh of West Linn OR (US) for intel corporation, Akash Garg of Portland OR (US) for intel corporation, Van Le of Beaverton OR (US) for intel corporation, Christopher Pelto of Beaverton OR (US) for intel corporation, Bernhard Sell of Portland OR (US) for intel corporation
IPC Code(s): H01L21/033, H10B12/00
CPC Code(s): H01L21/0337
Abstract: a method for manufacturing integrated circuit (ic) devices includes forming first and second mask patterns with overlapping and non-overlapping features. non-overlapping features may be removed before etching a target material layer. a third mask pattern may be formed from the overlapping features and used to etch a target material layer. the third mask pattern may be employed to make regular arrays of substantially rectangular structures.
Inventor(s): Allen Gardiner of Portland OR (US) for intel corporation, Nikhil Mehta of Portland OR (US) for intel corporation, Shu Zhou of Portland OR (US) for intel corporation, Travis LaJoie of Forest Grove OR (US) for intel corporation, Shem Ogadhoh of West Linn OR (US) for intel corporation, Akash Garg of Portland OR (US) for intel corporation, Van Le of Beaverton OR (US) for intel corporation, Christopher Pelto of Beaverton OR (US) for intel corporation, Bernhard Sell of Portland OR (US) for intel corporation
IPC Code(s): H01L21/033, H10B12/00
CPC Code(s): H01L21/0337
Abstract: an ic device may include an ic die, an array of structures on a layer of the ic die, and multiple groups of parallel stripes of indentations or depressions in the layer. the structures may each include a transistor and a capacitor.
Inventor(s): Mohammad HASAN of Aloha OR (US) for intel corporation, Angel AQUINO GONZALEZ of Beaverton OR (US) for intel corporation, Tahir GHANI of Portland OR (US) for intel corporation, Conor P. PULS of Portland OR (US) for intel corporation, Mitali CHINA of Portland OR (US) for intel corporation
IPC Code(s): H01L21/762, H01L29/775, H01L29/78
CPC Code(s): H01L21/76224
Abstract: integrated circuit structures having removed sub-fins, and methods of fabricating integrated circuit structures having removed sub-fins, are described. for example, an integrated circuit structure includes a channel structure, and a sub-fin isolation structure in a trench beneath the channel structure, wherein there is no residual silicon portion in the trench.
Inventor(s): Ramanan Ehamparam of Beaverton OR (US) for intel corporation, Ebubekir Dogan of Portland OR (US) for intel corporation, Maria Stancescu of Lake Oswego OR (US) for intel corporation
IPC Code(s): H01L21/768, H01L21/67
CPC Code(s): H01L21/76876
Abstract: devices, systems, and techniques are described herein related to reducing or eliminating galvanic corrosion of tungsten conductive features within tungsten-boron liners during wet clean thereof. the tungsten-boron liner is treated with a hydrogen/nitrogen plasma to modify a portion of the liner extending from the top surface to include tungsten, boron, nitrogen, and optionally oxygen. the modified portion of the liner reduces or eliminates galvanic corrosion during wet etch clean.
Inventor(s): Ehren MANNEBACH of Tigard OR (US) for intel corporation, Shaun MILLS of Hillsboro OR (US) for intel corporation, Joseph D’SILVA of Hillsboro OR (US) for intel corporation, Mauro J. KOBRINSKY of Portland OR (US) for intel corporation
IPC Code(s): H01L23/14, H01L23/00, H01L23/15
CPC Code(s): H01L23/147
Abstract: structures having alternative carriers for dual-sided devices are described. in an example, an integrated circuit structure includes a front side structure including a device layer, and a plurality of metallization layers above the device layer. a backside structure is below the device layer. a carrier wafer or substrate is bonded directly to and is in contact with the front side structure, or is bonded to the front side structure by a compliant bonding layer.
Inventor(s): Gang Duan of Chandler AZ (US) for intel corporation, Minglu Liu of Chandler AZ (US) for intel corporation, Srinivas Venkata Ramanuja Pietambaram of Chandler AZ (US) for intel corporation
IPC Code(s): H01L23/15, H01L23/24, H01L23/367, H01L23/538
CPC Code(s): H01L23/15
Abstract: systems, apparatus, articles of manufacture, and methods for package substrates with stacks of glass layers having different coefficients of thermal expansion are disclosed. an example substrate for an integrated circuit package includes: a first glass layer having a first coefficient of thermal expansion (cte); and a second glass layer having a second cte, the second cte different from the first cte.
Inventor(s): Gang Duan of Chandler AZ (US) for intel corporation, Srinivas Venkata Ramanuja Pietambaram of Chandler AZ (US) for intel corporation, Jeremy Ecton of Gilbert AZ (US) for intel corporation, Brandon Christian Marin of Gilbert AZ (US) for intel corporation
IPC Code(s): H01L23/15, H01L23/00, H01L23/31, H01L23/373, H01L23/498, H01L23/538, H01L25/065
CPC Code(s): H01L23/15
Abstract: glass cores including multiple layers and related methods are disclosed. an apparatus disclosed herein includes a printed circuit board and an integrated circuit package coupled to the printed circuit board, the integrated circuit package including a die and a glass core including a first layer having a first coefficient of thermal expansion and a second layer having a second coefficient of thermal expansion different than the first coefficient of thermal expansion.
Inventor(s): Gang Duan of Chandler AZ (US) for intel corporation, Minglu Liu of Chandler AZ (US) for intel corporation, Srinivas Venkata Ramanuja Pietambaram of Chandler AZ (US) for intel corporation
IPC Code(s): H01L23/15, H01L23/538
CPC Code(s): H01L23/15
Abstract: systems, apparatus, articles of manufacture, and methods for stacks of glass layers including thin film capacitors are disclosed. an example substrate includes a first glass layer, a dielectric layer on the first glass layer, a second glass layer, the first glass layer between the dielectric layer and the second glass layer, and a capacitor in the layer.
Inventor(s): Avijit Barik of Portland OR (US) for intel corporation, Tao Chu of Portland OR (US) for intel corporation, Minwoo Jang of Portland OR (US) for intel corporation, Aurelia Wang of Hillsboro OR (US) for intel corporation, Conor P. Puls of Portland OR (US) for intel corporation
IPC Code(s): H01L23/31, H01L21/02, H01L21/8234, H01L27/02, H01L27/088, H01L29/06, H01L29/417
CPC Code(s): H01L23/3171
Abstract: devices, transistor structures, systems, and techniques are described herein related to providing a backside passivation layer on a transistor semiconductor material. the semiconductor material is between source and drain structures, and a gate structure is adjacent a channel region of the semiconductor material. the passivation layer is formed as a conformal insulative layer on a backside of the semiconductor material and is then treated using an ozone/uv cure to remove trap charges from the semiconductor material.
Inventor(s): Jiun Hann Sir of Gelugor (MY) for intel corporation, Poh Boon Khoo of Perai (MY) for intel corporation
IPC Code(s): H01L23/427, H01L21/48, H01L25/18
CPC Code(s): H01L23/427
Abstract: a semiconductor assembly may include a package substrate. a semiconductor assembly may include a first semiconductor die on the package substrate. a semiconductor assembly may include a first heat spreader heat spreader is attached to the first semiconductor die opposite the package substrate, the heat spreader comprising a mesh infused with phase change material, wherein the heat spreader is configured to dissipate heat from the first semiconductor die.
Inventor(s): Nischal Arkali Radhakrishna of Hillsboro OR (US) for intel corporation, Chinhsuan Chen of Portland OR (US) for intel corporation, Sivakumar Venkataraman of Hillsboro OR (US) for intel corporation, Somashekar Bangalore Prakash of Portland OR (US) for intel corporation, Marni Nabors of Portland OR (US) for intel corporation
IPC Code(s): H01L23/48, H01L23/522, H01L23/528, H10B41/10, H10B41/27, H10B41/35, H10B43/10, H10B43/27, H10B43/35
CPC Code(s): H01L23/481
Abstract: an integrated circuit (ic) device may include standard cells with multiple parallel paths interconnecting transistors at a device level and over a transistor, in a higher layer of an interconnect structure. the parallel paths may include multiple power supply via contacts on a transistor source structure and multiple supply interconnect lines over the transistor and coupling the transistor to an associated power supply. the parallel paths may include multiple output via contacts on an integrated transistor drain structure and multiple output interconnect lines over a complementary transistor device. the parallel paths may include separate, rather than shared or integrated, adjacent source structures coupled to a same power supply.
20250006592. LOW-RESISTANCE VIA STRUCTURES_simplified_abstract_(intel corporation)
Inventor(s): Ming-Yi Shen of Portland OR (US) for intel corporation, Chi-Hing Choi of Portland OR (US) for intel corporation, Jaladhi Mehta of Beaverton OR (US) for intel corporation, Tofizur Rahman of Portland OR (US) for intel corporation, Payam Amin of Portland OR (US) for intel corporation, Justin E. Mueller of Portland OR (US) for intel corporation, Vincent Hipwell of Hillsboro OR (US) for intel corporation, Cortnie S. Vogelsberg of Beaverton OR (US) for intel corporation, Shivani Falgun Patel of Hillsboro OR (US) for intel corporation
IPC Code(s): H01L23/48, H01L21/768, H01L27/088
CPC Code(s): H01L23/481
Abstract: techniques to form low-resistance vias are discussed. in an example, semiconductor devices of a given row each include a semiconductor region extending in a first direction between corresponding source or drain regions, and a gate structure extending in a second direction over the semiconductor regions. any semiconductor device may be separated from an adjacent semiconductor device along the second direction by a dielectric structure, through which a via passes. the via may include a conductive portion that extends through a dielectric wall in a third direction along at least an entire thickness of the gate structure. the conductive portion includes a conductive liner directly on the dielectric wall and a conductive fill on the conductive liner. the conductive liner comprises a pure elemental metal, such as tungsten, molybdenum, ruthenium, or a nickel aluminum alloy, with no metal nitride or barrier layer present between the conductive liner and the dielectric wall.
Inventor(s): Gang Duan of Chandler AZ (US) for intel corporation, Ibrahim El Khatib of Chandler AZ (US) for intel corporation, Jesse Cole Jones of Chandler AZ (US) for intel corporation, Yi Li of Chandler AZ (US) for intel corporation, Minglu Liu of Chandler AZ (US) for intel corporation, Robin Shea McRee of Chandler AZ (US) for intel corporation, Srinivas Venkata Ramanuja Pietambaram of Chandler AZ (US) for intel corporation, Praveen Sreeramagiri of Gilbert AZ (US) for intel corporation
IPC Code(s): H01L23/498, H01L23/15, H01L25/065
CPC Code(s): H01L23/49822
Abstract: systems, apparatus, articles of manufacture, and methods for package substrates with stacks of glass layers having different coefficients of thermal expansion are disclosed. an example package substrate includes: a first glass layer including a first through glass via extending therethrough, the first glass layer having a first coefficient of thermal expansion (cte); and a second glass layer including a second through glass via extending therethrough, the second glass layer having a second cte different from the first cte, the first through glass via electrically coupled to the second through glass via.
Inventor(s): Srinivas Venkata Ramanuja Pietambaram of Chandler AZ (US) for intel corporation, Gang Duan of Chandler AZ (US) for intel corporation, Minglu Liu of Chandler AZ (US) for intel corporation
IPC Code(s): H01L23/498, H01L23/15, H01L25/065
CPC Code(s): H01L23/49822
Abstract: systems, apparatus, articles of manufacture, and methods for power delivery through package substrates with stacks of glass layers having different coefficients of thermal expansion are disclosed. an example substrate for an integrated circuit package includes: a first glass layer having a first coefficient of thermal expansion (cte); a second glass layer having a second cte, the second cte different from the first cte; and a magnetic material lining a first wall of a first opening in the first glass layer and lining a second wall of a second opening in the second glass layer.
Inventor(s): Srinivas Venkata Ramanuja Pietambaram of Chandler AZ (US) for intel corporation, Gang Duan of Chandler AZ (US) for intel corporation, Minglu Liu of Chandler AZ (US) for intel corporation
IPC Code(s): H01L23/498, H01L23/15, H01L23/64, H01L25/065
CPC Code(s): H01L23/49822
Abstract: systems, apparatus, articles of manufacture, and methods for power delivery through package substrates with stacks of glass layers having different coefficients of thermal expansion are disclosed. an example integrated circuit (ic) package includes: a package core including a first glass sheet and a second glass sheet distinct from the first glass sheet, the first glass sheet having a different coefficient of thermal expansion (cte) from the second glass sheet; a first redistribution layer on a first side of the package core; a second redistribution layer on a second side of the package core, the second side opposite the first side; and an interconnect extending through the package core, the interconnect including a magnetic material.
Inventor(s): Srinivas Venkata Ramanuja Pietambaram of Chandler AZ (US) for intel corporation, Gang Duan of Chandler AZ (US) for intel corporation, Minglu Liu of Chandler AZ (US) for intel corporation
IPC Code(s): H01L23/498, H01L23/15, H01L23/64, H01L25/065
CPC Code(s): H01L23/49822
Abstract: systems, apparatus, articles of manufacture, and methods for power delivery through package substrates with stacks of glass layers having different coefficients of thermal expansion are disclosed. an example substrate for an integrated circuit package includes: a first glass layer having a first coefficient of thermal expansion (cte); a second glass layer having a second cte, the second cte different from the first cte; a conductive material extending through a first hole in the first glass layer and a second hole in the second glass layer; and a magnetic material between an inner wall of the first hole and the conductive material.
Inventor(s): Srinivas Venkata Ramanuja Pietambaram of Chandler AZ (US) for intel corporation, Gang Duan of Chandler AZ (US) for intel corporation, Minglu Liu of Chandler AZ (US) for intel corporation
IPC Code(s): H01L23/498, H01L23/15, H01L23/538, H01L25/065
CPC Code(s): H01L23/49822
Abstract: systems, apparatus, articles of manufacture, and methods for package substrates with stacks of glass layers including interconnect bridges are disclosed. an example substrate for an integrated circuit package includes: a first glass layer having a cavity defined therein; a second glass layer different from the first glass layer; and an interconnect bridge at least partially in the cavity. the interconnect bridge electrically couples a first semiconductor die to a second semiconductor die.
Inventor(s): Suddhasattwa Nad of Chandler AZ (US) for intel corporation, Kristof Darmawikarta of Chandler AZ (US) for intel corporation, Jason Steill of Phoenix AZ (US) for intel corporation, Srinivas Pietambaram of Chandler AZ (US) for intel corporation, Marcel Wall of Phoenix AZ (US) for intel corporation
IPC Code(s): H01L23/498, H01L21/48, H01L23/00, H01L25/065, H01L25/18, H10B80/00
CPC Code(s): H01L23/49838
Abstract: ic die package with hybrid metallization surfaces. routing metallization features have lower surface roughness for reduced high-frequency signal transmission losses while ic die attach metallization features have higher surface roughness for greater adhesion. routing and die attach features may be formed within a same package metallization level, for example with a plating process. an insulator material may be formed over the surface of the metallization features, for example with a dry film lamination process. optionally, an interface material may be deposited upon at least the routing features to enhance adhesion of the insulator material to metallization surfaces of low roughness. an opening in the insulator material may be formed to expose a surface of a die attach feature. the exposed surface may be selectively roughened, and an ic die attached to the roughened surface.
Inventor(s): Shuqi Lai of Phoenix AZ (US) for intel corporation, Jieying Kong of Chandler AZ (US) for intel corporation, Dilan Seneviratne of Phoenix AZ (US) for intel corporation, Whitney Bryks of Tempe AZ (US) for intel corporation
IPC Code(s): H01L23/498
CPC Code(s): H01L23/49894
Abstract: microelectronic integrated circuit package structures include one or more integrated circuit (ic) package metallization levels comprising metallization features. a dielectric material is adjacent to one or more of the metallization features, where the dielectric material comprises a matrix material and a surfactant. a plurality of substantially spherical pores are within the matrix material, where the substantially spherical pores are surrounded by an outer shell comprising the matrix material.
Inventor(s): Leonard P. GULER of Hillsboro OR (US) for intel corporation, Vishal TIWARI of Hillsboro OR (US) for intel corporation, Akm Shaestagir CHOWDHURY of Portland OR (US) for intel corporation, Charles H. WALLACE of Portland OR (US) for intel corporation
IPC Code(s): H01L23/522, H01L21/768, H01L23/532
CPC Code(s): H01L23/5226
Abstract: embodiments of the disclosure are in the field of integrated circuit structure fabrication. in an example, an integrated circuit structure includes a conductive via in a first dielectric layer. the integrated circuit structure also includes a conductive line in a second dielectric layer, the conductive including a conductive liner having a conductive barrier therein, the conductive barrier having a conductive fill therein, wherein the conductive liner is directly on the conductive via.
Inventor(s): Carla Moran Guizan of Munich (DE) for intel corporation, Peter Baumgartner of Munich (DE) for intel corporation, Thomas Wagner of Regelsbach (DE) for intel corporation, Georg Seidemann of Landshut (DE) for intel corporation, Michael Langenbuch of Munich (DE) for intel corporation, Mamatha Yakkegondi Virupakshappa of Munich (DE) for intel corporation, Jonathan Jensen of Portland OR (US) for intel corporation, Roshini Sachithanandan of Munich (DE) for intel corporation, Philipp Riess of Munich (DE) for intel corporation
IPC Code(s): H01L23/522, H01L23/00, H01L23/528, H01L25/065
CPC Code(s): H01L23/5227
Abstract: described herein are integrated circuit devices that include conductive structures formed by direct bonding of different components, e.g., direct bonding of two dies, or of a die to a wafer. the conductive structures are formed from a top metallization layer of each of the components. for example, elongated conductive structures at the top metallization layer may be patterned and bonded to form large interconnects for high-frequency and/or high-power signals. in another example, the bonded conductive structures may form radio frequency passive devices, such as inductors or transformers.
Inventor(s): Debendra Mallik of Chandler AZ (US) for intel corporation, Ram Viswanath of Phoenix AZ (US) for intel corporation, Xavier Brun of Hillsboro OR (US) for intel corporation
IPC Code(s): H01L23/538, H01L21/48, H01L23/00, H01L23/373, H01L23/498, H01L25/065
CPC Code(s): H01L23/5381
Abstract: microelectronic integrated circuit package structures include a package substrate with a first die over the package substrate, and a second die adjacent to the first die, such that first sides of the first die and the second die are on a thermal solution. a bridge structure is directly on a portion of each of second sides of the first and second dies, such that the second sides include integrated circuit contact structures. bridge via structures couple the integrated circuit contact structures to the bridge structure.
Inventor(s): Xiao Liu of Chandler AZ (US) for intel corporation, Bohan Shan of Chandler AZ (US) for intel corporation, Dingying Xu of Chandler AZ (US) for intel corporation, Gang Duan of Chandler AZ (US) for intel corporation, Haobo Chen of Chandler AZ (US) for intel corporation, Hongxia Feng of Chandler AZ (US) for intel corporation, Jung Kyu Han of Chandler AZ (US) for intel corporation, Xiaoying Guo of Chandler AZ (US) for intel corporation, Zhixin Xie of Chandler AZ (US) for intel corporation, Xiyu Hu of Chandler AZ (US) for intel corporation, Robert Alan May of Chandler AZ (US) for intel corporation, Kristof Kuwawi Darmawikarta of Chandler AZ (US) for intel corporation, Changhua Liu of Chandler AZ (US) for intel corporation, Yosuke Kanaoka of () for intel corporation
IPC Code(s): H01L23/538, H01L23/00, H01L23/15, H01L23/31, H01L23/58, H01L25/10
CPC Code(s): H01L23/5381
Abstract: microelectronic assemblies, related devices and methods, are disclosed herein. in some embodiments, a microelectronic assembly may include a first layer of a substrate including a first material having a cavity and a conductive pad at a bottom of the cavity; a first microelectronic component having a first surface and an opposing second surface, the first microelectronic component in the cavity and electrically coupled to the conductive pad at the bottom of the cavity; a second layer of the substrate on the first layer of the substrate, the second layer including a second material that extends into the cavity and on and around the first microelectronic component, wherein the second material includes an organic photoimageable dielectric (pid) or an organic non-photoimageable dielectric (non-pid); and a second microelectronic component electrically coupled to the second surface of the first microelectronic component by conductive pathways through the second layer of the substrate.
Inventor(s): Xing Sun of Chandler AZ (US) for intel corporation, Srinivas Pietambaram of Chandler AZ (US) for intel corporation, Darko Grujicic of Chandler AZ (US) for intel corporation, Rengarajan Shanmugam of Tempe AZ (US) for intel corporation, Brian Balch of Chandler AZ (US) for intel corporation, Micah Armstrong of Scottsdale AZ (US) for intel corporation, Qiang Li of Chandler AZ (US) for intel corporation, Marcel Wall of Phoenix AZ (US) for intel corporation, Rahul Manepalli of Chandler AZ (US) for intel corporation
IPC Code(s): H01L23/538, H01L21/48, H01L23/00, H01L23/15, H01L25/065
CPC Code(s): H01L23/5384
Abstract: integrated circuit (ic) die packages including a glass with conductive through-glass vias (tgvs). the tgvs are lined with a buffer comprising an inorganic material having a low elastic (young's) modulus. the buffer may thereby accommodate internal stress between the glass and through via metallization formed over the buffer. the compliant inorganic material may be a metal or metal alloy, for example, different than that of the via metallization. the inorganic material may also be a metal nitride, metal silicide, or metal carbide. a tgv buffer may be one material layer of a stack comprising two or more material layers deposited upon tgv sidewall surfaces. a routing structure may be built-up on at least one side of the glass and ic die assembled to the routing structure. the buffer ipresent within the tgvs may be absent from metal features of the routing structure.
Inventor(s): Omkar G. Karhade of Chandler AZ (US) for intel corporation, Nitin A. Deshpande of Chandler AZ (US) for intel corporation, Francisco Maya of Portland OR (US) for intel corporation, Khant Minn of Chandler AZ (US) for intel corporation, Suresh V. Pothukuchi of Chandler AZ (US) for intel corporation, Arnab Sarkar of Chandler AZ (US) for intel corporation, Mohit Bhatia of Chandler AZ (US) for intel corporation, Bhaskar Jyoti Krishnatreya of Hillsboro OR (US) for intel corporation, Siyan Dong of Chandler AZ (US) for intel corporation
IPC Code(s): H01L23/544, H01L23/00
CPC Code(s): H01L23/544
Abstract: an apparatus comprising a first integrated circuit device, the first integrated circuit device comprising a fiducial having a length size greater than a width size of the fiducial, wherein the fiducial comprises at least one first area and at least one second area, wherein the at least one first area is to stop light from a light source and the at least one second area is to pass light from the light source during a determination of an alignment between the first integrated circuit device and a second integrated circuit device.
Inventor(s): Omkar G. Karhade of Chandler AZ (US) for intel corporation, Nitin A. Deshpande of Chandler AZ (US) for intel corporation, Francisco Maya of Portland OR (US) for intel corporation, Bhaskar Jyoti Krishnatreya of Hillsboro OR (US) for intel corporation, Tan Nguyen of Hillsboro OR (US) for intel corporation, Siyan Dong of Chandler AZ (US) for intel corporation, Alveera Gill of Hillsboro OR (US) for intel corporation, Keith E. Zawadzki of Portland OR (US) for intel corporation
IPC Code(s): H01L23/544, H01L23/00, H01L25/065
CPC Code(s): H01L23/544
Abstract: an apparatus comprising a first integrated circuit device, the first integrated circuit device comprising a first layer with an area comprising metallization and metal-free slits; and a fiducial in a second layer above the first layer, the fiducial formed over the area comprising the metallization and metal-free slits.
Inventor(s): Omkar G. Karhade of Chandler AZ (US) for intel corporation, Nitin A. Deshpande of Chandler AZ (US) for intel corporation, Bhaskar Jyoti Krishnatreya of Hillsboro OR (US) for intel corporation, Francisco Maya of Portland OR (US) for intel corporation, Siyan Dong of Chandler AZ (US) for intel corporation, Alveera Gill of Hillsboro OR (US) for intel corporation, Tan Nguyen of Hillsboro OR (US) for intel corporation, Keith E. Zawadzki of Portland OR (US) for intel corporation
IPC Code(s): H01L23/544, H01L23/00, H01L25/065
CPC Code(s): H01L23/544
Abstract: an apparatus comprising an integrated circuit device comprising a fiducial area of a first layer, the fiducial area comprising a metal area and a metal free area; and a plurality of zones that are metal free in multiple layers adjacent to the first layer, wherein the zones are defined by a footprint based on the fiducial area of the first layer and a second fiducial area of a second integrated circuit device, the footprint comprising multiple slits.
Inventor(s): Gang Duan of Chandler AZ (US) for intel corporation, Minglu Liu of Chandler AZ (US) for intel corporation, Srinivas Venkata Ramanuja Pietambaram of Chandler AZ (US) for intel corporation
IPC Code(s): H01L23/64, H01L23/00, H01L23/15, H01L23/31, H01L23/498, H01L23/535, H01L25/11, H01L25/18, H01L29/66
CPC Code(s): H01L23/642
Abstract: systems, apparatus, articles of manufacture, and methods for stacks of glass layers including deep trench capacitors are disclosed. an example substrate for an integrated circuit package disclosed herein includes a first glass layer, a second glass layer coupled to the first glass layer, and a deep trench capacitor embedded in the first core.
Inventor(s): Jiun Hann Sir of Gelugor (MY) for intel corporation, Poh Boon Khoo of Perai (MY) for intel corporation
IPC Code(s): H01L23/66, H01P3/08, H01P11/00
CPC Code(s): H01L23/66
Abstract: an integrated circuit (ic) device includes an ic die on a substrate, and the substrate includes a group of conductive lines between a high-permittivity dielectric layer and a low-permittivity dielectric layer, with a ground plane separated from the conductive lines by either the high- or low-permittivity dielectric layer. the substrate may include other low-permittivity dielectric layers. the substrate may include other groups of conductive lines between ground planes. the high-permittivity dielectric layer may be within a low-permittivity dielectric core layer.
Inventor(s): Georgios PANAGOPOULOS of Munich (DE) for intel corporation, Steven CALLENDER of Denver CO (US) for intel corporation, Richard GEIGER of Munich (DE) for intel corporation, Georgios C. DOGIAMIS of Chandler AZ (US) for intel corporation, Manisha DUTTA of Munich (DE) for intel corporation, Stefano PELLERANO of Beaverton OR (US) for intel corporation
IPC Code(s): H01L23/66, H01L29/16, H01L29/20, H03F3/195, H03F3/213
CPC Code(s): H01L23/66
Abstract: embodiments herein relate to systems, apparatuses, or processes directed to a package for wideband sub-terahertz communication, where the package includes a mixer and an amplifier, such as a power amplifier or a low noise amplifier, that are implemented within a layer of iii-v material. other embodiments may be described and/or claimed.
Inventor(s): Carla Moran Guizan of Munich (DE) for intel corporation, Peter Baumgartner of Munich (DE) for intel corporation, Michael Langenbuch of Munich (DE) for intel corporation, Mamatha Yakkegondi Virupakshappa of Munich (DE) for intel corporation, Jonathan Jensen of Portland OR (US) for intel corporation, Roshini Sachithanandan of Munich (DE) for intel corporation, Philipp Riess of Munich (DE) for intel corporation
IPC Code(s): H01L23/66, H01L23/528
CPC Code(s): H01L23/66
Abstract: waveguide structures are built into integrated circuit devices using standard processing steps for semiconductor device fabrication. a waveguide may include a base, a top, and two side walls. at least one of the walls (e.g., the base or the top) may be formed in a metal layer. the base or top may be patterned to provide a transition to a planar transmission line, such as a coplanar waveguide. the side walls may be formed using vias.
20250006671. SEMICONDUCTOR LAYER WITH DRY DEPOSITION LAYER_simplified_abstract_(intel corporation)
Inventor(s): Marcel Arlan Wall of Phoenix AZ (US) for intel corporation, Hamid Azimi of Chandler AZ (US) for intel corporation, Rahul N. Manepalli of Chandler AZ (US) for intel corporation, Srinivas Venkata Ramanuja Pietambaram of Chandler AZ (US) for intel corporation, Darko Grujicic of Chandler AZ (US) for intel corporation, Steve Cho of Chandler AZ (US) for intel corporation, Thomas L. Sounart of Chandler AZ (US) for intel corporation, Gang Duan of Chandler AZ (US) for intel corporation, Jung Kyu Han of Chandler AZ (US) for intel corporation, Suddhasattwa Nad of Chandler AZ (US) for intel corporation, Benjamin Duong of Phoenix AZ (US) for intel corporation, Shayan Kaviani of Phoenix AZ (US) for intel corporation
IPC Code(s): H01L23/00
CPC Code(s): H01L24/03
Abstract: an intermediary layer, such as a dry deposition layer or a surface finish, is deposited on at least one exposed surface of surfaces within a layer of a semiconductor substrate. the intermediary layer is deposited on at least an electrically conductive material within a cavity in a layer. the intermediary layer is deposited using a chemical deposition process such as physical vapor deposition, chemical vapor deposition or sputtering.
Inventor(s): Siva Prasad JANGILI GANGA of Jagityal Dist (IN) for intel corporation, Ajmeer Kaja AYUBKHAN of Bangalore (IN) for intel corporation, Bharath Reddy GUDIGOPURAM of Nalgonda (IN) for intel corporation
IPC Code(s): H01L23/00, H01L21/48, H01L23/498, H05K1/02
CPC Code(s): H01L24/05
Abstract: the present disclosure is directed to package-on-package structures having a package substrate with an embedded logic package disposed on the package substrate and having heat conductive pathways being provided in the package-on-package structure for removing heat from the logic package. in an aspect, the heat conductive pathways enable a downward transfer of the heat generated by the logic package toward the package substrate. in another aspect, the heat conducting pathways may include a heat transfer layer formed proximally to a bottom surface of the logic package. in a further aspect, the heat conducting pathways may include one or more metal vias in the package substrate.
Inventor(s): Omkar G. Karhade of Chandler AZ (US) for intel corporation, Harini Kilambi of Portland OR (US) for intel corporation, Kimin Jun of Portland OR (US) for intel corporation, Adel A. Elsherbini of Chandler AZ (US) for intel corporation, John Edward Zeug Matthiesen of Hillsboro OR (US) for intel corporation, Trianggono Widodo of Hillsboro OR (US) for intel corporation, Adita Das of Beaverton OR (US) for intel corporation, Mohit Bhatia of Chandler AZ (US) for intel corporation, Dimitrios Antartis of Hillsboro OR (US) for intel corporation, Bhaskar Jyoti Krishnatreya of Hillsboro OR (US) for intel corporation, Rajesh Surapaneni of Portland OR (US) for intel corporation, Xavier Francois Brun of Hillsboro OR (US) for intel corporation
IPC Code(s): H01L23/00, H01L23/31, H01L23/544, H01L25/065
CPC Code(s): H01L24/08
Abstract: disclosed herein are microelectronic assemblies, related apparatuses, and methods. in some embodiments, a microelectronic assembly may include a first die in a first layer; and a second and third die in a second layer, the second layer coupled to the first layer by hybrid bond interconnects having a first pad and a second pad, wherein the first pad is coupled to a first via in the second die and the first pad is offset from the first via by a first dimension, and the second pad is coupled to a second via in the third die and the second pad is offset from the second via by a second dimension different than the first dimension. in some embodiments, the first pad is offset from the first via in a first direction and the second pad is offset from the second via in a second direction different than the first direction.
20250006691. COMPLIANT INSERTS FOR PIN DIPPING PROCESSES_simplified_abstract_(intel corporation)
Inventor(s): George Robinson of Chandler AZ (US) for intel corporation, Mohamed Elhebeary of Chandler AZ (US) for intel corporation, Divya Jain of Mesa AZ (US) for intel corporation, Viet Chau of Vancouver WA (US) for intel corporation, Zewei Wang of Chandler AZ (US) for intel corporation, Mukund Ayalasomayajula of Chandler AZ (US) for intel corporation, Suraj Maganty of Chandler AZ (US) for intel corporation, Tingting Gao of Chandler AZ (US) for intel corporation, Andrew Wayne Carlson of Chandler AZ (US) for intel corporation, Khalid Mohammad Abdelaziz of Chandler AZ (US) for intel corporation, Craig Jerome Madison of Gilbert AZ (US) for intel corporation, Edvin Cetegen of Chandler AZ (US) for intel corporation, Joseph Petrini of Gilbert AZ (US) for intel corporation
IPC Code(s): H01L23/00
CPC Code(s): H01L24/81
Abstract: compliant inserts for pin dipping processes are disclosed herein. an example apparatus disclosed herein includes a pin array to transfer material to a package substrate of an integrated circuit package, a cover plate, an elastic insert to be disposed between the cover plate and the pin array.
Inventor(s): Bhaskar Jyoti Krishnatreya of Hillsboro OR (US) for intel corporation, Adel A. Elsherbini of Chandler AZ (US) for intel corporation, Brandon M. Rawlings of Chandler AZ (US) for intel corporation, Kimin Jun of Portland OR (US) for intel corporation, Omkar G. Karhade of Chandler AZ (US) for intel corporation, Mohit Bhatia of Chandler AZ (US) for intel corporation, Nitin A. Deshpande of Chandler AZ (US) for intel corporation, Prashant Majhi of San Jose CA (US) for intel corporation, Johanna M. Swan of Scottsdale AZ (US) for intel corporation
IPC Code(s): H01L25/065, H01L23/00, H01L23/31, H01L23/48
CPC Code(s): H01L25/0652
Abstract: microelectronic assemblies, related devices and methods, are disclosed herein. in some embodiments, a microelectronic assembly may include a first layer with a first die having a first contact; a second die having a second contact; and a pad layer, on the first and second dies, including a first pad and a second pad, where the first pad is coupled to and offset from the first contact in a first direction, and the second pad is coupled to and is offset from the second contact in a second direction different than the first direction; and a second layer including a third die having third and fourth contacts, where the first layer is coupled to the second layer by metal-to-metal bonds and fusion bonds, the first contact is coupled to the third contact by the first pad, and the second contact is coupled to the fourth contact by the second pad.
Inventor(s): Bharath Reddy GUDIGOPURAM of Nalgonda (IN) for intel corporation, Ajmeer Kaja AYUBKHAN of Bangalore (IN) for intel corporation, Siva Prasad JANGILI GANGA of Jagityal Dist (IN) for intel corporation
IPC Code(s): H01L25/10, H01L25/00, H01L25/16
CPC Code(s): H01L25/105
Abstract: disclosed herein is a device that provides for high power transfer. the device may include a printed circuit board and a package substrate disposed on the printed circuit board. the device may also include a plurality of high-power voltage regulators disposed on and electrically connected to the package substrate. the device may also include a plurality of low-power voltage regulators disposed on and electrically connected to the printed circuit board.
Inventor(s): Georgios Panagopoulos of Munich (DE) for intel corporation, Richard Geiger of Munich (DE) for intel corporation, Steven Callender of Denver CO (US) for intel corporation, Georgios Dogiamis of Chandler AZ (US) for intel corporation, Manisha Dutta of Munich (DE) for intel corporation, Stefano Pellerano of Beaverton OR (US) for intel corporation
IPC Code(s): H01L25/18, H01L23/00, H01Q1/22, H01Q23/00
CPC Code(s): H01L25/18
Abstract: example antenna module includes antenna units provided over an antenna unit support, and ics communicatively coupled to various antenna units. the ics are arranged in two or more subsets of one or more ics in each subset, where an individual ic belongs to only one subset, different subsets are in different layers with respect to the antenna unit support, and an average pitch of projections of all of the ics onto a plane parallel to the antenna unit support is substantially equal to, or smaller, than an average pitch of the antenna units. when an average width of the ics is larger than the average pitch of the antenna units, arranging the ics in two or more subsets in different layers means that at least one of the ics of one subset partially overlaps with at least one of the ics of another subset.
Inventor(s): Sukru Yemenicioglu of Portland OR (US) for intel corporation, Douglas Stout of Aurora CO (US) for intel corporation, Tai-Hsuan Wu of Portland OR (US) for intel corporation, Xinning Wang of Hillsboro OR (US) for intel corporation, Ruth Brain of Portland OR (US) for intel corporation, Chin-Hsuan Chen of Portland OR (US) for intel corporation, Sivakumar Venkataraman of Hillsboro OR (US) for intel corporation, Quan Shi of Portland OR (US) for intel corporation, Nikolay Ryzhenko Vladimirovich of Beaverton OR (US) for intel corporation
IPC Code(s): H01L27/02, G06F30/392, H01L29/06, H01L29/423, H01L29/775
CPC Code(s): H01L27/0207
Abstract: techniques are described for designing and forming cells comprising transistor devices for an integrated circuit. in an example, an integrated circuit structure includes a plurality of cells arranged in rows where some rows have different cell heights compared to other rows. additionally, the various rows of cells may contain semiconductor nanoribbons having different widths between different rows. for example, any number of first rows of cells can each have a first height and any number of second rows can each have a second height that is smaller than the first height. the first rows of cells may include transistors with semiconductor nanoribbons having a first width and the second rows of cells may include transistors with semiconductor nanoribbons having a second width smaller than the first width. in some cases, any of the first rows of cells may also include transistors with semiconductor nanoribbons having the second width.
Inventor(s): Krzysztof Domanski of Neubiberg (DE) for intel corporation, Harshit Dhakad of Bangalore (IN) for intel corporation
IPC Code(s): H01L27/02, H01L27/06
CPC Code(s): H01L27/0288
Abstract: an integrated circuit (ic) device comprises a conductive contact at a surface of the ic device. a resistive element is coupled between the conductive contact and first circuitry. second circuitry is coupled between the resistive element and the conductive contact. the second circuitry is further coupled with a supply line and comprises at least one of a diode or a power clamp. the resistive element is disposed in a first metallization layer of the ic device. a first dielectric layer is adjacent to the first metallization layer. a second metallization layer is adjacent to the first dielectric layer. a height of the first dielectric layer and the second metallization layer is a first distance. a zone overlaps the resistive element, and extends a second distance away from the resistive element. the zone is free of conductive material and the second distance is greater than the first distance.
Inventor(s): Swapnadip GHOSH of Hillsboro OR (US) for intel corporation, Chiao-Ti HUANG of Portland OR (US) for intel corporation, Amritesh RAI of Tigard OR (US) for intel corporation, Akitomo MATSUBAYASHI of Beaverton OR (US) for intel corporation, Fariha KHAN of Hillsboro OR (US) for intel corporation, Anupama BOWONDER of Portland OR (US) for intel corporation, Reken PATEL of Portland OR (US) for intel corporation, Chi-Hing CHOI of Portland OR (US) for intel corporation
IPC Code(s): H01L27/092, H01L21/8238
CPC Code(s): H01L27/092
Abstract: integrated circuit structures having differential epitaxial source or drain dent are described. for example, an integrated circuit structure includes a first sub-fin structure beneath a first stack of nanowires or fin. a second sub-fin structure is beneath a second stack of nanowires or fin. a first epitaxial source or drain structure is at an end of the first stack of nanowires of fin, the first epitaxial source or drain structure having no dent or a shallower dent therein. a second epitaxial source or drain structure is at an end of the second stack of nanowires or fin, the second epitaxial source or drain structure having a deeper dent therein.
Inventor(s): Tao Chu of Portland OR (US) for intel corporation, Minwoo Jang of Portland OR (US) for intel corporation, Yanbin Luo of Portland OR (US) for intel corporation, Paul Packan of Hillsboro OR (US) for intel corporation, Guowei Xu of Portland OR (US) for intel corporation, Chiao-Ti Huang of Portland OR (US) for intel corporation, Robin Chao of Portland OR (US) for intel corporation, Feng Zhang of Hillsboro OR (US) for intel corporation, Ting-Hsiang Hung of Beaverton OR (US) for intel corporation, Chia-Ching Lin of Portland OR (US) for intel corporation, Yang Zhang of Rio Rancho NM (US) for intel corporation, Chung-Hsun Lin of Portland OR (US) for intel corporation
IPC Code(s): H01L27/092, H01L29/06, H01L29/10, H01L29/423, H01L29/775, H01L29/78
CPC Code(s): H01L27/092
Abstract: an integrated circuit (ic) device includes a stripe of material perpendicular to, and spanning between, semiconductor structures with multiple widths, and the stripe is between transistors with channel regions of differing widths in the semiconductor structures. the material stripes cover transition portions between different widths of the semiconductor structures. the semiconductor structures may be channel structures of different types, including groups of fins or nanoribbons. channel regions of differing widths may include more or fewer fins or narrower or wider nanoribbons. the channel regions may have alternating conductivity types, n- and p-type.
Inventor(s): Aryan Navabi-Shirazi of Portland OR (US) for intel corporation, Michael Babb of Portland OR (US) for intel corporation, Kai Loon Cheong of Hillsboro OR (US) for intel corporation, Cheng-Ying Huang of Hillsboro OR (US) for intel corporation, Mohammad Hasan of Portland OR (US) for intel corporation, Leonard P. Guler of Hillsboro OR (US) for intel corporation, Marko Radosavljevic of Portland OR (US) for intel corporation
IPC Code(s): H01L27/092, H01L21/822, H01L21/8238, H01L29/06, H01L29/423, H01L29/66, H01L29/775, H01L29/786
CPC Code(s): H01L27/0922
Abstract: a material stack comprising a plurality of bi-layers, each bi-layer comprising two semiconductor material layers, is fabricated into a transistor structure including a first stack of channel materials that is coupled to an n-type source and drain and in a vertical stack with a second stack of channel materials that is coupled to a p-type source drain. within the first stack of channel material layers a first of two semiconductor material layers may be replaced with a first gate stack while within the second stack of channel materials a second of two semiconductor material layers may be replaced with a second gate stack.
Inventor(s): Nicole K. THOMAS of Portland OR (US) for intel corporation, Iulian HETEL of Brussels (BE) for intel corporation, Marko RADOSAVLJEVIC of Portland OR (US) for intel corporation
IPC Code(s): H01L27/092, H01L21/822, H01L21/8238, H01L29/06, H01L29/423, H01L29/66, H01L29/775
CPC Code(s): H01L27/0922
Abstract: embodiments described herein may be related to apparatuses, processes, systems, and/or techniques for integrating different materials into the channels for stacked transistor devices, for example in a cfet configuration, where the bottom device is an nmos device and the top device is a pmos device, or vice versa. other embodiments may be described and/or claimed.
Inventor(s): Leonard P. GULER of Hillsboro OR (US) for intel corporation, Vivek VISHWAKARMA of Hillsboro OR (US) for intel corporation, Jessica PANELLA of Banks OR (US) for intel corporation, Sean PURSEL of Hillsboro OR (US) for intel corporation, Dincer UNLUER of Hillsboro OR (US) for intel corporation, Shaun MILLS of Hillsboro OR (US) for intel corporation, Hongqian SUN of Sammamish WA (US) for intel corporation, Charles H. WALLACE of Portland OR (US) for intel corporation
IPC Code(s): H01L27/12, H01L21/84
CPC Code(s): H01L27/12
Abstract: integrated circuit structures having backside source or drain contact differentiated access are described. in an example, an integrated circuit structure includes first, second and third pluralities of horizontally stacked nanowires or fins, and first, second and third gate stacks. a first epitaxial source or drain structure is between the first plurality of horizontally stacked nanowires or fin and the second plurality of horizontally stacked nanowires or fin, the first epitaxial source or drain structure over a first conductive material having a first depth below the first epitaxial source or drain structure. a second epitaxial source or drain structure is between the second plurality of horizontally stacked nanowires or fin and the third plurality of horizontally stacked nanowires or fin, the second epitaxial source or drain structure over a second conductive material having a second depth below the second epitaxial source or drain structure, the second depth greater than the first depth.
Inventor(s): Thomas Sounart of Chandler AZ (US) for intel corporation, Henning Braunisch of Phoenix AZ (US) for intel corporation, Aleksandar Aleksov of Chandler AZ (US) for intel corporation, Kristof Darmawikarta of Chandler AZ (US) for intel corporation, Darko Grujicic of Chandler AZ (US) for intel corporation, Marcel Wall of Phoenix AZ (US) for intel corporation, Suddhasattwa Nad of Chandler AZ (US) for intel corporation, Benjamin Duong of Phoenix AZ (US) for intel corporation, Shayan Kaviani of Phoenix AZ (US) for intel corporation
IPC Code(s): H01G4/012, H01L21/48, H01L23/498
CPC Code(s): H01L28/91
Abstract: carbon nanofiber capacitor apparatus and related methods are disclosed herein. an example apparatus includes an integrated circuit package substrate, and a capacitor provided in the integrated circuit package substrate. the capacitor includes a carbon fiber array, a dielectric film positioned on the carbon fiber array, and an electrode film positioned on the dielectric film.
Inventor(s): Leonard P. GULER of Hillsboro OR (US) for intel corporation, Shao Ming KOH of Tigard OR (US) for intel corporation, Sean PURSEL of Hillsboro OR (US) for intel corporation, Charles H. WALLACE of Portland OR (US) for intel corporation, Hongqian SUN of Sammamish WA (US) for intel corporation
IPC Code(s): H01L29/06, H01L27/092, H01L29/423, H01L29/775, H01L29/78, H01L29/786
CPC Code(s): H01L29/0673
Abstract: an integrated circuit structure includes a first vertical stack of horizontal nanowires or a first fin having a first lateral width. a first gate electrode is over the first vertical stack of horizontal nanowires or the first fin, the first gate electrode having a second lateral width. a second vertical stack of horizontal nanowires or a second fin is laterally spaced apart from the first vertical stack of horizontal nanowires or the second fin, the second vertical stack of horizontal nanowires or the second fin having a third lateral width, the third lateral width less than the first lateral width. a second gate electrode is over the second vertical stack of horizontal nanowires or the second fin, the second gate electrode laterally spaced apart from the first gate electrode, and the second gate electrode having a fourth lateral width, the fourth lateral width less than the second lateral width.
Inventor(s): Anand Murthy of Portland OR (US) for intel corporation, Shishir Pandya of Hillsboro OR (US) for intel corporation, James Kally of Hillsboro OR (US) for intel corporation, Robert Ehlert of Portland OR (US) for intel corporation, Tahir Ghani of Portland OR (US) for intel corporation
IPC Code(s): H01L29/08, H01L21/02, H01L29/167, H01L29/45
CPC Code(s): H01L29/0847
Abstract: in some implementations, a device may include a channel material. in addition, the device may include a contact metal. the device may include a first layer between the channel material and the contact metal, the first layer having antimony and silicon. moreover, the device may include a second layer between the contact metal and the first layer, the second layer having phosphorus and silicon.
Inventor(s): Rachel A. Steinhardt of Beaverton OR (US) for intel corporation, Kevin P. O'Brien of Portland OR (US) for intel corporation, Dominique A. Adams of Portland OR (US) for intel corporation, Gauri Auluck of Hillsboro OR (US) for intel corporation, Pratyush P. Buragohain of Hillsboro OR (US) for intel corporation, Scott B. Clendenning of Portland OR (US) for intel corporation, Punyashloka Debashis of Hillsboro OR (US) for intel corporation, Arnab Sen Gupta of Hillsboro OR (US) for intel corporation, Brandon Holybee of Portland OR (US) for intel corporation, Raseong Kim of Portland OR (US) for intel corporation, Matthew V. Metz of Portland OR (US) for intel corporation, John J. Plombon of Portland OR (US) for intel corporation, Marko Radosavljevic of Portland OR (US) for intel corporation, Carly Rogan of North Plains OR (US) for intel corporation, Tristan A. Tronic of Aloha OR (US) for intel corporation, I-Cheng Tung of Hillsboro OR (US) for intel corporation, Ian Alexander Young of Olympia WA (US) for intel corporation, Dmitri Evgenievich Nikonov of Beaverton OR (US) for intel corporation
IPC Code(s): H01L29/08, H01L29/06, H01L29/12, H01L29/423, H01L29/51, H01L29/66, H01L29/775, H01L29/78, H01L29/786
CPC Code(s): H01L29/0847
Abstract: perovskite oxide field effect transistors comprise perovskite oxide materials for the channel, source, drain, and gate oxide regions. the source and drain regions are doped with a higher concentration of n-type or p-type dopants (depending on whether the transistor is an n-type or p-type transistor) than the dopant concentration in the channel region to minimize schottky barrier height between the source and drain regions and the source and drain metal contact and contact resistance.
Inventor(s): Anand Murthy of Portland OR (US) for intel corporation, Alexander Badmaev of Portland OR (US) for intel corporation, Zhiyi Chen of Portland OR (US) for intel corporation, Debaleena Nandi of Hillsboro OR (US) for intel corporation, Tahir Ghani of Portland OR (US) for intel corporation
IPC Code(s): H01L29/417, H01L27/092, H01L29/06, H01L29/423, H01L29/66, H01L29/775, H01L29/78, H01L29/786
CPC Code(s): H01L29/41733
Abstract: in some implementations, an apparatus may include a substrate having silicon. in addition, the apparatus may include a first layer of a source or drain region of a p-type transistor, the first layer positioned above the substrate, the first layer having boron, silicon and germanium. the apparatus may include a second layer coupled to the source or drain region, the second layer having a metal contact for the source or drain region. moreover, the apparatus may include a third layer positioned between the first layer and the second layer, the third layer having at least one monolayer having gallium, where the third layer is adjacent to the first layer.
Inventor(s): Leonard P. GULER of Hillsboro OR (US) for intel corporation, Mohammad HASAN of Aloha OR (US) for intel corporation, Charles H. WALLACE of Portland OR (US) for intel corporation
IPC Code(s): H01L29/417, H01L27/088, H01L29/06, H01L29/423, H01L29/775
CPC Code(s): H01L29/41775
Abstract: integrated circuit structures having internal spacer liners, and methods of fabricating integrated circuit structures having internal spacer liners, are described. for example, an integrated circuit structure includes a stack of horizontal nanowires. a gate structure is vertically around the stack of horizontal nanowires, the stack of horizontal nanowires extending laterally beyond the gate structure. an internal gate spacer is between vertically adjacent ones of the stack of horizontal nanowires and laterally adjacent to the gate structure. an internal spacer liner is intervening between the internal gate spacer and the vertically adjacent ones of the stack of horizontal nanowires, and the internal spacer liner is intervening between the internal gate spacer and the gate structure.
20250006810. TRANSISTOR WITH CHANNEL-SYMMETRIC GATE_simplified_abstract_(intel corporation)
Inventor(s): Shao-Ming Koh of Tigard OR (US) for intel corporation, Manish Chandhok of Beaverton OR (US) for intel corporation, Marvin Paik of Portland OR (US) for intel corporation, Shahidul Haque of Portland OR (US) for intel corporation, Jason Klaus of Portland OR (US) for intel corporation, Asad Iqbal of Beaverton OR (US) for intel corporation, Patrick Morrow of Portland OR (US) for intel corporation, Nikhil Mehta of Portland OR (US) for intel corporation, Alison Davis of Portland OR (US) for intel corporation, Sean Pursel of Tigard OR (US) for intel corporation, Steven Shen of Hillsboro OR (US) for intel corporation, Christopher Rochester of Hillsboro OR (US) for intel corporation, Matthew Prince of Portland OR (US) for intel corporation
IPC Code(s): H01L29/423, H01L21/28, H01L21/3213, H01L29/06, H01L29/66, H01L29/775
CPC Code(s): H01L29/42392
Abstract: transistor structures with gate material self-aligned to underlying channel material. a channel mask material employed for patterning channel material is retained during selective formation of a second mask material upon exposed surfaces of gate material. the channel mask material is then thinned to expose a sidewall of adjacent gate material. the exposed gate material sidewall is laterally recessed to expand an opening beyond an edge of underlying channel material. a third mask material may be formed in the expanded opening to protect an underlying portion of gate material during a gate etch that forms a trench bifurcating the underlying portion of gate material from an adjacent portion of gate material. the underlying portion of gate material extends laterally beyond the channel material by an amount that is substantially symmetrical about a centerline of the channel material and this amount has a height well controlled relative to the channel material.
Inventor(s): Sudipto Naskar of Portland OR (US) for intel corporation, Sukru Yemenicioglu of Portland OR (US) for intel corporation, Abhishek Anil Sharma of Portland OR (US) for intel corporation, Van Le of Beaverton OR (US) for intel corporation, Weimin Han of Portland OR (US) for intel corporation
IPC Code(s): H01L29/423, H01L21/8238, H01L27/092, H01L29/06, H01L29/08, H01L29/66, H01L29/775, H01L29/78, H01L29/786
CPC Code(s): H01L29/42392
Abstract: n-type gate-all-around (nanosheet, nanoribbon, nanowire) field-effect transistors (gaafets) vertically stacked on top of p-type gaafets in complementary fet (cfet) devices comprise non-crystalline silicon layers that form the n-type transistor source, drain, and channel regions. the non-crystalline silicon layers can be formed via deposition, which can provide for a simplified processing flow to form the middle dielectric layer between the n-type and p-type gaafets relative to processing flows where the silicon layers forming the n-type transistor source, drain, and channel regions are grown epitaxially.
Inventor(s): Richard GEIGER of Munich (DE) for intel corporation, Peter BAUMGARTNER of Munich (DE) for intel corporation
IPC Code(s): H01L29/78, H01L23/528, H01L27/088, H01L29/423
CPC Code(s): H01L29/7827
Abstract: structures having vertical-transport field effect transistors (fets) with bottom source connection are described. in an example, an integrated circuit structure includes a channel structure above a substrate. a gate structure is laterally surrounding the channel structure. a drain structure is above the gate structure and on the channel structure. a metal source structure is below the substrate and vertically beneath the channel structure. a conductive via is through the substrate, the conductive via coupling the metal source structure to the channel structure.
Inventor(s): Kevin P. O'Brien of Portland OR (US) for intel corporation, Dmitri Evgenievich Nikonov of Beaverton OR (US) for intel corporation, Rachel A. Steinhardt of Beaverton OR (US) for intel corporation, Pratyush P. Buragohain of Hillsboro OR (US) for intel corporation, John J. Plombon of Portland OR (US) for intel corporation, Hai Li of Portland OR (US) for intel corporation, Gauri Auluck of Hillsboro OR (US) for intel corporation, I-Cheng Tung of Hillsboro OR (US) for intel corporation, Tristan A. Tronic of Aloha OR (US) for intel corporation, Dominique A. Adams of Portland OR (US) for intel corporation, Punyashloka Debashis of Hillsboro OR (US) for intel corporation, Raseong Kim of Portland OR (US) for intel corporation, Carly Rogan of North Plains OR (US) for intel corporation, Arnab Sen Gupta of Hillsboro OR (US) for intel corporation, Brandon Holybee of Portland OR (US) for intel corporation, Marko Radosavljevic of Portland OR (US) for intel corporation, Uygar E. Avci of Portland OR (US) for intel corporation, Ian Alexander Young of Olympia WA (US) for intel corporation, Matthew V. Metz of Portland OR (US) for intel corporation
IPC Code(s): H01L29/78, H01L29/24, H01L29/49, H01L29/66
CPC Code(s): H01L29/78391
Abstract: a transistor device may include a first perovskite gate material, a first perovskite ferroelectric material on the first gate material, a first p-type perovskite semiconductor material on the first ferroelectric material, a second perovskite ferroelectric material on the first semiconductor material, a second perovskite gate material on the second ferroelectric material, a third perovskite ferroelectric material on the second gate material, a second p-type perovskite semiconductor material on the third ferroelectric material, a fourth perovskite ferroelectric material on the second semiconductor material, a third perovskite gate material on the fourth ferroelectric material, a first source/drain metal adjacent a first side of each of the first semiconductor material and the second semiconductor material, a second source/drain metal adjacent a second side opposite the first side of each of the first semiconductor material and the second semiconductor material, and dielectric materials between the source/drain metals and the gate materials.
Inventor(s): Rachel A. Steinhardt of Beaverton OR (US) for intel corporation, Kevin P. O'Brien of Portland OR (US) for intel corporation, Dmitri Evgenievich Nikonov of Beaverton OR (US) for intel corporation, John J. Plombon of Portland OR (US) for intel corporation, Tristan A. Tronic of Aloha OR (US) for intel corporation, Ian Alexander Young of Olympia WA (US) for intel corporation, Matthew V. Metz of Portland OR (US) for intel corporation, Marko Radosavljevic of Portland OR (US) for intel corporation, Carly Rogan of North Plains OR (US) for intel corporation, Brandon Holybee of Portland OR (US) for intel corporation, Raseong Kim of Portland OR (US) for intel corporation, Punyashloka Debashis of Hillsboro OR (US) for intel corporation, Dominique A. Adams of Portland OR (US) for intel corporation, I-Cheng Tung of Hillsboro OR (US) for intel corporation, Arnab Sen Gupta of Hillsboro OR (US) for intel corporation, Gauri Auluck of Hillsboro OR (US) for intel corporation, Scott B. Clendenning of Portland OR (US) for intel corporation, Pratyush P. Buragohain of Hillsboro OR (US) for intel corporation, Hai Li of Portland OR (US) for intel corporation
IPC Code(s): H01L29/78, H01L29/76, H01L29/786
CPC Code(s): H01L29/78391
Abstract: in one embodiment, a negative capacitance transistor device includes a perovskite semiconductor material layer with first and second perovskite conductors on opposite ends of the perovskite semiconductor material layer. the device further includes a dielectric material layer on the perovskite semiconductor material layer between the first and second perovskite conductors, a perovskite ferroelectric material layer on the dielectric material layer, and a third perovskite conductor on the perovskite ferroelectric material layer.
Inventor(s): Arnab Sen Gupta of Hillsboro OR (US) for intel corporation, Dmitri Evgenievich Nikonov of Beaverton OR (US) for intel corporation, John J. Plombon of Portland OR (US) for intel corporation, Rachel A. Steinhardt of Beaverton OR (US) for intel corporation, Punyashloka Debashis of Hillsboro OR (US) for intel corporation, Kevin P. O'Brien of Portland OR (US) for intel corporation, Matthew V. Metz of Portland OR (US) for intel corporation, Scott B. Clendenning of Portland OR (US) for intel corporation, Brandon Holybee of Portland OR (US) for intel corporation, Marko Radosavljevic of Portland OR (US) for intel corporation, Ian Alexander Young of Olympia WA (US) for intel corporation, I-Cheng Tung of Hillsboro OR (US) for intel corporation, Sudarat Lee of Hillsboro OR (US) for intel corporation, Raseong Kim of Portland OR (US) for intel corporation, Pratyush P. Buragohain of Hillsboro OR (US) for intel corporation
IPC Code(s): H01L29/78, H01L29/06, H01L29/221, H01L29/423, H01L29/775, H01L29/786
CPC Code(s): H01L29/78391
Abstract: technologies for a field effect transistor (fet) with a ferroelectric gate dielectric are disclosed. in an illustrative embodiment, a transistor includes a gate of strontium ruthenate and a ferroelectric gate dielectric layer of barium titanate. in order to prevent migration of ruthenium from the strontium ruthenate to the barium titanate, a barrier layer is placed between the gate and the ferroelectric gate dielectric layer. the barrier layer may be a metal oxide, such as strontium oxide, barium oxide, zirconium oxide, etc.
Inventor(s): Naoki Matsumura of San Jose CA (US) for intel corporation
IPC Code(s): H01M10/44, G01R31/36, G01R31/367, G01R31/3835, H01M10/42, H02J7/00
CPC Code(s): H01M10/448
Abstract: methods and apparatus relating to an adaptive battery usage window to extend battery longevity are described. in an embodiment, a state of charge (soc) for a rechargeable battery is controlled based on a plurality of limited charging modes that may selectively allow/prevent charging/discharging of the rechargeable battery to target level(s). other embodiments are also disclosed and claimed.
Inventor(s): Peter BAUMGARTNER of Munich (DE) for intel corporation, Richard GEIGER of Munich (DE) for intel corporation, Georgios C. DOGIAMIS of Chandler AZ (US) for intel corporation, Steven CALLENDER of Denver CO (US) for intel corporation, Telesphor KAMGAING of Chandler AZ (US) for intel corporation, Jonathan C. JENSEN of Greenville SC (US) for intel corporation, Harald GOSSNER of Riemerling (DE) for intel corporation
IPC Code(s): H01Q1/22, H01L25/10, H01Q21/24
CPC Code(s): H01Q1/2283
Abstract: embodiments disclosed herein include communication dies for mm-wave and/or sub-terahertz wavelength communications. in an embodiment, a communications die comprises a substrate with a first face and a second face. in an embodiment, edge surfaces connect the first face to the second face. in an embodiment, a circuitry element is on the first face, and an antenna on at least one of the edge surfaces.
Inventor(s): Krzysztof Domanski of Neubiberg (DE) for intel corporation, Robert Haeussler of Augsburg (DE) for intel corporation, Harshit Dhakad of Bangalore (IN) for intel corporation
IPC Code(s): H02H9/02
CPC Code(s): H02H9/026
Abstract: an integrated circuit (ic) device comprises a conductive contact at a surface of the ic device. first and second circuitry are coupled with the conductive contact. first and second supply lines are coupled with and provide power to the first circuitry, the first supply line providing a first voltage, and the second supply line providing a second voltage. the second circuitry is further coupled with the second supply line and a third supply line. the third supply line is to provide a third voltage and may provide a path for a current associated with an electrostatic discharge (esd) event. a resistive element is coupled between the first supply line and the third supply line. the resistive element may reduce a current in the first supply line associated with an esd event.
Inventor(s): Susanne Heber of Munich (DE) for intel corporation, Daniel Gruber of St. Andrae (AT) for intel corporation, Krzysztof Domanski of Neubiberg (DE) for intel corporation, Martin Clara of Santa Clara CA (US) for intel corporation
IPC Code(s): H02H9/04
CPC Code(s): H02H9/046
Abstract: an integrated circuit device includes a signal pad, an inductor coupled in series with the signal pad, and an electrostatic discharge (esd) protection circuit distributed before and after the inductor to provide esd protection for an esd event on the signal pad. other examples are disclosed and claimed.
20250007316. FAST BATTERY CHARGING_simplified_abstract_(intel corporation)
Inventor(s): Jagadish SINGH of Bangalore (IN) for intel corporation, Naoki MATSUMURA of San Jose CA (US) for intel corporation, Ravikumar S of Bangalore (IN) for intel corporation, Harshitha NANJUNDAPPA of San Jose CA (US) for intel corporation, David WOODS of El Dorado Hills CA (US) for intel corporation
IPC Code(s): H02J7/00
CPC Code(s): H02J7/007194
Abstract: some examples provide battery charging techniques that allow for reasonably fast charging while reducing charging temperature. in some examples, a target temperature limit is actively maintained through a control loop. in some examples, cc charge phases are interleaved with cv stages.
Inventor(s): Keng Chen of Acton MA (US) for intel corporation, Arvind Raghavan of Lexington MA (US) for intel corporation, Rachid Rayess of Hudson MA (US) for intel corporation, Tamir Salus of Zichron Yaakov (IL) for intel corporation, Christopher Schaef of Hillsboro OR (US) for intel corporation, Huanhuan Zhang of Ashland MA (US) for intel corporation, Sivaraman Masilamani of Northborough MA (US) for intel corporation, Gayathri Devi Sridharan of Northborough MA (US) for intel corporation, Subhrashankha Ghosh of Beaverton OR (US) for intel corporation
IPC Code(s): H02M3/07, G05F1/575, H02M1/00
CPC Code(s): H02M3/07
Abstract: a switched capacitor voltage regulator (scvr) design, such as a continuous capacitive voltage regulator (c2vr) design, may use capacitors and switches to provide improved cost and space efficiencies. a remote sensing circuit may be used to improve c2vr performance. by adding a remote sensing circuit to the regulation feedback loop within the c2vr circuit design, the c2vr circuit may provide improved accuracy in voltage regulation, such as by providing a correction based on the voltage error between the remote-sensed voltage and the reference target. the remote sensing circuit may also provide transient information for under-voltage detection at an output terminal. this detected transient may become an alternating current (ac) portion of the under-voltage detection threshold, which improves the ability of the c2vr circuit to provide early detection for any under-voltage fault.
Inventor(s): Eduardo Alban of Hillsboro OR (US) for intel corporation, Hao Luo of Milpitas CA (US) for intel corporation, Nasser A. Kurd of Portland OR (US) for intel corporation, Kedar Mangrulkar of Folsom CA (US) for intel corporation, Mohamed A. Abdelmoneum of Portland OR (US) for intel corporation, Brent R. Carlton of Portland OR (US) for intel corporation
IPC Code(s): H03K5/1252, G06F1/06, H03B5/36
CPC Code(s): H03K5/1252
Abstract: an apparatus includes an oscillator circuit and a low-pass filter circuit coupled to an output terminal of the oscillator circuit. the apparatus further includes a first digital signal generator coupled to at least one of an output terminal of the low-pass filter circuit and the output terminal of the oscillator circuit and a second digital signal generator coupled to at least one of the output terminal of the low-pass filter circuit and the output terminal of the oscillator circuit. the second digital signal generator generates a second digital clock signal based on a non-differential signal output of the oscillator circuit. the apparatus further includes a radio frequency interference (rfi) detection circuit coupled to the first digital signal generator and the second digital signal generator. the rfi detection circuit detects rfi associated with the non-differential signal output of the oscillator circuit.
Inventor(s): Ofir DEGANI of Haifa (IL) for intel corporation, Assaf BEN-BASSAT of Haifa (IL) for intel corporation
IPC Code(s): H03M1/46, H03M1/80
CPC Code(s): H03M1/468
Abstract: disclosed herein are devices, methods, and systems that relate to wireless communications architectures and, in particular, multi-band radio-frequency circuitry. disclosed herein is a capacitive digital-to-analog converter (cdac). the cdac may include a plurality of circuits configured to receive a digital signal to be converted into an analog signal, wherein each circuit of the plurality of circuits may include: a variable capacitive element; and a driver configured to cause the variable capacitive element to be charged or discharged to convert the received digital signal into the analog signal.
Inventor(s): Yang-Seok Choi of Portland OR (US) for intel corporation, Sagar Dhakal of Los Altos CA (US) for intel corporation, Husam Elfadil of Cedar Park TX (US) for intel corporation, Thushara Hewavithana of Tempe AZ (US) for intel corporation, Xiaofeng Li of Elk Grove CA (US) for intel corporation, Peng Lu of Elk Grove CA (US) for intel corporation, Tariq Qureshi of Hillsboro OR (US) for intel corporation, Jan Schreck of San Jose CA (US) for intel corporation
IPC Code(s): H04B7/08, H04B7/0426, H04B7/06
CPC Code(s): H04B7/0854
Abstract: techniques are disclosed to address issues related to the computation of channel state information (csi) and angular spectrum (as) to perform beamforming. the csi and as, as well as various statistical channel parameters of a wireless channel, may be computed using different techniques, which include the use of domain knowledge enhanced neural networks (dke-nns). the csi and as may be further utilized to perform beamforming using various techniques. one of these techniques may include the implementation of eigen beamforming, which provides artificially generated power at locations within the as that are identified with estimated eigenvector beam locations. as a result of the artificially-generated power, the resulting vector decomposition used to provide the beamforming weights results in widened eigenvector beams.
20250007687. FULLY HOMOMORPHIC ENCRYPTION_simplified_abstract_(intel corporation)
Inventor(s): Sanu MATHEW of Portland OR (US) for intel corporation, Vikram SURESH of Portland OR (US) for intel corporation, Sachin TANEJA of Hillsboro OR (US) for intel corporation, Raghavan KUMAR of Hillsboro OR (US) for intel corporation, Christopher WILKERSON of Portland OR (US) for intel corporation
IPC Code(s): H04L9/00
CPC Code(s): H04L9/008
Abstract: techniques for fully homomorphic encryption are described. in some examples, a register file to store polynomials is coupled to a butterfly compute path. the butterfly compute path includes a multiplier coupled to a first input and a second input to multiply the first and second input to, when enabled, generate a multiplication output, a first multiplexer coupled to an output of the multiplier and to the first input to output a selection between the output of the multiplier and the first input, an adder to add, when enabled, a third input to the selected output of the first multiplexer, a subtractor to subtract, when enabled, an output of the multiplier from the third input, and a second multiplexer coupled to an output of the multiplier and to the first input to, when enabled, output a selection between the output of the multiplier and the subtractor.
Inventor(s): Raghavan KUMAR of Hillsboro OR (US) for intel corporation, Sanu K. MATHEW of Portland OR (US) for intel corporation, Sachin TANEJA of Hillsboro OR (US) for intel corporation, Christopher B. WILKERSON of Portland OR (US) for intel corporation, Minxuan ZHOU of San Diego CA (US) for intel corporation
IPC Code(s): H04L9/00, G06F17/14, H04L9/30
CPC Code(s): H04L9/008
Abstract: a reconfigurable compute circuitry to perform fully homomorphic encryption (fhe) enables a full utilization of compute resources and data movement resources by mapping multiple n*1024 polynomials on to a (m*n)*1024 polynomial. to counteract the shuffling of the coefficients during number-theoretic-transforms (ntt) and inverse-ntt operations, compute elements in the compute circuitry operate in a bypass mode that is enabled by a data movement instruction, to convert from the shuffled form to contiguous form without modifying the values of the coefficients.
Inventor(s): Santosh GHOSH of Hillsboro OR (US) for intel corporation, Qian WANG of Portland OR (US) for intel corporation, Manoj R. SASTRY of Portland OR (US) for intel corporation
IPC Code(s): H04L9/06, H04L9/08, H04L9/30
CPC Code(s): H04L9/0643
Abstract: kyber is a secure key encapsulation mechanism (kem) for secure key exchange. performance overhead associated with use of kyber for secure key exchange is reduced by computing multiple coefficients of different polynomials for independent operations in parallel and localizing them in memory for fast access for polynomial multiplications used in key generation, encapsulation, and decapsulation allowing for parallelization of keccak calls.
Inventor(s): Pascal Nasahl of Graz (AT) for intel corporation, Salmin Sultana of Hillsboro OR (US) for intel corporation, Hans Goran Liljestrand of Helsinki (FI) for intel corporation, Karanvir Grewal of Hillsboro OR (US) for intel corporation, Michael LeMay of Hillsboro OR (US) for intel corporation, David M. Durham of Beaverton OR (US) for intel corporation
IPC Code(s): H04L9/08
CPC Code(s): H04L9/088
Abstract: techniques for cryptographically enforcing control-flow integrity are described. in certain examples, a processor includes: a cryptographic circuit to encrypt, with a first key, a first code section to be stored in a single page of memory, and to encrypt, with a second key, a second code section to be stored in the single page of memory; decoder circuitry to decode a single instruction into a decoded single instruction, the single instruction comprising a key identifier, an identifier of the second code section, and an opcode that is to indicate execution circuitry is to, when executing the first code section, determine if the key identifier corresponds to the second key, and in response to corresponding, cause the cryptographic circuit to switch to using the second key to decrypt the second code section, and transfer execution from the first code section to the second code section; and the execution circuitry to execute the decoded instruction according to the opcode.
Inventor(s): Santosh Ghosh of Hillsboro OR (US) for intel corporation, Qian Wang of Portland OR (US) for intel corporation, Manoj Sastry of Portland OR (US) for intel corporation
IPC Code(s): H04L9/32, H04L9/08
CPC Code(s): H04L9/3247
Abstract: techniques for implementing a hardware engine for stateless hash-based signatures according to a sphincs+standard with encryption according to a sha256 encryption standard are described. in certain examples, a system includes a processor core; and an accelerator coupled to the processor core, the accelerator comprising: one or more hash engine circuits, a coupling to allow for communication between the one or more hash engine circuits and a memory, and hash control circuitry to, for a request to perform a stateless hash-based signature operation on an input, cause performance of a one-time signature scheme function and a forest of random subsets function by the one or more hash engine circuits to generate a resultant.
Inventor(s): Christopher Gutierrez of HILLSBORO OR (US) for intel corporation, Marcio Juliato of Portland OR (US) for intel corporation, Manoj Sastry of Portland OR (US) for intel corporation, Vuk Lesi of Cornelius OR (US) for intel corporation, Shabbir Ahmed of HILLSBORO OR (US) for intel corporation
IPC Code(s): H04L9/40, H04L9/32
CPC Code(s): H04L9/40
Abstract: techniques include a method, apparatus, system and computer-readable medium to detect, quantify and localize attacks to enhance security for time-synchronized networking. embodiments include a diagnostic stream producer to produce diagnostic information providing evidence of a timing attack on a node of a time-synchronized network. embodiments include a diagnostic stream consumer to consume diagnostic information, analyze the diagnostic information, and determine whether a node is under a timing attack. other embodiments are described and claimed.
Inventor(s): Susnata Mondal of Hillsboro OR (US) for intel corporation, Mozhgan Mansuri of Portland OR (US) for intel corporation
IPC Code(s): H04L25/03, H03F1/32, H03F3/45
CPC Code(s): H04L25/03878
Abstract: methods and apparatus are disclosed for complex-zero equalizers. an example circuit comprises driver circuitry including a first input, and equalizer circuitry including a second input, a first output coupled to the first input, a transistor including a gate terminal, a drain terminal, and a source terminal, the gate terminal coupled to the second input and the drain terminal coupled to the first output, an inductor including a first inductor terminal and a second inductor terminal, the first inductor terminal coupled to the source terminal of the transistor, a resistor coupled to the second inductor terminal, and a capacitor including a first terminal and a second terminal coupled to the source terminal and to the first inductor terminal and the second terminal coupled to ground.
Inventor(s): Marcio Juliato of Portland OR (US) for intel corporation, Javier Perez-Ramirez of North Plains OR (US) for intel corporation, Mikhail Galeev of Beaverton OR (US) for intel corporation, Manoj Sastry of Portland OR (US) for intel corporation, Dave Cavalcanti of Portland OR (US) for intel corporation, Christopher Gutierrez of Hillsboro OR (US) for intel corporation, Shabbir Ahmed of Hillsboro OR (US) for intel corporation, Vuk Lesi of Cornelius OR (US) for intel corporation
IPC Code(s): H04L43/0817, H04L9/40, H04L43/067
CPC Code(s): H04L43/0817
Abstract: techniques include a method, apparatus, system and computer-readable medium to detect, quantify and localize attacks to enhance security for time-synchronized networking. embodiments include a diagnostic stream producer to produce diagnostic information providing evidence of a timing attack on a node of a time-synchronized network. embodiments include a diagnostic stream consumer to consume diagnostic information, analyze the diagnostic information, and determine whether a node is under a timing attack. other embodiments are described and claimed.
Inventor(s): Evrim Binboga of Pleasanton CA (US) for intel corporation, Stanley J. Baran of Chandler AZ (US) for intel corporation, Anh Viet Nguyen of Beaverton OR (US) for intel corporation, Aline C. Kenfack Sadate of Hillsboro OR (US) for intel corporation
IPC Code(s): H04N7/15, H04N7/14
CPC Code(s): H04N7/152
Abstract: systems and methods for receive-side customization of presentation of mixed media data. systems and methods focus on the receive path so that each participant in a video conference or other mixed media application can, as a receiver of mixed media data signals, customize the individual incoming mixed media data signals for display on the receiver's user device. user customization options include blocking video or avatars, converting (to avatars), and filtering distracting behavior. embodiments enable all participating users (not just a host user) to respectively receive-side customize the presentation/display of the mixed media data. additionally, systems and methods can be implemented in an existing server.
Inventor(s): Navneet Kumar Singh of Bangalore (IN) for intel corporation, Shailendra Singh Chauhan of Bengaluru (IN) for intel corporation, Usha of Bengaluru (IN) for intel corporation
IPC Code(s): H04R29/00, H04R1/10, H04R1/22
CPC Code(s): H04R29/001
Abstract: example systems, apparatus, articles of manufacture, and methods to improve audio quality based on load impedance sensing are disclosed. an example apparatus disclosed herein is to cause at least one test signal to be output to an audio device, a voltage of the at least one test signal based on a default load impedance. the example apparatus disclosed herein is to execute the instructions to measure a current drawn by the audio device based on the at least one test signal. the example apparatus disclosed herein is to execute the instructions to change the voltage based on an impedance profile, the impedance profile based on the measured current.
Inventor(s): Hector Cordourier Maruri of Guadalajara (MX) for intel corporation, Jesus Rodrigo Ferrer Romero of Zapopan (MX) for intel corporation, Diego Mauricio Cortes Hernandez of Hillsboro OR (US) for intel corporation, Rosa Jacqueline Sanchez Mesa of Zapopan (MX) for intel corporation, Sandra Coello Chavarin of Zapopan (MX) for intel corporation, Margarita Jauregui Franco of Zapopan (MX) for intel corporation, Willem Beltman of West Linn OR (US) for intel corporation, Valeria Cortez Gutierrez of San Luis Potosi (MX) for intel corporation
IPC Code(s): H04S7/00, G06N3/0464
CPC Code(s): H04S7/40
Abstract: a system, article, device, apparatus, and method of audio processing comprises receiving, by processor circuitry, binaural audio signals at least overlapping at a same time and of a same two or more audio sources. the method also comprises generating localization map data indicating locations of the two or more audio sources relative to microphones providing the binaural audio signals and comprising inputting at least one version of the binaural audio signals into at least one neural network (nn).
Inventor(s): Vaibhav SINGH of New Delhi (IN) for intel corporation, Christian MACIOCCO of Portland OR (US) for intel corporation
IPC Code(s): H04W24/02, G06N20/00, H04W72/04
CPC Code(s): H04W24/02
Abstract: a device may include a memory configured to store an artificial intelligence or machine learning model (ai/ml) configured to provide an output used in radio resource management of a plurality of cells; and a processor configured to: obtain cell-specific parameters of the plurality of cells of a mobile communication network; select a subset of the plurality of cells based on obtained cell-specific parameters; and cause the ai/ml to be trained with radio access network (ran)-related data of the subset of the plurality of cells.
Inventor(s): Ido OUZIELI of Tel Aviv (IL) for intel corporation, Laurent CARIOU of Milizac (FR) for intel corporation, Emily H. QI of Gig Harbor WA (US) for intel corporation
IPC Code(s): H04W36/06, H04W36/00, H04W72/0453
CPC Code(s): H04W36/06
Abstract: this disclosure describes systems, methods, and devices related to enhanced channel performance. a device may evaluate a planned channel-switch operation without specifying a switching time. the device may determine whether to start beaconing on a new channel immediately following a switch. the device may transmit a channel switch announcement element or an extended channel switch announcement element without additional information on an expected time to start beaconing. the device may include a min absence following channel switch time element in a beacon or action-frame.
20250008661. DEFLECTION SPRING COMPRESSION MOUNTING_simplified_abstract_(intel corporation)
Inventor(s): Arturo Navarro Alvarez of Grecia (CR) for intel corporation, Jeff Ku of Taipei (TW) for intel corporation, Luis Carlos Sanchez Herrera of Alajuela (CR) for intel corporation, Min Suet Lim of Gelugor (MY) for intel corporation, Pin Wang of Portland OR (US) for intel corporation, Tongyan Zhai of Portland OR (US) for intel corporation, Raghavendra Ramesh Rao of Bengaluru (IN) for intel corporation
IPC Code(s): H05K1/18
CPC Code(s): H05K1/181
Abstract: deflection spring compression mounting is disclosed. a disclosed example deflection spring for an electronics package includes first and second end portions having first and second locking interfaces, respectively, to at least partially constrain the first and second end portions relative to a support, a curved portion, and a medial portion having a third locking interface to fix the medial portion relative to the support, wherein fixing the medial portion relative to the support causes the curved portion to contact and press against the electronics package.
Inventor(s): Jeff Ku of Taipei (TW) for intel corporation, Min Suet Lim of Gelugor (MY) for intel corporation, Lance Lin of Taipei City (TW) for intel corporation, Arnab Sen of Bangalore (IN) for intel corporation, Jiacheng Wu of Taipei (TW) for intel corporation
IPC Code(s): H05K7/20, G06F1/20
CPC Code(s): H05K7/20145
Abstract: thermal management systems for electronic devices and related methods are disclosed. an example electronic device includes a chassis including a first cover and a second cover, the first cover including an upper surface and a plurality of side walls and the second cover including a lower surface of the chassis, the first cover and the second cover defining an internal cavity of the chassis, the first cover including a first device inlet formed in a first side wall of the first cover; a fan positioned in the internal cavity, the fan including a first fan inlet and a second fan inlet opposite the first fan inlet; and a side channel positioned between the first device inlet and the first fan inlet to direct fluid flow between the first device inlet and the first fan inlet.
20250008685. FAN MODULES FOR ELECTRONIC DEVICES_simplified_abstract_(intel corporation)
Inventor(s): Jeff Ku of Taipei (TW) for intel corporation, Nirmala Bailur of Bangalore (IN) for intel corporation, Min Suet Lim of Gelugor (MY) for intel corporation, Tongyan Zhai of Portland OR (US) for intel corporation, Chee Chun Yee of Bayan Lepas (MY) for intel corporation, Ruander Cardenas of Hillsboro OR (US) for intel corporation, Lance Lin of Taipei (TW) for intel corporation, Eng Huat Goh of Paya Terubong (MY) for intel corporation, Javed Shaikh of Bengaluru (IN) for intel corporation, Jun Liao of Portland OR (US) for intel corporation, Kavitha Nagarajan of Bangalore (IN) for intel corporation, Tin Poay Chuah of Bayan Baru (MY) for intel corporation, Martin M. Chang of Beaverton OR (US) for intel corporation, Shantanu D. Kulkarni of Hillsboro OR (US) for intel corporation, Telesphor Kamgaing of Chandler AZ (US) for intel corporation
IPC Code(s): H05K7/20, F04D19/00, F04D29/52, G06F1/20
CPC Code(s): H05K7/202
Abstract: systems, apparatus, articles of manufacture, and methods are disclosed for cooling electronic devices. an example apparatus includes a fan module for an electronic device. the fan module includes a first cover; a second cover; an input/output (io) board adjacent the second cover, the second cover and io board beneath the first cover; and a fan between the first cover and the second cover, the fan to operate above the second cover and a portion of the io board.
20250008697. DIE CONTACT TORSIONAL SPRINGS_simplified_abstract_(intel corporation)
Inventor(s): Juha Tapani Paavola of Hillsboro OR (US) for intel corporation, Shawn S. McEuen of Portland OR (US) for intel corporation, Kari Mansukoski of Hillsboro OR (US) for intel corporation, Sami Markus Heinisuo of Dallas OR (US) for intel corporation, Cody Hougnon of Hillsboro OR (US) for intel corporation
IPC Code(s): H05K7/20
CPC Code(s): H05K7/2049
Abstract: die contact torsional springs are disclosed. a disclosed lid assembly for use with a circuit board includes a lid; a lug, a crank rotatably coupled to the lug, the crank including a spine, a jog to apply force to the lid, and a lever arm extending from the spine to apply a rotational moment to the spine when pressed against a surface.
Inventor(s): Juha PAAVOLA of Hillsboro OR (US) for intel corporation, Curtis KOEPSELL of Beaverton WA (US) for intel corporation, Sami HEINISUO of Dallas OR (US) for intel corporation, Kari MANSUKOSKI of Hillsboro OR (US) for intel corporation, Jeff KU of Taipei City (TW) for intel corporation
IPC Code(s): H05K9/00, H05K1/02
CPC Code(s): H05K9/0032
Abstract: an electronic device and method for assembling an electronic device. the device includes a shielding structure at least partially, laterally surrounding an electrical component on a circuit board. the device further includes a lid affixed to the top of the shielding structure and covering the electrical component, a spring directly or indirectly applying a load force to the electronic component, and a fastener affixing the lid and the spring to the circuit board.
20250008723. THREE-DIMENSIONAL FLOATING BODY MEMORY_simplified_abstract_(intel corporation)
Inventor(s): Abhishek A. Sharma of Portland OR (US) for intel corporation, Wilfred Gomes of Portland OR (US) for intel corporation, Tahir Ghani of Portland OR (US) for intel corporation, Anand S. Murthy of Portland OR (US) for intel corporation, Sagar Suthram of Portland OR (US) for intel corporation
IPC Code(s): H10B12/00, H01L23/528, H01L29/06, H01L29/423, H01L29/775, H01L29/78, H01L29/786
CPC Code(s): H10B12/20
Abstract: integrated circuit (ic) devices implementing three-dimensional (3d) floating body memory are disclosed. an example ic device includes a floating body memory cell comprising a transistor having a first source or drain (s/d) region, a second s/d region, and a gate over a channel portion between the first and second s/d regions; a bl coupled to the first s/d region and parallel to a first axis of a cartesian coordinate system; a sl coupled to the second s/d region and parallel to a second axis of the coordinate system; and a wl coupled to or being a part of the gate and parallel to a third axis of the coordinate system. ic devices implementing 3d floating body memory as described herein may be used to address the scaling challenges of conventional memory technologies and enable high-density embedded memory compatible with advanced cmos processes.
Inventor(s): Wriddhi Chakraborty of Hillsboro OR (US) for intel corporation, Sourav Dutta of Hillsboro OR (US) for intel corporation, Nazila Haratipour of Portland OR (US) for intel corporation, Sou-Chi Chang of Portland OR (US) for intel corporation, Shriram Shivaraman of Hillsboro OR (US) for intel corporation, Gilbert Dewey of Beaverton OR (US) for intel corporation, Uygar Avci of Portland OR (US) for intel corporation
IPC Code(s): H10B53/20, H10B53/30
CPC Code(s): H10B53/20
Abstract: an integrated circuit device includes a stack of capacitors with a vertical first electrode coupled to a stack of individual second electrodes by an insulating storage material between first and second electrodes, and an access transistor coaxially aligned with, and coupled to, the vertical first electrode. the storage material may be a ferroelectric material. a gate dielectric of the access transistor may be around, and coaxial with, a channel region. the channel region may be vertically oriented and coaxial with the first electrode. a second access transistor may be similarly aligned with the first electrode and the stack of capacitors with the capacitor stack between the transistors. a channel of the second transistor may be around, and coaxial with, a gate dielectric. the transistors and capacitor stack may be in arrays of transistors and capacitor stacks. a self-aligned process may be used to form the capacitor and transistor arrays.
Inventor(s): Punyashloka Debashis of Hillsboro OR (US) for intel corporation, Dominique A. Adams of Portland OR (US) for intel corporation, Gauri Auluck of Hillsboro OR (US) for intel corporation, Scott B. Clendenning of Portland OR (US) for intel corporation, Arnab Sen Gupta of Hillsboro OR (US) for intel corporation, Brandon Holybee of Portland OR (US) for intel corporation, Raseong Kim of Portland OR (US) for intel corporation, Matthew V. Metz of Portland OR (US) for intel corporation, Kevin P. O'Brien of Portland OR (US) for intel corporation, John J. Plombon of Portland OR (US) for intel corporation, Marko Radosavljevic of Portland OR (US) for intel corporation, Carly Rogan of North Plains OR (US) for intel corporation, Hojoon Ryu of Hillsboro OR (US) for intel corporation, Rachel A. Steinhardt of Beaverton OR (US) for intel corporation, Tristan A. Tronic of Aloha OR (US) for intel corporation, I-Cheng Tung of Hillsboro OR (US) for intel corporation, Ian Alexander Young of Olympia WA (US) for intel corporation, Dmitri Evgenievich Nikonov of Beaverton OR (US) for intel corporation
IPC Code(s): H10N70/00, H10B63/00, H10B99/00
CPC Code(s): H10N70/8836
Abstract: a two-terminal ferroelectric perovskite diode comprises a region of ferroelectric perovskite material positioned adjacent to a region of n-type doped perovskite semiconductor material. asserting a positive voltage across the diode can cause the polarization of the ferroelectric perovskite material to be set in a first direction that causes the diode to be placed in a low resistance state due to the formation of an accumulation region in the perovskite semiconductor material at the ferroelectric perovskite-perovskite semiconductor boundary. asserting a negative voltage across the diode can cause the polarization of the ferroelectric perovskite material to be set in a second direction that causes the diode to be placed in a high resistance state due to the formation of a depletion region in the perovskite semiconductor material at the ferroelectric perovskite-perovskite semiconductor material. these non-volatile low and high resistance states enable the diode to be used as a non-volatile memory element.
- Intel Corporation
- B25J9/16
- CPC B25J9/1661
- Intel corporation
- CPC B25J9/1679
- B25J15/12
- G06T7/215
- G06T7/80
- CPC B25J9/1697
- F04D29/46
- F04D29/42
- F04D29/58
- CPC F04D29/464
- F28D15/04
- F28D15/02
- CPC F28D15/046
- G01R31/26
- CPC G01R31/2621
- G01R31/28
- H05K1/02
- CPC G01R31/2896
- G01S13/42
- G01S7/35
- G01S13/89
- CPC G01S13/426
- G02B6/26
- G02B3/00
- CPC G02B6/262
- G02B6/27
- G02B6/42
- CPC G02B6/2746
- G02B6/30
- CPC G02B6/30
- G02B6/02
- CPC G02B6/4214
- CPC G02B6/4227
- CPC G02B6/4233
- CPC G02B6/4243
- G02B6/44
- CPC G02B6/4279
- CPC G02B6/428
- CPC G02B6/4292
- CPC G02B6/4293
- G03F7/30
- CPC G03F7/3092
- G03F7/00
- G03F1/22
- CPC G03F7/706845
- G03H1/08
- G03H1/04
- G06N3/02
- G06N3/067
- G06T1/20
- G06T7/00
- G06T7/66
- G06T9/00
- G06T19/00
- CPC G03H1/0808
- G05F1/46
- CPC G05F1/46
- G06F1/16
- H01H13/7073
- H01H13/785
- CPC G06F1/1662
- G06F1/3296
- G06F1/324
- CPC G06F1/3296
- G06F3/0354
- CPC G06F3/03545
- G06F7/485
- G06F7/487
- G06F7/76
- G06F9/30
- G06F9/38
- G06F17/16
- CPC G06F7/485
- G06F7/544
- CPC G06F9/30014
- CPC G06F9/30036
- CPC G06F9/30145
- CPC G06F9/30181
- CPC G06F9/3802
- CPC G06F9/3818
- CPC G06F9/3848
- G06F9/46
- CPC G06F9/465
- G06F9/48
- CPC G06F9/4881
- G06F1/26
- CPC G06F9/4893
- G06F9/50
- CPC G06F9/5038
- G06F9/54
- CPC G06F9/505
- G06F13/42
- CPC G06F9/5083
- G06F11/07
- CPC G06F11/079
- G06F11/10
- CPC G06F11/106
- G06F21/60
- CPC G06F11/1068
- G06F11/18
- CPC G06F11/181
- G06F11/27
- CPC G06F11/27
- G06F13/38
- G06F13/40
- CPC G06F13/382
- G06F15/78
- G06F7/575
- G06F7/58
- G06F12/02
- G06F12/06
- G06F12/0802
- G06F12/0804
- G06F12/0811
- G06F12/0862
- G06F12/0866
- G06F12/0871
- G06F12/0875
- G06F12/0882
- G06F12/0891
- G06F12/0893
- G06F12/0895
- G06F12/0897
- G06F12/1009
- G06F12/128
- G06F15/80
- G06F17/18
- G06N3/08
- G06T1/60
- G06T15/06
- H03M7/46
- CPC G06F15/7839
- G06F17/14
- CPC G06F17/14
- G06F17/15
- H04L9/00
- CPC G06F17/156
- G06F21/54
- G06F21/55
- CPC G06F21/54
- G06F21/78
- G06F21/57
- G06F21/64
- CPC G06F21/57
- G06F8/65
- G06F21/44
- CPC G06F21/572
- G06F21/72
- G06F21/74
- CPC G06F21/72
- G06F21/75
- CPC G06F21/75
- CPC G06F21/755
- G06F30/394
- CPC G06F30/394
- G06F30/398
- G06F30/392
- CPC G06F30/398
- G06N3/082
- G06F18/2113
- G06N3/063
- G06N5/04
- CPC G06N3/082
- G06N20/00
- CPC G06N20/00
- G06F3/14
- G06N3/044
- G06N3/045
- G06N3/084
- G06T15/00
- G06T15/04
- G09G5/36
- CPC G06T1/20
- G06T3/4053
- G06T3/4046
- G06T5/50
- G06T5/70
- CPC G06T3/4053
- G06T5/60
- G06T7/246
- CPC G06T5/60
- G06T7/194
- G06T3/40
- G06T7/11
- CPC G06T7/194
- G06V10/60
- G06T5/00
- G06V10/25
- G09G3/3208
- CPC G06V10/60
- G06V20/59
- B60K35/28
- B60K35/29
- G06V10/75
- G06V10/82
- G06V10/94
- G06V10/98
- CPC G06V20/59
- G09G3/20
- CPC G09G3/2096
- G09G3/34
- CPC G09G3/3406
- G09G5/22
- G06F3/01
- G09G5/377
- H04N19/107
- H04N19/159
- H04N19/174
- CPC G09G5/227
- G11C7/10
- G11C7/22
- CPC G11C7/106
- H01G7/06
- H10B53/00
- CPC H01G7/06
- H10B12/00
- H01L21/033
- CPC H01L21/0337
- H01L21/762
- H01L29/775
- H01L29/78
- CPC H01L21/76224
- H01L21/768
- H01L21/67
- CPC H01L21/76876
- H01L23/14
- H01L23/00
- H01L23/15
- CPC H01L23/147
- H01L23/24
- H01L23/367
- H01L23/538
- CPC H01L23/15
- H01L23/31
- H01L23/373
- H01L23/498
- H01L25/065
- H01L21/02
- H01L21/8234
- H01L27/02
- H01L27/088
- H01L29/06
- H01L29/417
- CPC H01L23/3171
- H01L23/427
- H01L21/48
- H01L25/18
- CPC H01L23/427
- H01L23/48
- H01L23/522
- H01L23/528
- H10B41/10
- H10B41/27
- H10B41/35
- H10B43/10
- H10B43/27
- H10B43/35
- CPC H01L23/481
- CPC H01L23/49822
- H01L23/64
- H10B80/00
- CPC H01L23/49838
- CPC H01L23/49894
- H01L23/532
- CPC H01L23/5226
- CPC H01L23/5227
- CPC H01L23/5381
- H01L23/58
- H01L25/10
- CPC H01L23/5384
- H01L23/544
- CPC H01L23/544
- H01L23/535
- H01L25/11
- H01L29/66
- CPC H01L23/642
- H01L23/66
- H01P3/08
- H01P11/00
- CPC H01L23/66
- H01L29/16
- H01L29/20
- H03F3/195
- H03F3/213
- CPC H01L24/03
- CPC H01L24/05
- CPC H01L24/08
- CPC H01L24/81
- CPC H01L25/0652
- H01L25/00
- H01L25/16
- CPC H01L25/105
- H01Q1/22
- H01Q23/00
- CPC H01L25/18
- H01L29/423
- CPC H01L27/0207
- H01L27/06
- CPC H01L27/0288
- H01L27/092
- H01L21/8238
- CPC H01L27/092
- H01L29/10
- H01L21/822
- H01L29/786
- CPC H01L27/0922
- H01L27/12
- H01L21/84
- CPC H01L27/12
- H01G4/012
- CPC H01L28/91
- CPC H01L29/0673
- H01L29/08
- H01L29/167
- H01L29/45
- CPC H01L29/0847
- H01L29/12
- H01L29/51
- CPC H01L29/41733
- CPC H01L29/41775
- H01L21/28
- H01L21/3213
- CPC H01L29/42392
- CPC H01L29/7827
- H01L29/24
- H01L29/49
- CPC H01L29/78391
- H01L29/76
- H01L29/221
- H01M10/44
- G01R31/36
- G01R31/367
- G01R31/3835
- H01M10/42
- H02J7/00
- CPC H01M10/448
- H01Q21/24
- CPC H01Q1/2283
- H02H9/02
- CPC H02H9/026
- H02H9/04
- CPC H02H9/046
- CPC H02J7/007194
- H02M3/07
- G05F1/575
- H02M1/00
- CPC H02M3/07
- H03K5/1252
- G06F1/06
- H03B5/36
- CPC H03K5/1252
- H03M1/46
- H03M1/80
- CPC H03M1/468
- H04B7/08
- H04B7/0426
- H04B7/06
- CPC H04B7/0854
- CPC H04L9/008
- H04L9/30
- H04L9/06
- H04L9/08
- CPC H04L9/0643
- CPC H04L9/088
- H04L9/32
- CPC H04L9/3247
- H04L9/40
- CPC H04L9/40
- H04L25/03
- H03F1/32
- H03F3/45
- CPC H04L25/03878
- H04L43/0817
- H04L43/067
- CPC H04L43/0817
- H04N7/15
- H04N7/14
- CPC H04N7/152
- H04R29/00
- H04R1/10
- H04R1/22
- CPC H04R29/001
- H04S7/00
- G06N3/0464
- CPC H04S7/40
- H04W24/02
- H04W72/04
- CPC H04W24/02
- H04W36/06
- H04W36/00
- H04W72/0453
- CPC H04W36/06
- H05K1/18
- CPC H05K1/181
- H05K7/20
- G06F1/20
- CPC H05K7/20145
- F04D19/00
- F04D29/52
- CPC H05K7/202
- CPC H05K7/2049
- H05K9/00
- CPC H05K9/0032
- CPC H10B12/20
- H10B53/20
- H10B53/30
- CPC H10B53/20
- H10N70/00
- H10B63/00
- H10B99/00
- CPC H10N70/8836
